1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
Single, 128-taps Low Voltage Digitally Controlled
Potentiometer (XDCP™)
ISL23318
The ISL23318 is a volatile, low voltage, low noise, low power,
I2C Bus™, 128 Taps, single digitally controlled potentiometer
(DCP), which integrates DCP core, wiper switches and control
logic on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) that can be directly written to and
read by the user. The contents of the WR controls the position
of the wiper. When powered on, the ISL23318’s wiper will
always commence at mid-scale (64 tap position).
The low voltage, low power consumption, and small package
of the ISL23318 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23318 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23318 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
Features
•128 resistor taps
•I
2C serial interface
- No additional level translator for low bus supply
- Two address pins allow up to four devices per bus
•Power supply
-V
CC = 1.7V to 5.5V analog power supply
-V
LOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70Ω typical @ VCC = 3.3V
• Shutdown Mode - forces the DCP into an end-to-end open
circuit and RW is shorted to RL internally
• Power-on preset to mid-scale (64 tap position)
• Shutdown and standby current <2.8µA max
• DCP terminal voltage from 0V to VCC
•10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40°C to +125°C
• 10 Ld MSOP or 10 Ld UTQFN packages
• Pb-free (RoHS compliant)
Applications
• Gain adjustment in battery powered instruments
• Trimming sensor circuits
• Power supply margining
• RF power amplifier bias compensation
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10k DCP
FIGURE 2. VREF ADJUSTMENT
0
2000
4000
6000
8000
10000
0326496128
TAP POSITION (DECIMAL)
RESISTANCE (Ω)
VREF_M
ISL28114
ISL23318 +
-
VREF
RL
RW
RH
July 26, 2011
FN7887.0
ISL23318
2FN7887.0
July 26, 2011
Block Diagram
LEVEL
SHIFTER
VCC
RH
GND
RL
RW
SCL
SDA
A1
A0
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
WR
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
VLOGIC
I/O
BLOCK
Pin Configurations
ISL23318
(10 LD MSOP)
TOP VIEW
ISL23318
(10 LD UTQFN)
TOP VIEW
1
2
3
4
56
10
9
8
7
SDA
VLOGIC
A1
A0
GND
SCL
RL
RW
RH
VCC
9
8
7
6
1
2
3
4
RL
A1
VCC
RH
GND
SCL
A0
510
SDA
RW
VLOGIC
Pin Descriptions
MSOP UTQFN SYMBOL DESCRIPTION
110V
LOGIC I2C bus /logic supply. Range 1.2V to
5.5V
2 1 SCL Logic Pin - Serial bus clock input
3 2 SDA Logic Pin - Serial bus data
input/open drain output
4 3 A0 Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
5 4 A1 Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
6 5 RL DCP “low” terminal
7 6 RW DCP wiper terminal
8 7 RH DCP “high” terminal
98 V
CC Analog power supply.
Range 1.7V to 5.5V
10 9 GND Ground pin
ISL23318
3FN7887.0
July 26, 2011
Ordering Information
PART NUMBER
(Note 5) PART MARKING
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL23318TFUZ (Notes 1, 3) 3318T 100 -40 to +125 10 Ld MSOP M10.118
ISL23318UFUZ (Notes 1, 3) 3318U 50 -40 to +125 10 Ld MSOP M10.118
ISL23318WFUZ (Notes 1, 3) 3318W 10 -40 to +125 10 Ld MSOP M10.118
ISL23318TFRUZ-T7A (Notes 2, 4) HH 100 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
ISL23318TFRUZ-TK (Notes 2, 4) HH 100 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
ISL23318UFRUZ-T7A (Notes 2, 4) HG 50 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
ISL23318UFRUZ-TK (Notes 2, 4) HG 50 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
ISL23318WFRUZ-T7A (Notes 2, 4) HF 10 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
ISL23318WFRUZ-TK (Notes 2, 4) HF 10 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A
NOTES:
1. Add "-TK" or "-T7A" suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23318. For more information on MSL please see techbrief TB363.
ISL23318
4FN7887.0
July 26, 2011
Absolute Maximum Ratings Thermal Information
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
10 Ld MSOP Package (Notes 6, 7). . . . . . . 170 70
10 Ld UTQFN Package (Notes 6, 7) . . . . . . 145 90
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For θJC, the “case temp” location is the center top of the package.
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
RTOTAL RH to RL Resistance W option 10 kΩ
U option 50 kΩ
T option 100 kΩ
RH to RL Resistance Tolerance -20 ±2 +20 %
End-to-End Temperature Coefficient W option 175 ppm/°C
U option 85 ppm/°C
T option 70 ppm/°C
VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0V
CC V
RWWiper Resistance RH - floating, VRL = 0V, force IW current
to the wiper,
IW = (VCC - VRL)/RTOTAL,
VCC = 2.7V to 5.5V
70 200 Ω
VCC = 1.7V 580 Ω
CH/CL/CWTerminal Capacitance See “DCP Macro Model” on page 8 32 pF
ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA
Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz
Wiper at middle point, U option 49 nV/√Hz
Wiper at middle point, T option 61 nV/√Hz
Feed Thru Digital Feed-Through from Bus to Wiper Wiper at middle point -65 dB
PSRR Power Supply Reject Ratio Wiper output change if VCC change
±10%; wiper at middle point
-75 dB
ISL23318
5FN7887.0
July 26, 2011
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL
(Note 13)
Integral Non-linearity, Guaranteed
Monotonic
W, U, T options -0.5 ±0.15 +0.5 LSB
(Note 9)
DNL
(Note 12)
Differential Non-linearity, Guaranteed
Monotonic
W, U, T options -0.5 ±0.15 +0.5 LSB
(Note 9)
FSerror
(Note 11)
Full-scale Error W option -2.5 -1.5 0LSB
(Note 9)
U, T option -1.0 -0.7 0LSB
(Note 9)
ZSerror
(Note 10)
Zero-scale Error W option 01.5 2.5 LSB
(Note 9)
U, T option 00.7 1.0 LSB
(Note 9)
TCV
(Notes 14)
Ratiometric Temperature Coefficient W option, Wiper Register set to 40 hex 8 ppm/°C
U option, Wiper Register set to 40 hex 4 ppm/°C
T option, Wiper Register set to 40 hex 2.3 ppm/°C
Large Signal Wiper Settling Time From code 0 to 7F hex 300 ns
fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz
Wiper at middle point U option 250 kHz
Wiper at middle point T option 120 kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 18)
Integral Non-linearity, Guaranteed
Monotonic
W option; VCC = 2.7V to 5.5V -1.0 ±0.5 +1.0 MI
(Note 15)
W option; VCC = 1.7V ±3.0 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI
(Note 15)
U, T option; VCC = 1.7V ±1.0 MI
(Note 15)
RDNL
(Note 17)
Differential Non-linearity, Guaranteed
Monotonic
W option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI
(Note 15)
W option; VCC = 1.7V ±0.4 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI
(Note 15)
U, T option; VCC = 1.7V ±0.4 MI
(Note 15)
Roffset
(Note 16)
Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 01.8 3.0 MI
(Note 15)
W option; VCC = 1.7V 3.0 MI
(Note 15)
U, T option; VCC = 2.7V to 5.5V 00.3 1MI
(Note 15)
U, T option; VCC = 1.7V 0.5 MI
(Note 15)
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
ISL23318
6FN7887.0
July 26, 2011
TCR
(Note 19)
Resistance Temperature Coefficient W option; Wiper register set between
19 hex and 7F hex
220 ppm/°C
U option; Wiper register set between 19
hex and 7F hex
100 ppm/°C
T option; Wiper register set between 19
hex and 7F hex
75 ppm/°C
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V,
fSCL = 400kHz (for I2C active read and
write)
200 µA
VLOGIC = 1.2V, VCC = 1.7V,
fSCL = 400kHz (for I2C active read and
write)
5µA
ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 18 µA
VLOGIC = 1.2V, VCC = 1.7V 10 µA
ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1.3 µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.4 µA
ICC SB VCC Standby Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1.5 µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
1µA
ILOGIC SHDN VLOGIC Shutdown Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1.3 µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.4 µA
ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V,
I2C interface in standby
1.5 µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
1µA
ILkgDig Leakage Current, at Pins A0, A1, SDA, SCL Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA
tDCP Wiper Response Time SCL rising edge of the acknowledge bit
after data byte to wiper new position
1.5 µs
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
1.5 µs
VCC, VLOGIC
Ramp
(Note 21)
VCC ,VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms
ISL23318
7FN7887.0
July 26, 2011
Serial Interface Specification For SCL, SDA, A0, A1 unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
VIL Input LOW Voltage -0.3 0.3 x VLOGIC V
VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V
Hysteresis SDA and SCL Input Buffer
Hysteresis
VLOGIC > 2V 0.05 x VLOGIC V
VLOGIC < 2V 0.1 x VLOGIC
VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V
IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V
Cpin SDA, SCL Pin Capacitance 10 pF
fSCL SCL Frequency 400 kHz
tsp Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
50 ns
tAA SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
of VLOGIC, until SDA exits the
30% to 70% of VLOGIC window
900 ns
tBUF Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VLOGIC
during a STOP condition, to
SDA crossing 70% of VLOGIC
during the following START
condition
1300 ns
tLOW Clock LOW Time Measured at the 30% of
VLOGIC crossing
1300 ns
tHIGH Clock HIGH Time Measured at the 70% of
VLOGIC crossing
600 ns
tSU:STA START Condition Set-up Time SCL rising edge to SDA falling
edge; both crossing 70% of
VLOGIC
600 ns
tHD:STA START Condition Hold Time From SDA falling edge
crossing 30% of VLOGIC to SCL
falling edge crossing 70% of
VLOGIC
600 ns
tSU:DAT Input Data Set-up Time From SDA exiting the 30% to
70% of VLOGIC window, to SCL
rising edge crossing 30% of
VLOGIC
100 ns
tHD:DAT Input Data Hold Time From SCL falling edge crossing
70% of VCC to SDA entering
the 30% to 70% of VLOGIC
window
0ns
tSU:STO STOP Condition Set-up Time From SCL rising edge crossing
70% of VLOGIC, to SDA rising
edge crossing 30% of VLOGIC
600 ns
tHD:STO STOP Condition Hold Time for Read
or Write
From SDA rising edge to SCL
falling edge; both crossing
70% of VLOGIC
1300 ns
tDH Output Data Hold Time From SCL falling edge crossing
30% of VLOGIC, until SDA
enters the 30% to 70% of
VLOGIC window.
IOL =3mA,V
LOGIC > 2V.
IOL = 0.5mA, VLOGIC < 2V
0ns
tRSDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns
ISL23318
8FN7887.0
July 26, 2011
DCP Macro Model
tFSDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
tSU:A A1, A0 Set-up Time Before START condition 600 ns
tHD:A A1, A0 Hold Time After STOP condition 600 ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)127 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127.
14. For i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00
hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW127/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127.
19. For i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC
first followed by the VCC.
Serial Interface Specification For SCL, SDA, A0, A1 unless otherwise noted. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
TCV
Max V RW()
i
()Min V RW()
i
()–
VRW
i+25°C()()
------------------------------------------------------------------------------106
+165°C
---------------------
×=
TCR
Max Ri()Min Ri()–[]
Ri +25°C()
-------------------------------------------------------10
6
+165°C
---------------------
×=
32pF
RH
RTOTAL
CH
32pF
CW
CL
32pF
RW
RL
ISL23318
9FN7887.0
July 26, 2011
Timing Diagrams
SDA vs SCL Timing
A0 and A1 Pin Timing
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tFtLOW
tBUF
tAA
tRtsp
tHD:A
SCL
SDA
A0, A1
tSU:A
CLK 1
START STOP
Typical Performance Curves
FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V
-0.4
-0.2
0
0.2
0.4
0 163248648096112128
DNL (LSB)
TAP POSITION (DECIMAL)
-0.04
-0.02
0
0.02
0.04
0 163248648096112128
DNL (LSB)
TAP POSITION (DECIMAL)
ISL23318
10 FN7887.0
July 26, 2011
FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V
FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V
FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V
Typical Performance Curves (Continued)
-0.4
-0.2
0
0.2
0.4
0 16 32 48 64 80 96 112 128
INL (LSB)
TAP POSITION (DECIMAL)
-0.16
-0.08
0
0.08
0.16
0 16 32 48 64 80 96 112 128
INL (LSB)
TAP POSITION (DECIMAL)
-0.4
-0.2
0
0.2
0.4
0 163248648096112128
RDNL (MI)
TAP POSITION (DECIMAL)
-0.10
-0.05
0
0.05
0.10
0 163248648096112128
RDNL (MI)
TAP POSITION (DECIMAL)
-0.4
-0.2
0
0.2
0.4
0 163248648096112128
RINL (MI)
TAP POSITION (DECIMAL)
-0.16
-0.08
0
0.08
0.16
0 163248648096112128
RINL (MI)
TAP POSITION (DECIMAL)
ISL23318
11 FN7887.0
July 26, 2011
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION
FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION
Typical Performance Curves (Continued)
0
10
20
30
40
50
60
0 163248648096112128
WIPER RESISTANCE (Ω)
TAP POSITION (DECIMAL)
+125°C
-40°C
+25°C
0
10
20
30
40
50
0 163248648096112128
WIPER RESISTANCE (Ω)
TAP POSITION (DECIMAL)
+125°C
-40°C
+25°C
0
20
40
60
80
100
120
140
16 32 48 64 80 96 112 128
TCv (ppm/°C)
TAP POSITION (DECIMAL)
0
5
10
15
20
25
30
16 32 48 64 80 96 112 128
TCv (ppm/°C)
TAP POSITION (DECIMAL)
0
50
100
150
200
250
300
350
16 32 48 64 80 96 112 128
TCr (ppm/°C)
TAP POSITION (DECIMAL)
0
25
50
75
100
16 32 48 64 80 96 112 128
TCr (ppm/°C)
TAP POSITION (DECIMAL)
ISL23318
12 FN7887.0
July 26, 2011
FIGURE 17. 100k TCv vs TAP POSITION FIGURE 18. 100k TCr vs TAP POSITION
FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
Typical Performance Curves (Continued)
0
5
10
15
20
16 32 48 64 80 96 112 128
TCv (ppm/°C)
TAP POSITION (DECIMAL)
100
110
120
130
140
150
16 32 48 64 80 96 112 128
TCr (ppm/°C)
TAP POSITION (DECIMAL)
1µs/DIV
SCL CLOCK
RW PI
N
1V/DIV
10mV/DIV
20mV/DIV
5µs/DIV
1V/DIV
1µs/DIV
SCL 9TH CLOCK OF THE
WIPER
DATA BYTE (ACK)
1V/DIV
0.1s/DIV
VRH = VCC
VRW
ISL23318
13 FN7887.0
July 26, 2011
Functional Pin Descriptions
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23318 are
equivalent to the fixed terminals of a mechanical potentiometer.
RH and RL are referenced to the relative position of the wiper and
not the voltage potential on the terminals. With WR set to 127
decimal, the wiper will be closest to RH, and with the WR set to 0,
the wiper is closest to RL.
RW
RW is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, wiper address and data
from an I2C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23318. A
maximum of four ISL23318 devices may occupy the I2C serial
bus (see Table 3).
VLOGIC
This is an input pin that supplies internal level translator for serial
bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23318 is an integrated circuit incorporating one DCP with
its associated registers and an I2C serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
Voltage at any DCP pins, RH, RL or RW, should not exceed VCC
level at any conditions during power-up and normal operation.
The VLOGIC pin needs to be connected to the I2C bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by a 7-bit volatile
Wiper Register (WR). When the WR of a DCP contains all zeroes
(WR[7:0] = 00h), its wiper terminal (RW) is closest to its “Low”
terminal (RL). When the WR register of a DCP contains all ones
(WR[7:0] = 7Fh), its wiper terminal (RW) is closest to its “High”
terminal (RH). As the value of the WR increases from all zeroes
(0) to 0111 1111b (127 decimal), the wiper moves
FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
RTOTAL = 10k
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
CH1: 0.5V/DIV, 0.2µs/DIV RH PIN
CH2: 0.2V/DIV, 0.2µs/DIV RW PIN
0
0.2
0.4
0.6
0.8
1.0
1.2
-40 -15 10 35 60 85 110
STANDBY CURRENT I
CC
(µA)
TEMPERATURE (°C)
VCC = 5.5V, VLOGIC = 5.5V
VCC = 1.7V, VLOGIC = 1.2V
ISL23318
14 FN7887.0
July 26, 2011
monotonically from the position closest to RL to the position
closest to RH. At the same time, the resistance between RW
and RL increases monotonically, while the resistance between
RH and RW decreases monotonically.
While the ISL23318 is being powered up, the WR is reset to 40h
(64 decimal), which locates RW roughly at the center between RL
and RH.
The WR can be read or written to directly using the I2C serial
interface as described in the following sections.
Memory Description
The ISL23318 contains two volatile 8-bit registers: Wiper Register
(WR) and Access Control Register (ACR). The memory map of
ISL23318 is shown in Table 1. The Wiper Register (WR) at address 0
contains current wiper position. The Access Control Register (ACR)
at address 10h contains information and control bits described
in Table 2.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1
In the shutdown mode, the RW terminal is shorted to the RL
terminal with around 2kΩ resistance as shown in Figure 25. When
the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
I2C Serial Interface
The ISL23318 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23318 operates as a slave device
in all applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23318, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23318 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23318 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10 ACR 40
0WR 40
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 76543210
NAME/
VALUE
0SHDN
000000
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
2kΩ
RW
RL
RH
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
POWER-UP
USER PROGRAMMED
MID SCALE = 80H
SHDN ACTIVATED SHDN RELEASED
AFTER SHDN
WIPER VOLTAGE, VRW (V)
SHDN MODE
TIME (s)
WIPER RESTORE TO
THE ORIGINAL POSITION
0
ISL23318
15 FN7887.0
July 26, 2011
after successful receipt of an Address Byte. The ISL23318 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 10100 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
10100A1A0R/W
(MSB) (LSB)
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
10100
A
C
K
WRITE
SIGNAL AT SDA 000
A0A1
FIGURE 29. BYTE WRITE SEQUENCE
0
ISL23318
16 FN7887.0
July 26, 2011
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23318 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 28 and 29).
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23318 responds
with an ACK; then the ISL23318 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
Applications Information
VLOGIC Requirements
It is recommended to keep VLOGIC powered all the time during
normal operation. In a case where turning VLOGIC OFF is
necessary, it is recommended to ground the VLOGIC pin of the
ISL23318. Grounding the VLOGIC pin or both VLOGIC and VCC does
not affect other devices on the same bus. It is good practice to
put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as
possible.
VCC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
7Eh to 7Fh, which have higher transient glitch. Note that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
10100
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
000A0A1 A0A1
FIGURE 30. READ SEQUENCE
A
C
K
001010
READ
ISL23318
17
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7887.0
July 26, 2011
For additional products, see www.intersil.com/product_tree
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
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DATE REVISION CHANGE
7/26/11 FN7887.0 Initial Release
ISL23318
18 FN7887.0
July 26, 2011
Mini Small Outline Plastic Packages (MSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Da tum Plane. Mold flash, p rotrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums and to be determined at Datum plane
.
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
L
0.25
(0.010)
L1
R1
R
4X θ
4X θ
GAUGE
PLANE
SEATING
PLANE
EE1
N
12
TOP VIEW
INDEX
AREA
-C-
-B-
0.20 (0.008) ABC
SEATING
PLANE
0.20 (0.008) C
0.10 (0.004) C
-A-
-H-
SIDE VIEW
b
e
D
A
A1
A2
-B-
END VIEW
0.20 (0.008) CD
E1
C
L
C
a
- H -
-A - - B -
- H -
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.037 0.043 0.94 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.030 0.037 0.75 0.95 -
b 0.007 0.011 0.18 0.27 9
c 0.004 0.008 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
e 0.020 BSC 0.50 BSC -
E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -
N10 107
R 0.003 - 0.07 - -
R1 0.003 - 0.07 - -
5o15o5o15o-
α0o6o0o6o-
Rev. 0 12/02
θ
ISL23318
19 FN7887.0
July 26, 2011
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
1
2X
0.10
1.60
2.10
B
A
INDEX AREA
PIN 1
1
(6X 0.50 )
(10 X 0.20)
(0.10 MIN.)
(0.05 MIN)
8.
(10X 0.60)
PACKAGE
(2.00) (0.80)
(1.30)
(2.50)
0.08
SEATING PLANE
0.10 C
C
C
SEE DETAIL "X"
MAX. 0.55
0 . 125 REF
0-0.05
C
6
9
1
5
6X 0.50
C
C
10 X 0.20 4
0.10
M
MAB
0.80
PIN #1 ID
4
10
0.10 MIN.
0.05 MIN.
4X 0.20 MIN.
8.
10X 0.40
OUTLINE
Lead width dimension applies to the metallized terminal and is measured
The configuration of the pin #1 identifier is optional, but must be located within
the zone indicated. The pin #1 identifier may be either a mold or mark feature.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
Unless otherwise specified, tolerance : Decimal ± 0.05
1.
All Dimensions are in millimeters. Angles are in degrees.
Dimensions in ( ) for Reference Only.
between 0.15mm and 0.30mm from the terminal tip.
Maximum package warpage is 0.05mm.
4.
5.
2.
3.
NOTES:
Maximum allowable burrs is 0.076mm in all directions.6.
Same as JEDEC MO-255UABD except:7.
No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm
Lead Length dim. = 0.45mm max. not 0.42mm.
8.
