IMAGE SENSOR CCD image sensor S10420-1006/-1106 High UV sensitivity CCD image sensor S10420-1006/-1106 are back-thinned type CCD image sensors specifically designed for spectrophotometers. S10420-1006/-1106 offer nearly flat spectral response characteristics with high quantum efficiency from the UV to near infrared region. They also feature low noise, low dark current, and a wide dynamic range, enabling low-light-level detection by setting a long integration time. Features Applications l High sensitivity over a wide spectral range and nealy flat spectral response characteristics l High CCD node sensitivity: 6.5 V/e- (RL=100 k) l High full well capacity and wide dynamic range l Spectrometer, etc. (with anti-blooming function). l Pixel size: 14 x 14 m l Active area: 14.336 (H) x 0.896 (V) mm (S10420-1006) 28.672 (H) x 0.896 (V) mm (S10420-1106) General ratings Parameter Pixel size Number of pixels Number of active pixels Active area Vertical clock phase Horizontal clock phase Output circuit Package Window S10420-1006 1044 x 70 1024 x 64 14.336 (H) x 0.896 (V) mm 2068 x 70 2048 x 64 28.672 (H) x 0.896 (V) mm 2-phase 4-phase One-stage MOSFET source follower 24-pin ceramic DIP Quartz glass Spectral response (without window) Symbol Topr Tstg VOD VRD VOFD VISV, VISH VOFG VIG1V, VIG2V VIG1H, VIG2H VSG VOG VRG VTG VP1V, VP2V VP1H, VP2H VP3H, VP4H Min. -50 -50 -0.5 -0.5 -0.5 -0.5 -10 -10 -10 -10 -10 -10 -10 -10 Typ. - Max. +50 +70 +30 +18 +18 +18 +15 +15 +15 +15 +15 +15 +15 +15 Unit C C V V V V V V V V V V V V -10 - +15 V (Typ. Ta=25 C) 100 QUANTUM EFFICIENCY (%) Absolute maximum ratings (Ta=25 C) Parameter Operating temperature Storage temperature OD voltage RD voltage OFD voltage ISH voltage OFG voltage IGV voltage IGH voltage SG voltage OG voltage RG voltage TG voltage Vertical clock voltage Horizontal clock voltage S10420-1106 14 (H) x 14 (V) m 80 60 40 20 0 200 400 600 800 1000 1200 WAVELENGTH (nm) KMPDB0265EA 1 CCD image sensor S10420-1006/-1106 Operating conditions (MPP mode, Ta=25 C) Parameter Output transistor drain voltage Reset drain voltage Over flow drain voltage Over flow gate voltage Output gate voltage Substrate voltage Test point (input source) Test point (vertical input gate) Test point (horizontal input gate) Vertical shift register clock voltage Horizontal shift register clock voltage Summing gate voltage Reset gate voltage Transfer gate voltage High Low High Low High Low High Low High Low Symbol VOD VRD VOFD VOFG VOG VSS VISH VIG1V, VIG2V VIG1H, VIG2H VP1VH, VP2VH VP1VL, VP2VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL VTGH VTGL Min. 23 11 11 0 5 -9 -9 4 -9 4 -6 4 -6 4 -6 4 -9 Typ. 24 12 12 13 6 0 VRD -8 -8 6 -8 6 -5 6 -5 6 -5 6 -8 Max. 25 13 13 14 7 0 0 8 -7 8 -4 8 -4 8 -4 8 -7 Unit V V V V V V V V V Symbol fc CP1V, CP2V CP1H, CP2H CP3H, CP4H CSG CRG CTG CTE Vout Zo P Min. - Typ. 250 1200 Max. 500 - Unit kHz pF - 160 - pF 10 10 80 0.99999 18 10 4 19 - pF pF pF V k mW Typ. Fw x Sv 80 200 6.5 50 6 33300 13300 200 to 1100 3 Max. 7.5 500 15 10 Unit V V V V V V Electrical characteristics (Ta=25 C) Parameter Signal output frequency *1 Vertical shift register capacitance Horizontal shift register capacitance Summing gate capacitance Reset gate capacitance Transfer gate capacitance Charge transfer efficiency *2 0.99995 DC output level *1 17 Output impedance *1 Power consumption *1, *3 *1: VOD=24 V, RL=100 k *2: Charge transfer efficiency per pixel, measured at half of the full well capacity *3: Total power consumption of the on-chip amplifier and load resistance Electrical and optical characteristics (Ta=25 C, unless otherwise noted) Parameter Symbol Min. Saturation output voltage Vsat Vertical 60 Full well capacity Fw Horizontal 150 CCD node sensitivity *4 Sv 5.5 Dark current *5 DS Readout noise *6 Nr Line binning 12000 Dynamic range *7 DR Area scanning 4270 Spectral response range Photo response non-uniformity *8 PRNU *4: VOD=24 V, RL=100 k *5: Dark current is reduced to half for every 5 to 7 C decrease in temperature. *6: -40 C, Readout frequency is 20 kHz. *7: Dynamic range (DR) = Full well capacity/Readout noise *8: Measured at the half of the full well capacity output. Photo response non-uniformity (PRNU) [%] 2 Fixed pattern noise (peak to peak) Signal x 100 ke - V/e e /pixel/s e rms - nm % CCD image sensor S10420-1006/-1106 Device structure (Conceptual drawing of top view) THINNING 22 21 20 19 18 17 16 2 BEVEL 23 64 SIGNAL OUT THINNING 64 15 5 4 3 2 1 2 3 4 5 14 1024 13 4 BEVEL 24 1 2 3 4 BLANK 6 BEVEL 4 5 6 7 8 9 10 11 2048 SIGNAL OUT 12 4 BLANK 6 BEVEL KMPDC0269EA Timing chart (Line binning) INTEGRATION PERIOD (Shutter must be open) Tpwv VERTICAL BINNING PERIOD (Shutter must be closed) READOUT PERIOD (Shutter must be closed) P1V Tovr P2V, TG Tpwh, Tpws Tovrh P1H P2H P3H P4H, SG Tpwr RG OS KMPDC0270EB Parameter Symbol Remark Pulse width Tpwv P1V, P2V, TG *9 Rise and fall time Tprv, Tpfv Pulse width Tpwh *9 Rise and fall time Tprh, Tpfh P1H, P2H, P3H, P4H Pulse overlap time Tovrh Duty ratio *9 Pulse width Tpws *9 Rise and fall time Tprs, Tpfs SG Pulse overlap time Tovrh Duty ratio *9 Pulse width Tpwr RG Rise and fall time Tprr, Tpfr TG (P2V) - P1H Overlap time Tovr *9: Symmetrical clock pulses should be overlapped at 50 % of maximum pulse amplitude. Min. 6 20 1000 10 500 40 1000 10 500 40 100 5 1 Typ. 8 2000 1000 50 2000 1000 50 1000 2 Max. 50 60 - Unit s ns ns ns ns % ns ns ns % ns ns s 3 CCD image sensor S10420-1006/-1106 Dimensional outline (unit: mm) 38.10 0.4 3.3 0.35 13 1 12 0.25-0.03 +0.05 10.03 0.3 10.41 0.25 27.94 0.3 24 INDEX MARK 2.54 0.13 0.46 0.05 1.27 0.2 3.0 0.5 1.47 1.27 0.25 PHOTOSENSITIVE SURFACE KMPDA0223EA Pin connections Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol OS OD OG SG SS RD P4H P3H P2H P1H IG2H IG1H OFG OFD ISH ISV SS RD IG2V IG1V P2V P1V TG RG Function Output transistor source Output transistor drain Output gate Summing gate Substrate Reset drain CCD horizontal register clock-4 CCD horizontal register clock-3 CCD horizontal register clock-2 CCD horizontal register clock-1 Test point (horizontal input gate-2) Test point (horizontal input gate-1) Over flow gate Over flow drain Test point (horizontal input source) Test point (vertical input source) Substrate Reset drain Test point (vertical input gate-2) Test point (vertical input gate-1) CCD vertical register clock-2 CCD vertical register clock-1 Transfer gate Reset gate Remark (standard operation) RL=100 k +24 V +6 V Same pulse as P4H GND +12 V Connect to RD Connect to RD GND Same pulse as P2V Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. (c)2008 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvagen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1102E02 Jul. 2008 DN 4