CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
Document Title
128K x16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
Remark
Preliminary
Final
History
Initial Draft
Finalize
- Change operation voltage:
Vcc=2.3~3.3V Vcc=2.3~2.7V
- Release operating current
ICC=2mA 5mA
ICC1 Read/Write=3/15mA 5/20mA
Draft Data
October 1, 1997
August 27, 1998
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
128K x16 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The KM616S2000 families are fabricated by SAMSUNGs
advanced CMOS process technology. The families support
various operating temperature ranges and small package
for user flexibility of system design. The families also sup-
port low data retention voltage for battery back-up operation
with low data retention current.
FEATURES
Process Technology : TFT
Organization :128Kx16
Power Supply Voltage
KM616S2000 Family : 2.3~2.7V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 44-TSOP2 -400F
PIN DESCRIPTION
Name Function Name Function
CS Chip Select Input I/O1~I/O16 Data Inputs/Outputs
OE Output Enable Input A0~A16 Address Inputs
WE Write Enable Input Vcc Power
UB Upper Block Select Input Vss Ground
LB Lower Block Select Input N.C No Connection
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Produc Family Operating Temperature Vcc Range Speed(ns) Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2,Max)
KM616S2000L-L Commercial(0~70°C) 2.3~2.7V 1201)/150ns 10µA45mA 44-TSOP2-F
KM616S2000LI-L Industrial(-40~85°C) 15µA
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
A9
A10
A11
N.C
44-TSOP2
Forward
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Precharge circuit.
Memory array
1024 rows
128×16 columns
I/O Circuit
Column select
Clk gen.
Row
select
A9 A10 A11 A12 A13 A14A15
A0
A1
A2
A3
A4
A5
A6
A7
CS
OE
UB
WE
I/O1~I/O8
A8
Data
cont
Data
cont
Data
cont
LB
I/O9~I/O16
Vcc
Vss
A16
Control
logic
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
PRODUCT LIST
Note : LL - Low Low Standby Current
Commercial Temperature Product(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
KM616S2000LT-12L
KM616S2000LT-15L 44-TSOP2, 120ns, 2.3~2.7V, LL
44-TSOP2, 150ns, 2.3~2.7V, LL KM616S2000LTI-12L
KM616S2000LTI-15L 44-TSOP2, 120ns, 2.3~2.7V, LL
44-TSOP2, 150ns, 2.3~2.7V, LL
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-
Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CKM616S2000L
-40 to 85 °CKM616S2000LI
Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -
FUNCTIONAL DESCRIPTION
1. X means dont care. (Must be in low or high state)
CS OE WE LB UB I/O1~8 I/O9~16 Mode Power
HX1) X1) X1) X1) High-Z High-Z Deselected Standby
LH H X1) X1) High-Z High-Z Output Disabled Active
LX1) X1) H H High-Z High-Z Output Disabled Active
L L HLHDout High-Z Lower Byte Read Active
L L H H LHigh-Z Dout Upper Byte Read Active
L L HL L Dout Dout Word Read Active
LX1) L L HDin High-Z Lower Byte Write Active
LX1) LHLHigh-Z Din Upper Byte Write Active
LX1) L L L Din Din Word Write Active
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+1.0V in case of pulse width 20ns
3. Undershoot : -1.0V in case of pulse width 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Product Min Typ Max Unit
Supply voltage Vcc KM616S2000 Family 2.3 2.5 2.7 V
Ground Vss All Family 000V
Input high voltage VIH KM616S2000 Family 2.0 -Vcc+0.32) V
Input low voltage VIL KM616S2000 Family -0.33) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
DC AND OPERATING CHARACTERISTICS
1. KM616S2000I Family =15µA
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 -1µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 5mA
Average operating current ICC1 Cycle time=1µs, 100% duty IIO=0mA,
CS0.2V, VIN0.2V or VINVcc-0.2V Read - - 5mA
Write - - 20
ICC2 Cycle time=Min, 100% duty - - 45 mA
Output low voltage VOL IOL=0.5mA at 2.3~2.7V - - 0.4 V
Output high voltage VOH IOH=-0.5mA 2.0 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA
Standby Current (CMOS) ISB1 CSVcc-0.2V, Other inputs=0~Vcc - - 101) µA
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
AC CHARACTERISTICS (Vcc=2.3~2.7V, KM616S2000 Family : TA=0 to 70°C, KM616S2000I Family : TA=-40 to 85°C)
1. The parameter is measured with 30pF test load.
Parameter List Symbol Speed Bins Units
1201)ns 150ns
Min Max Min Max
Read
Read cycle time tRC 120 -150 -ns
Address access time tAA -120 -150 ns
Chip select to output tCO -120 -150 ns
Output enable to valid output tOE -60 -75 ns
Byte enable to valid output tBA -60 -75 ns
Chip select to low-Z output tLZ 20 -20 -ns
Output enable to low-Z output tOLZ 10 -10 -ns
UB, LB enable to low-Z output tBLZ 10 -10 -ns
Output hold from address change tOH 15 -15 -ns
Chip disable to high-Z output tHZ -35 0 40 ns
Output disable to high-Z output tOHZ -35 0 40 ns
UB, LB disable to high-Z output tBHZ -35 0 40 ns
Write
Write cycle time tWC 120 -150 -ns
Chip select to end of write tCW 100 -120 -ns
Address set-up time tAS 0-0-ns
Address valid to end of write tAW 100 -120 -ns
UB, LB valid to end of write tBW 100 -120 -ns
Write pulse width tWP 80 -100 -ns
Write recovery time tWR 0-0-ns
Write to output high-Z tWHZ 0 30 0 40 ns
Data to write time overlap tDW 50 -60 -ns
Data hold from write time tDH 0-0-ns
End write to output low-Z tOW 5-5-ns
DATA RETENTION CHARACTERISTICS
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CSVcc-0.2V 2.0 -2.7 V
Data retention current IDR Vcc=2.0V, CSVcc-0.2V - - 10 µA
Data retention set-up time tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
CL1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL1)=30pF+1TTL
1. Refer to AC CHARACTERISTICS
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
tRC
CS
Address
UB, LB
OE
Data out
tAA
tRC
tOH
tOH
tAA
tCO
tBA
tOE
tOLZ
tBLZ
tLZ tOHZ
tBHZ
tHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
Data Undefined
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
tWC
tCW(2) tWR(4)
tAWtBW
tWP(1)
tAS(3) tDH
tDW
tWHZ tOW
tWC
tCW(2)
tAW tBW
tWP(1)
tDH
tDW
tWR(4)
High-Z High-Z
Data Valid
tAS(3)
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
Address
CS
Data Valid
UB, LB
WE
Data in
Data out High-Z High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
DATA RETENTION WAVE FORM
CS controlled
VCC
2.3V
2.2V
VDR
CS
GND
Data Retention Mode
CSVCC - 0.2V
tSDR tRDR
tAS(3)
CMOS SRAMKM616S2000 Family
Revision 1.0
August 1998
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
Unit : millimeter(inch)
0.002
#1
0.05
#22
#44 #23
0.35±0.10
0.014±0.004 0.80
0.0315
MIN.
0.047
1.20MAX.
0.741
18.81MAX.
18.41±0.10
0.725±0.004
11.76±0.20
0.463±0.008
+ 0.10
- 0.05
0.50
+ 0.004
- 0.002
0.15
0.006
0.020
10.16
0.400
0.10
0.004
PACKAGE DIMENSIONS
0~8°
0.45 ~0.75
0.018 ~ 0.030
0.25
( )
0.010
( )
0.805
0.032
( )
MAX
1.00±0.10
0.039±0.004