KM616S2000 Family CMOS SRAM Document Title 128K x16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial Draft October 1, 1997 Preliminary 1.0 Finalize - Change operation voltage: Vcc=2.3~3.3V Vcc=2.3~2.7V - Release operating current ICC=2mA 5mA ICC1 Read/Write=3/15mA 5/20mA August 27, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM 128K x16 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology : TFT * Organization :128Kx16 * Power Supply Voltage KM616S2000 Family : 2.3~2.7V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : 44-TSOP2 -400F The KM616S2000 families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and small package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Produc Family Operating Temperature KM616S2000L-L Commercial(0~70C) KM616S2000LI-L Industrial(-40~85C) Vcc Range Speed(ns) 2.3~2.7V 1201)/150ns Standby (ISB1, Max) 10A Operating (ICC2,Max) PKG Type 45mA 44-TSOP2-F 15A 1. The parameter is measured with 30pF test load. PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward Function CS Chip Select Input OE Output Enable Input WE Write Enable Input FUNCTIONAL BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Clk gen. A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 N.C Name Precharge circuit. A0 Vcc Vss A1 A2 A3 Row select A4 A5 Memory array 1024 rows 128x16 columns A6 A7 A8 A16 I/O1~I/O8 Data cont I/O Circuit Column select Data cont I/O9~I/O16 Data cont Function A9 A10 A11 A12 A13 A14 A15 I/O1~I/O16 Data Inputs/Outputs A0~A16 Vcc Address Inputs Power CS OE UB Upper Block Select Input Vss Ground LB Lower Block Select Input N.C No Connection UB Control logic LB WE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM PRODUCT LIST Commercial Temperature Product(0~70C) Part Name Industrial Temperature Products(-40~85C) Function KM616S2000LT-12L KM616S2000LT-15L Part Name 44-TSOP2, 120ns, 2.3~2.7V, LL 44-TSOP2, 150ns, 2.3~2.7V, LL KM616S2000LTI-12L KM616S2000LTI-15L Function 44-TSOP2, 120ns, 2.3~2.7V, LL 44-TSOP2, 150ns, 2.3~2.7V, LL Note : LL - Low Low Standby Current FUNCTIONAL DESCRIPTION CS OE H X L H WE 1) X 1) H LB UB I/O1~8 I/O9~16 1) 1) X High-Z X1) X1) High-Z X Mode Power High-Z Deselected Standby High-Z Output Disabled Active L X H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active X 1) L L H Din High-Z Lower Byte Write Active L X 1) L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active L 1) X 1) 1. X means dont care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 C - 0 to 70 C KM616S2000L -40 to 85 C KM616S2000LI 260C, 10sec (Lead Only) - - Voltage on any pin relative to Vss Storage temperature Operating Temperature Soldering temperature and time TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit 2.3 2.5 2.7 V 0 0 0 Supply voltage Vcc KM616S2000 Family Ground Vss All Family Input high voltage VIH KM616S2000 Family 2.0 - Vcc+0.3 Input low voltage VIL KM616S2000 Family -0.33) - 0.6 V V 2) V Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : Vcc+1.0V in case of pulse width 20ns 3. Undershoot : -1.0V in case of pulse width 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIN=Vss to Vcc -1 - 1 A Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 5 mA ICC1 Cycle time=1s, 100% duty IIO=0mA, CS0.2V, VIN0.2V or VINVcc-0.2V Read - - 5 Write - - 20 - - 45 mA - - 0.4 V 2.0 - - V Input leakage current Average operating current Symbol Test Conditions ICC2 Cycle time=Min, 100% duty Output low voltage VOL IOL=0.5mA at 2.3~2.7V Output high voltage VOH IOH=-0.5mA mA Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA Standby Current (CMOS) ISB1 CSVcc-0.2V, Other inputs=0~Vcc - - 101) A 1. KM616S2000I Family =15A Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. Refer to AC CHARACTERISTICS AC CHARACTERISTICS (Vcc=2.3~2.7V, KM616S2000 Family : TA=0 to 70C, KM616S2000I Family : TA=-40 to 85C) Speed Bins Parameter List Symbol 120 ns Min Read Write Units 150ns 1) Max Min Max Read cycle time tRC 120 - 150 - ns Address access time tAA - 120 - 150 ns Chip select to output tCO - 120 - 150 ns Output enable to valid output tOE - 60 - 75 ns Byte enable to valid output tBA - 60 - 75 ns Chip select to low-Z output tLZ 20 - 20 - ns Output enable to low-Z output tOLZ 10 - 10 - ns UB, LB enable to low-Z output tBLZ 10 - 10 - ns Output hold from address change tOH 15 - 15 - ns Chip disable to high-Z output tHZ - 35 0 40 ns Output disable to high-Z output tOHZ - 35 0 40 ns UB, LB disable to high-Z output tBHZ - 35 0 40 ns Write cycle time tWC 120 - 150 - ns Chip select to end of write tCW 100 - 120 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 100 - 120 - ns UB, LB valid to end of write tBW 100 - 120 - ns Write pulse width tWP 80 - 100 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 30 0 40 ns Data to write time overlap tDW 50 - 60 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns 1. The parameter is measured with 30pF test load. DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol Test Condition VDR CSVcc-0.2V Vcc=2.0V, CSVcc-0.2V Data retention current IDR Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 2.7 V A - - 10 0 - - 5 - - ms Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 2.3V 2.2V VDR CSVCC - 0.2V CS GND Revision 1.0 August 1998 KM616S2000 Family CMOS SRAM PACKAGE DIMENSIONS Unit : millimeter(inch) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.410.10 0.7250.004 0 + 0.1 5 - 0.0 04 + 0.0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 1.0 August 1998