ADC08200
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SNAS136M –APRIL 2001–REVISED MARCH 2013
ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-
and-Hold
Check for Samples: ADC08200
1FEATURES DESCRIPTION
The ADC08200 is a low-power, 8-bit, monolithic
2• Single-Ended Input analog-to-digital converter with an on-chip track-and-
• Internal Sample-and-Hold Function hold circuit. Optimized for low cost, low power, small
• Low Voltage (Single +3V) Operation size and ease of use, this product operates at
conversion rates up to 230 Msps while consuming
• Small Package just 1.05 mW per MHz of clock frequency, or 210 mW
• Power-Down Feature at 200 Msps. Raising the PD pin puts the ADC08200
into a Power Down mode where it consumes about 1
KEY SPECIFICATIONS mW.
• Resolution 8 Bits The unique architecture achieves 7.3 Effective Bits
• Maximum sampling frequency 200 Msps (min) with 50 MHz input frequency. The ADC08200 is
resistant to latch-up and the outputs are short-circuit
• DNL ±0.4 LSB (typ) proof. The top and bottom of the ADC08200's
• ENOB (fIN = 50 MHz) 7.3 bits (typ) reference ladder are available for connections,
• THD (fIN = 50 MHz) 61 dB (typ) enabling a wide range of input possibilities. The
digital outputs are TTL/CMOS compatible with a
• Power Consumption separate output power supply pin to support
– Operating 1.05 mW/Msps (typ) interfacing with 3V or 2.5V logic. The digital inputs
– Power Down 1 mW (typ) (CLK and PD) are TTL/CMOS compatible. The output
data format is straight binary.
APPLICATIONS The ADC08200 is offered in a 24-lead TSSOP
• Flat Panel Displays package and, while specified over the industrial
temperature range of −40°C to +85°C, it will function
• Projection Systems over the to −40°C to +105°C temperature range.
• Set-Top Boxes
• Battery-Powered Instruments
• Communications
• Medical Imaging
• Astronomy
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VRT
VRM
256
1
SWITCHES
CLOCK
GEN
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
CLK
17
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
VA(pin 18)
AGND
VIN
8
8
OUTPUT
DRIVERS
MUX 8 8 DATA
OUT
PD
DR VD
DR GND
(pin 17)
VRB
VIN GND
ADC08200
SNAS136M –APRIL 2001–REVISED MARCH 2013
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Block Diagram
Pin Configuration
Figure 1. 24-Lead TSSOP
See PW Package
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VD
DGND
ADC08200
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Equivalent Circuit Description
6 VIN Analog signal input. Conversion range is VRB to VRT.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and
3 VRT VRB inputs define the VIN conversion range. Bypass well. See
THE ANALOG INPUT for more information.
Mid-point of the reference ladder. This pin should be bypassed
9 VRM to a quiet point in the ground plane with a 0.1 µF capacitor.
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 0.5V).
10 VRB Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
Power Down input. When this pin is high, the converter is in
23 PD the Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. VIN is sampled on
24 CLK the rising edge of CLK input.
13 thru 16 Conversion data digital Output pins. D0 is the LSB, D7 is the
and D0–D7 MSB. Valid data is output just after the rising edge of the CLK
19 thru 22 input.
7 VIN GND Reference ground for the single-ended analog input, VIN.
Positive analog supply pin. Connect to a quiet voltage source
of +3V. VAshould be bypassed with a 0.1 µF ceramic chip
1, 4, 12 VAcapacitor for each pin, plus one 10 µF capacitor. See POWER
SUPPLY CONSIDERATIONS for more information.
Power supply for the output drivers. If connected to VA,
18 VDR decouple well from VA.
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Supply Voltage (VA) 3.8V
Driver Supply Voltage (VDR) VA+0.3V
Voltage on Any Input or Output Pin −0.3V to VA
Reference Voltage (VRT, VRB) VAto AGND
CLK, PD Voltage Range −0.05V to
(VA+ 0.05V)
Input Current at Any Pin (4) ±25 mA
Package Input Current (4) ±50 mA
Power Dissipation at TA= 25°C See (5)
ESD Susceptibility (6) Human Body Model 2500V
Machine Model 200V
Soldering Temperature, Infrared,
10 seconds (7) 235°C
Storage Temperature −65°C to +150°C
(1) All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VAor VDR), the
current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can
safely exceed the power supplies with an input current of 25 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA) / θJA. The values for maximum power dissipation listed above will be reached only when this device is operated
in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO
Ohms.
(7) See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability” (SNOA742).
Operating Ratings (1)(2)
Operating Temperature Range −40°C ≤TA≤+105°C
Supply Voltage (VA) +2.7V to +3.6V
Driver Supply Voltage (VDR) +2.4V to VA
Ground Difference |GND - DR GND| 0V to 300 mV
Upper Reference Voltage (VRT) 0.5V to (VA−0.3V)
Lower Reference Voltage (VRB) 0V to (VRT −0.5V)
VIN Voltage Range VRB to VRT
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package θJA
24-Lead TSSOP 92°C/W
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Converter Electrical Characteristics
The following specifications apply for VA= VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL= 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ= 25°C (1)(2)(3)
Units
Symbol Parameter Conditions Typical (4) Limits (4) (Limits)
DC ACCURACY
+1.0 +1.9 LSB (max)
INL Integral Non-Linearity −0.3 −1.2 LSB (min)
DNL Differential Non-Linearity ±0.4 ±0.95 LSB (max)
Missing Codes 0(max)
FSE Full Scale Error 36 50 mV (max)
VOFF Zero Scale Offset Error 46 60 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
VRB V (min)
VIN Input Voltage 1.6 VRT V (max)
(CLK LOW) 3 pF
CIN VIN Input Capacitance VIN = 0.75V +0.5 Vrms (CLK HIGH) 4 pF
RIN RIN Input Resistance >1 MΩ
BW Full Power Bandwidth 500 MHz
VAV (max)
VRT Top Reference Voltage 1.9 0.5 V (min)
VRT −0.5 V (max)
VRB Bottom Reference Voltage 0.3 0V (min)
1.0 V (min)
VRT - VRB Reference Voltage Delta 1.6 2.3 V (max)
120 Ω(min)
RREF Reference Ladder Resistance VRT to VRB 160 200 Ω(max)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH Logical High Input Voltage VDR = VA= 3.6V 2.0 V (min)
VIL Logical Low Input Voltage VDR = VA= 2.7V 0.8 V (max)
IIH Logical High Input Current VIH = VDR = VA= 3.6V 10 nA
IIL Logical Low Input Current VIL = 0V, VDR = VA= 2.7V −50 nA
CIN Logic Input Capacitance 3 pF
(1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only
and are not ensured.
(2) The analog inputs are protected as shown below. Input voltage magnitudes up to VA+ 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV.
For example, if VAis 2.7VDC the full-scale input voltage must be ≤2.8VDC to ensure accurate conversions.
(3) To ensure accuracy, it is required that VAand VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(4) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specifid to TI's AOQL (Average Outgoing
Quality Level).
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Converter Electrical Characteristics (continued)
The following specifications apply for VA= VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL= 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ= 25°C (1)(2)(3)
Units
Symbol Parameter Conditions Typical (4) Limits (4) (Limits)
DIGITAL OUTPUT CHARACTERISTICS
VOH High Level Output Voltage VA= VDR = 2.7V, IOH =−400 µA 2.6 2.4 V (min)
VOL Low Level Output Voltage VA= VDR = 2.7V, IOL = 1.0 mA 0.4 0.5 V (max)
DYNAMIC PERFORMANCE
fIN = 4 MHz, VIN = FS −0.25 dB 7.5 Bits
fIN = 20 MHz, VIN = FS −0.25 dB 7.4 Bits
ENOB Effective Number of Bits fIN = 50 MHz, VIN = FS −0.25 dB 7.3 6.9 Bits (min)
fIN = 70 MHz, VIN = FS −0.25 dB 7.2 Bits
fIN = 100 MHz, VIN = FS −0.25 dB 7.0 Bits
fIN = 4 MHz, VIN = FS −0.25 dB 47 dB
fIN = 20 MHz, VIN = FS −0.25 dB 46 dB
SINAD Signal-to-Noise & Distortion fIN = 50 MHz, VIN = FS −0.25 dB 46 43.3 dB (min)
fIN = 70 MHz, VIN = FS −0.25 dB 45 dB
fIN = 100 MHz, VIN = FS −0.25 dB 44 dB
fIN = 4 MHz, VIN = FS −0.25 dB 47 dB
fIN = 20 MHz, VIN = FS −0.25 dB 46 dB
SNR Signal-to-Noise Ratio fIN = 50 MHz, VIN = FS −0.25 dB 46 43.4 dB (min)
fIN = 70 MHz, VIN = FS −0.25 dB 45 dB
fIN = 100 MHz, VIN = FS −0.25 dB 44 dB
fIN = 4 MHz, VIN = FS −0.25 dB 60 dBc
fIN = 20 MHz, VIN = FS −0.25 dB 58 dBc
SFDR Spurious Free Dynamic Range fIN = 50 MHz, VIN = FS −0.25 dB 60 dBc
fIN = 70 MHz, VIN = FS −0.25 dB 57 dBc
fIN = 100 MHz, VIN = FS −0.25 dB 54 dBc
fIN = 4 MHz, VIN = FS −0.25 dB −60 dBc
fIN = 20 MHz, VIN = FS −0.25 dB −58 dBc
THD Total Harmonic Distortion fIN = 50 MHz, VIN = FS −0.25 dB −60 dBc
fIN = 70 MHz, VIN = FS −0.25 dB -56 dBc
fIN = 100 MHz, VIN = FS −0.25 dB −53 dBc
fIN = 4 MHz, VIN = FS −0.25 dB −66 dBc
fIN = 20 MHz, VIN = FS −0.25 dB -68 dBc
HD2 2nd Harmonic Distortion fIN = 50 MHz, VIN = FS −0.25 dB −66 dBc
fIN = 70 MHz, VIN = FS −0.25 dB -60 dBc
fIN = 100 MHz, VIN = FS −0.25 dB −55 dBc
fIN = 4 MHz, VIN = FS −0.25 dB −72 dBc
fIN = 20 MHz, VIN = FS −0.25 dB −58 dBc
HD3 3rd Harmonic Distortion fIN = 50 MHz, VIN = FS −0.25 dB −72 dBc
fIN = 70 MHz, VIN = FS −0.25 dB -58 dBc
fIN = 100 MHz, VIN = FS −0.25 dB −60 dBc
f1= 11 MHz, VIN = FS −6.25 dB
IMD Intermodulation Distortion -55 dBc
f2= 12 MHz, VIN = FS −6.25 dB
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Converter Electrical Characteristics (continued)
The following specifications apply for VA= VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL= 5 pF, fCLK = 200 MHz at 50% duty
cycle. Boldface limits apply for TJ= TMIN to TMAX: all other limits TJ= 25°C (1)(2)(3)
Units
Symbol Parameter Conditions Typical (4) Limits (4) (Limits)
POWER SUPPLY CHARACTERISTICS
DC Input 69.75 86 mA (max)
IAAnalog Supply Current fIN = 10 MHz, VIN = FS −3 dB 69.75 mA
IDR Output Driver Supply Current DC Input, PD = Low 0.25 0.6 mA (max)
DC Input, PD = Low 70 86.6 mA (max)
IA+ IDR Total Operating Current CLK Low, PD = Hi 0.3 mA
DC Input, Excluding Reference 210 260 mW (max)
PC Power Consumption CLK Low, PD = Hi 1 mW
FSE change with 2.7V to 3.3V change in
PSRR1Power Supply Rejection Ratio 54 dB
VA
SNR reduction with 200 mV at 1MHz on
PSRR2Power Supply Rejection Ratio 45 dB
supply
AC ELECTRICAL CHARACTERISTICS
fC1 Maximum Conversion Rate 230 200 MHz (min)
fC2 Minimum Conversion Rate 10 MHz
tCL Minimum Clock Low Time 0.87 1.0 ns (min)
tCH Minimum Clock High Time 0.65 0.75 ns (min)
CLK to Data Invalid, VA= 3.3V to 3.6V, tA
Output Hold Time, Output Falling (5) 2.4 3.3 ns (max)
=−40°C to +105°C, CL= 8 pF
tOH CLK to Data Invalid, VA= 3.3V to 3.6V, tA
Output Hold Time, Output Rising (5) 1.9 2.5 ns (max)
=−40°C to +105°C, CL= 8 pF
2.4 ns (min)
CLK to Data Transition, VA= 3.3V to
Output Delay, Output Falling (5) 3.9
3.6V, VA=−40°C to +105°C, CL= 8 pF 5.1 ns (max)
tOD 2.4 ns (min)
CLK to Data Transition, VA= 3.3V to
Output Delay, Output Rising (5) 3.3
3.6V, tA=−40°C to +105°C, CL= 8 pF 4.0 ns (max)
Output Falling, VA= 3.3V, CL= 8 pF, 0.73 V/ns
tA=−40°C to +105°C
tSLEW Output Slew Rate(6) Output Rising, VA= 3.3V, CL= 8 pF, 0.88 V/ns
tA=−40°C to +105°C
Pipeline Delay (Latency) 6 Clock Cycles
tAD Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns
tAJ Aperture Jitter 2 ps rms
(5) These specifications are ensured by design and not tested.
(6) Typical output slew rate is based upon the maximum tOD and tOH figures.
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Specification Definitions
APERTURE (SAMPLING) DELAYis that time required after the rise of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode
tAD after the clock goes high.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 200 Msps with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL-SCALE ERRORis a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is
defined as:
Vmax + 1.5 LSB – VRT
where
• Vmax is the voltage at which the transition to the maximum (full scale) code occurs (1)
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code
value. The end point test method is used. Measured at 200 Msps with a ramp input.
INTERMODULATION DISTORTION (IMD)is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the
power in the second and third order intermodulation products to the power in one of the original
frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at
the output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that
data is presented to the output driver stage. New data is available at every clock cycle, but the data lags
the conversion by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08200, PSRR1 is the ratio of the change in Full-Scale Error that results from a
change in the DC power supply voltage, expressed in dB. PSRR2 is a measure of how well an AC signal
riding upon the power supply is rejected from the output and is here defined as
where
• SNR0 is the SNR measured with no noise or signal on the supply line
• SNR1 is the SNR measured with a 1 MHz, 200 mVP-P signal riding upon the supply lines (2)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
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THD = 20 x log + . . . + AAf22
f102
Af12
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SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR)is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in
the output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
where
• Af1 is the RMS power of the fundamental (output) frequency
• Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum (3)
ZERO SCALE OFFSET ERRORis the error in the input voltage required to cause the first code transition. It is
defined as
VOFF = VZT −VRB
where
• VZT is the first code transition input voltage (4)
Timing Diagram
Figure 2. ADC08200 Timing Diagram
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Typical Performance Characteristics
VA= VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated
INL
vs.
INL Temperature
Figure 3. Figure 4.
INL INL
vs. vs.
Supply Voltage Sample Rate
Figure 5. Figure 6.
DNL
vs.
DNL Temperature
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
VA= VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated
DNL DNL
vs. vs.
Supply Voltage Sample Rate
Figure 9. Figure 10.
SNR SNR
vs. vs.
Temperature Supply Voltage
Figure 11. Figure 12.
SNR SNR
vs. vs.
Sample Rate Input Frequency
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
VA= VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated
SNR Distortion
vs. vs.
Clock Duty Cycle Temperature
Figure 15. Figure 16.
Distortion Distortion
vs. vs.
Supply Voltage Sample Rate
Figure 17. Figure 18.
Distortion Distortion
vs. vs.
Input Frequency Clock Duty Cycle
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
VA= VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated
SINAD/ENOB SINAD/ENOB
vs. vs.
Temperature Supply Voltage
Figure 21. Figure 22.
SINAD/ENOB SINAD/ENOB
vs. vs.
Sample Rate Input Frequency
Figure 23. Figure 24.
SINAD/ENOB Power Consumption
vs. vs.
Clock Duty Cycle Sample Rate
Figure 25. Figure 26.
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Typical Performance Characteristics (continued)
VA= VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated
Spectral Response @ fIN = 50 MHz Spectral Response @ fIN = 76 MHz
Figure 27. Figure 28.
Spectral Response @ fIN = 99 MHz Intermodulation Distortion
Figure 29. Figure 30.
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8 11
AGND
ADC08200
D7 13
D6 14
D5 15
D0 22
D1 21
D2 20
D3 19
D4 16
6
3
+3V
110
517
DR GND
10
VRT
VIN
10 PF+
220
2
VRB
24
CLK
0.1 PF
9
23 PD
0.1 PF
10 PF
+
+
1 4 18
0.1 PF
10 PF
DR VD
VA
Choke
0.1 PF
10 PF
+
12
+3V
1%
1%
0.1 PF
1.5V,
nominal
7VIN GND
ADC08200
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FUNCTIONAL DESCRIPTION
The ADC08200 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and
beyond 100 MHz.
The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages
below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word
to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08200 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital
outputs 6 clock cycles plus tOD later. The ADC08200 will convert as long as the clock signal is present. The
output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes just 1.4 mW . Holding the clock input low will further reduce the power consumption in the
power down mode to about 1 mW.
APPLICATIONS INFORMATION
REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in the Operating Ratings Table. Any device used to drive the reference pins should
be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin to maintain the
desired voltages.
Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for
some applications.
Figure 31. Simple, low component count reference biasing.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADC08200
8 11
AGND
ADC08200
D7 13
D6 14
D5 15
D0 22
D1 21
D2 20
D3 19
D4 16
6
4.7k
3
0.1 PF
309:
+3V
470:
517
DR GND
10
VRT
VIN
1/2
LM8272
-
+1
8
4
3
2
10 PF
+
+3V
0.01 PF
1 PF
1/2
LM8272
+
-
6
5
1.62k
0.01 PF
7
604:
LM4040-2.5
2
0.1 PF
10 PF
+
+
124 18
0.1 PF
10 PF
DR VD
VA
Choke
1
VRB
24
CLK
0.1 PF
9
23 PD
0.1 PF
7VIN GND
1 PF
4.7k
1 PF
ADC08200
SNAS136M –APRIL 2001–REVISED MARCH 2013
www.ti.com
The reference bias circuit of Figure 31 is very simple and the performance is adequate for many applications.
However, circuit tolerances will lead to a wide reference voltage range. Better reference stability can be achieved
by driving the reference pins with low impedance sources.
The circuit of Figure 32 will allow a more accurate setting of the reference voltages. The upper amplifier must be
able to source the reference current as determined by the value of the reference resistor and the value of (VRT −
VRB). The lower amplifier must be able to sink this reference current. Both amplifiers should be stable with a
capacitive load. The LM8272 was chosen because of its rail-to-rail input and output capability, its high current
output and its ability to drive large capacitive loads.
The divider resistors at the inputs to the amplifiers could be changed to suit the application reference voltage
needs, or the divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder
(VRB) may be returned to ground if the minimum input signal excursion is 0V.
VRT should always be more positive than VRB by the minimum VRT - VRB difference in Electrical Characteristics to
minimize noise. While VRT may be as high as the VAsupply voltage and VRB may be as low as ground, the
difference between these two voltages (VRT −VRB) should not exceed 2.3V to prevent waveform distortion.
The VRM pin is the center of the reference ladder and should be bypassed to a quiet point in the ground plane
with a 0.1 µF capacitor. DO NOT leave this pin open and DO NOT load this pin with more than 10µA.
Figure 32. Driving the reference to force desired values requires driving with a low impedance source.
THE ANALOG INPUT
The analog input of the ADC08200 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of
the analog input causes current spikes at the input that result in voltage spikes there. Any amplifier used to drive
the analog input must be able to settle within the clock high time. The LMH6702 and the LMH6628 have been
found to be good amplifiers to drive the ADC08200.
16 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: ADC08200
22
+
-200
12
240
47
100
10 pF
Signal
Input
8 11
AGND
ADC08200 D7 13
D6 14
D5 15
D0 22
D1 21
D2 20
D3 19
D4 16
6
3
7
10
VRT
5
0.1 PF
10 PF
+
+
124 18
0.1 PF
10 PF
DR VD
VA
Choke
1
VRB
24
CLK
9
23 PD
+3V
LMH6702
2
17
DR GND
+5V
-5V
0.1 PF
0.1 PF
10
Gain
Adjust
4.7k
1k1k
0.33 PF
+3V
*
*
Offset
Adjust
*
*URXQGFRQQHFWLRQVPDUNHGZLWK³*´
should enter the ground plane at a
common point
VIN
7VIN GND
VRM
ADC08200
www.ti.com
SNAS136M –APRIL 2001–REVISED MARCH 2013
Figure 33 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some
gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than
with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a
higher gain, as shown in Figure 33.
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 18Ωand 47Ωand the
capacitor value chose according to the formula
(5)
The value of "C" in the formula above should include the ADC input capacitance when the clock is high
This will provide optimum SNR performance for Nyquist applications. Best THD performance is realized when the
capacitor and resistor values are both zero, but this would compromise SNR and SINAD performance. Generally,
the capacitor should not be added for undersampling applications.
The circuit of Figure 33 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may result in signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.
Full scale and offset adjustments may also be made by adjusting VRT and VRB, perhaps with the aid of a pair of
DACs.
Figure 33. The input amplifier should incorporate some gain for best performance (see text).
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADC08200
ADC08200
SNAS136M –APRIL 2001–REVISED MARCH 2013
www.ti.com
While a single voltage source is recommended for the VAand VDR supplies of the ADC08200, these supply pins
should be well isolated from each other to prevent any digital noise from being coupled into the analog portions
of the ADC. A choke or 27Ωresistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08200 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
analog circuitry.
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08200 power pins.
THE DIGITAL INPUT PINS
The ADC08200 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08200 into a low power mode where power consumption is
reduced to about 1.4 mW with the clock running, or to about 1 mW with the clock held low. Output data is valid
and accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
high.
The ADC08200 Clock
Although the ADC08200 is tested and its performance is ensured with a 200 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 230 MHz.
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08200 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 200 Msps, ADC08200
performance is typically maintained with clock high and low times of 0.65 ns and 0.87 ns, respectively,
corresponding to a clock duty cycle range of 13% to 82.5% with a 200 MHz clock. Note that minimum low and
high times may not be simultaneously asserted.
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line if the
clock line is longer than
where
• tris the clock rise time
• tprop is the propagation rate of the signal along the trace
• (6)
Typical tprop is about 150 ps/inch (59 ps/cm) on FR-4 board material.
If the clock source is used to drive more than just the ADC08200, the CLOCK pin should be a.c. terminated with
a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and
the capacitor value is
where
• tPD is the signal propagation rate down the clock line
• "L" is the line length
• ZOis the characteristic impedance of the clock line (7)
18 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: ADC08200
RC
LMH6702
ADC Clock
Source
Locate Clock Source
near ADC clock pin
RF
RIN
Single
Ground
Plane
ADC
08200 Locate power supply on
the digital side of the
ADC
Locate driving amplifier
near ADC input pin
ADC08200
www.ti.com
SNAS136M –APRIL 2001–REVISED MARCH 2013
This termination should be located as close as possible to, but within one centimeter of, the ADC08200 clock pin.
Further, this termination should be close to but beyond the ADC08200 clock pin as seen from the clock source.
Typical tprop is about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes
where
• L is the length of the clock line in inches (8)
This termination should be located as close as possible to, but within one centimeter of, the ADC08200 clock pin.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined
analog and digital ground plane should be used.
Coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance that may seem impossible to isolate and remedy. The solution is to keep all lines separated from
each other by at least six times the height above the reference plane, and to keep the analog circuitry well
separated from the digital circuitry.
The DR GND connection to the ground plane should not use the same feedthrough used by other ground
connections.
High power digital components should not be located on or near a straight line between the ADC or any linear
component and the power supply area as the resulting common return current path could cause fluctuation in the
analog input “ground” return of the ADC.
Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog
path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should
be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be
avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies
is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be
connected to a very clean point in the ground plane.
Figure 34. Layout Example
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADC08200
ADC08200
SNAS136M –APRIL 2001–REVISED MARCH 2013
www.ti.com
Figure 34 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed together away from any digital components.
DYNAMIC PERFORMANCE
The ADC08200 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the
clock source driving the CLK input must exhibit less than 2 ps (rms) of jitter. For best a.c. performance, isolating
the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See
Figure 35.
It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other
signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the
analog path.
Figure 35. Isolating the ADC Clock from Digital Circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on
even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits
(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ωresistor in
series with the offending digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC08200. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the
digital data outputs (with a 74AF541, for example) may be necessary if the data bus capacitance exceeds 5 pF.
Dynamic performance can also be improved by adding 47Ωto 56Ωseries resistors at each digital output,
reducing the energy coupled back into the converter input pins.
Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, the
capacitance seen at the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is
more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device.
Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the
ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source
sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with
devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of
dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally
inadequate as a clock source.
20 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: ADC08200
ADC08200
www.ti.com
SNAS136M –APRIL 2001–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision L (March 2013) to Revision M Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: ADC08200
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC08200CIMT ACTIVE TSSOP PW 24 61 Non-RoHS
& Green Call TI Call TI -40 to 85 ADC08200
CIMT
ADC08200CIMT/NOPB ACTIVE TSSOP PW 24 61 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ADC08200
CIMT
ADC08200CIMTX/NOPB ACTIVE TSSOP PW 24 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ADC08200
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC08200CIMTX/NOPB TSSOP PW 24 2500 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC08200CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
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