Data Sheet
©2008 CADEKA Microcircuits LLC www.cadeka.com
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
Comlinear® CLC2000
High Output Current Dual Amplier
Amplify the Human Experience
FEATURES
n 9.4Vpp output drive into RL= 25
Ω
n Using both ampliers, 18.8Vpp
differential output drive into RL= 25
Ω
n ±200mA @ Vo = 9.4Vpp
n 0.009%/0.06˚ differential gain/
phase error
n 250MHz -3dB bandwidth at G = 2
n 510MHz -3dB bandwidth at G = 1
n 210V/μs slew rate
n 4.5nV/
√
Hz input voltage noise
n 2.7pA/
√
Hz input current noise
n 7mA supply current
n Fully specied at 5V and 12V supplies
n Pb-free SOIC-8 package
APPLICATIONS
n ADSL PCI modem cards
n ADSL external modems
n Cable drivers
n Video line driver
n Twisted pair driver/receiver
General Description
The
Comlinear
CLC2000 is a dual voltage feedback amplier that offers
±200mA of output current at 9.4Vpp. The CLC2000 is capable of driving
signals to within 1V of the power rails. When connected as a differential line
driver, the dual amplier drives signals up to 18.8Vpp into a 25Ω load, which
supports the peak upstream power levels for upstream full-rate ADSL CPE
applications.
The
Comlinear
CLC2000 can operate from single or dual supplies from 5V to
12V. It consumes only 7mA of supply current per channel. The combination
of wide bandwidth, low noise, low distortion, and high output current capabil-
ity makes the CLC2000 ideally suited for Customer Premise ADSL or video line
driving applications.
Typical Application - ADSL Application
Ordering Information
Part Number Package Pb-Free Operating Temperature Range Packaging Method
CLC2000ISO8X SOIC-8 Yes -40°C to +85°C Reel
CLC2000ISO8 SOIC-8 Yes -40°C to +85°C Rail
Moisture sensitivity level for all parts is MSL-1.
+
VIN
Vo+
1:2
Vo-
Ro+=12.5Ω
RL=100Ω
Ro-=12.5Ω
1/2
CLC2000
1/2
CLC2000
Rg
Rf+
-
Rf-
VOUT
-Vs
+Vs
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 2
CLC2000 Pin Assignments
Pin No. Pin Name Description
1 OUT1 Output, channel 1
2 -IN1 Negative input, channel 1
3 +IN1 Positive input, channel 1
4-VSNegative supply
5 +IN2 Positive input, channel 2
6 -IN2 Negative input, channel 2
7 OUT2 Output, channel 2
8 +VSPositive supply
CLC2000 Pin Conguration
2
3
45
6
7
8
OUT2
+IN1 -IN2
+IN2
1
-IN1
OUT1
-V
S
+V
S
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 3
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should
not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device func-
tion. The information contained in the Electrical Characteristics tables and Typical Performance plots reect the operating
conditions noted on the tables and plots.
Parameter Min Max Unit
Supply Voltage 0 ±7 or 14 V
Input Voltage Range -Vs -0.5V +Vs +0.5V V
Reliability Information
Parameter Min Typ Max Unit
Junction Temperature 150 °C
Storage Temperature Range -65 150 °C
Lead Temperature (Soldering, 10s) 260 °C
Package Thermal Resistance
8-Lead SOIC 100 °C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
ESD Protection
Product SOIC-8
Human Body Model (HBM) 2.5kV
Charged Device Model (CDM) 2kV
Recommended Operating Conditions
Parameter Min Typ Max Unit
Operating Temperature Range -40 +85 °C
Supply Voltage Range ±2.5 ±6.5 V
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 4
Electrical Characteristics
TA = 25°C, Vs = 5V, Rf = Rg = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
UGBW -3dB Bandwidth G = +1, VOUT = 0.2Vpp, Rf = 0 422 MHz
BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 236 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 68 MHz
BW0.1dB 0.1dB Gain Flatness G = +2, VOUT = 0.2Vpp 77 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 1V step; (10% to 90%) 3.7 ns
tSSettling Time to 0.1% VOUT = 2V step 20 ns
OS Overshoot VOUT = 0.2V step 6 %
SR Slew Rate VOUT = 2V step 200 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion
2Vpp, 100KHz, RL = 25Ω -83 dBc
2Vpp, 1MHz, RL = 100Ω -85 dBc
HD3 3rd Harmonic Distortion
2Vpp, 100KHz, RL = 25Ω -86 dBc
2Vpp, 1MHz, RL = 100Ω -82 dBc
DGDifferential Gain NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.01 %
DPDifferential Phase NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.05 °
enInput Voltage Noise > 1MHz 4.2 nV/√Hz
inInput Current Noise > 1MHz 2.7 pA/√Hz
XTALK Crosstalk Channel-to-channel 5MHz -63 dB
DC Performance
VIO Input Offset Voltage 0.3 mV
dVIO Average Drift 0.383 µV/°C
IIO Input Offset Current 0.2 µA
IbInput Bias Current 10 µA
dIbni Average Drift 2.5 nA/°C
PSRR Power Supply Rejection Ratio DC 81 dB
AOL Open-Loop Gain RL = 25Ω 76 dB
ISSupply Current per channel 6.75 mA
Input Characteristics
RIN Input Resistance Non-inverting 2.5 MΩ
CIN Input Capacitance 1 pF
CMIR Common Mode Input Range 0.4 to
4.6 V
CMRR Common Mode Rejection Ratio DC 80 dB
Output Characteristics
ROOutput Resistance Closed Loop, DC 0.01 Ω
VOUT Output Voltage Swing
RL = 25Ω 0.95 to
4.05 V
RL = 1kΩ 0.75 to
4.25 V
ISC Short-Circuit Output Current VOUT = VS / 2 1000 mA
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 5
Electrical Characteristics
TA = 25°C, Vs = 12V, Rf = Rg = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
UGBW -3dB Bandwidth G = +1, VOUT = 0.2Vpp, Rf = 0 510 MHz
BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 250 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 4Vpp 35 MHz
BW0.1dB 0.1dB Gain Flatness G = +2, VOUT = 0.2Vpp 32 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 4V step; (10% to 90%) 13.3 ns
tSSettling Time to 0.1% VOUT = 2V step 20 ns
OS Overshoot VOUT = 0.2V step 2 %
SR Slew Rate VOUT = 4V step 210 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion
2Vpp, 100KHz, RL = 25Ω -84 dBc
2Vpp, 1MHz, RL = 100Ω -86 dBc
8.4Vpp, 100KHz, RL = 25Ω -63 dBc
8.4Vpp, 1MHz, RL = 100Ω -82 dBc
HD3 3rd Harmonic Distortion
2Vpp, 100KHz, RL = 25Ω -88 dBc
2Vpp, 1MHz, RL = 100Ω -80 dBc
8.4Vpp, 100KHz, RL = 25Ω -63 dBc
8.4Vpp, 1MHz, RL = 100Ω -83 dBc
DGDifferential Gain NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.009 %
DPDifferential Phase NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.06 °
enInput Voltage Noise > 1MHz 4.5 nV/√Hz
inInput Current Noise > 1MHz 2.7 pA/√Hz
XTALK Crosstalk Channel-to-channel 5MHz -62 dB
DC Performance
VIO Input Offset Voltage(1) -6 0.3 6 mV
dVIO Average Drift 0.383 µV/°C
IIO Input Offset Current(1) -2 0.2 2 µA
IbInput Bias Current(1) 10 20 µA
dIbni Average Drift 2.5 nA/°C
PSRR Power Supply Rejection Ratio(1) DC 73 81 dB
AOL Open-Loop Gain RL = 25 76 dB
ISSupply Current(1) per channel 7 12 mA
Input Characteristics
RIN Input Resistance Non-inverting 2.5 MΩ
CIN Input Capacitance 1 pF
CMIR Common Mode Input Range 0.6 to
11.4 V
CMRR Common Mode Rejection Ratio(1) DC 70 79 dB
Output Characteristics
ROOutput Resistance Closed Loop, DC 0.01 Ω
VOUT Output Voltage Swing
RL = 25Ω (1) 1.5 1.2 to
10.8 10.5 V
RL = 1kΩ 0.8 to
11.2 V
ISC Short-Circuit Output Current VOUT = VS / 2 1000 mA
Notes:
1. 100% tested at 25°C
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 6
Typical Performance Characteristics
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Frequency Response vs. RLFrequency vs. RL (VS = 5V)
Inverting Frequency Response Inverting Frequency Response (VS=5V)
Non-Inverting Frequency Response Non-Inverting Frequency Response (VS=5V)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = 1
R
f
= 0
G = 2
G = 5
G = 1 0
V
OU T
= 0.2V
pp
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = 1
R
f
= 0
G = 2
G = 5
G = 1 0
V
OU T
= 0.2V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = -1
G = -2
G = -5
G = -10
V
OU T
= 0.2V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = -1
G = -2
G = -5
G = -10
V
OU T
= 0.2V
pp
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
R
L
= 5kΩ
V
OU T
= 0.2V
pp
R
L
= 1kΩ
R
L
= 150Ω
R
L
= 50Ω
R
L
= 25Ω
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
R
L
= 5kΩ
V
OU T
= 0.2V
pp
R
L
= 1kΩ
R
L
= 150Ω
R
L
= 50Ω
R
L
= 25Ω
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 7
Typical Performance Characteristics
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Frequency Response vs. VOUT Frequency Response vs. VOUT (VS = 5V)
Recommended RS vs. CLRecommended RS vs. CL (VS = 5V)
Frequency vs. CLFrequency vs. CL (VS = 5V)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
C
L
= 1000pF
R
s
= 5 Ω
C
L
= 500pF
R
s
= 6 Ω
C
L
= 100pF
R
s
= 1 3 Ω
C
L
= 50pF
R
s
= 2 0 Ω
C
L
= 10pF
R
s
= 3 0 Ω
V
OU T
= 0.2V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
C
L
= 1000pF
R
s
= 5 Ω
C
L
= 500pF
R
s
= 6 Ω
C
L
= 100pF
R
s
= 1 3 Ω
C
L
= 50pF
R
s
= 2 5 Ω
C
L
= 10pF
R
s
= 4 5 Ω
V
OU T
= 0.2V
pp
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
10 100 1000
R
S
(Ω)
C
L
(pf)
V
OU T
= 0.2V
pp
R
S
optimized for <1dB peaking
0
5
10
15
20
25
30
35
40
45
10 100 1000
R
S
(Ω)
V
OU T
= 0.2V
pp
R
S
optimized for <1dB peaking
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
V
OU T
= 1V
pp
V
OU T
= 2V
pp
V
OU T
= 4V
pp
V
OU T
= 5V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
V
OU T
= 1V
pp
V
OU T
= 2V
pp
V
OU T
= 3V
pp
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 8
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Open Loop Transimpendance Gain/Phase vs. Frequency Input Voltage Noise
-3dB Bandwidth vs. Output Voltage -3dB Bandwidth vs. Output Voltage (VS=5V)
Frequency Response vs. Temperature Frequency vs. Temperature (VS = 5V)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
V
OU T
= 0.2V
pp
+ 85degC
-40degC
+ 25degC
V
OU T
= 2V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
+ 85degC
-40degC
+ 25degC
V
OU T
= 0.2V
pp
+ 85degC
-40degC
+ 25degC
V
OU T
= .2V
pp
0
25
50
75
100
125
150
175
200
225
250
275
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
0
25
50
75
100
125
150
175
200
225
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
Open Loop Gain (dB)
Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
-20
80
70
60
Gain
40
20
0
50
30
10
-10
Open Loop Phase (deg)
-200
0
-20
-40
-80
-120
-160
-60
-100
-140
-180
Phase
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
0.0001 0.001 0.01 0.1 1 10 100
0
50
40
30
20
10
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 9
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Differential Gain & Phase AC Coupled Differential Gain & Phase DC Coupled
2nd Harmonic Distortion vs. VOUT 3rd Harmonic Distortion vs. VOUT
2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL
-100
-90
-80
-70
-60
-50
-40
-30
-20
0 5 10 15 20
Distortion (dBc)
Frequency (MHz)
R
L
= 100Ω
V
OU T
= 2V
pp
R
L
= 1kΩ
R
L
= 25Ω
-100
-90
-80
-70
-60
-50
-40
-30
-20
0 5 10 15 20
Distortion (dBc)
Frequency (MHz)
R
L
= 100Ω
V
OU T
= 2V
pp
R
L
= 1kΩ
R
L
= 25Ω
-100
-90
-80
-70
-60
-50
-40
-30
-20
0.5 0.75 11.25 1.5 1.75 22.25 2.5 2.75 3
Distortion (dBc)
Output Amplitude (V
pp
)
10MHz
5MHz
1MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
0.5 0.75 11.25 1.5 1.75 22.25 2.5 2.75 3
Distortion (dBc)
Output Amplitude (V
pp
)
10MHz
5MHz
1MHz
-0.01
-0.0075
-0.005
-0.0025
0
0.0025
0.005
0.0075
0.01
-0 . 7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0 . 7
Diff Gain (%) and Diff Phase (°)
I n p u t V o l t a g e ( V )
DG
R
L
= 150Ω
AC coupled into 220µF
DP
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
-0 . 7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0 . 7
Diff Gain (%) and Diff Phase (°)
I n p u t V o l t a g e ( V )
V
OU T
= 2V
pp
DG
R
L
= 150Ω
DC coupled
DP
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 10
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Differential Gain & Phase AC Coupled (VS=5V) Differential Gain & Phase DC Coupled (VS=5V)
2nd Harmonic Distortion vs. VOUT (VS=5V) 3rd Harmonic Distortion vs. VOUT (VS=5V)
2nd Harmonic Distortion vs. RL (VS=5V) 3rd Harmonic Distortion vs. RL (VS=5V)
-100
-90
-80
-70
-60
-50
-40
-30
-20
0 5 10 15 20
Distortion (dBc)
Frequency (MHz)
R
L
= 25Ω
V
OU T
= 2V
pp
R
L
= 1kΩ
R
L
= 100Ω
-100
-90
-80
-70
-60
-50
-40
-30
-20
0 5 10 15 20
Distortion (dBc)
Frequency (MHz)
R
L
= 25Ω
V
OU T
= 2V
pp
R
L
= 1kΩ
R
L
= 100Ω
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
0.5 0.75 11.25 1.5 1.75 22.25 2.5 2.75 3
Distortion (dBc)
Output Amplitude (Vpp)
10MHz
5MHz
1MHz
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
0.5 0.75 11.25 1.5 1.75 22.25 2.5 2.75 3
Distortion (dBc)
Output Amplitude (V
pp
)
10MHz
5MHz
1MHz
-0.01
-0.0075
-0.005
-0.0025
0
0.0025
0.005
0.0075
0.01
-0.4 -0.3 -0.2 -0.1 00.1 0.2 0.3 0.4
Diff Gain (%) and Diff Phase (°)
I n p u t V o l t a g e ( V )
DG
R
L
= 150Ω
AC coupled into 220µF
DP
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-0.4 -0.2 00.2 0.4
Diff Gain (%) and Diff Phase (°)
I n p u t V o l t a g e ( V )
DG
R
L
= 150Ω
DC coupled
DP
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 11
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Crosstalk vs. Frequency Crosstalk vs. Frequency (VS=5V)
Small Signal Pulse Response (VS=5V) Large Signal Pulse Response (VS=5V)
Small Signal Pulse Response Large Signal Pulse Response
5.85
5.9
5.95
6
6.05
6.1
6.15
020 40 60 80 100 120 140 160 180 200
Voltage (V)
T i m e ( n s )
3.0
4.0
5.0
6.0
7 . 0
8.0
9.0
020 40 60 80 100 120 140 160 180 200
Voltage (V)
T i m e ( n s )
V
OUT
= 4V
pp
V
OUT
= 2V
pp
2.35
2.40
2.45
2.50
2.55
2.60
2.65
020 40 60 80 100 120 140 160 180 200
Voltage (V)
T i m e ( n s )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
020 40 60 80 100 120 140 160 180 200
Voltage (V)
T i m e ( n s )
V
OUT
= 3V
pp
V
OUT
= 2V
pp
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
0.1 110 100
Crosstalk (dB)
Frequency (MHz)
V
OU T
= 2V
pp
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
0.1 110 100
Crosstalk (dB)
Frequency (MHz)
V
OU T
= 2V
pp
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 12
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
PSRR vs. Frequency Input Voltage vs. Output Current
Closed Loop Output Impedance vs. Frequency CMRR vs. Frequency
Output Impedance (Ω)
Frequency (Hz)
1k 10k 100k 1M 10M 100M
0.001
10
1
0.1
0.01
CMRR (dB)
Frequency (Hz)
10 100 1k 10k 100k 1M 10M 100M
-90
-10
-20
-30
-40
-50
-60
-70
-80
PSRR (dB)
Frequency (Hz)
-100
-30
-40
-50
-60
-70
-80
-90
10 100 1k 10k 100k 1M 10M 100M
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT (A)
VIN (±V)
I
OUT+
R
L
= 2.668Ω
G = -1
V
S
= ±6V
I
OU T-
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 13
Application Information
Basic Operation
Figures 1 and 2 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1. Typical Non-Inverting Gain Circuit
Figure 2. Typical Inverting Gain Circuit
Power Supply and Decoupling
The CLC2000 can be powered with a low noise supply
anywhere in the range from +5V to +13V. Ensure ad-
equate metal connections to power pins in the PC board
layout with careful attention paid to decoupling the power
supply.
High quality capacitors with low equivalent series resis-
tance (ESR) such as multilayer ceramic capacitors (MLCC)
should be used to minimize supply voltage ripple and
power dissipation.
Two decoupling capacitors should be placed on each pow-
er pin with connection to a local PC board ground plane.
A large, usually tantalum, 10μF to 47μF capacitor is re-
quired to provide good decoupling for lower frequency
signals and to provide current for fast, large signal chang-
es at the CLC2000 outputs. It should be within 0.25” of
the pin. A secondary smaller 0.1μF MLCC capacitor should
located within 0.125” to reject higher frequency noise on
the power line.
Power Dissipation
Power dissipation is an important consideration in applica-
tions with low impedance DC, coupled loads. Guidelines
listed below can be used to verify that the particular ap-
plication will not cause the device to operate beyond its
intended operating range. Calculations below relate to a
single amplier. For the CLC2000, both ampliers power
contribution needs to be added for the total power dis-
sipation.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
perature, the package thermal resistance value ThetaJA
(ӨJA) is used along with the total die power dissipation.
TJunction = TAmbient + (ӨJA × PD)
Where TAmbient is the temperature of the working environ-
ment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equa-
tion.
Psupply = Vsupply × I(RMS supply)
Vsupply = V(S+) - V(S-)
Power delivered to a purely resistive load is:
Pload = ((VLOAD)RMS2) / Rloadeff
The effective load resistor will need to include the effect
of the feedback network. For instance,
Rloadeff in gure 1 would be calculated as:
RL || (Rf + Rg)
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 14
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - PLoad
Quiescent power can be derived from the specied IS val-
ues along with known supply voltage, VSupply. Load power
can be calculated as above with the desired signal ampli-
tudes using:
(VLOAD)RMS = VPEAK / √2
( ILOAD)RMS = (VLOAD)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDYNAMIC = (VS+ - VLOAD)RMS × (ILOAD)RMS
Assuming the load is referenced in the middle of the pow-
er rails or Vsupply/2.
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the 8 Lead
SOIC packages.
0
0.5
1
1.5
2
2.5
-40 -20 020 40 60 80
Maximum Power Dissipation (W)
Ambient Temperature (°C)
SOIC-8
Figure 3. Maximum Power Derating
Better thermal ratings can be achieved by maximizing
PC board metallization at the package pins. However, be
careful of stray capacitance on the input pins.
In addition, increased airow across the package can also
help to reduce the effective ӨJA of the package.
In the event of a short circuit condition, the CLC2000 has
circuitry to limit output drive capability to ±1000mA. This
will only protect against a momentary event. Extended
duration under these conditions will cause junction tem-
peratures to exceed 150°C. Due to internal metallization
constraints, continuous output current should be limited
to ±100mA.
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplier and the load to help improve
stability and settling performance. Refer to Figure 4.
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 4. Addition of RS for Driving
Capacitive Loads
Table 1 provides the recommended RS for various capaci-
tive loads. The recommended RS values result in <=1dB
peaking in the frequency response. The Frequency Re-
sponse vs. CL plots, on page 7, illustrates the response of
the CLC2000.
CL (pF) RS (Ω) -3dB BW (MHz)
10 40 275
20 24.5 250
50 20 175
100 13.5 135
500 6 75
1000 5 45
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 15
Overdrive Recovery
An overdrive condition is dened as the point when either
one of the inputs or the output exceed their specied volt-
age range. Overdrive recovery is the time needed for the
amplier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is ex-
ceeded. The CLC2000 will typically recover in less than
40ns from an overdrive condition. Figure 5 shows the
CLC2000 in an overdriven condition.
Figure 5. Overdrive Recovery
Using the CLC2000 as a Differential Line Driver
The combination of good large signal bandwidth and high
output drive capability makes the CLC2000 well suited for
low impedance line driver applications, such as the up-
stream data path for a ADSL CPE modem. The dual chan-
nel conguration of the CLC2000 provides better channel
matching than a typical single channel device, resulting
in better overall performance in differential applications.
When congured as a differential amplier as in gure 6, it
can easily deliver the 13dBm to a standard 100Ω twisted-
pair CAT3 or CAT5 cable telephone network, as required in
a ADSL CPE application.
Differential circuits have several advantages over single-
ended congurations. These include better rejection of
common mode signals and improvement of power-supply
rejection. The use of differential signaling also improves
overall dynamic performance. Total harmonic distortion
(THD) is reduced by the suppression of even signal har-
monics and the larger signal swings allow for an improved
signal to noise ratio (SNR).
+
VIN
Vo+
1:2
Vo-
Ro+=12.5Ω
RL=100Ω
Ro-=12.5Ω
1/2
CLC2000
1/2
CLC2000
Rg
Rf+
-
Rf-
VOUT
-Vs
+Vs
Figure 6: Typical Differential Transmission Line Driver
For any transmission requirement, the fundamental de-
sign parameters needed are the effective impedance of
the transmission line, the power required at the load, and
knowledge concerning the content of the transmitted sig-
nal. The basic design of such a circuit is briey outlined
below, using the ADSL parameters as a guideline.
Data transmission techniques, such as ADSL, utilize ampli-
tude modulation techniques which are sensitive to output
clipping. A signal’s PEAK to RMS ratio, or Crest Factor (CF),
can be used to determine the adequate peak signal levels
to insure delity for a given signal.
For an ADSL system, the signal consists of 256 indepen-
dent frequencies with varying amplitudes. This results in
a noise-like signal with a crest factor of about 5.3. If the
driver does not have enough swing to handle the signal
peaks, clipping will occur and amplitude modulated infor-
mation can be corrupted, causing degradation in the sig-
nals Bit Error Rate.
To determine the required swing, rst use the specied
load impedance to convert the RMS power to an RMS volt-
age. Then, multiply the RMS voltage by the crest factor to
get the peak values. For example 13dBm, as referenced to
1mW, is ~20mW. 20mW into the 100Ω CAT5 impedance
yields a RMS voltage of 1.413 VRMS . Using the ADSL crest
factor of 5.3 yields ~ ±7.5V peak signals.
-6
-4
-2
0
2
4
6
-3
-2
-1
0
1
2
3
020 40 60 80 100 120 140 160 180 200
Output Voltage (V)
Input Voltage (V)
T i m e ( n s )
Output
Input
V
IN
= 2.5V
pp
G = 5
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 16
Line coupling through a 1:2 transformer is used to realize
these levels. Standard back termination is used to match
the characteristic 100Ω impedance of the CAT5 cable. For
proper power transfer, this requires an effective 1:4 im-
pedance match of 25Ω at the inputs of the transformer. To
account for the voltage drop of the impedance matching
resistors, the signal levels at the output of the amplier
need to be doubled. Thus each amplier will swing ±3.75V
about a centered common mode output voltage.
In general, the CLC2000 can be used in any application
where an economical and local hardwired connection is
needed. For example, routing analog or digital video infor-
mation for a in-cabin entertainment system. Networking of
a local surveillance system also could be considered.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation board is available to aid in the
testing and layout of this device:
Evaluation Board # Products
CEB006 CLC2000
Evalutaion Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 7-9. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
Figure 7. CEB006 Schematic
Figure 8. CEB006 Top View
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 17
Figure 9. CEB006 Bottom View
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5415 (toll free)
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplier Rev 1A
Amplify the Human Experience
Mechanical Dimensions
SOIC-8 Package