ADC1175CIMTC/NOPB - Texas Instruments High-Performance Analog

September 2007

ADC1175

8-Bit, 20MHz, 60mW A/D Converter

General Description

The ADC1175 is a low power, 20 Msps analog-to-digital con-

verter that digitizes signals to 8 bits while consuming just 60

mW of power (typ). The ADC1175 uses a unique architecture

that achieves 7.5 Effective Bits. Output formatting is straight

binary coding.

The excellent DC and AC characteristics of this device, to-

gether with its low power consumption and +5V single supply

operation, make it ideally suited for many video, imaging and

communications applications, including use in portable equip-

ment. Furthermore, the ADC1175 is resistant to latch-up and

the outputs are short-circuit proof. The top and bottom of the

ADC1175's reference ladder is available for connections, en-

abling a wide range of input possibilities.

The ADC1175 is offered in a TSSOP. It is designed to operate

over the commercial temperature range of -20°C to +75°C.

Features

■Internal Sample-and-Hold Function

■Single +5V Operation

■Internal Reference Bias Resistors

■Industry Standard Pinout

■TRI-STATE Outputs

Key Specifications

■ Resolution 8 Bits

■ Maximum Sampling Frequency 20 Msps (min)

■ DNL 0.75 LSB (max)

■ ENOB 7.5 Bits (typ)

■ Guaranteed No Missing Codes

■ Power Consumption

(excluding IREF)

60mW (typ)

Applications

■Video Digitization

■Digital Still Cameras

■Personal Computer Video Cameras

■CCD Imaging

■Electro-Optics

Pin Configuration

ADC1175 Pin Configuration

10009201

ADC1175 8-Bit, 20MHz, 60mW A/D Converter

Ordering Information

Order Code Temperature Description

ADC1175CIJM * −20°C to +75°C SOIC (EIAJ)

ADC1175CIJMX * −20°C to +75°C SOIC (EIAJ) (tape & reel)

ADC1175CIMTC −20°C to +75°C TSSOP

ADC1175CIMTCX −20°C to +75°C TSSOP (tape & reel)

ADC1175EVAL * Evaluation Board

* Discontinured in the SOIC (EIAJ) package. The Evaluation Board is also discontinued. Shown for reference only.

Block Diagram

10009202

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ADC1175

Pin Descriptions and Equivalent Circuits

No. Symbol Equivalent Circuit Description

19 VIN Analog signal input. Conversion range is VRB to VRT.

16 VRTS

Reference Top Bias with internal pull-up resistor. Short this

pin to VRT to self bias the reference ladder.

17 VRT

Analog Input that is the high (top) side of the reference

ladder of the ADC. Nominal range is 1.0V to AVDD. Voltage

on VRT and VRB inputs define the VIN conversion range.

Bypass well. See Section 2.0 for more information.

23 VRB

Analog Input that is the low (bottom) side of the reference

ladder of the ADC. Nominal range is 0V to 4.0V. Voltage on

VRT and VRB inputs define the VIN conversion range. Bypass

well. See Section 2.0 for more information.

22 VRBS

Reference Bottom Bias with internal pull down resistor.

Short to VRB to self bias the reference ladder.

1 OE

CMOS/TTL compatible Digital input that, when low, enables

the digital outputs of the ADC1175. When high, the outputs

are in a high impedance state.

12 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on

the falling edge of CLK input.

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ADC1175

No. Symbol Equivalent Circuit Description

3 thru 10 D0-D7

Conversion data digital Output pins. D0 is the LSB, D7 is

the MSB. Valid data is output just after the rising edge of the

CLK input. These pins are enabled by bringing the OE pin

low.

13 DVDD

Positive digital supply pin. Connect to a clean voltage

source of +5V. AVDD and DVDD should have a common

source and be separately bypassed with a 10µF capacitor

and a 0.1µF ceramic chip capacitor. See Section 3.0 for

more information.

11 DVDD

This digital supply pin supplies power for the digital output

drivers. This pin should be connected to a supply source in

the range of 2.5V to the Pin 13 potential.

2, 24 DVSS

The ground return for the digital supply. AVSS and DVSS

should be connected together close to the ADC1175.

14, 15,

18 AVDD

Positive analog supply pin. Connected to a quiet voltage

source of +5V. AVDD and DVDD should have a common

source and be separately bypassed with a 10 µF capacitor

and a 0.1 µF ceramic chip capacitor. See Section 3.0 for

more information.

20, 21 AVSS

The ground return for the analog supply. AVSS and DVSS

should be connected together close to the ADC1175

package.

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ADC1175

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

AVDD, DVDD 6.5V

Voltage on Any Pin −0.3V to 6.5V

VRT, VRB AVSS to AVDD

CLK, OE Voltage −0.5 to (AVDD + 0.5V)

Digital Output Voltage DVSS to DVDD

Input Current (Note 3) ±25mA

Package Input Current

(Note 3) ±50mA

Package Dissipation at 25°C (Note 4)

ESD Susceptibility (Note 5)

Human Body Model 2000V

Machine Model 200V

Soldering Temp., Infrared, 10 sec.

(Note 6) 300°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −20°C ≤ TA ≤ +75°C

Supply voltage (AVDD, DVDD) +4.75V to +5.25V

AVDD − DVDD <0.5V

|AVSS - DVSS| 0V to 100 mV

Pin 13 - Pin 11 Voltage <0.5V

VRT 1.0V to VDD

VRB 0V to 4.0V

VRT - VRB 1V to 2.8V

VIN Voltage Range VRB to VRT

Package Thermal Resistance

Package θJA

TSSOP-24 92°C / W

Converter Electrical Characteristics

The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at

50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C (Notes 7, 8)

Symbol Parameter Conditions Typical

(Note 9)

Limits

(Note 9) Units

DC Accuracy

INL Integral Non Linearity f CLK = 20 MHz ±0.5 ±1.3 LSB ( max)

INL Integral Non Linearity f CLK = 30 MHz ±1.0 LSB ( max)

DNL Differential Non Linearity f CLK = 20 MHz ±0.35 ±0.75 LSB ( max)

DNL Differential Non Linearity f CLK = 30 MHz ±1.0 LSB ( max)

Missing Codes 0(max)

EOT Top Offset −24 mV

EOB Bottom Offset +37 mV

Video Accuracy

DP Differential Phase Error fin = 4.43 MHz sine wave,

fCLK = 17.7 MHz 0.5 Degree

DG Differential Gain Error fin = 4.43 MHz sine wave,

fCLK = 17.7 MHz 0.4 %

Analog Input and Reference Characteristics

VIN Input Range 2.0 VRB

VRT

V (min)

V (max)

CIN VIN Input Capacitance VIN = 1.5V + 0.7Vrms (CLK LOW) 4 pF

(CLK HIGH) 11

RIN RIN Input Resistance >1 MΩ

BW Analog Input Bandwidth 120 MHz

RRT Top Reference Resistor 360 Ω

RREF Reference Ladder Resistance VRT to VRB 300 200 Ω (min)

400 Ω (max)

RRB Bottom Reference Resistor 90 Ω

IREF Reference Ladder Current

VRT =VRTS, VRB =VRBS 74.8 mA (min)

9.3 mA (max)

VRT =VRTS,VRB =AVSS 85.4 mA (min)

10.5 mA (max)

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ADC1175

Symbol Parameter Conditions Typical

(Note 9)

Limits

(Note 9) Units

VRT Reference Top Self Bias Voltage VRT connected to VRTS

VRB connected to VRBS

2.6 V

VRB

Reference Bottom Self Bias

Voltage

VRT connected to VRTS 0.6 0.55 V (min)

VRB connected to VRBS 0.65 V (max)

VRTS -

VRBS

Self Bias Voltage Delta

VRT connected to VRTS,

VRB connected to VRBS

21.89

2.15

µA (min)

µA (max)

VRT connected to VRTS,

VRB connected to AVSS

2.3 V

VRT - VRB Reference Voltage Delta 2 1.0 V (min)

2.8 V (max)

Power Supply Characteristics

IADD Analog Supply Current DVDD = AVDD =5.25V 9.5 mA

IDDD Digital Supply Current DVDD = AVDD =5.25V 2.5 mA

IAVDD +

IDVDD

Total Operating Current

DVDD AVDD =5.25V, fCLK = 20 MHz 12 17 mA (max)

DVDD AVDD =5.25V, fCLK = 30 MHz 13

DVDD = AVDD =5.25V, CLK Low

(Note 10) 9.6 mA

Power Consumption DVDD = AVDD =5.25V, fCLK = 20 MHz 60 85 mW (max)

DVDD = AVDD =5.25V, fCLK = 30 MHz 65 mW

CLK, OE Digital Input Characteristics

VIH Logical High Input Voltage DVDD = AVDD = +5.25V 3.0 V (min)

VIL Logical Low Input Voltage DVDD = AVDD = +5.25V 1.0 V (max)

IIH Logical High Input Current VIH = DVDD = AVDD = +5.25V 5 µA

IIL Logic Low Input Current VIL = 0V, DVDD = AVDD = +5.25V −5 µA

CIN Logic Input Capacitance 5 pF

Digital Output Characteristics

IOH High Level Output Current DVDD = 4.75V, VOH = 2.4V −1.1 mA (max)

IOL Low Level Output Current DVDD = 4.75V, VOL = 0.4V 1.6 mA (min)

IOZH,

IOZL

Tri-State® Leakage Current

DVDD = 5.25V

OE = DVDD, VOL

= 0V or VOH = DVDD

±20 µA

AC Electrical Characteristics

fC1 Maximum Conversion Rate 30 20 MHz (min)

fC2 Minimum Conversion Rate 1 MHz

tOD Output Delay CLK rise to data rising 19.5 ns

CLK rise to data falling 16 ns

Pipeline Delay (Latency) 2.5 Clock Cycles

tDS Sampling (Aperture) Delay CLK low to acquisition of data 3 ns

tAJ Aperture Jitter 30 ps rms

tOH Output Hold Time CLK high to data invalid 10 ns

tEN OE Low to Data Valid Loaded as in Figure 2 11 ns

tDIS OE High to High Z State Loaded as in Figure 2 15 ns

ENOB Effective Number of Bits

fIN = 1.31 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, VIN = FS - 2 LSB

fIN = 9.9 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, fCLK = 30 MHz

7.5

7.3

7.2

6.5

7.0

Bits (min)

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ADC1175

Symbol Parameter Conditions Typical

(Note 9)

Limits

(Note 9) Units

SINAD Signal-to- Noise & Distortion

fIN = 1.31 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, VIN = FS - 2 LSB

fIN = 9.9 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, fCLK = 30 MHz

46.9

45.7

45.1

40.9

dB (min)

SNR Signal-to- Noise Ratio

fIN = 1.31 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, VIN = FS - 2 LSB

fIN = 9.9 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, fCLK = 30 MHz

47.6

46.1

42.1

dB (min)

SFDR Spurious Free Dynamic Range

fIN = 1.31 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, VIN = FS - 2 LSB

fIN = 9.9 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, fCLK = 30 MHz

THD Total Harmonic Distortion

fIN = 1.31 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, VIN = FS - 2 LSB

fIN = 9.9 MHz, VIN = FS - 2 LSB

fIN = 4.43 MHz, fCLK = 30 MHz

−55

−57

−52

−47

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input

current of 25 mA to two.

Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance θJA, and the ambient temperature, TA, and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are

driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.

Note 6: See AN–450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However,

errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75VDC, the full-scale input

voltage must be ≤4.80VDC to ensure accurate conversions.

10009210

Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality

Level).

Note 10: At least two clock cycles must be presented to the ADC1175 after power up. See Section 4.0 for details.

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ADC1175

Typical Performance Characteristics

INL vs. Temp at fCLK

10009220

DNL vs. Temp at fCLK

10009221

SNR vs. Temp at fCLK

10009222

SNR vs. Temp at fCLK

10009233

THD vs. Temp

10009223

THD vs. Temp

10009232

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ADC1175

SINAD/ENOB vs. Temp

10009224

SINAD/ENOB vs. Temp

10009231

SINAD and ENOB vs. Clock Duty Cycle

10009225

SFDR vs. Temp and fIN

10009229

SFDR vs. Temp and fIN

10009230

Differential Gain vs. Temperature

10009226

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ADC1175

Differential Phase vs. Temperature

10009227

Spectral Response at fCLK = 20 MSPS

10009228

Specification Definitions

ANALOG INPUT BANDWIDTH is a measure of the frequen-

cy at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input. The test is

performed with fIN equal to 100 kHz plus integer multiples of

fCLK. The input frequency at which the output is −3 dB relative

to the low frequency input signal is the full power bandwidth.

APERTURE JITTER is the time uncertainty of the sampling

point (tDS), or the range of variation in the sampling delay.

BOTTOM OFFSET is the difference between the input volt-

age that just causes the output code to transition to the first

code and the negative reference voltage. Bottom offset is de-

fined as EOB = VZT - VRB, where VZT is the first code transition

input voltage. Note that this is different from the normal Zero

Scale Error.

DIFFERENTIAL GAIN ERROR is the percentage difference

between the output amplitudes of a high frequency recon-

structed sine wave at two different d.c. levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DIFFERENTIAL PHASE ERROR is the difference in the out-

put phase of a reconstructed small signal sine wave at two

different d.c. levels.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from zero

scale (½LSB below the first code transition) through positive

full scale (½LSB above the last code transition). The deviation

of any given code from this straight line is measured from the

center of that code value. The end point test method is used.

OUTPUT DELAY is the time delay after the rising edge of the

input clock before the data update is present at the output

pins.

OUTPUT HOLD TIME is the length of time that the output data

is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles

between initiation of conversion and when that data is pre-

sented to the output stage. Data for any give sample is

available the Pipeline Delay plus the Output Delay after that

sample is taken. New data is available at every clock cycle,

but the data lags the conversion by the pipeline delay.

SAMPLING (APERTURE) DELAY is that time required after

the fall of the clock input for the sampling switch to open. The

Sample/Hold circuit effectively stops capturing the input sig-

nal and goes into the "hold" mode tDS after the clock goes low.

SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value

of the input signal to the rms value of the other spectral com-

ponents below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or

SINAD) is the ratio of the rms value of the input signal to the

rms value of all of the other spectral components below half

the clock frequency, including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

TOP OFFSET is the difference between the positive refer-

ence voltage and the input voltage that just causes the output

code to transition to full scale and is defined as EOT = VFT −

VRT. Where VFT is the full scale transition input voltage. Note

that this is different from the normal Full Scale Error.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first six harmonic components, to the rms val-

ue of the input signal.

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ADC1175

Timing Diagram

10009211

FIGURE 1. ADC1175 Timing Diagram

10009212

FIGURE 2. tEN , tDIS Test Circuit

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ADC1175

Functional Description

The ADC1175 uses a new, unique architecture to achieve 7.2

effective bits at and maintains superior dynamic performance

up to ½ the clock frequency.

The analog signal at VIN that is within the voltage range set

by VRT and VRB are digitized to eight bits at up to 30 MSPS.

Input voltages below VRB will cause the output word to consist

of all zeroes. Input voltages above VRT will cause the output

word to consist of all ones. VRT has a range of 1.0 Volt to the

analog supply voltage, AVDD, while VRB has a range of 0 to

4.0 Volts. VRT should always be between 1.0 Volt and 2.8

Volts more positive than VRB.

If VRT and VRTS are connected together and VRB and VRBS are

connected together, the nominal values of VRT and VRB are

2.6V and 0.6V, respectively. If VRT and VRTS are connected

together and VRB is grounded, the nominal value of VRT is

2.3V.

Data is acquired at the falling edge of the clock and the digital

equivalent of the data is available at the digital outputs 2.5

clock cycles plus tOD later. The ADC1175 will convert as long

as the clock signal is present at pin 12. The Output Enable

pin OE, when low, enables the output pins. The digital outputs

are in the high impedance state when the OE pin is high.

Applications Information

1.0 THE ANALOG INPUT

The analog input of the ADC1175 is a switch followed by an

integrator. The input capacitance changes with the clock lev-

el, appearing as 4 pF when the clock is low, and 11 pF when

the clock is high. Since a dynamic capacitance is more difficult

to drive than a fixed capacitance, choose an amplifier that can

drive this type of load. The LMH6702, LMH6609, LM6152,

LM6154, LM6181 and LM6182 have been found to be excel-

lent devices for driving the ADC1175. Do not drive the input

beyond the supply rails. Figure 3 shows an example of an

input circuit using the LMH6702.

Driving the analog input with input signals up to 2.8 VP-P will

result in normal behavior where signals above VRT will result

in a code of FFh and input voltages below VRB will result in an

output code of zero. Input signals above 2.8 VP-P may result

in odd behavior where the output code is not FFh when the

input exceeds VRT.

2.0 REFERENCE INPUTS

The reference inputs VRT (Reference Top) and VRB (Refer-

ence Bottom) are the top and bottom of the reference ladder.

Input signals between these two voltages will be digitized to

8 bits. External voltages applied to the reference input pins

should be within the range specified in the Operating Ratings

table (1.0V to AVDD for VRT and 0V to (AVDD - 1.0V) for VRB).

Any device used to drive the reference pins should be able to

source sufficient current into the VRT pin and sink sufficient

current from the VRB pin.

The reference ladder can be self-biased by connecting VRT to

VRTS and connecting VRB to VRBS to provide top and bottom

reference voltages of approximately 2.6V and 0.6V, respec-

tively, with VCC = 5.0V. This connection is shown in Figure

3. If VRT and VRTS are tied together, but VRB is tied to analog

ground, a top reference voltage of approximately 2.3V is gen-

erated. The top and bottom of the ladder should be bypassed

with 10µF tantalum capacitors located close to the reference

pins.

The reference self-bias circuit of Figure 3 is very simple and

performance is adequate for many applications. Superior per-

formance can generally be achieved by driving the reference

pins with a low impedance source.

By forcing a little current into or out of the top and bottom of

the ladder, as shown in Figure 4, the top and bottom reference

voltages can be trimmed and performance improved over the

self-bias method of Figure 3. The resistive divider at the am-

plifier inputs can be replaced with potentiometers. The

LMC662 amplifier shown was chosen for its low offset voltage

and low cost. Note that a negative power supply is needed for

these amplifiers if their outputs are required to go slightly

negative to force the required reference voltages.

If reference voltages are desired that are more than a few tens

of millivolts from the self-bias values, the circuit of Figure 5

will allow forcing the reference voltages to whatever levels are

desired. This circuit provides the best performance because

of the low source impedance of the transistors. Note that the

VRTS and VRBS pins are left floating.

VRT can be anywhere between VRB + 1.0V and the analog

supply voltage, and VRB can be anywhere between ground

and 1.0V below VRT. To minimize noise effects and ensure

accurate conversions, the total reference voltage range (VRT

- VRB) should be a minimum of 1.0V and a maximum of about

2.8V. If VRB is not required to be below about +700mV, the

-5V points in Figure 5 can be returned to ground and the neg-

ative supply eliminated.

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ADC1175

10009213

FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the reference

voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text).

10009214

FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference voltages are trimmed by

providing a small trim current with the operational amplifiers.

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ADC1175

10009215

FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source, provided by the

transistors. Note that pins 16 and 22 are not connected.

3.0 POWER SUPPLY CONSIDERATIONS

Many A/D converters draw sufficient transient current to cor-

rupt their own power supplies if not adequately bypassed. A

10µF tantalum or aluminum electrolytic capacitor should be

placed within an inch (2.5 centimeters) of the A/D power pins,

with a 0.1 µF ceramic chip capacitor placed as close as pos-

sible to the converter's power supply pins. Leadless chip

capacitors are preferred because they have low lead induc-

tance.

While a single voltage source should be used for the analog

and digital supplies of the ADC1175, these supply pins should

be well isolated from each other to prevent any digital noise

from being coupled to the analog power pins. A wideband

choke, such as the JW Miller FB20010-3B, is recommended

between the analog and digital supply lines, with a ceramic

capacitor close to the analog supply pin. Avoid inductive com-

ponents in the analog supply line.

The converter digital supply should not be the supply that is

used for other digital circuitry on the board. It should be the

same supply used for the A/D analog supply.

As is the case with all high speed converters, the ADC1175

should be assumed to have little a.c. power supply rejection,

especially when self-biasing is used by connecting VRT and

VRTS together.

No pin should ever have a voltage on it that is in excess of the

supply voltages or below ground, not even on a transient ba-

sis. This can be a problem upon application of power to a

circuit. Be sure that the supplies to circuits driving the CLK,

OE, analog input and reference pins do not come up any

faster than does the voltage at the ADC1175 power pins.

Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply

point for the digital core of the ADC, where pin 13 is used only

to provide power to the ADC output drivers. As such, pin 11

may be connected to a voltage source that is less than the

+5V used for AVDD and DVDD to ease interfacing to low volt-

age devices. Pin 11 should never exceed the pin 13 potential

by more than 0.5V.

4.0 THE ADC1175 CLOCK

Although the ADC1175 is tested and its performance is guar-

anteed with a 20MHz clock, it typically will function with clock

frequencies from 1MHz to 30MHz.

If continuous conversions are not required, power consump-

tion can be reduced somewhat by stopping the clock at a logic

low when the ADC1175 is not being used. This reduces the

current drain in the ADC1175's digital circuitry from a typical

value of 2.5mA to about 100µA.

Note that powering up the ADC1175 without the clock running

may not save power, as it will result in an increased current

flow (by as much as 170%) in the reference ladder. In some

cases, this may increase the ladder current above the speci-

fied limit. Toggling the clock twice at 1MHz or higher and

returning it to the low state will eliminate the excess ladder

current.

An alternative power-saving technique is to power up the

ADC1175 with the clock active, then halt the clock in the low

state after two or more clock cycles. Stopping the clock in the

high state is not recommended as a power-saving technique.

5.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals is essential

to ensure accurate conversion. Separate analog and digital

ground planes that are connected beneath the ADC1175 may

be used, but best EMI practices require a single ground plane.

However, it is important to keep analog signal lines away from

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ADC1175

digital signal lines and away from power supply currents. This

latter requirement requires the careful separation and place-

ment of power planes. The use of power traces rather than

one or more power planes is not recommended as higher fre-

quencies are not well filtered with lumped capacitances. To

filter higher frequency noise components it is necessary to

have sufficient capacitance between the power and ground

planes.

If separate analog and digital ground planes are used, the

analog and digital grounds may be in the same layer, but

should be separated from each other. If separate analog and

digital ground layers are used, they should never overlap

each other.

Capacitive coupling between a typically noisy digital ground

plane and the sensitive analog circuitry can lead to poor per-

formance that may seem impossible to isolate and remedy.

The solution is to keep the analog circuity well separated from

the digital circuitry.

Digital circuits create substantial supply and ground current

transients. The logic noise thus generated could have signif-

icant impact upon system noise performance. The best logic

family to use in systems with A/D converters is one which

employs non-saturating transistor designs, or has low noise

characteristics, such as the 74HC(T) and 74AC(T)Q families.

The worst noise generators are logic families that draw the

largest supply current transients during clock or signal edges,

like the 74F and the 74AC(T) families. In general, slower logic

families will produce less high frequency noise than do high

speed logic families.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise.

This is because of the skin effect. Total surface area is more

important than is total ground plane volume.

An effective way to control ground noise is by using a single,

solid ground plane, splitting the power plane into analog and

digital areas and having power and ground planes in adjacent

board layers. There should be no traces within either the

power or the ground layers of the board. The analog and dig-

ital power planes should reside in the same board layer so

that they can not overlap each other. The analog and digital

power planes define the analog and digital areas of the board.

Generally, analog and digital lines should cross each other at

90 degrees to avoid getting digital noise into the analog path.

In high frequency systems, however, avoid crossing analog

and digital lines altogether. Clock lines should be isolated

from ALL other lines, analog and digital. Even the generally

accepted 90 degree crossing should be avoided as even a

little coupling can cause problems at high frequencies. Best

performance at high frequencies and at high resolution is ob-

tained with a straight signal path.

Be especially careful with the layout of inductors. Mutual in-

ductance can change the characteristics of the circuit in which

they are used. Inductors should not be placed side by side,

not even with just a small part of their bodies being beside

each other.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected between

the converter's input and ground should be connected to a

very clean point in the ground return.

6.0 DYNAMIC PERFORMANCE

The ADC1175 is a.c. tested and its dynamic performance is

guaranteed. To meet the published specifications, the clock

source driving the CLK input must be free of jitter. For best

a.c. performance, isolating the ADC clock from any digital cir-

cuitry should be done with adequate buffers, as with a clock

tree. See Figure 6.

10009217

FIGURE 6. Isolating the ADC clock from Digital Circuitry.

It is good practice to keep the ADC clock line as short as pos-

sible and to keep it well away from any other signals. Other

signals can introduce jitter into the clock signal.

7.0 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, all inputs should not go

more than 50mV below the ground pins or 50mV above the

supply pins. Exceeding these limits on even a transient basis

can cause faulty or erratic operation. It is not uncommon for

high speed digital circuits to exhibit undershoot that goes

more than a volt below ground due to improper line termina-

tion. A resistor of 50Ω to 100Ω in series with the offending

digital input, located close to the signal source, will usually

eliminate the problem.

Care should be taken not to overdrive the inputs of the

ADC1175. Such practice may lead to conversion inaccura-

cies and even to device damage.

Attempting to drive a high capacitance digital data bus.

The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current is re-

quired from DVDD and DGND. These large charging current

spikes can couple into the analog section, degrading dynamic

performance. Buffering the digital data outputs (with an

74AC541, for example) may be necessary if the data bus to

be driven is heavily loaded. Dynamic performance can also

be improved by adding 47Ω to 100Ω series resistors at each

digital output, reducing the energy coupled back into the con-

verter output pins.

Using an inadequate amplifier to drive the analog input.

As explained in Section 1.0, the capacitance seen at the input

alternates between 4 pF and 11 pF with the clock. This dy-

namic capacitance is more difficult to drive than is a fixed

capacitance, and should be considered when choosing a

driving device. The LMH6702, LMH6609, LM6152, LM6154,

LM6181 and LM6182 have been found to be excellent de-

vices for driving the ADC1175 analog input.

Driving the VRT pin or the VRB pin with devices that can

not source or sink the current required by the ladder. As

mentioned in section 2.0, care should be taken to see that any

driving devices can source sufficient current into the VRT pin

and sink sufficient current from the VRB pin. If these pins are

not driven with devices than can handle the required current,

these reference pins will not be stable, resulting in a reduction

of dynamic performance.

Using a clock source with excessive jitter, using an ex-

cessively long clock signal trace, or having other signals

coupled to the clock signal trace. This will cause the sam-

15 www.national.com

ADC1175

pling interval to vary, causing excessive output noise and a

reduction in SNR performance. Simple gates with RC timing

is generally inadequate as a clock source.

Input test signal contains harmonic distortion that inter-

feres with the measurement of dynamic signal to noise

ratio. Harmonic and other interfering signals can be removed

by inserting a filter at the signal input. Suitable filters are

shown in Figure 7 and Figure 8. The circuit of Figure 7 has

cutoff of about 5.5 MHz and is suitable for input frequencies

of 1 MHz to 5 MHz. The circuit of Figure 8 has a cutoff of about

11 MHz and is suitable for input frequencies of 5 MHz to 10

MHz. These filters should be driven by a generator of 75 Ohm

source impedance and terminated with a 75 ohm resistor.

10009218

FIGURE 7. 5.5 MHz Low Pass Filter to Eliminate

Harmonics at the Signal Input.

10009219

FIGURE 8. 11 MHz Low Pass filter to eliminate harmonics

at the signal input. Use at input frequencies of 5 MHz to

10 MHz

Not considering the effect on a driven CMOS digital cir-

cuit(s) when the ADC1175 is in the power down mode.

Because the ADC1175 output goes into a high impedance

state when in the power down mode, any CMOS device con-

nected to these outputs will have their inputs floating when

the ADC is in power down. Should the inputs of the circuit

being driven by the ADC digital outputs float to a level near

2.5V, a CMOS device could exhibit relative large supply cur-

rents as the input stage toggles rapidly. The solution is to use

pull-down resistors at the ADC outputs. The value of these

resistors is not critical, as long as they do not cause excessive

currents in the outputs of the ADC1175. Low pull-down resis-

tor values could result in degraded SNR and SINAD perfor-

mance of the ADC1175. Values between 5 kΩ and 100 kΩ

should work well.

www.national.com 16

ADC1175

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Package JM

Ordering Number ADC1175CIJM

NS Package Number M24D

24-Lead Package TC

Ordering Number ADC1175CIMTC

NS Package Number MTC24

17 www.national.com

ADC1175

Notes

ADC1175 8-Bit, 20MHz, 60mW A/D Converter

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