ADC1175 8-Bit, 20MHz, 60mW A/D Converter General Description Features The ADC1175 is a low power, 20 Msps analog-to-digital converter that digitizes signals to 8 bits while consuming just 60 mW of power (typ). The ADC1175 uses a unique architecture that achieves 7.5 Effective Bits. Output formatting is straight binary coding. The excellent DC and AC characteristics of this device, together with its low power consumption and +5V single supply operation, make it ideally suited for many video, imaging and communications applications, including use in portable equipment. Furthermore, the ADC1175 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC1175's reference ladder is available for connections, enabling a wide range of input possibilities. The ADC1175 is offered in a TSSOP. It is designed to operate over the commercial temperature range of -20C to +75C. Internal Sample-and-Hold Function Single +5V Operation Internal Reference Bias Resistors Industry Standard Pinout TRI-STATE Outputs Key Specifications Resolution Maximum Sampling Frequency DNL 8 Bits 20 Msps (min) 0.75 LSB (max) ENOB 7.5 Bits (typ) Guaranteed No Missing Codes Power Consumption 60mW (typ) (excluding IREF) Applications Video Digitization Digital Still Cameras Personal Computer Video Cameras CCD Imaging Electro-Optics Pin Configuration ADC1175 Pin Configuration 10009201 (c) 2007 National Semiconductor Corporation 100092 www.national.com ADC1175 8-Bit, 20MHz, 60mW A/D Converter September 2007 ADC1175 Ordering Information Order Code Temperature Description ADC1175CIJM * -20C to +75C SOIC (EIAJ) ADC1175CIJMX * -20C to +75C SOIC (EIAJ) (tape & reel) ADC1175CIMTC -20C to +75C TSSOP ADC1175CIMTCX -20C to +75C TSSOP (tape & reel) ADC1175EVAL * Evaluation Board * Discontinured in the SOIC (EIAJ) package. The Evaluation Board is also discontinued. Shown for reference only. Block Diagram 10009202 www.national.com 2 ADC1175 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 19 VIN 16 VRTS Reference Top Bias with internal pull-up resistor. Short this pin to VRT to self bias the reference ladder. VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AVDD. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 23 VRB Analog Input that is the low (bottom) side of the reference ladder of the ADC. Nominal range is 0V to 4.0V. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 22 VRBS Reference Bottom Bias with internal pull down resistor. Short to VRB to self bias the reference ladder. 1 OE CMOS/TTL compatible Digital input that, when low, enables the digital outputs of the ADC1175. When high, the outputs are in a high impedance state. 12 CLK CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input. 17 Analog signal input. Conversion range is VRB to VRT. 3 www.national.com ADC1175 Pin No. Symbol Equivalent Circuit Description D0-D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are enabled by bringing the OE pin low. 13 DVDD Positive digital supply pin. Connect to a clean voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10F capacitor and a 0.1F ceramic chip capacitor. See Section 3.0 for more information. 11 DVDD This digital supply pin supplies power for the digital output drivers. This pin should be connected to a supply source in the range of 2.5V to the Pin 13 potential. 2, 24 DVSS The ground return for the digital supply. AVSS and DVSS should be connected together close to the ADC1175. 14, 15, 18 AVDD Positive analog supply pin. Connected to a quiet voltage source of +5V. AVDD and DVDD should have a common source and be separately bypassed with a 10 F capacitor and a 0.1 F ceramic chip capacitor. See Section 3.0 for more information. 20, 21 AVSS The ground return for the analog supply. AVSS and DVSS should be connected together close to the ADC1175 package. 3 thru 10 www.national.com 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. AVDD, DVDD Voltage on Any Pin VRT, VRB CLK, OE Voltage Digital Output Voltage Input Current (Note 3) Package Input Current (Note 3) Package Dissipation at 25C ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temp., Infrared, 10 sec. (Note 6) Storage Temperature (Notes 1, 2) Operating Temperature Range Supply voltage (AVDD, DVDD) AVDD - DVDD |AVSS - DVSS| Pin 13 - Pin 11 Voltage VRT VRB VRT - VRB VIN Voltage Range 6.5V -0.3V to 6.5V AVSS to AVDD -0.5 to (AVDD + 0.5V) DVSS to DVDD 25mA -20C TA +75C +4.75V to +5.25V <0.5V 0V to 100 mV <0.5V 1.0V to VDD 0V to 4.0V 1V to 2.8V VRB to VRT 50mA (Note 4) Package Thermal Resistance 2000V 200V Package JA TSSOP-24 92C / W 300C -65C to +150C Converter Electrical Characteristics The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units 0.5 1.3 LSB ( max) DC Accuracy INL Integral Non Linearity f CLK = 20 MHz INL Integral Non Linearity f CLK = 30 MHz 1.0 DNL Differential Non Linearity f CLK = 20 MHz 0.35 DNL Differential Non Linearity f CLK = 30 MHz 1.0 Missing Codes LSB ( max) 0.75 LSB ( max) LSB ( max) 0 (max) EOT Top Offset -24 mV EOB Bottom Offset +37 mV Video Accuracy DP Differential Phase Error fin = 4.43 MHz sine wave, fCLK = 17.7 MHz 0.5 Degree DG Differential Gain Error fin = 4.43 MHz sine wave, fCLK = 17.7 MHz 0.4 % Analog Input and Reference Characteristics VRB VRT V (min) V (max) VIN Input Range CIN VIN Input Capacitance RIN RIN Input Resistance >1 M BW Analog Input Bandwidth 120 MHz RRT Top Reference Resistor 360 RREF Reference Ladder Resistance RRB Bottom Reference Resistor IREF 2.0 VIN = 1.5V + 0.7Vrms VRT to VRB (CLK LOW) 4 (CLK HIGH) 11 300 pF 200 (min) 400 (max) mA (min) mA (max) mA (min) mA (max) 90 VRT =VRTS, VRB =VRBS 7 4.8 9.3 VRT =VRTS,VRB =AVSS 8 5.4 10.5 Reference Ladder Current 5 www.national.com ADC1175 Operating Ratings Absolute Maximum Ratings (Notes 1, 2) ADC1175 Symbol Parameter VRT Reference Top Self Bias Voltage VRB Reference Bottom Self Bias Voltage VRTS VRBS Self Bias Voltage Delta VRT - VRB Reference Voltage Delta Conditions VRT connected to VRTS VRB connected to VRBS VRT connected to VRTS VRB connected to VRBS Typical (Note 9) Limits (Note 9) 2.6 0.6 VRT connected to VRTS, VRB connected to VRBS 2 VRT connected to VRTS, VRB connected to AVSS 2.3 2 Units V 0.55 V (min) 0.65 V (max) 1.89 2.15 A (min) A (max) V 1.0 2.8 V (min) V (max) Power Supply Characteristics IADD Analog Supply Current DVDD = AVDD =5.25V 9.5 mA IDDD Digital Supply Current DVDD = AVDD =5.25V 2.5 mA DVDD AVDD =5.25V, fCLK = 20 MHz 12 DVDD AVDD =5.25V, fCLK = 30 MHz 13 DVDD = AVDD =5.25V, CLK Low (Note 10) 9.6 DVDD = AVDD =5.25V, fCLK = 20 MHz 60 DVDD = AVDD =5.25V, fCLK = 30 MHz 65 IAVDD + IDVDD Total Operating Current Power Consumption 17 mA (max) mA 85 mW (max) mW CLK, OE Digital Input Characteristics VIH Logical High Input Voltage DVDD = AVDD = +5.25V VIL Logical Low Input Voltage DVDD = AVDD = +5.25V IIH Logical High Input Current VIH = DVDD = AVDD = +5.25V 5 A IIL Logic Low Input Current VIL = 0V, DVDD = AVDD = +5.25V -5 A CIN Logic Input Capacitance 5 pF 3.0 V (min) 1.0 V (max) Digital Output Characteristics IOH High Level Output Current DVDD = 4.75V, VOH = 2.4V -1.1 mA (max) IOL Low Level Output Current DVDD = 4.75V, VOL = 0.4V 1.6 mA (min) Tri-State(R) Leakage Current DVDD = 5.25V OE = DVDD, VOL = 0V or VOH = DVDD IOZH, IOZL 20 A AC Electrical Characteristics fC1 Maximum Conversion Rate fC2 Minimum Conversion Rate tOD Output Delay 30 Sampling (Aperture) Delay MHz (min) 1 MHz CLK rise to data rising 19.5 ns CLK rise to data falling 16 ns 2.5 Clock Cycles Pipeline Delay (Latency) tDS 20 CLK low to acquisition of data 3 ns 30 ps rms tAJ Aperture Jitter tOH Output Hold Time CLK high to data invalid 10 ns tEN OE Low to Data Valid Loaded as in Figure 2 11 ns tDIS OE High to High Z State Loaded as in Figure 2 15 ns Effective Number of Bits fIN = 1.31 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, VIN = FS - 2 LSB fIN = 9.9 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, fCLK = 30 MHz 7.5 7.3 7.2 6.5 ENOB www.national.com 6 7.0 Bits (min) SINAD SNR SFDR THD Parameter Typical (Note 9) Conditions Limits (Note 9) Units Signal-to- Noise & Distortion fIN = 1.31 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, VIN = FS - 2 LSB fIN = 9.9 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, fCLK = 30 MHz 46.9 45.7 45.1 40.9 Signal-to- Noise Ratio fIN = 1.31 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, VIN = FS - 2 LSB fIN = 9.9 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, fCLK = 30 MHz 47.6 46 46.1 42.1 Spurious Free Dynamic Range fIN = 1.31 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, VIN = FS - 2 LSB fIN = 9.9 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, fCLK = 30 MHz 56 58 53 47 dB Total Harmonic Distortion fIN = 1.31 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, VIN = FS - 2 LSB fIN = 9.9 MHz, VIN = FS - 2 LSB fIN = 4.43 MHz, fCLK = 30 MHz -55 -57 -52 -47 dB 43 44 dB (min) dB (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance JA, and the ambient temperature, TA, and can be calculated using the formula PDMAX = (TJmax - TA )/JA. The values for maximum power dissipation listed above will be reached only when the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5k resistor. Machine model is 220 pF discharged through ZERO . Note 6: See AN-450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75VDC, the full-scale input voltage must be 4.80VDC to ensure accurate conversions. 10009210 Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: At least two clock cycles must be presented to the ADC1175 after power up. See Section 4.0 for details. 7 www.national.com ADC1175 Symbol ADC1175 Typical Performance Characteristics INL vs. Temp at fCLK DNL vs. Temp at fCLK 10009221 10009220 SNR vs. Temp at fCLK SNR vs. Temp at fCLK 10009222 10009233 THD vs. Temp THD vs. Temp 10009223 www.national.com 10009232 8 ADC1175 SINAD/ENOB vs. Temp SINAD/ENOB vs. Temp 10009224 10009231 SINAD and ENOB vs. Clock Duty Cycle SFDR vs. Temp and fIN 10009225 10009229 SFDR vs. Temp and fIN Differential Gain vs. Temperature 10009226 10009230 9 www.national.com ADC1175 Differential Phase vs. Temperature Spectral Response at fCLK = 20 MSPS 10009227 10009228 OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output stage. Data for any give sample is available the Pipeline Delay plus the Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. SAMPLING (APERTURE) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the "hold" mode tDS after the clock goes low. SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as EOT = VFT - VRT. Where VFT is the full scale transition input voltage. Note that this is different from the normal Full Scale Error. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components, to the rms value of the input signal. Specification Definitions ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is -3 dB relative to the low frequency input signal is the full power bandwidth. APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling delay. BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom offset is defined as EOB = VZT - VRB, where VZT is the first code transition input voltage. Note that this is different from the normal Zero Scale Error. DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency reconstructed sine wave at two different d.c. levels. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two different d.c. levels. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (1/2LSB below the first code transition) through positive full scale (1/2LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. www.national.com 10 ADC1175 Timing Diagram 10009211 FIGURE 1. ADC1175 Timing Diagram 10009212 FIGURE 2. tEN , tDIS Test Circuit 11 www.national.com ADC1175 Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings table (1.0V to AVDD for VRT and 0V to (AVDD - 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin. The reference ladder can be self-biased by connecting VRT to VRTS and connecting VRB to VRBS to provide top and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with VCC = 5.0V. This connection is shown in Figure 3. If VRT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10F tantalum capacitors located close to the reference pins. The reference self-bias circuit of Figure 3 is very simple and performance is adequate for many applications. Superior performance can generally be achieved by driving the reference pins with a low impedance source. By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 4, the top and bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 3. The resistive divider at the amplifier inputs can be replaced with potentiometers. The LMC662 amplifier shown was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these amplifiers if their outputs are required to go slightly negative to force the required reference voltages. If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of Figure 5 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left floating. VRT can be anywhere between VRB + 1.0V and the analog supply voltage, and VRB can be anywhere between ground and 1.0V below VRT. To minimize noise effects and ensure accurate conversions, the total reference voltage range (VRT - VRB) should be a minimum of 1.0V and a maximum of about 2.8V. If VRB is not required to be below about +700mV, the -5V points in Figure 5 can be returned to ground and the negative supply eliminated. Functional Description The ADC1175 uses a new, unique architecture to achieve 7.2 effective bits at and maintains superior dynamic performance up to 1/2 the clock frequency. The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 30 MSPS. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones. VRT has a range of 1.0 Volt to the analog supply voltage, AVDD, while VRB has a range of 0 to 4.0 Volts. VRT should always be between 1.0 Volt and 2.8 Volts more positive than VRB. If VRT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of VRT and VRB are 2.6V and 0.6V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal value of VRT is 2.3V. Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC1175 will convert as long as the clock signal is present at pin 12. The Output Enable pin OE, when low, enables the output pins. The digital outputs are in the high impedance state when the OE pin is high. Applications Information 1.0 THE ANALOG INPUT The analog input of the ADC1175 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load. The LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for driving the ADC1175. Do not drive the input beyond the supply rails. Figure 3 shows an example of an input circuit using the LMH6702. Driving the analog input with input signals up to 2.8 VP-P will result in normal behavior where signals above VRT will result in a code of FFh and input voltages below VRB will result in an output code of zero. Input signals above 2.8 VP-P may result in odd behavior where the output code is not FFh when the input exceeds VRT. 2.0 REFERENCE INPUTS The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference ladder. www.national.com 12 ADC1175 10009213 FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text). 10009214 FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. 13 www.national.com ADC1175 10009215 FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source, provided by the transistors. Note that pins 16 and 22 are not connected. to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never exceed the pin 13 potential by more than 0.5V. 3.0 POWER SUPPLY CONSIDERATIONS Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10F tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters) of the A/D power pins, with a 0.1 F ceramic chip capacitor placed as close as possible to the converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source should be used for the analog and digital supplies of the ADC1175, these supply pins should be well isolated from each other to prevent any digital noise from being coupled to the analog power pins. A wideband choke, such as the JW Miller FB20010-3B, is recommended between the analog and digital supply lines, with a ceramic capacitor close to the analog supply pin. Avoid inductive components in the analog supply line. The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should be the same supply used for the A/D analog supply. As is the case with all high speed converters, the ADC1175 should be assumed to have little a.c. power supply rejection, especially when self-biasing is used by connecting VRT and VRTS together. No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins. Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is used only www.national.com 4.0 THE ADC1175 CLOCK Although the ADC1175 is tested and its performance is guaranteed with a 20MHz clock, it typically will function with clock frequencies from 1MHz to 30MHz. If continuous conversions are not required, power consumption can be reduced somewhat by stopping the clock at a logic low when the ADC1175 is not being used. This reduces the current drain in the ADC1175's digital circuitry from a typical value of 2.5mA to about 100A. Note that powering up the ADC1175 without the clock running may not save power, as it will result in an increased current flow (by as much as 170%) in the reference ladder. In some cases, this may increase the ladder current above the specified limit. Toggling the clock twice at 1MHz or higher and returning it to the low state will eliminate the excess ladder current. An alternative power-saving technique is to power up the ADC1175 with the clock active, then halt the clock in the low state after two or more clock cycles. Stopping the clock in the high state is not recommended as a power-saving technique. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog and digital ground planes that are connected beneath the ADC1175 may be used, but best EMI practices require a single ground plane. However, it is important to keep analog signal lines away from 14 a.c. performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 6. 10009217 FIGURE 6. Isolating the ADC clock from Digital Circuitry. It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 50mV below the ground pins or 50mV above the supply pins. Exceeding these limits on even a transient basis can cause faulty or erratic operation. It is not uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground due to improper line termination. A resistor of 50 to 100 in series with the offending digital input, located close to the signal source, will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC1175. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from DVDD and DGND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with an 74AC541, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic performance can also be improved by adding 47 to 100 series resistors at each digital output, reducing the energy coupled back into the converter output pins. Using an inadequate amplifier to drive the analog input. As explained in Section 1.0, the capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for driving the ADC1175 analog input. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in section 2.0, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sam- 6.0 DYNAMIC PERFORMANCE The ADC1175 is a.c. tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best 15 www.national.com ADC1175 digital signal lines and away from power supply currents. This latter requirement requires the careful separation and placement of power planes. The use of power traces rather than one or more power planes is not recommended as higher frequencies are not well filtered with lumped capacitances. To filter higher frequency noise components it is necessary to have sufficient capacitance between the power and ground planes. If separate analog and digital ground planes are used, the analog and digital grounds may be in the same layer, but should be separated from each other. If separate analog and digital ground layers are used, they should never overlap each other. Capacitive coupling between a typically noisy digital ground plane and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuity well separated from the digital circuitry. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In general, slower logic families will produce less high frequency noise than do high speed logic families. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. An effective way to control ground noise is by using a single, solid ground plane, splitting the power plane into analog and digital areas and having power and ground planes in adjacent board layers. There should be no traces within either the power or the ground layers of the board. The analog and digital power planes should reside in the same board layer so that they can not overlap each other. The analog and digital power planes define the analog and digital areas of the board. Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies and at high resolution is obtained with a straight signal path. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, not even with just a small part of their bodies being beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the ground return. ADC1175 pling interval to vary, causing excessive output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a clock source. Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input. Suitable filters are shown in Figure 7 and Figure 8. The circuit of Figure 7 has cutoff of about 5.5 MHz and is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 8 has a cutoff of about 11 MHz and is suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm source impedance and terminated with a 75 ohm resistor. Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175 is in the power down mode. Because the ADC1175 output goes into a high impedance state when in the power down mode, any CMOS device connected to these outputs will have their inputs floating when the ADC is in power down. Should the inputs of the circuit being driven by the ADC digital outputs float to a level near 2.5V, a CMOS device could exhibit relative large supply currents as the input stage toggles rapidly. The solution is to use pull-down resistors at the ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents in the outputs of the ADC1175. Low pull-down resistor values could result in degraded SNR and SINAD performance of the ADC1175. Values between 5 k and 100 k should work well. 10009218 FIGURE 7. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input. 10009219 FIGURE 8. 11 MHz Low Pass filter to eliminate harmonics at the signal input. Use at input frequencies of 5 MHz to 10 MHz www.national.com 16 ADC1175 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Package JM Ordering Number ADC1175CIJM NS Package Number M24D 24-Lead Package TC Ordering Number ADC1175CIMTC NS Package Number MTC24 17 www.national.com ADC1175 8-Bit, 20MHz, 60mW A/D Converter Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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