TLC320AC01C Data Manual Single-Supply Analog Interface Circuit SLAS057D October 1996 Printed on Recycled Paper Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Register Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-3 1-5 1-8 2 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Reset and Power-Down Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Conditions of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Software and Hardware Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Register Default Values After POR, Software Reset, or RESET Is Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Master-Slave Terminal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Number of Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Required Minimum Number of MCLK Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 TLC320AC01 AIC Master-Slave Summary . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation . . . . . . . . . . . . . 2.9 Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 Master and Stand-Alone Operating Frequencies . . . . . . . . . . . . . . . . . . . 2.9.2 Slave and Codec Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Switched-Capacitor Filter Frequency (FCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 Filter Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 Master and Stand-Alone Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.2 Master and Stand-Alone Functional Sequence . . . . . . . . . . . . . . . . . . . . . 2.13 Slave and Codec Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13.1 Slave and Codec Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13.2 Slave Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.1 Frame-Sync Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.2 Data Out (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.3 Data In (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.4 Hardware Program Terminals (FC1 and FC0) . . . . . . . . . . . . . . . . . . . . . . 2.14.5 Midpoint Voltages (ADC VMID and DAC VMID) . . . . . . . . . . . . . . . . . . . . . 2.15 Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.1 Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.2 Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-2 2-2 2-2 2-2 2-2 2-4 2-4 2-4 2-4 2-5 2-6 2-6 2-7 2-9 2-9 2-9 2-9 2-9 2-9 2-9 2-10 2-10 2-11 2-11 2-11 2-11 2-12 2-12 2-12 2-13 2-13 2-13 2-14 iii Contents (Continued) Section 2.16 2.17 2.18 2.19 2.20 3 iv Title Page 2.15.3 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.4 Free-Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.5 Force Secondary Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.6 Enable Analog Input Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15.7 DAC Channel (sin x)/x Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During Primary and Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16.2 Slave and Codec-Mode Word Sequence and Information Content During Primary and Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Request for Secondary Serial Communication and Phase Shift . . . . . . . . . . . . 2.17.1 Initiating a Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17.2 Normal Combinations of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17.3 Additional Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.18.1 Primary Serial Communications Data Format . . . . . . . . . . . . . . . . . . . . . . 2.18.2 Data Format From DOUT During Primary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.19.1 Data Format to DIN During Secondary Serial Communications . . . . . . . 2.19.2 Control Data-Bit Function in Secondary Serial Communication . . . . . . . Internal Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.1 Pseudo-Register 0 (No-Op Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.2 Register 1 (A Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.3 Register 2 (B Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.4 Register 3 (A Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.5 Register 4 (Amplifier Gain-Select Register) . . . . . . . . . . . . . . . . . . . . . . . . 2.20.6 Register 5 (Analog Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . 2.20.7 Register 6 (Digital Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.8 Register 7 (Frame-Sync Delay Register) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.20.9 Register 8 (Frame-Sync Number Register) . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-14 2-14 2-15 2-15 2-15 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, MCLK = 5.184 MHz, VDD = 5 V, Outputs Unloaded, Total Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V, Digital I/O Terminals (DIN, DOUT, EOC, FC0, FC1, FS, FSD, MCLK, M/S, SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-16 2-17 2-17 2-17 2-17 2-18 2-19 2-19 2-19 2-19 2-19 2-20 2-20 2-20 2-21 2-21 2-22 2-22 2-23 2-23 2-24 3-1 3-1 3-1 3-2 3-2 Contents (Continued) Section 3.5 3.6 3.7 Title Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V, ADC and DAC Channels . . . . . . . . . . . . . . . 3.5.1 ADC Channel Filter Transfer Function, FCLK = 144 kHz, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 ADC Channel Input, VDD = 5 V, Input Amplifier Gain = 0 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 ADC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 DAC Channel Filter Transfer Function, FCLK = 144 kHz, fs = 9.6 kHz, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 DAC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 System Distortion, VDD = 5 V, fs = 8 kHz, FCLK = 144 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.7 Noise, Low-Pass and Band-Pass SwitchedCapacitor Filters Included, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.8 Absolute Gain Error, VDD = 5 V, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 Relative Gain and Dynamic Range, VDD = 5 V, fs = 8 kHz . . . . . . . . . . . 3.5.10 Power-Supply Rejection, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11 Crosstalk Attenuation, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.12 Monitor Output Characteristics, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements and Specifications in Master Mode . . . . . . . . . . . . . . . . . 3.6.1 Recommended Input Timing Requirements for Master Mode, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Operating Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements and Specifications in Slave Mode and Codec Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 Recommended Input Timing Requirements for Slave Mode, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Operating Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3-2 3-2 3-3 3-3 3-3 3-4 3-4 3-5 3-5 3-5 3-6 3-6 3-7 3-8 3-8 3-8 3-9 3-9 3-9 4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Appendix A Primary Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Appendix C TLC320AC01C/TLC320AC02C Specification Comparisons . . . . . . . C-1 Appendix D Multiple TLC320AC01/TLC320AC02 Analog Interface Circuits on One TMS320C5X DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Appendix E Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 v List of Illustrations Figure Title Page 1-1 Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2-1 2-2 2-3 2-4 Functional Sequence for Primary and Secondary Communication . . . . . . . . . . . Timing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master and Stand-Alone Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Codec Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4 - 10 2-5 2-6 2-16 2-16 IN+ and IN - Gain-Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AIC Stand-Alone and Master-Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AIC Slave and Codec Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master or Stand-Alone FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave FS to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUT Enable Timing From Hi-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUT Delay Timing to Hi-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EOC Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master-Slave Frame-Sync Timing After a Delay Has Been Programmed Into the FSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11 Master and Slave Frame-Sync Sequence with One Slave . . . . . . . . . . . . . . . . . . 4-5 4-5 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-1 6-1 6-2 6-2 6-3 6-3 6-3 6-4 6-4 Stand-Alone Mode (to DSP Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Codec Mode (to DSP Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master With Slave (to DSP Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Ended Input (Ground Referenced) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Ended to Differential Input (Ground Referenced) . . . . . . . . . . . . . . . . . . . . Differential Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Drive (Ground Referenced) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Impedance Output Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Ended Output Drive (Ground Referenced) . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-2 4-3 4-3 4-3 4-4 4-4 4-4 List of Tables Table Title Page 1-1 Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2-1 2-2 2-3 Master-Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Sampling Variation With A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Software and Hardware Requests for Secondary Serial-Communication and Phase-Shift Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 4-1 Gain Control (Analog Input Signal Required for Full-Scale Bipolar A /D-Conversion 2s Complement) . . . . . . . . . . . . . . . . . . . . . . . 4-1 vi 1 Introduction The TLC320AC01 analog interface circuit (AIC) is an audio-band processor that provides an analog-to-digital and digital-to-analog input/output interface system on a single monolithic CMOS chip. This device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC), a low-pass switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control transfers. The internal circuit configuration and performance parameters are determined by reading control information into the eight available data registers. The register data sets up the device for a given mode of operation and application. The major functions of the TLC320AC01 are: 1. To convert audio-signal data to digital format by the ADC channel 2. To provide the interface and control logic to transfer data between its serial input and output terminals and a digital signal processor (DSP) or microprocessor 3. To convert received digital data back to an audio signal through the DAC channel The antialiasing input low-pass filter is a switched-capacitor filter with a sixth-order elliptic characteristic. The high-pass filter is a single-pole filter to preserve low-frequency response as the low-pass filter cutoff is adjusted. There is a three-pole continuous-time filter that precedes this filter to eliminate any aliasing caused by the filter clock signal. The output-reconstruction switched-capacitor filter is a sixth-order elliptic transitional low-pass filter followed by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to eliminate images of the filter clock signal. The TLC320AC01 consists of two signal-processing channels, an ADC channel and a DAC channel, and the associated digital control. The two channels operate synchronously; data reception at the DAC channel and data transmission from the ADC channel occur during the same time interval. The data transfer is in 2s-complement format. There are three basic modes of operation available: the stand-alone analog-interface mode, the master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC01 generates the shift clock and frame synchronization for the data transfers and is the only AIC used. The master-slave mode has one TLC320AC01 as the master that generates the master-shift clock and frame synchronization; the remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the framesynchronization signals are externally generated and the timing can be any of the standard codec-timing patterns. Typical applications for this device include modems, speech processing, analog interface for DSPs, industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and instrumentation recorders. The TLC320AC01C is characterized for operation from 0C to 70C. The TLC320AC01 is functionally equivalent to the TLC320AC02 and differs in the electrical specifications as shown in Appendix C. 1-1 1.1 Features * General-Purpose Signal-Processing Analog Front End (AFE) * Single 5-V Power Supply * Power Dissipation . . . 100 mW Typ * Signal-to-Distortion Ratio . . . 70 dB Typ * Programmable Filter Bandwidths (Up to 10.8 kHz) and Synchronous ADC and DAC Sampling * Serial-Port Interface * Monitor Output With Programmable Gains of 0 dB, - 8 dB, - 18 dB, and Squelch * Two Sets of Differential Inputs With Programmable Gains of 0 dB, 6 dB, 12 dB, and Squelch * Differential or Single-Ended Analog Output With Programmable Gains of 0 dB, - 6 dB, - 12 dB, and Squelch * Differential Outputs Drive 3-V Peak Into a 600- Differential Load * Differential Architecture Throughout * 1-m Advanced LinEPIC Process * 14-Bit Dynamic-Range ADC and DAC * 2s-Complement Data Format * Application Report Available Designing with the TLC320AC01 Analog Interface for DSPs (SLAA006) LinEPIC is a trademark of Texas Instruments Incorporated. 1-2 1.2 Functional Block Diagram IN + IN - AUX IN + AUX IN - MON OUT M/S FC0 FC1 26 25 28 27 Filter M U X M U X Serial Port ADC 1 12 14 13 18 ADC Channel Internal Voltage Reference DAC Channel 15 16 3 4 (sin x)/x Correction 2 5 PWR DWN DAC VDD 7 DAC GND 9 20 DGTL GND DOUT FS MCLK SCLK 10 DIN 17 FSD Filter OUT + OUT - 11 DGTL VDD 23 24 ADC VMID ADC VDD 22 ADC GND 19 EOC DAC 21 6 SUBS DAC VMID 8 RESET Terminal numbers shown are for the FN package. Terminal Assignments DAC VDD DAC VMID DAC GND RESET DGTL VDD DIN DOUT 5 4 IN + OUT - OUT + PWR DWN MON OUT AUX IN + AUX IN - FN PACKAGE (TOP VIEW) 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 IN - ADC VDD ADC VMID ADC GND SUBS DGTL GND EOC FS SCLK MCLK FC0 FC1 FSD M/S 1.3 1-3 1.3 Terminal Assignments (Continued) 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EOC NC NC NC NC DGTL GND NC SUBS NC NC ADC GND NC NC ADC VMID NC ADC V DD DIN NC DOUT FS NC NC NC SCLK NC MCLK FC0 FC1 NC FSD NC M/S NC DAC VDD NC NC NC NC NC DGTL V DD NC RESET NC NC DAC GND NC NC DAC VMID PM PACKAGE (TOP VIEW) NC - No internal connection 1-4 NC NC OUT- NC NC OUT+ PWR DWN NC MON OUT NC AUXIN + AUXIN - IN + IN - NC NC 1.4 Terminal Functions TERMINAL NO. NAME NO. I/O DESCRIPTION ADC VDD 24 32 I Analog supply voltage for the ADC channel ADC VMID 23 30 O Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be buffered when used as an external reference. ADC GND 22 27 I Analog ground for the ADC channel AUX IN + 28 38 I Noninverting input to auxiliary analog input amplifier AUX IN - 27 37 I Inverting input to auxiliary analog input amplifier DAC VDD 5 49 I Analog supply voltage for the DAC channel DAC VMID 6 51 O Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be buffered when used as an external reference. DAC GND 7 54 I Analog ground for the DAC channel DIN 10 1 I Data input. DIN receives the DAC input data and command information and is synchronized with SCLK. DOUT 11 3 O Data output. DOUT outputs the ADC data results and register read contents. DOUT is synchronized with SCLK. DGTL VDD 9 59 I Digital supply voltage for control logic DGTL GND 20 22 I Digital ground for control logic EOC 19 17 O End-of-conversion output. EOC goes high at the start of the ADC conversion period and low when conversion is complete. EOC remains low until the next ADC conversion period begins and indicates the internal device conversion period. FC0 15 11 I Hardware control input. FC0 is used in conjunction with FC1 to request secondary communication and phase adjustments. FC0 should be tied low if it is not used. FC1 16 12 I Hardware control input. FC1 is used in conjunction with FC0 to request secondary communication and phase adjustments. FC1 should be tied low if it is not used. FS 12 4 I/O Frame synchronization. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data bits. In master mode, FS is low during the simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is externally generated and must be low for one shift-clock period minimum to initiate the data transfer. FSD 17 14 O Frame-synchronization delayed output. This active-low output synchronizes a slave device to the frame synchronization timing of the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but delayed in time by the number of shift clocks programmed in the FSD register. IN + 26 36 I Noninverting input to analog input amplifier IN - 25 35 I Inverting input to analog input amplifier MCLK 14 10 I The master-clock input drives all the key logic signals of the AIC. 1 40 O The monitor output allows monitoring of analog input and is a high-impedance output. 18 16 I Master/slave select input. When M/S is high, the device is the master and when low, it is a slave. MON OUT M/S Terminal numbers shown are for the FN package. Terminal numbers shown are for the PM package. 1-5 1.4 Terminal Functions (Continued) TERMINAL NO. NAME NO. I/O DESCRIPTION OUT+ 3 43 O Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or high-impedance loads directly in a differential connection or a single-ended configuration with a buffered VMID. OUT- 4 46 O Inverting output of analog output power amplifier. OUT- is functionally identical with and complementary to OUT+. PWR DWN 2 42 I Power-down input. When PWR DWN is taken low, the device is powered down such that the existing internally programmed state is maintained. When PWR DWN is brought high, full operation resumes. RESET 8 57 I Reset input that initializes the internal counters and control registers. RESET initiates the serial data communications, initializes all of the registers to their default values, and puts the device in a preprogrammed state. After a low-going pulse on RESET, the device registers are initialized to provide a 16-kHz data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock input signal. 13 8 I/O Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the frame-synchronization interval. When configured as an output (M/S high), SCLK is generated internally by dividing the master clock signal frequency by four. When configured as an input (M/S low), SCLK is generated externally and synchronously to the master clock. This signal clocks the serial data into and out of the device. SCLK SUBS 21 24 I Substrate connection. SUBS should be tied to ADC GND. Terminal numbers shown are for the FN package. Terminal numbers shown are for the PM package. 1-6 Processor 5.184 MHz 10.368 MHz MCLK Divide by 4 SCLK 1.296 MHz 2.592 MHz A Register + A Register (8 bits) 2s Complement A Register (8 bits) FCLK [low-pass filter and (sin x)/x filter clock] Control Normal Phase Shift B Register (8 bits) Single, A-Counter Period One-Shot Program Divide A Counter (8 bits) Conversion Rate Divide by 2 576 kHz B Counter 288 kHz Figure 1-1. Control Flow Diagram Table 1-1. Operating Frequencies FCLK (kHz) LOW-PASS FILTER BANDWIDTH (kHz) 144 3.6 288 432 B REGISTER CONTENTS (Program No. of Filter Clocks) (Decimal) CONVERSION RATE (kHz) HIGH-PASS POLE FREQUENCY (Hz) 20 (see Note 1) 18 15 10 (see Note 2) 7.2 8 9.6 14.4 36 40 48 72 7.2 20 (see Note 1) 18 15 10 (see Notes 2 and 3) 14.4 16 19.2 28.8 72 80 96 144 10.8 20 (see Note 1) 18 15 (see Note 3) 10 (see Notes 2 and 3) 21.6 24 28.8 43.2 108 120 144 216 NOTES: 1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than 7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required. 2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not completed before the next frame-sync signal and the results are in error. 3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is 25 kHz. 1-7 1.5 Register Functional Summary There are nine data registers that are used as follows: Register 0 The No-op register. The 0 address allows phase adjustments to be made without reprogramming a data register. Register 1 The A register controls the count of the A counter. Register 2 The B register controls the count of the B counter. Register 3 The A register controls the phase adjustment of the sampling period. The adjustment is equal to the register value multiplied by the input master period. Register 4 The amplifier gain register controls the gains of the input, output, and monitor amplifiers. Register 5 The analog configuration register controls: Register 6 * The addition/deletion of the high-pass filter to the ADC signal path * The enable/disable of the analog loopback * The selection of the regular inputs or auxiliary inputs * The function that allows processing of signals that are the sum of the regular inputs and the auxiliary inputs (VIN + VAUX IN) The digital configuration register controls: * Selection of the free-run function * FSD [frame-synchronization (sync) delay] output enable/disable * Selection of 16-bit function * Forcing secondary communications * Software reset * Software power down Register 7 The frame-sync delay register controls the time delay between the master-device frame sync and slave-device frame sync. Register 7 must be the last register programmed when using slave devices since all register data is latched and valid on the sixteenth falling edge of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted by this programmed amount. Register 8 The frame-sync number register informs the master device of the number of slaves that are connected in the chain. The frame-sync number is equal to the number of slaves plus one. 1-8 2 2.1 Detailed Description Definitions and Terminology ADC Channel Codec Mode d Dxx DAC Channel All signal processing circuits between the analog input and the digital conversion results at DOUT The operating mode under which the device receives shift clock and frame-sync signals from a host processor. The device has no slaves. The d represents valid programmed or default data in the control register format (see Section 2.19) when discussing other data-bit portions of the register. Bit position in the primary data word (xx is the bit number) All signal processing circuits between the digital data word applied to DIN and the differential output analog signal available at OUT+ and OUT- Data Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16 shift clocks regardless of whether the shift clock is internally or externally generated. The data transfer is initiated by the falling edge of the frame-sync signal. DSxx Bit position in the secondary data word (xx is the bit number) FCLK An internal clock frequency that is a division of MCLK that controls the low-pass filter and (sinx)/x filter clock (see Figure 1-1 and Table 1-1). fi The analog input frequency of interest Frame Sync The falling edge of the signal that initiates the data-transfer interval. The primary frame sync starts the primary communications, and the secondary frame sync starts the secondary communications. Frame Sync and The time between falling edges of successive primary frame-sync signals Sampling Period Frame-Sync Interval The time period occupied by 16 shift clocks. Regardless of the mode of operation, there is always an internal frame-sync interval signal that goes low on the rising edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK. The sampling frequency that is the reciprocal of the sampling period. fs Host Any processing system that interfaces to DIN, DOUT, SCLK, or FS. Master Mode The operating mode under which the device generates and uses its own shift clock and frame-sync signal and generates all delayed frame-sync signals necessary to support slave devices. Phase Adjustment The programmed time variation from the falling edge of one frame-sync signal to the falling edge of the next frame sync signal. The time variation is determined by the contents of the A register. Since the time between falling edges of successive frame-sync signals is the the sampling period, the sampling period is adjusted. Primary (Serial) The digital data-transfer interval. Since the device is synchronous, the signal data Communications words from the ADC channel and to the DAC channel occur simultaneously. Secondary (Serial) The digital control and configuration data-transfer interval into DIN and the register Communications read-data cycle from DOUT. The data-transfer interval occurs when requested by hardware or software. Signal Data The input signal and all of the converted representations through the ADC channel and return through the DAC channel to the analog output. This is contrasted with the purely digital software-control data. Slave Mode The operating mode under which the device receives shift clock and frame-sync signals from a master device. 2-1 Stand-Alone Mode The operating mode under which the device generates and uses its own shift clock and frame-sync signal. The device has no slave devices. X The X represents a don't-care bit position within the control register format. 2.2 Reset and Power-Down Functions 2.2.1 Reset The TLC320AC01 resets both the internal counters and registers, including the programmed registers, by any of the following: * * * Applying power to the device, causing a power-on reset (POR) Applying a low reset pulse to RESET Reading in the programmable software reset bit (DS01 in register 6) PWR DWN resets the counters only and preserves the programmed register contents. 2.2.2 Conditions of Reset The two internal reset signals used for the reset and synchronization functions are as follows: 1. Counter reset: This signal resets all flip-flops and latches that are not externally programmed with the exception of those generating the reset pulse itself. In addition, this signal resets the software power-down bit. Counter reset = power-on reset + RESET + RESET bit + PWR DWN 2. Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset except those generating the reset pulse itself. Register reset = power-on reset + RESET + RESET bit Both reset signals are at least one master-clock period long and release on the falling edge of the master clock. 2.2.3 Software and Hardware Power-Down Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared by resetting the software bit (DS00 in register 6) to zero. It is also cleared by either cycling the power to the device, bringing PWR DWN low, or bringing RESET low. PWR DWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling PWR DWN high to low and back to high resets all flip-flops and latches that are not externally programmed, thereby preserving the register contents. When PWR DWN is not used, it should be tied high. 2.2.4 Register Default Values After POR, Software Reset, or RESET Is Applied Register 1 - The A Register The default value of the A-register data is decimal 18 as shown below. 2-2 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 1 0 0 1 0 Register 2 - The B Register The default value of the B-register data is decimal 18 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 1 0 0 1 0 Register 3 - The A Register The default value of the A-register data is decimal 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 Register 4 - The Amplifier Gain-Select Register The default value of the amplifier gain-select register data is shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 1 0 1 Register 5 - The Analog Control-Configuration Register The power-up and reset conditions are as shown below. In the read mode, 8 bits are read but the 4 LSBs are repeated as the 4 MSBs. DS03 DS02 DS01 DS00 0 0 0 1 Register 6 - The Digital Configuration Register The default value of DS07 - DS00 is 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 Register 7 - The Frame-Sync Delay Register The default value of DS07 - DS00 is 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 Register 8 - The Frame-Sync Number Register The default value of DS07 - DS00 is 1 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 1 2-3 2.3 Master-Slave Terminal Function Table 2-1 describes the function of the master/slave (M/S) input. The only difference between master and slave operations in the TLC320AC01 is that SCLK and FS are outputs when M/S is high and inputs when M/S is low. Table 2-1. Master-Slave Selection MODE Master and Stand Alone M/S FS SCLK H Output Output Slave and Codec Emulation L Input Input When the stand-alone mode is desired or when the device is permanently in the master mode, M/S must be high. 2.4 ADC Signal Channel To produce excellent common-mode rejection of unwanted signals, the analog signal is processed differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the input amplifier. The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit digital words, representing sampled values of the analog input signal, are clocked out of the serial port (DOUT), one word for each primary communication interval. During secondary communications, the data previously programmed into the registers can be read out with the appropriate register address and with the read bit set to 1. When a register read is not requested, all 16 bits are 0. 2.5 DAC Signal Channel DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing filter. An output buffer with three software-programmable gains (0 dB, - 6 dB, and - 12 dB), as shown in register 4, drives the differential outputs OUT + and OUT -. A squelch mode can also be programmed for the output buffer. During secondary communications, the configuration program data are read into the device control registers. 2.6 Serial Interface The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN. During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into DIN. The functional sequence is shown in Figure 2-1. 2-4 AAAAAA AAAAAA AAAAAA AAAAAA AAAA AAAA AAA AAA [ (B register)/2] FCLK Periods Frame-Sync Interval (primary communication) SCLK Frame-Sync Interval (secondary communication) 16 SCLKs FS DOUT 16 SCLKs ADC Conversion Result DIN Register Read Data or All 0s A A A DAC Input Data AAAAAAAA A A Control and Device Parameter Data The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods. Figure 2-1. Functional Sequence for Primary and Secondary Communication 2.7 Number of Slaves The maximum number of slaves is determined by the sum of the individual device delays from the frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1: (n) / tp(FS - FSD) < 1/2 shift-clock period (1) Where: n is the number of slave devices. Example: From equation 1 above, the number of slaves is given by equation 2: (n) v 12 x (SCLK period) x * FSD) 1 tp(FS (2) assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS - FSD) is 40 ns, then according to equation 3, the number of slaves is: n v 2.59651 MHz x 1 x 1 2 40 ns + 1000 + 4.8 192 (3) The maximum number of slaves under these conditions is four. 2-5 2.8 Required Minimum Number of MCLK Periods Master with slave operation is summarized in the following sections. 2.8.1 TLC320AC01 AIC Master-Slave Summary After initial setup and the master and slave frame syncs are separated, when secondary communication is needed for a slave device, a 11 must be placed in the 2 LSBs of each primary data word for all devices in the system, master and slave, by the host processor. In other words, all AICs must receive secondary frame requests. The host processor must issue the command by setting D01 and D00 to a 1 in the primary frame sync data word of all devices. Then the master generates the master primary frame sync and, after the number of shift clocks set by the FSD register value, the slave primary frame sync intervals. Then, after (B register value/2) FCLK periods, the master secondary frame sync occurs first, and then the slave secondary frame sync occurs. These are also rippled through the slave devices. In other words, when a secondary communications interval is requested by the host processor as described above: 1. The master outputs the master primary frame sync interval, and then the slave primary frame sync intervals after the FSD register value number of shift clocks. 2. After (B register value/2) FCLK periods, the master then outputs the master secondary frame sync interval, and after the FSD register value number of shift clocks, the slave secondary frame sync intervals. This sequence is shown in Figure 2-2. The host must keep track of whether the master or a slave is then being addressed and also the number of slave devices. The master always outputs a 00 in the last 2 bits of the DOUT word, and a slave always outputs a 1 in the LSB of the DOUT word. This information allows the system to recognize a starting point by interrogating the least significant bit of the DOUT word. If the LSB is 0, then that device is the master, and the system is at the starting point. Note: This identification always happens except in 16-bit mode when the 2 LSBs are not available for identification purposes. (B Register Value/2) FCLK Periods Sampling Period FSD Value in SCLKs Frame Sync Sequence Period Symbol MP SP1 SP2 SPn MS SS1 SS2 SSn Periods shown: Each period must be a minimum of 16 SCLKs plus 2 additional SCLKs MP SP1 SP2 SPn = Master Primary Period = 1st Slave Primary Period = 2nd Slave Primary Period = nth Slave Primary Period MS SS1 SS2 SSn = Master Secondary Period = 1st Slave Secondary Period = 2nd Slave Secondary Period = nth Slave Secondary Period Figure 2-2. Timing Sequence 2-6 MP 2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation Master/slave operational detail is summarized in the following notes: 1. The slave devices can be programmed independently of the master as long as the clock divide register numbers are not changed. The gain settings, for example, can be changed independently. 2. The method that is used to program a slave independently is to request a secondary communication of the master and all slaves and ripple the delayed frame sync to the desired slave device to be programmed. 3. Secondary frame syncs must be requested for all devices in the system or none. This is required so that the master generates secondary frames for the slaves and allows the slaves to know that the second frame syncs they receive are secondary frame syncs. Each device in the system must receive a secondary frame request in its corresponding primary frame sync period (11 in the last 2 LSBs). 4. Calculation of the sampling frequency in terms of the master clock and the shift clock and the respective register ratios is (see equations 4-6): FCLK Sampling frequency fs B register value + + f(MCLK) + 2 (A register value) (B register value) (4) Therefore, f(MCLK) fs +2 (A register value) (B register value) (5) and in terms of the shift clock frequency, since f(MCLK) +4 f(SCLK) fs + (A register value) 2 (B register value) f(SCLK) then of SCLK periods + Number Sampling period 5. (6) The minimum number of shift clocks between falling edges of any two frame syncs is 18 because the frame sync delay register minimum number is 18. When a secondary communication is requested by the host, the master secondary frame sync begins at the middle of the sampling period (followed by the slave secondary frame syncs), so all primary frame sync intervals (master and slave) must occur within one-half the sampling time. 2-7 The first secondary frame-sync falling edge, therefore, occurs at the following time (see equation 7): B register value (FCLK periods) Time to first secondary frame sync 2 + + B register value (number of MCLK periods) + A register value A register value B register value 4 6. (number of SCLK periods) (7) Number of frame sync intervals using equation 8. All master and slave primary frame sync intervals must occur within the time of equation 7. Since 18 shift clocks are required for each frame sync interval, then the number of frame sync intervals from equation 8 is: Number of frame sync intervals value B register value + 4A register 18 (SCLKsframe sync interval) + A register value 72 B register value 7. (8) Number of devices, master and slave, in terms of f(MCLK) and fs. Substituting the value from equation 5 for the A x B register value product gives the total number of devices, including the master and all slaves that can be used, for a given master clock and sampling frequency. Therefore, using equation 9: Number of devices 8. f(MCLK) + 144 fs (9) Number of devices, master and slave, if slave devices are reprogrammed. Equation 9 does not include reprogramming the slave devices after the frame sync delay occurs. So if programming is required after shifting the slave frame syncs by the FSD register, then the total number of devices is given by equation 10 is: Number of devices 9. f(MCLK) + 288 fs Example of the maximum number of devices if the slave devices are reprogrammed assuming the following values: f(MCLK) + 10.368 MHz, fs + 8 kHz then from equation 10, Maximum number of devices MHz + 4.5 + 10.368 288 (8 kHz) therefore, one master and three slaves can be used. 2-8 (10) 2.9 Operating Frequencies 2.9.1 Master and Stand-Alone Operating Frequencies The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11: fs + Sampling (conversion) frequency + (A register value) MCLK (B register value) 2 (11) The inverse is the time between the falling edges of two successive primary frame-synchronization signals. The input and output data clock (SCLK) frequency is given in equation 12: SCLK frequency 2.9.2 + MCLK frequency 4 (12) Slave and Codec Operating Frequencies The slave operating frequencies are either the default values or programmed by the control data word from the master and codec conversion and the data frequencies are determined by the externally applied SCLK and FS signals. 2.10 Switched-Capacitor Filter Frequency (FCLK) The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the B counter clock. The frequency of the filter clock is derived by equation 13: FCLK + (A registerMCLK value) (13) 2 2.11 Filter Bandwidths The low-pass (LP) filter - 3 dB corner is derived in equation 14: f (LP) + FCLK + 40 40 MCLK (A register value) (14) 2 The high-pass (HP) filter - 3 dB corner is derived in equation 15: f (HP) + Sampling200frequency + 200 2 MCLK (A register value) (B register value) (15) 2.12 Master and Stand-Alone Modes The difference between the master and stand-alone modes is that in the stand-alone mode there are no slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are derived from the input master clock.The master clock applied at the MCLK input determines the internal device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long). To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync occurs approximately 648 master clocks after the reset condition disappears. 2.12.1 Register Programming All register programming occurs during secondary communications, and data is latched and valid on the sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles are required to set up the eight programmable registers. Registers 1 through 8 are programmed in secondary communications intervals 1 through 8, respectively. If the default value for a particular register is desired, that register does not need to be addressed during the secondary communications. The no-op command addresses the pseudo-register (register 0), and no register programming takes place during this communications. The no-op command allows phase shifts of the sampling period without reprogramming any register. During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back 2-9 during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the register is in the read mode, no data can be written to the register during this cycle. To return this register to the write mode requires a subsequent secondary communication (see Section 2.19 for detailed register description). 2.12.2 Master and Stand-Alone Functional Sequence The A counter counts according to the contents of the A register, and the A counter frequency is divided by two to produce the filter clock (FCLK). The B counter is clocked by FCLK with the following functional sequence: 1. The B counter starts counting down from the B register value minus one. Each count remains in the counter for one FCLK period including the zero count. This total counter time is referred to as the B cycle. The end of the zero count is called the end of B cycle. 2. When the B counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts. 3. The A-to-D conversion is complete ten FCLK periods later. 4. FS goes low on a rising edge of SCLK after the A-to-D conversion is complete. That rising edge of SCLK must be preceded by a falling edge of SCLK, which is the first falling edge to occur after the end of B cycle. 5. The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is complete ten FCLK periods later. 2.13 Slave and Codec Modes The only difference between the slave and codec modes is that the codec mode is controlled directly by the host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are both externally generated and must be synchronous with MCLK. The conversion frequency is set by the time interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5 of register 6 (see Section 2.15.4). The slave device or devices share the shift clock generated by the master device but receive the frame sync from the previous slave in the chain. The Nth slave FS receives the (N -1)st slave FSD output and so on. The first slave device in the chain receives FSD from the master. 2-10 2.13.1 Slave and Codec Functional Sequence The A counter counts according to the contents of the A register, and the A counter frequency is divided by two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through 3 of the B cycle description in the master mode but differs as follows: 1. Same as master 2. Same as master 3. Same as master 4. All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle. 5. All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes low. This operation provides the synchronization necessary when using an external FS signal. 6. The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval at the end of the 16-shift clock data transfer. In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are externally generated and provide the timing for the ADC and DAC if the free-run function has not been selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments; however, any required phase adjustments must be made by adjusting the external frame-sync timing (sampling time). 2.13.2 Slave Register Programming When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as the master frame-sync signal and all slave devices are programmed during the master secondary framesync interval with the same data as the master. The last register programmed must be the frame-sync delay (FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that frame- sync interval. After the FSD register programming is completed for the master and slave, the slave primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host serial port for data transfers for itself and all slave devices. The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master frame-sync intervals are separated in time by the delay time specified by the FSD register (register 7). These master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide the data-transfer time slot for the slave devices. 2.14 Terminal Functions 2.14.1 Frame-Sync Function The frame-sync signal indicates that the device is ready to send and receive data for both master and slave modes. The data transfer begins on the falling edge of the frame-sync signal. 2.14.1.1 Frame Sync (FS), Master Mode The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the 16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame sync for each slave that is being used. 2-11 2.14.1.2 Frame-Sync Delayed (FSD), Master Mode For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for the time delay through the master and slave devices. The timing relationships are as follows: 1. When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising edge of SCLK when FS goes low (see Figure 4 - 4). 2. When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that is the FSD register number of SCLKs after the falling edge of FS. Register data values from 1 to 17 should not be used. 2.14.1.3 Frame Sync (FS), Slave Mode The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized and can remain low until the next data frame is required. 2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode This output is fed from the master to the first slave and the first slave FSD output to the second and so on down the chain. The FSD timing sequence in the slave mode is as follows: 1. When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4 - 5). 2. When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is the FSD register number of SCLKs after the falling edge of FS. Data values from 1 to 17 should not be used. 2.14.2 Data Out (DOUT) DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external) after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion result. In the secondary communication, the data is the register read results when requested by the read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If no register read is requested, the secondary word is all zeroes. 2.14.2.1 Data Out, Master Mode In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The most significant data bit then appears on DOUT. 2.14.2.2 Data Out, Slave Mode In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4 - 7). The falling edge of frame sync can occur 1/4 SCLK period around the SCLK rising edge (see Figure 4 - 3). The most significant data bit then appears on DOUT. 2.14.3 Data In (DIN) In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary communication, the data is the control and configuration data to set up the device for a particular function (see Section 2.16). 2.14.4 Hardware Program Terminals (FC1 and FC0) These inputs provide for hardware programming requests for secondary communication or phase adjustment. These inputs work in conjunction with the control bits D01 and D00 of the primary data word or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FC0 are latched on the rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should be tied low if not used (see Section 2.17 and Table 2-3). 2-12 2.14.5 Midpoint Voltages (ADC VMID and DAC VMID) Since the device operates at a single-supply voltage, two midpoint voltages are generated for internal signal processing. ADC VMID is used for the ADC channel reference, and DAC VMID is used for the DAC channel reference. Two references minimize channel-to-channel noise and crosstalk. ADC VMID and DAC VMID must be buffered when used as a reference for external signal processing. 2.15 Device Functions 2.15.1 Phase Adjustment In some applications, such as modems, the device sampling period may require an adjustment to synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC01 can adjust the sampling period through the use of the A register and the control bits. 2.15.1.1 Phase-Adjustment Control A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted according to the data value in the A register, and the phase adjustment is that number of master clocks (MCLK). An adjustment is made during device operation with data bits D01 and D00 in the primary communication, with data bits DS15 and DS14 in the secondary word or in combination with the hardware terminals FC1 and FC0 (see Table 2 - 3). This adjustment request is latched on the rising edge of the next internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment, another phase request must be initiated. 2.15.1.2 Use of the A Register for Phase Adjustment The A register value makes slight timing adjustments to the sampling period. The sampling period increases or decreases according to the sign of the programmed A register value and the state of data bits D01 and D00 in the primary data word. The general equation for the conversion frequency is given in equation 16: fs = conversion frequency + (2 A register value MCLK B register value) " (A register value) (16) Therefore, if A = 0, the device conversion (sampling) frequency and period is constant. If a nonzero A value is programmed, the sampling frequency and period responds as shown in Table 2-2. Table 2-2. Sampling Variation With A SIGN OF THE A REGISTER VALUE D01 D00 PLUS VALUE (+) NEGATIVE VALUE (-) 0 1 (increase command) Frequency decreases, period increases Frequency increases, period decreases 1 0 (decrease command) Frequency increases, period decreases Frequency decreases, period increases An adjustment to the sampling period, which must be requested through D01 and D00 of the primary data word to DIN, is valid for the following sampling period only. When the adjustment is required for the subsequent sampling period, it must be requested again through D01 and D00 of the primary data word. For each request, only the sampling period occurring immediately after the primary data word request is affected. 2-13 The amount of time shift in the entire sampling period (1/fs) is as follows: When the sampling period is set to 125 s (8 kHz), the A register is loaded with decimal 10 and the TLC320AC01 master clock frequency is 10.386 MHz. The amount of time each sampling period is increased or decreased, when requested, is given in equation 17: Time shift = (A register value) x (MCLK period) (17) The device changes the entire sampling period by only the MCLK period times the A register value as given in equation 18: Change in sampling period = contents of A register x master clock period = 10 x 96.45 ns = 964 ns (less than 1% of the sampling period) (18) The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data word (i.e., once per sampling period). It is evident then that the change in sampling period is very small compared to the sampling period. To observe this effect over a long period of time ( > sampling period), this change must be continuously requested by the primary data word. If the adjustment is not requested again, the sampling period changes only once and it may appear that there was no execution of the command. This is especially true when bench testing the device. Automatic test equipment can test for results within a single sampling period. Internally, the A register value only affects one cycle (period) of the A counter. The A and A values are additive, but only for one A-counter period. The A counter begins the first count at the default or programmed A-register value and counts down to the A-register value. As the A value increases or decreases, the first clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter period affected by the A register such that only this single period is increased or decreased. 2.15.2 Analog Loopback This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT- are internally connected to IN + and IN -. The DAC data bits D15 to D02 that are applied to DIN can be compared with the ADC output data bits D15 to D02 at DOUT. There are some differences due to the ADC and DAC channel offset. The loopback function is implemented by setting DS01 and DS00 to zero in control register 5 (see Section 2.19). When analog loopback is enabled, the external inputs to IN+ and IN- are disconnected, but the signals at OUT+ and OUT- may still be read. 2.15.3 16-Bit Mode In the 16-bit mode, the device ignores the last two control bits (D01 and D00) of the primary word and requests continual secondary communications to occur. By ignoring the last two primary communication bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting bit DS03 to 1 in register 6. To return to normal operation, DS03 must be reprogrammed to 0. 2.15.4 Free-Run Mode With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer. The ADC and DAC timing are controlled by the A and B register values, and the phase-shift adjustment must be done as if the device is in stand-alone mode (by the software or the state of FC1 and FC0). Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and B registers). When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the external frame sync takes precedence over an internal load command. The latching of the ADC conversion data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock. 2.15.5 Force Secondary Communication With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software and hardware requests concerning secondary communication. Phase shifting, however, can still be performed with the software and hardware. 2-14 2.15.6 Enable Analog Input Summing By setting bits DS01 and DS00 to 11 in register 5, the normal analog input voltage is summed with the auxiliary input voltage. The gain for the analog input amplifier is set by data bits DS03 and DS02 in register 4. 2.15.7 DAC Channel (sin x)/x Error Correction The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the filter cannot be removed from the signal path, operation using another B-register value results in an error in the reconstructed analog output. The error is given by equation 19. Any error compensation needed by a given application can be performed in the software. DAC channel frequency response error + 20 sin log 10 sin 2p A B f MCLK 30p A f MCLK f f 15 B (19) where: f fMCLK A B = the frequency of interest = the TLC320AC01 master-clock frequency = the A-register value = the B-register value and the arguments of the sin functions are in radians. 2.16 Serial Communications 2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During Primary and Secondary Communications For the stand-alone and master modes, the sequence in Figure 2-2 shows the relationship between the primary and secondary communications interval, the data content into DIN, and the data content from DOUT. The TLC320AC01 can provide a phase-shift command or the next secondary communications interval by decoding 1) the programmed state of the FC1 and FC0 inputs and the D01 and D00 data bits in the primary data word, or 2) the state of the FC1 and FC0 inputs and the DS15 and DS14 data bits in the secondary data word (see Table 2 - 3). When DS13 (the R/W bit) is the default value of 0, all 16 bits from DOUT are 0 during secondary communication. However, when the R/W bit is set to 1 in the secondary communication control word, the secondary transmission from DOUT still contains 0s in the eight MSBs. The lower order 8 bits contain the data of the register currently being addressed. This function provides register status information for the host. 2-15 [ (B register)/2] FCLK Periods Primary Frame Sync (16 SCLKs long) Secondary Frame Sync (16 SCLKs long) DOUT 2s-Complement ADC Output (14 bits plus 00 for the two LSBs) 16 Bits All 0s, Except When in Read Mode (then least significant 8 bits are register data) DIN 2s-Complement Input for the DAC Channel (14 bits plus two function bits). If the 2 LSBs Are Set to 1, Secondary Frame Sync Is Generated by the TLC320AC01 Input Data for the Internal Registers (16 bits containing control, address, and data information) FS The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods. Figure 2-3. Master and Stand-Alone Functional Sequence 2.16.2 Slave and Codec-Mode Word Sequence and Information Content During Primary and Secondary Communications For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes with the exception that the frame sync and the shift clock are generated and controlled externally as shown in Figure 2-3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted externally if required. 1 SCLK Minimum 1 SCLK Minimum FS Primary Frame Sync Secondary Frame Sync DOUT 2s-Complement ADC Output (14 bits plus 00 for the 2 LSBs in master and stand-alone mode and 01 in slave mode) 16 Bits, All 0s, Except When in Read Mode (then least significant 8 bits are register data) DIN 2s-Complement Input for the DAC Channel (14 bits plus two function bits) Input Data for the Internal Registers (16 bits containing control, address, and data information) NOTE A: The time between the primary and secondary frame syncs is determined by the application; however, enough time must be provided so that the host can execute the required number of software instructions in the time between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling edge of the secondary frame sync (start of secondary communications). Figure 2-4. Slave and Codec Functional Sequence 2-16 2.17 Request for Secondary Serial Communication and Phase Shift The following paragraphs describe a request for secondary serial communication and phase shift using hardware control inputs FC1 and FC0, primary data bits D01 and D00, and secondary data bits DS15 and DS14. 2.17.1 Initiating a Request Combinations of FC1 and FC0 input conditions, bits D01 and D00 in the primary serial data word, FC1 and FC0, and bits DS15 and DS14 in the secondary serial data word can initiate a secondary serial communication or request a phase shift according to the following rules (see Table 2-3). 1. Primary word phase shifts can be requested by either the hardware or software when the other set of signals are 11 or 00. If both hardware and software request phase shifts, the software request is performed. 2. Secondary words can be requested by either the software or hardware at the same time that the other set of signals is requesting a phase shift. 3. Hardware inputs FC1 and FC0 are ignored during the secondary word unless DS15 and DS14 are 11. When DS15 and DS14 are 01 or 10, the corresponding phase shift is performed. When DS15 and DS14 are 00, no phase shift is performed even when the hardware requests a phase shift. 2.17.2 Normal Combinations of Control The normal combinations of control are as follows: 1. Use D01 and D00 and DS15 and DS14 to request phase shifts and secondary words by holding FC1 and FC0 to 00. 2. Use FC1 and FC0 exclusively to request phase shifts and secondary words by holding D01 and D00 to 00 and DS15 and DS14 to 11. 3. Use D01 and D00 only to request secondary words and FC1 and FC0 to perform phase shifts once per period by holding DS15 and DS14 to 00. 2.17.3 Additional Control Options Additional control options are unusual and are rarely needed or used; however, they are as follows: 1. Use D01 and D00 only to request secondary words and FC1 and FC0 to perform phase shifts twice per period by holding DS15 and DS14 to 11. 2. Use FC1 and FC0 exclusively to request secondary words and D01 and D00 and DS15 and DS14 to perform phase shifts twice per period. 3. Use FC1 and FC0 to perform the phase shift after the primary word and DS15 and DS14 to perform a phase shift after the secondary word by holding D01 and D00 to 11. 2-17 Table 2-3. Software and Hardware Requests for Secondary Serial-Communication and Phase-Shift Truth Table WITHIN PRIMARY OR SECONDARY DATA WORD Primary Secondary CONTROL BITS HARDWARE TERMINALS PHASE-SHIFT ADJUSTMENT (see Section 2.15.1) D01 D00 FC1 FC0 EARLIER LATER 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 DS15 DS14 FC1 FC0 EARLIER LATER 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 SECONDARY REQUEST (see Note 1) No request can be made for secondary communication within the secondary word. NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a secondary communication is being requested. 2.18 Primary Serial Communications Primary serial communications transfer the 14-bit DAC input plus two control bits (D01 and D00) to DIN of the TLC320AC01.They simultaneously transfer the 14-bit ADC conversion result from DOUT to the processor. The 2 LSBs are set to 0 in the ADC result. 2-18 2.18.1 D15 Primary Serial Communications Data Format D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 14-bit DAC Conversion Result 2s-Complement Format D01 D00 Control Bits Since the supply voltage is single ended, the reference for 2s-complement format is ADC VMID. Voltages above this reference have a 0 as the MSB, and voltages below this reference have a 1 as the MSB. During primary serial communications, when D01 and D00 are both high in the DAC data word to DIN, a subsequent 16 bits of control information is received by the device at DIN during a secondary serial-communication interval. This secondary serial-communication interval begins at 1/2 the programmed conversion time when the B register data value is even or 1/2 the programmed value minus one FCLK when the B register data value is odd. The time between primary and secondary serial communication is measured from the falling edge of the primary frame sync to the falling edge of the secondary frame sync (see Section 2.19 for function and format of control words). 2.18.2 D15 Data Format From DOUT During Primary Serial Communications D14 D13 D12 D11 D10 D09 D08 D07 D06 14-Bit ADC Conversion Result 2s-Complement Format D15 is the Sign Bit D05 D04 D03 D02 D01 D00 +0 +0 D01 + 0 D00 + 1 Master Mode D01 D00 Slave Mode 2.19 Secondary Serial Communications 2.19.1 Data Format to DIN During Secondary Serial Communications There are nine 16-bit configuration and control registers numbered from zero to eight. All register data contents are represented in 2s-complement format. The general format of the commands during secondary serial communications is as follows. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits (2 bits) R/W Bit Register Address (5 bits) Register Data Value (8 bits) All control register words are latched in the register and valid on the sixteenth falling edge of SCLK. 2.19.2 Control Data-Bit Function in Secondary Serial Communication 2.19.2.1 DS15 and DS14 In the secondary data word, bits DS15 and DS14 perform the same control function as the primary control bits D01 and D00 do in the primary data word. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W Register Address Register Data Hardware terminals FC1 and FC0 are valid inputs when DS15 and DS14 are both high, and they are ignored for all other conditions. 2-19 2.19.2.2 DS13 (R/W Bit) Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set to 1, however, the previous data content of the register being addressed is read out to the host from DOUT as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to 0. Reading the data out is nondestructive, and the contents of the register remain unchanged. A. Write Mode (DS13 = 0) Data In. The data word to DIN has the following general format in the write mode. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits 0 Register Address Register Data Data Out. The shift clock shifts out all 0s as the pattern to the host from DOUT. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B. Read Mode (DS13 = 1) Data In. The data word to DIN has the following format to allow a register read. Phase shifts can also be done in the read mode. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits 1 Register Address Ignored Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in the 8 LSBs. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 Register Data 2.20 Internal Register Format 2.20.1 Pseudo-Register 0 (No-Op Address) This address represents a no-operation command. No register I/O operation takes place, so the device can receive secondary commands for phase adjustment without reprogramming any register. A read of the no-op is 0. The format of the command word is as follows: DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits 2.20.2 X 0 0 0 0 0 X X X X X X X X Register 1 (A Register) The following command loads DS07 (MSB) - DS00 into the A register. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R / W 0 0 0 0 1 Register Data The data in DS07 - DS00 determines the division of the master clock to produce the internal FCLK. FCLK frequency = MCLK/(A register contents x 2) 2-20 The default value of the A-register data is decimal 18 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 2.20.3 0 0 1 0 0 1 0 Register 2 (B Register) The following command loads DS07 (MSB) - DS00 into the B register. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 0 1 0 Register Data The data in DS07 - DS00 controls the division of FCLK to generate the conversion clock as given in equation 20: + FCLK(B register contents) MCLK + 2 A register contents B register contents Conversion frequency (20) The default value of the B-register data is decimal 18 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 2.20.4 0 0 1 0 0 1 0 Register 3 (A Register) The following command contains the A-register address and loads DS07(MSB) - DS00 into the A register. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 0 1 1 Register Data The data in DS07 - DS00 is in 2s-complement format and controls the number of master-clock periods that the sampling time is shifted. The default value of the A-register data is 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 2-21 2.20.5 Register 4 (Amplifier Gain-Select Register) The following command contains the amplifier gain-select register address with selection code for the monitor output (DS05 - DS04), analog input (DS03 - DS02), and analog output (DS01 - DS00) programmable gains. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 1 0 0 X X Monitor output gain = squelch Monitor output gain = 0 dB Monitor output gain = - 8 dB Monitor output gain = - 18 dB * * 0 0 1 1 0 1 0 1 Analog input gain = squelch Analog input gain = 0 dB Analog input gain = 6 dB Analog input gain = 12 dB * 0 0 1 1 * * * 0 1 0 1 Analog output gain = squelch Analog output gain = 0 dB Analog output gain = - 6 dB Analog output gain = - 12 dB 0 0 1 1 0 1 0 1 The default value of the monitor output gain is squelch, which corresponds to data bits DS05 and DS04 equal to 00 (binary). The default value of the analog input gain is 0 dB, which corresponds to data bits DS03 and DS02 equal to 01 (binary). The default value of the analog output gain is 0 dB, which corresponds to data bits DS01 and DS00 equal to 01 (binary). The default data value is shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 2.20.6 0 0 0 0 1 0 1 Register 5 (Analog Configuration Register) The following command loads the analog configuration register with the individual bit functions described below. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 1 0 1 X X X * * Analog loopback enabled 0 0 Enables IN + and IN - (disables AUXIN + and AUXIN -) 0 1 Enables AUXIN + and AUXIN - (disables IN + and IN -) 1 0 Enable analog input summing 1 1 Must be set to 0 High-pass filter disabled High-pass filter enabled X * * 0 1 0 The default value of the high-pass-filter enable bit is 0, which places the high-pass filter in the signal path. The default values of DS01 and DS00 are 0 and 1 which enables IN + and IN -. 2-22 The power-up and reset conditions are as shown below. DS03 DS02 DS01 DS00 0 0 0 1 In the read mode, eight bits are read but the 4 LSBs are repeated as the 4 MSBs. 2.20.7 Register 6 (Digital Configuration Register) The following command loads the digital configuration register with the individual bit functions described below. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 1 1 0 X X * ADC and DAC conversion free run Inactive * * * * * 1 0 FSD output disable Enable 1 0 16-Bit mode, ignore primary LSBs Normal operation 1 0 Force secondary communications Normal operation 1 0 Software reset (upon reset, this bit is automatically reset to 0) Inactive reset 1 0 Software power-down active (automatically reset to 0 after PWR DWN is cycled high to low and back to high) 1 Power-down function external (uses PWR DWN) 0 The default value of DS07 - DS00 is 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 2.20.8 0 0 0 0 0 0 0 Register 7 (Frame-Sync Delay Register) The following command contains the frame-sync delay (FSD) register address and loads DS07 (MSB) - DS00 into the FSD register. The data byte (DS01 - DS00) determines the number of SCLKs between FS and the delayed frame-sync signal, FSD. The minimum data value for this register is decimal 18. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 0 1 1 1 Register Data The default value of DS07 - DS00 is 0 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 0 0 0 0 0 0 0 When using a slave device, register 7 must be the last register programmed. 2-23 2.20.9 Register 8 (Frame-Sync Number Register) The following command contains the frame-sync number (FSN) register address and loads DS07 (MSB) - DS00 into the FSN register. The data byte determines the number of frame-sync signals generated by the TLC320AC01. This number is equal to the number of slaves plus one. DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 Control Bits R/W 0 1 0 0 0 Register Data The default value of DS07 - DS00 is 1 as shown below. DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00 0 2-24 0 0 0 0 0 0 1 3 3.1 Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted) Supply voltage range, DGTL VDD (see Notes 1 and 2) . . . . . . . . . . . . . . . - 0.3 V to 6.5 V Supply voltage range, DAC VDD (see Notes 1 and 2) . . . . . . . . . . . . . . . . - 0.3 V to 6.5 V Supply voltage range, ADC VDD (see Notes 1 and 2) . . . . . . . . . . . . . . . . - 0.3 V to 6.5 V Differential supply voltage range, DGTL VDD to DAC VDD . . . . . . . . . . . . - 0.3 V to 6.5 V Differential supply voltage range, all positive supply voltages to ADC GND, DAC GND, DGTL GND, SUBS . . . . . . . . . . . . . . . . . . . . - 0.3 V to 6.5 V Output voltage range, DOUT . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DGTL VDD + 0.3 V Input voltage range, DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DGTL VDD + 0.3 V Ground voltage range, ADC GND, DAC GND, DGTL GND, SUBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DGTL VDD + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3.2 Recommended Operating Conditions (see Note 2) VDD Positive supply voltage MIN NOM MAX 4.5 5 5.5 V 0.1 V Steady-state differential voltage between any two supplies VIH VIL High-level digital input voltage Low-level digital input voltage 0.8 V IO Load output current from ADC VMID and DAC 100 A Conversion time for the ADC and DAC channels fMCLK VID(PP) RL 2.2 UNIT V 10 FCLK periods Master-clock frequency 10.368 Analog input voltage (differential, peak to peak) 6 Differential output load resistance 600 Single-ended to buffered DAC VMID voltage load resistance 300 15 MHz V TA Operating free-air temperature 0 70 C NOTES: 1. Voltage values for DGTL VDD are with respect to DGTL GND, voltage values for DAC VDD are with respect to DAC GND, and voltage values for ADC VDD are with respect to ADC GND. For the subsequent electrical, operating, and timing specifications, the symbol VDD denotes all positive supplies. DAC GND, ADC GND, DGTL GND, and SUBS are at 0 V unless otherwise specified. 2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence below should be followed when applying power: (1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground. (2) Connect voltages ADC VDD,and DAC VDD. (3) Connect voltage DGTL VDD. (4) Connect the input signals. When removing power, follow the steps above in reverse order. 3-1 3.3 Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, MCLK = 5.184 MHz, VDD = 5 V, Outputs Unloaded, Total Device PARAMETER TEST CONDITIONS Supplyy current IDD MIN Power dissipation MAX UNIT PWR DWN = 1 and clock signals present 20 25 mA PWR DWN = 0 after 500 s and clock signals present 1 2 mA PWR DWN = 1 and clock signals present PD TYP 100 mW PWR DWN = 0 after 500 s and clock signals present 5 mW Software power down, (bit D00, register 6 set to 1) 15 20 mW ADC VMID Midpoint voltage No load ADC VDD/2 - 0.1 ADC VDD/2 + 0.1 V DAC VMID Midpoint voltage No load DAC VDD/2 - 0.1 DAC VDD/2 + 0.1 V 3.4 Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V, Digital I/O Terminals (DIN, DOUT, EOC, FC0, FC1, FS, FSD, MCLK, M/S, SCLK) PARAMETER TEST CONDITIONS TYP MAX High-level output voltage IIH IIL High-level input current, any digital input Ci Input capacitance 5 pF Co Output capacitance 5 pF Low-level input current, any digital input 2.4 UNIT VOH VOL Low-level output voltage IOH = - 1.6 mA IOL = 1.6 mA MIN V VI = 2.2 V to DGTL VDD VI = 0 V to 0.8 V 0.4 V 10 A 10 A All typical values are at VDD = 5 V and TA = 25C. 3.5 3.5.1 Electrical Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V, ADC and DAC Channels ADC Channel Filter Transfer Function, FCLK = 144 kHz, fs = 8 kHz PARAMETER TEST CONDITIONS fi = 50 Hz fi = 200 Hz Gain relative to gain at fi = 1020 Hz (see Note 3) fi = 300 Hz to 3 kHz fi = 3.3 kHz fi = 3.4 kHz fi = 4 kHz fi 4.6 kHz MIN MAX UNIT -2 - 1.8 - 0.15 - 0.15 0.15 - 0.35 0.03 -1 - 0.1 dB - 14 - 32 NOTE 3: The differential analog input signals are sine waves at 6 V peak to peak. The reference gain is at 1020 Hz. 3-2 3.5.2 ADC Channel Input, VDD = 5 V, Input Amplifier Gain = 0 dB (Unless Otherwise Noted) PARAMETER VI(PP) Peak to peak input voltage (see Note 4) Peak-to-peak ADC converter offset error CMRR Common-mode rejection ratio at IN +, IN -, AUX IN +, AUX IN - (see Note 5) ri Input resistance at IN +, IN -, AUX IN +, AUX IN - TEST CONDITIONS MIN MAX UNIT Single-ended 3 V Differential 6 V Band-pass filter selected DS03, DS02 = 0 in register 4 Squelch TYP 10 30 mV 55 dB 100 k 60 dB All typical values are at VDD = 5 V and TA = 25C. NOTES: 4. The differential range corresponds to the full-scale digital output. 5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC converter offset error with a common-mode nonzero signal applied to either IN + and IN - together or AUX IN + and AUX IN - together. 3.5.3 ADC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) PARAMETER ADC channel signal-todistortion ratio (see Note 6) TEST CONDITIONS AV = 0 dB MIN MAX AV = 6 dB MIN MAX AV = 12 dB MIN MAX VI = - 6 dB to - 1 dB VI = - 12 dB to - 6 dB 68 -- -- 63 68 -- VI = - 18 dB to - 12 dB VI = - 24 dB to - 18 dB 56 63 68 51 57 63 VI = - 30 dB to - 24 dB VI = - 36 dB to - 30 dB 43 51 57 39 45 51 VI = - 42 dB to - 36 dB VI = - 48 dB to - 42 dB 33 39 45 27 32 39 UNIT dB NOTE 6: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for the analog-input signal. 3.5.4 DAC Channel Filter Transfer Function, FCLK = 144 kHz, fs = 9.6 kHz, VDD = 5 V PARAMETER TEST CONDITIONS fi < 200 Hz fi = 200 Hz Gain relative to gain at fi = 1020 Hz (see Note 7) fi = 300 Hz to 3 kHz fi = 3.3 kHz fi = 3.4 kHz fi = 4 kHz MIN MAX UNIT 0.15 - 0.5 0.15 - 0.15 0.15 - 0.35 0.03 -1 - 0.1 dB - 14 fi 4.6 kHz - 32 NOTE 7: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. 3-3 3.5.5 DAC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) PARAMETER TEST CONDITIONS DAC channel signal-todistortion ratio (see Note 8) AV = 0 dB MIN MAX AV = - 6 dB MIN MAX AV = - 12 dB MIN MAX VO = - 6 dB to 0 dB VO = - 12 dB to - 6 dB 68 -- 63 68 -- VO = - 18 dB to - 12 dB VO = - 24 dB to - 18 dB 57 63 68 51 57 63 VO = - 30 dB to - 24 dB VO = - 36 dB to - 30 dB 45 51 57 39 45 51 VO = - 42 dB to - 36 dB VO = - 48 dB to - 42 dB 33 39 48 27 33 39 UNIT -- dB NOTE 8: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. 3.5.6 System Distortion, VDD = 5 V, fs = 8 kHz, FCLK = 144 kHz (Unless Otherwise Noted) PARAMETER Second harmonic ADC channel attenuation TEST CONDITIONS Single ended input (see Note 9) Single-ended Differential input (see Note 9) Third harmonic and higher harmonics Second harmonic DAC channel attenuation Differential input (see Note 9) MAX UNIT 82 77 70 Single-ended output (buffered DAC VMID) (see Note 10) Single-ended output (see Note 10) TYP 82 70 Single-ended input (see Note 9) Differential output (see Note 10) Third harmonic and higher harmonics MIN 77 82 70 dB 82 77 Differential output (see Note 10) 70 77 All typical values are at VDD = 5 V and TA = 25C. NOTES: 9. The input signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input level of - 1 dB. 10. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB. 3-4 3.5.7 Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included, VDD = 5 V (Unless Otherwise Noted) PARAMETER MIN Inputs tied to ADC VMID, fs = 8 kHz kHz, FCLK = 144 kHz, kHz (see Note 11) ADC idle-channel idle channel noise Broad-band noise DAC idle-channel idle channel noise TEST CONDITIONS Noise (0 to 7.2 kHz) Noise (0 to 3.6 kHz) DIN INPUT = 00000000000000, fs = 8 kHz, FCLK = 144 kHz, ( (see Note N 12)) TYP MAX 180 300 180 300 180 300 UNIT Vrms 300 All typical values are at VDD = 5 V and TA = 25C. NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC channel and converting to microvolts. 12. The DAC channel noise is measured differentially from OUT + to OUT - across 600 . 3.5.8 180 Absolute Gain Error, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) PARAMETER ADC channel absolute gain error (see Note 13) DAC channel absolute gain error (see Note 14) TEST CONDITIONS MIN MAX 1 dB input signal - 1-dB TA = 25C TA = 0 - 70C 0.5 0-dB input signal, g RL = 600 TA = 25C TA = 0 - 70C 0.5 UNIT 1 dB 1 NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels. The gain is measured with a - 1-dB, 1020-Hz sine wave. The - 1-dB input signal allows for any positive gain or offset error that may affect gain measurements at or close to 0-dB input signal levels. 14. The DAC input signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital fullscale input = 0 dB). The nominal differential DAC channel output voltage with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. 3.5.9 Relative Gain and Dynamic Range, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN MAX ADC channel relative gain tracking error (see Note 15) - 48-dB to - 1-dB input signal range 0.15 DAC channel relative gain tracking error (see Note 16) - 48-dB to 0-dB input signal range RL(diff) = 600 0.15 UNIT dB NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured at any other input level. The ADC channel input is a -1-dB 1020-Hz sine wave input signal. A -1-dB input signal allows for any positive gain or offset error that may affect gain measurements at or close to 0-dB ADC input signal levels. 16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain measured at any other input level. The DAC-channel input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal differential DAC channel output voltage with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. 3-5 3.5.10 Power-Supply Rejection, VDD = 5 V (Unless Otherwise Noted) (see Note 17) PARAMETER TEST CONDITIONS MIN TYP Supply Supply-voltage voltage rejection ratio, ratio ADC channel fi = 0 to 30 kHz fi = 30 to 50 kHz 50 Supply Supply-voltage voltage rejection ratio, ratio DAC channel fi = 0 to 30 kHz fi = 30 to 50 kHz 40 DGTL VDD Supply Supply-voltage voltage rejection ratio, ratio ADC channel fi = 0 to 30 kHz fi = 30 to 50 kHz 50 ADC VDD DAC VDD UNIT 55 45 55 Single ended, fi = 0 to 30 kHz DGTL VDD Supply Supply-voltage voltage rejection ratio, ratio DAC channel MAX dB 40 fi = 30 to 50 kHz Differential, fi = 0 to 30 kHz fi = 30 to 50 kHz 45 40 45 All typical values are at VDD = 5 V and TA = 25C. NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV peak-to-peak signal applied to the appropriate supply. 3.5.11 Crosstalk Attenuation, VDD = 5 V (Unless Otherwise Noted) PARAMETER ADC channel crosstalk attenuation DAC channel crosstalk attenuation TEST CONDITIONS MIN TYP DAC channel idle with DIN = 00000000000000, ADC input = 0 dB, 1020-Hz sine wave, Gain = 0 dB (see Note 18) 80 ADC channel idle with INP, INM, AUX IN +, and AUX IN - at ADC VMID 80 DAC channel input = digital equivalent of a 1020-Hz sine wave (see Note 19) 80 MAX UNIT dB dB All typical values are at VDD = 5 V and TA = 25C. NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB = 6-V peak-to-peak reference level for the analog input signal. 19. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. 3-6 3.5.12 Monitor Output Characteristics, VDD = 5 V (Unless Otherwise Noted) (see Note 20) TEST CONDITIONS MIN TYP VO(PP) Peak-to-peak ac output voltage Quiescent level = ADC VMID ZL = 10 k and 60 pF 1.3 1.5 VOO Output offset voltage No load, single ended relative to ADC VMID VOC Output common-mode voltage No load ro DC output resistance PARAMETER AV Voltage gain (see Note 21) 5 0.4 ADC VDD 0.5 ADC VDD MAX UNIT V 10 0.6 ADC VDD mV V 50 Gain = 0 dB - 0.2 0 0.2 Gain 2 = - 8 dB - 8.2 -8 - 7.8 Gain 3 = - 18 dB - 18.4 - 18 - 17.6 dB Squelch (see Note 22) - 60 All typical values are at VDD = 5 V and TA = 25C. NOTES: 20. All monitor output tests are performed with a 10-k load resistance. 21. Monitor gains are measured with a 1020-Hz, 6-V peak-to-peak sine wave applied differentially between IN + and IN -.The monitor output gains are nominally 0 dB, - 8 dB, and - 18 dB relative to its input; however, the output gains are - 6 dB relative to IN + and IN - or AUX IN + and AUX IN -. 22. Squelch is measured differentially with respect to ADC VMID. 3-7 3.6 Timing Requirements and Specifications in Master Mode 3.6.1 Recommended Input Timing Requirements for Master Mode, VDD = 5 V MIN tr(MCLK) tf(MCLK) MAX UNIT 5 ns Master clock fall time 5 ns Master clock duty cycle 40% tw(RESET) tsu(DIN) RESET pulse duration 1 MCLK th(DIN) DIN hold time after SCLK low (see Figure 4-2) 3.6.2 NOM Master clock rise time DIN setup time before SCLK low (see Figure 4-2) 60% 25 ns 20 ns Operating Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23) PARAMETER tf(SCLK) tr(SCLK) MIN Shift clock fall time (see Figure 4-2) Shift clock rise time (see Figure 4-2) Shift clock duty cycle TYP MAX 13 18 ns 18 ns 13 45% UNIT 55% td(CH-FL) Delay time from SCLK high to FSD low (see Figures 4-2 and 4-4 and Note 24) 5 15 ns td(CH-FH) Delay time from SCLK high to FS high (see Figure 4-2) 5 20 ns td(CH-DOUT) Delay time from SCLK high to DOUT valid (see Figures 4-2 and 4-7) 20 ns td(CH-DOUTZ) Delay time from SCLK to DOUT in high-impedance state (see Figure 4-8) 20 ns td(ML-EL) td(ML-EH) Delay time from MCLK low to EOC low (see Figure 4-9) 40 ns Delay time from MCLK low to EOC high (see Figure 4-9) 40 ns tf(EL) tr(EH) EOC fall time (see Figure 4-9) 13 ns EOC rise time (see Figure 4-9) 13 ns td(MH-CH) Delay time from MCLK high to SCLK high 50 ns td(MH-CL) Delay time from MCLK high to SCLK low 50 ns All typical values are at VDD = 5 V and TA = 25C. NOTES: 23. All timing specifications are valid with CL = 20 pF. 24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode. 3-8 3.7 Timing Requirements and Specifications in Slave Mode and Codec Emulation Mode 3.7.1 Recommended Input Timing Requirements for Slave Mode, VDD = 5 V MIN tr(MCLK) tf(MCLK) NOM UNIT 5 ns Master clock fall time 5 ns Master clock duty cycle 40% tw(RESET) tsu(DIN) RESET pulse duration 1 MCLK th(DIN) tsu(FL-CH) DIN hold time after SCLK high (see Figure 4-3) 3.7.2 MAX Master clock rise time DIN setup time before SCLK low (see Figure 4-3) 60% 20 ns Setup time from FS low to SCLK high 20 ns SCLK/4 ns Operating Characteristics Over Recommended Range of Operating Free-Air Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23) PARAMETER MIN TYP MAX Shift clock cycle time (see Figure 4-3) Shift clock fall time (see Figure 4-3) 18 ns tr(SCLK) Shift clock rise time (see Figure 4-3) 18 ns Shift clock duty cycle td(CH-FDL) td(CH-FDH) 125 UNIT tc(SCLK) tf(SCLK) ns 45% 55% Delay time from SCLK high to FSD low (see Figure 4-6) 50 ns Delay time from SCLK high to FSD high 40 ns td(FL-FDL) Delay time from FS low to FSD low (slave to slave) (see Figure 4-5) 40 ns td(CH-DOUT) Delay time from SCLK high to DOUT valid (see Figures 4-3 and 4-7) 40 ns td(CH-DOUTZ) Delay time from SCLK to DOUT in high-impedance state (see Figure 4-8) 20 ns td(ML-EL) td(ML-EH) Delay time from MCLK low to EOC low (see Figure 4-9) 40 ns Delay time from MCLK low to EOC high (see Figure 4-9) 40 ns tf(EL) tr(EH) EOC fall time (see Figure 4-9) 13 ns EOC rise time (see Figure 4-9) 13 ns td(MH-CH) Delay time from MCLK high to SCLK high td(MH-CL) Delay time from MCLK high to SCLK low All typical values are at VDD = 5 V and TA = 25C. NOTE 23: All timing specifications are valid with CL = 20 pF. 50 ns 50 ns 3-9 3-10 4 Parameter Measurement Information Rfb _ R + IN + or AUX IN + R IN - or AUX IN - To Multiplexer _ + Rfb Rfb = R for DS03 = 0 and DS02 = 1 Rfb = 2R for DS03 = 1 and DS02 = 0 Rfb = 4R for DS03 = 1 and DS02 = 1 R = 100 k nominal Figure 4 - 1. IN + and IN - Gain-Control Circuitry Table 4 - 1. Gain Control (Analog Input Signal Required for Full-Scale Bipolar A /D-Conversion 2s Complement) INPUT CONFIGURATION Differential configuration Analog input = IN + - IN - = AUX IN + - AUX IN - Single-ended configuration Analog input = IN + - VMID = AUX IN + - VMID CONTROL REGISTER 4 DS03 DS02 0 0 0 1 1 0 1 1 0 0 0 1 1 0 ANALOG INPUT A /D CONVERSION RESULT All Squelch VID = 3 V VID = 1.5 V Full scale VID = 0.75 V All Full scale VI = 1.5 V VI = 1.5 V Half scale Full scale Squelch Full scale 1 1 VI = 0.75 V Full scale VDD = 5 V VID = differential input voltage, VI = input voltage referenced to ADC VMID with IN - or AUX IN - connected to ADC VMID. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale. For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be referenced to the internal reference voltage, ADC VMID, for best common-mode performance. 4-1 tf(SCLK) SCLK 2V tr(SCLK) 2V 2V 0.8 V td(CH-FH) td(CH-FL) FS 2V 0.8 V td(CH-DOUT) DOUT D15 D14 D13 D12 D11 D2 D1 D0 D13 D12 D11 D2 D1 D0 tsu(DIN) D15 DIN D14 th(DIN) The time between falling edges of two primary FS signals is the conversion period. The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling edge of the shift clock. Figure 4 - 2. AIC Stand-Alone and Master-Mode Timing tf(SCLK) SCLK 2V tr(SCLK) 2V tc(SCLK) 2V 2V 0.8 V FS td(CH-DOUT) DOUT D15 D14 D13 D12 D11 D2 D1 D0 D13 D12 D11 D2 D1 D0 tsu(DIN) DIN D15 D14 th(DIN) The time between falling edges of two primary FS signals is the conversion period. The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling edge of the shift clock. The high-to-low transition of FS must must occur within 1/4 of a shift-clock period around the 2-V level of the shift clock for the codec mode. Figure 4 - 3. AIC Slave and Codec Emulation Mode 4-2 2.4 V SCLK SCLK Period/2 FSD 0.8 V td(CH-FL) FS 0.8 V NOTE A: Timing shown is for the TLC320AC01 operating as the master or as a stand-alone device. Figure 4 - 4. Master or Stand-Alone FS and FSD Timing FS 0.8 V td(FL-FDL) FSD 0.8 V NOTE A: Timing shown is for the TLC320AC01 operating in the slave mode (FS and SCLK signals are generated externally). The programmed data value in the FSD register is 0. Figure 4 - 5. Slave FS to FSD Timing 2.4 V SCLK 0.8 V td(CH-FDL) FSD 0.8 V NOTE A: Timing shown is for the TLC320AC01 operating in the slave mode (FS and SCLK signals are generated externally). There is a data value in the FSD register greater than 18 (decimal). Figure 4 - 6. Slave SCLK to FSD Timing 4-3 2V SCLK 0.8 V td(CH-DOUT) DOUT Hi-Z 2.4 V 0.4 V 2.4 V 0.4 V Figure 4 - 7. DOUT Enable Timing From Hi-Z 2V SCLK 0.8 V td(CH-DOUTZ) Hi-Z 0.8 V DOUT Figure 4 - 8. DOUT Delay Timing to Hi-Z td(ML-EH) 2V 2V MCLK 0.8 V 0.8 V tr(EH) 2.4 V 2.4 V EOC td(ML-EL) 0.4 V 0.4 V tf(EL) Internal ADC Conversion Time Figure 4 - 9. EOC Frame Timing 4-4 Delay Is m Shift Clocks Master FS Delay Is m Shift Clocks Master FSD, Slave Device 1 FS Delay Is m Shift Clocks Slave Device 1 FSD, Slave Device 2 FS Slave Device 2 FSD, Slave Device 3 FS Slave Device (n - 1) FSD, Slave Device n FS The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word programs the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have the same delay time. Figure 4 - 10. Master-Slave Frame-Sync Timing After a Delay Has Been Programmed Into the FSD Registers t=0 t=1 t=2 Sampling Period Master AIC Only Primary Frame Sync FS MP MP MP 1/2 Period Master AIC Only Primary and Secondary Frame Sync FS MP MS MP MS MP FSD Value Master and Slave FS AIC Primary Frame Sync MP SP Master and Slave AIC Primary and FS Secondary Frame Sync MP SP MP = Master Primary MS = Master Secondary SP = Slave Primary SS = Slave Secondary MS SS MP SP MP SP MS SS MP SP MP SP MS SS Figure 4 - 11. Master and Slave Frame-Sync Sequence with One Slave 4-5 4-6 Typical Characteristics ADC LOW-PASS RESPONSE 0 TA = 25C FCLK = 144 kHz - 10 Attenuation - dB 5 - 20 - 30 - 40 - 50 - 60 0 1 2 3 4 5 6 7 8 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 9 10 FCLK (kHz) Figure 5 - 1 5-1 ADC LOW-PASS RESPONSE 0.5 TA = 25C FCLK = 144 kHz 0.4 0.3 Attenuation - dB 0.2 0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 0 0.5 1 1.5 2 2.5 3 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 Figure 5 - 2 5-2 3.5 4 FCLK (kHz) ADC GROUP DELAY 1 TA = 25C FCLK = 144 kHz 0.9 0.8 Time - ms 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 9 10 FCLK (kHz) Figure 5 - 3 5-3 ADC BAND-PASS RESPONSE 0 TA = 25C fs = 8 kHz FCLK = 144 kHz Attenuation - dB - 10 - 20 - 30 - 40 - 50 - 60 0 1 2 3 4 5 6 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 Figure 5 - 4 5-4 7 8 FCLK (kHz) ADC BAND-PASS RESPONSE 0.5 Attenuation - dB TA = 25C 0.4 fs = 8 kHz FCLK = 144 kHz 0.3 0.2 0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 0 0.5 1 1.5 2 2.5 3 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 3.5 4 FCLK (kHz) Figure 5 - 5 5-5 ADC HIGH-PASS RESPONSE -0 Attenuation - dB -5 - 10 - 15 - 20 - 25 TA = 25C fs = 8 kHz FCLK = 144 kHz - 30 0 50 100 150 200 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 Figure 5 - 6 5-6 250 FCLK (kHz) ADC BAND-PASS GROUP DELAY 1 TA = 25C fs = 8 kHz FCLK = 144 kHz 0.9 0.8 Time - ms 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 7 8 FCLK (kHz) Figure 5 - 7 5-7 DAC LOW-PASS RESPONSE 0 TA = 25C fs = 9.6 kHz FCLK = 144 kHz Attenuation - dB - 10 - 20 - 30 - 40 - 50 - 60 0 1 2 3 4 5 6 7 8 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 Figure 5 - 8 5-8 9 10 FCLK (kHz) DAC LOW-PASS RESPONSE 0.5 TA = 25C 0.4 fs = 9.6 kHz FCLK = 144 kHz 0.3 Attenuation - dB 0.2 0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 0 0.5 1 1.5 2 2.5 3 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 3.5 4 FCLK (kHz) Figure 5 - 9 5-9 DAC LOW-PASS GROUP DELAY 1 TA = 25C fs = 9.6 kHz FCLK = 144 kHz 0.9 0.8 Time - ms 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 fi - Input Frequency - kHz NOTE A : Absolute Frequency (kHz) + Normalized Frequency 144 Figure 5 - 10 5-10 FCLK (kHz) DAC (sin x)/x CORRECTION FILTER RESPONSE 4 Magnitude - dB 2 0 -2 -4 TA = 25C Input = 3-V Sine Wave -6 0 2 4 NOTE A : Absolute Frequency (kHz) 6 8 10 12 14 16 Normalized Frequency 18 20 + Normalized Frequency 288 FCLK (kHz) Figure 5 - 11 5-11 DAC (sin x)/x CORRECTION FILTER RESPONSE 500 TA = 25C Input = 3-V Sine Wave Group Delay - s 400 300 200 100 0 0 2 4 6 8 10 12 14 16 Normalized Frequency NOTE A : Absolute Frequency (kHz) + Normalized Frequency 288 Figure 5 - 12 5-12 18 20 FCLK (kHz) DAC (sin x)/x CORRECTION ERROR 2 TA = 25C Input = 3-V Sine Wave 1.6 1.2 (sin x) /x Correction Magnitude - dB 0.8 0.4 Error 0 - 0.4 - 0.8 19.2-kHz (sin x) /x Distortion -1.2 -1.6 -2 0 1 2 3 4 5 6 7 8 9 10 Normalized Frequency NOTE A : Absolute Frequency (kHz) + Normalized Frequency 288 FCLK (kHz) Figure 5 - 13 5-13 5-14 6 Application Information TMS320C2x/3x TLC320AC01 DAC VDD CLKOUT DX DR FSX 14 10 11 12 DAC VMID MCLK DIN DAC GND DOUT ADC VDD FS ADC VMID FSR CLKX 13 ADC GND SCLK 5 5V 6 7 0.1 F 0.1 F 24 5V 23 22 0.1 F 0.1 F 9 5V DGTL VDD CLKR DGTL GND 0.1 F 20 DGND AGND NOTE A: Terminal numbers shown are for the FN package. Figure 6 -1. Stand-Alone Mode (to DSP Interface) TMS320C2x/3x TLC320AC01 CLKOUT DX DR FSX 14 10 11 12 MCLK DIN DOUT FS FSR CLKX 13 SCLK CLKR NOTE A: Terminal numbers shown are for the FN package. Figure 6 -2. Codec Mode (to DSP Interface) 6-1 TMS320C2x/3x TLC320AC01 14 CLKOUT 10 DX 11 DR 12 FSX MCLK DIN DOUT Master Mode FS FSD FSR 13 CLKX SCLK CLKR TLC320AC01 14 10 11 12 MCLK DIN DOUT FS FSD 13 Slave Mode SCLK NOTE A: Terminal numbers shown are for the FN package. Figure 6 - 3. Master With Slave (to DSP Interface) 10 k 10 k + VI - - + IN + TLE2022 10 k 10 k ADC VMID - + IN - TLE2022 The VI source must be capable of sinking a current equal to [ADC VMID + |VI|(max)]/10 k . Figure 6 - 4. Single-Ended Input (Ground Referenced) 6-2 IN+ 10 k VI 10 k 10 k 10 k - + - + TLE2064 4 TLE2064 4 10 k - + TLE2064 4 10 k IN - ADC VMID The VI source must be capable of sinking a current equal to [(ADC VMID/2) + |VI|(max)]/10 k . Figure 6 - 5. Single-Ended to Differential Input (Ground Referenced) OUT- 600- Load OUT+ Figure 6 - 6. Differential Load 10 k 5V 10 k - + OUT- OUT+ 10 k TLE2062 600- Load -5V 10 k NOTE A: When a signal changes from a single supply with a nonzero reference system to a grounded load, the operational amplifier must be powered from plus and minus supplies or the load must be capacitively coupled. Figure 6 -7. Differential Output Drive (Ground Referenced) 6-3 - + OUT + TLE2062 600- Load - + OUT - TLE2062 Figure 6 - 8. Low-Impedance Output Drive 100 k 5V 100 k - + OUT+ DAC VMID 100 k 600- Load TLE2062 -5V 100 k NOTE A: When a signal changes from a single supply with a nonzero reference system to a grounded load, the operational amplifier must be powered from plus and minus supplies or the load must be capacitively coupled. Figure 6 -9. Single-Ended Output Drive (Ground Referenced) 6-4 Appendix A Primary Control Bits The function of the primary-word control bits D01 and D00 and the hardware terminals FC0 and FC1 are shown below. Any combinational state of D01, D00, FC1, and FC0 not shown is ignored. CONTROL FUNCTION OF CONTROL BITS BITS TERMINALS D01 D00 FC1 FC0 0 0 0 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. 0 0 0 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of FC1 and FC0 such that on the next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods equal to the value contained in the A register. When the A register value is negative, the internal falling edge of FS occurs earlier. 0 0 1 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of FC1 and FC0 such that on the rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, the internal falling edge of FS occurs later. 0 0 1 1 On the next falling edge of the primary FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. 0 1 0 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of D01 and D00 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, the falling edge of FS occurs earlier. 1 0 0 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of D01 and D00. On the next rising edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, the internal falling edge of FS occurs later. 1 1 0 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. When D00 and D01 are both high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. A-1 CONTROL FUNCTION OF CONTROL BITS (Continued) BITS TERMINALS D01 D00 FC1 FC0 0 1 1 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of D01 and D00 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs earlier. When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. 1 0 1 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of D01 and D00. On the next rising edge of FS, the next ADC/DAC sample time occurs earlier by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs later. When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. 1 1 1 1 On the next falling edge of the primary FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary FS occurs at 1/2 the sampling time measured from the falling edge of the primary FS. 1 1 0 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. The phase adjustment is determined by the state of FC1 and FC0 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs earlier. 1 1 1 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 to DIN and transmits the ADC data D15 - D00 from DOUT. When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as measured from the falling edge of the primary FS. The phase adjustment is determined by the state of FC1 and FC0 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs earlier. 1 1 1 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a secondary FS to receive a secondary control word at DIN. The secondary FS occurs at 1/2 the sampling time measured from the falling edge of the primary FS. A-2 Appendix B Secondary Communications The function of the control bits DS15 and DS14 and the hardware terminals FC0 and FC1 are shown below. Any combinational state of DS15, DS14, FC1, and FC0 not shown is ignored. CONTROL FUNCTION OF SECONDARY COMMUNICATION BITS TERMINALS DS15 DS14 0 0 FC1 Ignored FC0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. 0 1 Ignored On the next falling edge of the FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of DS15 and DS14 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs earlier. 1 0 Ignored On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of D01 and D00. On the next rising edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs later. 1 1 0 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. 1 1 0 1 On the next falling edge of the FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of FC1 and FC0 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs later by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs earlier. 1 1 1 0 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. The phase adjustment is determined by the state of FC1 and FC0 such that on the next rising edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK periods determined by the value contained in the A register. When the A register value is negative, FS occurs later. 1 1 1 1 On the next falling edge of FS, the AIC receives DAC data D15 - D02 at DIN and transmits the ADC data D15 - D00 from DOUT. B-1 B-2 Appendix C TLC320AC01C/TLC320AC02C Specification Comparisons Texas Instruments manufactures the TLC320AC01C and the TLC320AC02C specified for the 0C to 70C commercial temperature range and the TLC320AC02I specified for the - 40C to 85C temperature range. The TLC320AC02C and TLC320AC02I operate at a relaxed TLC320AC01C specification. The differences are listed in the following tables. ADC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) (see Note 1) PARAMETER TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TEST CONDITIONS VI = - 6 dB to - 1 dB VI = - 12 dB to - 6 dB VI = - 18 dB to - 12 dB VI = - 24 dB to - 18 dB VI = - 30 dB to - 24 dB VI = - 36 dB to - 30 dB VI = - 42 dB to - 36 dB VI = - 48 dB to - 42 dB AV = 0 dB MIN MAX AV = 6 dB MIN MAX AV = 12 dB MIN MAX 68 -- -- 64 -- -- 63 68 -- 59 64 -- 57 63 68 56 59 64 51 57 63 50 56 59 45 51 57 44 50 56 39 45 51 38 44 50 33 39 45 32 38 44 27 33 39 26 32 38 UNIT dB NOTE 1: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for the analog input signal. C-1 DAC Channel Signal-to-Distortion Ratio, VDD = 5 V, fs = 8 kHz (Unless Otherwise Noted) (see Note 2) PARAMETER TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TEST CONDITIONS VO = - 6 dB to 0 dB VO = - 12 dB to - 6 dB VO = - 18 dB to - 12 dB VO = - 24 dB to - 18 dB VO = - 30 dB to - 24 dB VO = - 36 dB to - 30 dB VO = - 42 dB to - 36 dB VO = - 48 dB to - 42 dB AV = 0 dB MIN MAX 68 AV = - 6 dB MIN MAX AV = - 12 dB MIN MAX -- -- 64 -- -- 63 68 -- 59 64 -- 57 63 68 56 59 64 51 57 63 50 56 59 45 51 57 44 50 56 39 45 51 38 44 50 33 39 45 32 38 44 27 33 39 26 32 38 UNIT dB NOTE 2: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. C-2 System Distortion, ADC Channel Attenuation, VDD = 5 V, fs = 8 kHz, FCLK = 144 kHz (Unless Otherwise Noted) PARAMETER TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TEST CONDITIONS Second harmonic Differential input (see Note 3) Third harmonic and higher harmonics MIN MAX UNIT 70 dB 64 dB 70 dB 64 dB NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level of - 1 dB. System Distortion, DAC Channel Attenuation, VDD = 5 V, fs = 8 kHz, FCLK = 144 kHz (Unless Otherwise Noted) PARAMETER TLC320AC01 TLC320AC02 TLC320AC01 TLC320AC02 TEST CONDITIONS Second harmonic Differential output (see Note 4) Third harmonic and higher harmonics MIN MAX UNIT 70 dB 64 dB 70 dB 64 dB NOTE 4: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC output buffer is 600 from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB. C-3 C-4 Appendix D Multiple TLC320AC01/02 Analog Interface Circuits on One TMS320C5X DSP Serial Port In many applications, digital signal processors (DSP) must obtain information from multiple analog-to-digital (A/D) channels and transmit digital data to multiple digital-to-analog (D/A) conversion channels. The problem is how to do it easily and efficiently. This application report addresses the issue of connecting two channels of an analog interface circuit (AIC) to one TMS320C5X DSP serial port. In this application report, the AIC is the TLC320AC01. The TLC320AC01 (and TLC320AC02) analog interface circuit contains both A/D and D/A converters and using the master/slave mode, it is possible to connect two of them to one TMS320C5X DSP serial port with no additional logic. The hardware schematic is shown in Figure D-1. D-1 TMS320C5x TLC320AC01 CLKOUT DX DR FSX 14 10 11 12 DIN DOUT Master Mode FS FSD FSR CLKX MCLK 13 SCLK CLKR TLC320AC01 14 10 11 12 MCLK DIN DOUT FS FSD 13 SCLK Slave Mode NOTE A: Terminal numbers shown are for the FN package. Figure D-1. Master With Slave (to DSP Interface) HARDWARE AND SOFTWARE SOLUTION Once the hardware connections are completed, the issue becomes distinguishing one channel from another. Fortunately, this is very easy to do in software and adds very little overhead. The mode that the AC01s run in is called master/slave mode. One AC01 is the master and all of the rest of the AC01s are slaves. The master can be distinguished from all of the slaves by examining the least significant bit (LSB) in the receive word coming from the AC01. The master has a 0 in the LSB and all of the slaves have a 1 in the LSB. The AC01s in master/slave mode take turns communicating with the DSP serial port. They do this is a round robin or circular fashion. Synchronizing the system involves looking for the master AC01 and then starting the software associated with the first AC01. All other AC01s follow in order. It is possible to have different software for each AC01. A reference design was constructed using a TMS320C5X DSP starter kit (DSK). The AC01s were connected to the TDM serial port which is available at the headers on the edge of the DSK. A listing of the DSK assembly code for a simple stereo input/output program is included in the following section. D-2 SOFTWARE MODULE MODULE NAME: INOUTB.ASM In-out routine for C5X DSK with two TLC320AC01s on the TDM serial port of the C5X in master/slave mode. This version performs the in/out task for both the master and slave TLC320AC01 in the receive interrupt service routine. ******************* ******************* ***************************************************************************** ***************************************************************************** * .mmregs .ds 01000h PR1 .word 0104h ;A register PR2 .word 0219h ;B register PR3 .word 0300h ;A prime register PR4 .word 0405h ;amplifier gain register PR5 .word 0501h ;analog configuration register PR6 .word 0600h ;digital configuration register PR7 .word 0730h ;frame synch delay register PR8 .word 0802h ;frame synch number register value .word 0800h value2 .word 0800h val_add .word 0200h val_add2 .word 0400h ****** ****** ***************************************************************************** Set up the ISR vector ***************************************************************************** .ps 080ah rint: B RECEIVE ; 0A; Serial port receive interrupt RINT. xint: B TRANSMIT ; 0C; Serial port transmit interrupt XINT. trint: B TDMREC txint: B TDMTX ; * ****** ****** ***************************************************************************** TMS320C5X INITIALIZATION ***************************************************************************** .ps 0a00h .entry START: SETC INTM ; Disable interrupts LDP #0 ; Set data page pointer OPL #0834h,PMST LACC #0 SAMM CWSR SAMM PDWSR D-3 splk #00c8h SPLK 082h,IMR call AC01INIT CLRC OVM ; OVM = 0 SPM 0 ; PM = 0 SPLK #042h,IMR ; TDMA ser port rec interrupt SPLK #0C8h,TSPC ; CLRC INTM ; enable interrupts loop ; main program here does nothing. nop b ; ; a user program can be inserted. loop ; end of main program ; ; ; TDM serial port receiver interrupt service routine ; TDMREC: ; This loop insures that the master AC01 ldp #trcv ; is the first one that is written to in the bit trcv,15 ; loop. the slave AC01(s) will follow in bcnd xxx,tc ; sequential order. The master AC01 has a ; 0 in the 1sb. the slave AC01(s) have a 1 ; in the 1sb of the receive word. ldp #trcv lacc trcv and #0fffch ; ; user code would go here for master AC01 ; sacl tdxr b yyy ldp #trcv lacc trcv and #0fffch xxx ; ; user code would go here for slave AC01 ; sacl yyy rete D-4 tdxr ; ; TDM serial port transmit interrupt service routine ; TDMTX: rete ; ; RECEIVER INTERRUPT SERVICE ROUTINE ; RECEIVE: rete TRANSMIT: RETE D-5 AC01INIT SPLK #020h,TCR SPLK #01h,PRD MAR *,AR0 LACC #0008h SACL TSPC LACC #00c8h SACL TSPC SETC SXM LDP #PR1 LACC PR1 CALL AC01_2ND LDP #PR2 LACC PR2 CALL AC01_2ND LDP #PR8 LACC PR8 CALL AC01_2ND LDP #PR7 LACC PR7 CALL AC01_2ND ; ; ; ; ret AC01_2ND: LDP #0 SACH TDXR CLRC INTM ; IDLE ADD #6h, 15 ; 0000 0000 0000 0011 XXXX XXXX XXXX XXXX b SACH TDXR ; TDXR ; LACL #0 ; SACL TDXR ; make sure the word got sent INTM ; IDLE SACL IDLE IDLE SETC RET D-6 D-7 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) TLC320AC01CDW TLC320AC01CFN Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) Package Type Package Drawing OBSOLETE SOIC DW 28 TBD Call TI ACTIVE PLCC FN 28 37 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TLC320AC01CFNR ACTIVE PLCC FN 28 750 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TLC320AC01CPM ACTIVE LQFP PM 64 160 TBD CU NIPDAU Level-3-220C-168 HR TLC320AC01CPMR ACTIVE LQFP PM 64 1000 TBD CU NIPDAU Level-3-220C-168 HR Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC320AC01CPMR Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.1 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC320AC01CPMR LQFP PM 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MPLC004A - OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0- 7 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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