KAF-0402 768 (H) x 512 (V) Full Frame CCD Image Sensor Description The KAF-0402 Image Sensor is a high performance area CCD (charge-coupled device) image sensor with 768 (H) x 512 (V) photoactive pixels designed for a wide range of image sensing applications. The sensor incorporates true two-phase CCD technology, simplifying the support circuits required to drive the sensor as well as reducing dark current without compromising charge capacity. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. Optional microlenses focus the majority of the light through the transparent gate, increasing the optical response further. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Full Frame CCD, Enhanced Response Total Number of Pixels 784 (H) x 520 (V) Number of Active Pixels 768 (H) x 512 (V) = approx. 0.4 Mp Pixel Size 9.0 mm (H) x 9.0 mm (V) Active Image Size 6.91 mm (H) x 4.6 mm (V) 8.3 mm (Diagonal) 1/2 Optical Format Die Size 8.4 mm (H) x 5.5 mm (V) Figure 1. KAF-0402 Full Frame CCD Image Sensor Applications * Digitization * Medical * Scientific ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Aspect Ratio 3:2 Saturation Signal 100,000 electrons Quantum Efficiency (with Microlens) Peak: 77% 400 nm: 45% Quantum Efficiency (No Microlens) Peak: 65% 400 nm: 30% Output Sensitivity 10 mV/e- Read Noise 15 electrons Dark Current < 10 pA/cm2 at 25C Dark Current Doubling Temperature 6.3C Dynamic Range 76 dB Charge Transfer Efficiency > 0.99999 Blooming Suppression None Maximum Date Rate 10 MHz Package CERDIP Package (Sidebrazed) Cover Glass Clear or AR Coated, 2 Sides NOTE: Parameters above are specified at T = 25C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2015 April, 2015 - Rev. 2 1 Publication Order Number: KAF-0402/D KAF-0402 ORDERING INFORMATION Table 2. ORDERING INFORMATION - KAF-0402 IMAGE SENSOR Part Number Description Marking Code KAF-0402-AAA-CB-B1 Monochrome, No Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass (No Coatings), Grade 1 KAF-0402-AAA-CB-AE Monochrome, No Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass (No Coatings), Engineering Sample KAF-0402-AAA-CP-B1 Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 1 KAF-0402-AAA-CP-B2 Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 2 KAF-0402-AAA-CP-AE Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Engineering Sample KAF-0402-ABA-CD-B1 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAF-0402-ABA-CD-B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (Both Sides), Grade 2 KAF-0402-ABA-CD-AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KAF-0402-ABA-CP-B1 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 1 KAF-0402-ABA-CP-B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 2 KAF-0402-ABA-CP-AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Engineering Sample KAF-0402-AAA Serial Number KAF-0402-ABA Serial Number Table 3. ORDERING INFORMATION - EVALUATION SUPPORT Part Number KAF-0402-12-5-A-EVK Description Evaluation Board (Complete Kit) See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF-0402 DEVICE DESCRIPTION Architecture 4 Dark Lines fV1 fV2 KAF-0402 Usable Active Image Area 768 (H) x 512 (V) 9 x 9 mm Pixels GUARD 3:2 Aspect Ratio VRD fR VDD VOUT VSS EE EE 768 Active Pixels/Line 4 Dark 10 Inactive 12 Dark 2 Inactive E E 4 Dark Lines fH1 fH2 SUB VOG Figure 2. Block Diagram The sensor consists of 784 parallel (vertical) CCD shift registers each 520 elements long. These registers act as both the photosensitive elements and as the transport circuits that allow the image to be sequentially read out of the sensor. The parallel (vertical) CCD registers transfer the image one line at a time into a single 796-element (horizontal) CCD shift register. The horizontal register transfers the charge to a single output amplifier. The output amplifier is a two-stage source follower that converts the photo-generated charge to a voltage for each pixel. Microlenses Microlenses are formed along each row. They are effectively half of a cylinder centered on the transparent gates, extending continuously in the row direction. They act to direct the photons away from the polysilicon gate and through the transparent gate. This increases the response, especially at the shorter wavelengths (< 600 nm). Microlens V1 V2 Silicon Figure 3. Microlens www.onsemi.com 3 KAF-0402 H1 H2 H1 HCCD Charge Transfer H2 VDD VOG R VRD Floating Diffusion VOUT Source Follower #1 Source Follower #2 Figure 4. Output Schematic false signal depending on operating conditions. There are two more dummy pixels at the end of each line. Output Structure Charge presented to the floating diffusion is converted into a voltage and current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the floating diffusion. Once the signal has been sampled by the system electronics, the reset gate (fR) is clocked to remove the signal and the floating diffusion is reset to the potential applied by Vrd (see Figure 4). More signal at the floating diffusion reduces the voltage seen at the output pin. In order to activate the output structure, an off-chip load must be added to the Vout pin of the device such as shown in Figure 8. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the sensor. These photon induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons will leak into the adjacent pixels within the same column. This is termed blooming. During the integration period, the fV1 and fV2 register clocks are held at a constant (low) level. See Figure 9. Dark Reference Pixels There are 4 light shielded pixels at the beginning of each line, and 12 at the end. There are 4 dark lines at the start of every frame and 4 dark lines at the end of each frame. Under normal circumstances, these pixels do not respond to light. However, dark reference pixels in close proximity to an active pixel can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal. Charge Transport Referring again to Figure 10, the integrated charge from each photogate is transported to the output using a two-step process. Each line (row) of charge is first transported from the vertical CCD to the horizontal CCD register using the fV1 and fV2 register clocks. The horizontal CCD is presented a new line on the falling edge of fV2 while fH1 is held high. The horizontal CCD then transports each line, pixel by pixel, to the output structure by alternately clocking the fH1 and fH2 pins in a complementary fashion. On each falling edge of fH2 a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier. Dummy Pixels Within the horizontal shift register are 10 leading additional pixels that are not associated with a column of pixels within the vertical register. These pixels contain only horizontal shift register dark current signal and do not respond to light. A few leading dummy pixels may scavenge www.onsemi.com 4 KAF-0402 Physical Description Pin Description and Device Orientation VOG 1 24 N/C Pin 1 VOUT 2 23 GUARD Pixel 1,1 VDD 3 22 fV1 VRD 4 21 fV1 fR 5 20 fV2 VSS 6 19 fV2 fH1 7 18 fV2 fH2 8 17 fV2 N/C 9 16 fV1 N/C 10 15 fV1 14 VSUB VSUB 11 N/C 12 13 N/C Figure 5. Pinout Diagram Table 4. PIN DESCRIPTION Pin Name Output Gate 13 N/C Video Output 14 VSUB VDD Amplifier Supply 15 fV1 Vertical CCD Clock - Phase 1 VRD Reset Drain 16 fV1 Vertical CCD Clock - Phase 1 5 fR Reset Clock 17 fV2 Vertical CCD Clock - Phase 2 6 VSS Amplifier Supply Return 18 fV2 Vertical CCD Clock - Phase 2 7 fH1 Horizontal CCD Clock - Phase 1 19 fV2 Vertical CCD Clock - Phase 2 8 fH2 Horizontal CCD Clock - Phase 2 20 fV2 Vertical CCD Clock - Phase 2 9 N/C No Connection 21 fV1 Vertical CCD Clock - Phase 1 No Connection 22 fV1 Vertical CCD Clock - Phase 1 Substrate 23 GUARD No Connection 24 N/C Pin Name 1 VOG 2 VOUT 3 4 10 N/C 11 VSUB 12 N/C Description www.onsemi.com 5 Description No Connection Substrate Guard Ring No Connection KAF-0402 IMAGING PERFORMANCE Specifications Electro-Optical All values measured at 25C and nominal operating conditions. These parameters exclude defective pixels. Table 5. SPECIFICATIONS Description Saturation Signal Vertical CCD Capacity Horizontal CCD Capacity Output Node Capacity Symbol Min. Nom. Max. NSAT Quantum Efficiency (see Figure 6) 85,000 170,000 190,000 100,000 200,000 220,000 - 240,000 - - - - Units Notes Verification Plan e-/pix 1 Design9 Design9 Photoresponse Non-Linearity PRNL - 1.0 2.0 % 2 Photoresponse Non-Uniformity PRNU - 0.8 - % 3 Die8 Dark Signal JDARK - - 15 6 30 10 e-/pix/sec pA/cm2 4 Die8 - 6.3 7 C DSNU - 15 30 e-/pix/sec 5 Die8 Dynamic Range DR 72 76 - dB 6 Design9 Charge Transfer Efficiency CTE 0.99997 0.99999 - Output Amplifier DC Offset VODC VRD VRD + 0.5 VRD + 1.0 V Design9 Output Amplifier Sensitivity VOUT/Ne- 9 10 - mV/e- Design9 ZOUT 180 200 220 W Design9 ne- - 15 20 electrons Dark Signal Doubling Temperature Dark Signal Non-Uniformity Output Amplifier Output Impedance Noise Floor 1. 2. 3. 4. 5. 6. 7. Design9 Die8 7 For pixel binning applications, electron capacity up to 330,000 can be achieved with modified CCD inputs. Worst case deviation from straight line fit, between 2% and 90% of VSAT. One Sigma deviation of a 128 x 128 sample when CCD illuminated uniformly at half of saturation. Average of all pixels with no illumination at 25C. Average dark signal of any of 11 x 8 blocks within the sensor (each block is 128 x 128 pixels). 20LOG (NSAT / ne-) at nominal operating frequency and 25C. Noise floor is specified at the nominal pixel frequency and excludes any dark or pattern noises. It is dominated by the output amplifier power spectrum with a bandwidth = 5 pixel rate. 8. A parameter that is measured on every sensor during production testing. 9. A parameter that is quantified during the design verification activity. www.onsemi.com 6 KAF-0402 TYPICAL PERFORMANCE CURVES KAF-0402 Spectral Response 1 0.9 KAF-0402 (with microlenses) KAF-0402 (no microlenses) Absolute Quantum Efficiency 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 Wavelength (nm) Figure 6. Typical Spectral Response www.onsemi.com 7 900 1000 KAF-0402 DEFECT DEFINITIONS Table 6. SPECIFICATIONS (Defect tests performed at T = 25C) Grade Point Defect Cluster Defect Column Defect C1 <5 0 0 C2 < 10 <4 0 Point Defects Dark: A pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation. Bright: A pixel whose dark current > 5,000 e-/pix/sec at 25C. A column containing a pixel with dark current > 12,000 e-/pix/sec at 25C (Bright column). A column that does not meet the minimum vertical CCD charge capacity (Low charge capacity column). A column that loses > 250 e- under 2 ke- (Trap defect). Cluster Defect A grouping of not more than 5 adjacent point defects. Neighboring Pixels The surrounding 128 x 128 pixels or 64 columns/rows. Column Defect A grouping of > 5 contiguous point defects along a single column. Defect Separation Column and cluster defects are separated by no less than 2 pixels in any direction (excluding single pixel defects). 1, 512 768, 512 1, 1 768, 1 Figure 7. Active Pixel Region www.onsemi.com 8 KAF-0402 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Diode Pin Voltages VDIODE 0 20 V 1, 2 Gate Pin Voltages VGATE1 -16 16 V 1, 3, 5 IOUT - -10 mA 4 CLOAD - 15 pF 4 Output Bias Current Output Load Capacitance Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Referenced to pin VSUB or between each pin in this group. 2. Includes pins: VRD, VDD, VSS, VOUT. 3. Includes pins: fV1, fV2, fH1, fH2, VOG, VLG, fR. 4. Avoid shorting output pins to ground or any low impedance source during operation. 5. This sensor contains gate protection circuits to provide some protection against ESD events. The circuits will turn on when greater than 16 V appears between any two gate pins. Permanent damage can result if excessive current is allowed to flow under these conditions. Table 8. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) Reset Drain VRD 10 11.0 11.5 V 0.01 Output Amplifier Return VSS 1.5 2.0 2.5 V -0.5 Output Amplifier Supply VDD 14.75 15 15.5 V IOUT Substrate VSUB 0 0 0 V 0.01 Output Gate VOG 3.75 4 5 V 0.01 Guard Ring GUARD 8.0 9.0 12.0 V 0.01 IOUT - -5 -10 mA - Description Video Output Current 1. An output load sink must be applied to VOUT to activate output amplifier - see Figure 8. +15 V 0.1 mF ~5ma VOUT 2N3904 or Equivalent Buffered Output 140 W 1 kW Figure 8. Example Output Structure Load Diagram www.onsemi.com 9 Notes 1 KAF-0402 AC Operating Conditions Table 9. CLOCK LEVELS Symbol Level Minimum Nominal Maximum Units Effective Capacitance Vertical CCD Clock - Phase 1 fV1 Low -10.5 -10 -9.5 V 6 nF (All fV1 Pins) Vertical CCD Clock - Phase 1 fV1 High -0.5 0 1.0 V 6 nF (All fV1 Pins) Vertical CCD Clock - Phase 2 fV2 Low -10.5 -10.0 -9.5 V 6 nF (All fV2 Pins) Vertical CCD Clock - Phase 2 fV2 High -0.5 0 1.0 V 6 nF (All fV2 Pins) Horizontal CCD Clock - Phase 1 fH1 Low -4.5 -4.0 -3.5 V 50 pF Horizontal CCD Clock - Phase 1 fH1 Amplitude 9.5 10.0 10.5 V 50 pF Horizontal CCD Clock - Phase 2 fH2 Low -4.5 -4.0 -3.5 V 50 pF Horizontal CCD Clock - Phase 2 fH2 Amplitude 9.5 10.0 10.5 V 50 pF Reset Clock fR Low -3.0 -2.0 -1.75 V 5 pF Reset Clock fR Amplitude 5.0 6.0 7.0 V 5 pF Description 1. All pins draw less than 10 mA DC current. 2. Capacitance values relative to VSUB. www.onsemi.com 10 KAF-0402 TIMING Table 10. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Notes fH - 4 10 MHz 1, 2, 3 Pixel Period (1 Count) tPIX 100 250 - ns fH1, fH2 Set-up Time tfHS 0.5 1 - ms fV1, fV2 Clock Pulse Width tfV 1.5 2 - ms 2 Reset Clock Pulse Width tfR 10 20 - ns 4 tREADOUT 43.7 107 - ms 5 Integration Time tINT - - - Line Time tLINE 84.1 206 - fH1, fH2 Clock Frequency Readout Time 6 ms 7 1. 50% duty cycle values. 2. CTE may degrade above the nominal frequency. 3. Rise and fall times (10/90% levels) should be limited to 5-10% of clock period. Crossover of register clocks should be between 40-60% of amplitude. 4. fR should be clocked continuously. 5. tREADOUT = (520 tLINE) 6. Integration time (tINT) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot noise. 7. tLINE = (3 tfV) + tfHS + (796 tPIX) + tPIX Frame Timing Frame Timing tINT tREADOUT 1 Frame = 520 Lines fV1 fV2 Line 1 2 fH1 fH2 Figure 9. Frame Timing Diagram www.onsemi.com 11 519 520 KAF-0402 Line Timing and Pixel Timing Line Timing Detail Pixel Timing Detail 1 Line = 796 Pixels tfR tfV fR fV1 tfV fH1 fV2 tPIX 1 Count tPIX tfHS fH2 fH1 VPIX fH2 VOUT 796 Counts VSAT VDARK fR VODC VSUB Line Content 1-10 11-14 VSAT VDARK 15-782 783-794 795-796 VPIX Photoactive VODC VSUB Dummy Pixels Saturated pixel video output signal Video output signal in no-light situation, not zero due to JDARK Pixel video output signal level, more electrons = more negative Video level offset with respect to VSUB* Analog ground * See Image Acquisition section. Dark Reference Figure 10. Line and Pixel Timing Diagrams www.onsemi.com 12 KAF-0402 STORAGE AND HANDLING Table 11. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Storage Temperature TST - 100 C Humidity RH 5 90 % Notes 1 1. T = 25C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 13 KAF-0402 MECHANICAL INFORMATION Completed Assembly Figure 11. Completed Assembly (1 of 2) www.onsemi.com 14 KAF-0402 Figure 12. Completed Assembly (2 of 2) www.onsemi.com 15 KAF-0402 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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