MCP3905-I/SS - Microchip Technology

MCP3905/06

Features

• Supplie s active (real) power measurement f or

single-phase, residential energy-metering

• Supports the IEC 62053 International Energy

Metering Specification and legacy IEC

1036/61036/687 Specifications

• Two multi-bit, Digital-to-Analog Converters

(DACs), second-order, 16-bit, Delta-Sigma

Analog-to-Digital Converters (ADCs)

• 0.1% typical measurement error over 500:1

dynami c range (MCP3905)

• 0.1% typical measurement error over 1000:1

dynamic range (MCP3906)

• Programmable Gain Amplifier (PGA) for small-

signal inputs supports low-value shunt current

sensor

-16:1 PGA - MCP3905

-32:1 PGA - MCP3906

• Ultra-low drift on-chip reference: 15 ppm/°C (typ.)

• Direct drive for electromagnetic mechanical

counter and two-phas e ste ppe r motors

•Low I

DD of 4 mA (typ.)

• Tamper output pin for negative power indication

• Industrial Temperature Range: -40°C to +85°C

• Supplies instantaneous active (real) power on

HFOUT for meter calibration

US Patents Pending

Description

The MCP3905/06 devices are energy-metering ICs

designed to support the IEC 62053 International

Metering Standard Specification. They supply a

frequency output proportional to the average active

(real) power, as well as a higher-frequency output

proportional to the instantaneous power for meter

calibration. They include two 16-bit, delta-sigma ADCs

for a wide range of IB and IMAX currents and/or small

shunt (< 200 µOhms) meter designs. It includes an

ultra-low drift voltage reference with < 15 ppm/°C

through a specially designed band gap temperature

curve for the minimum gradient across the industrial

temperature range. A fixed-function DSP block is on-

chip for active (real) power calculation. Strong output

drive for mechanical counters are on-chip to reduce

field failures and mechanical counter sticking. A no-

load threshold block prevents any current creep mea-

surements. A Power-On Reset (POR) block restricts

meter performance during low-voltage situations.

These accurate energy-metering ICs with high field

reliabil ity are avai lab le in the ind us try-s t a nda rd pino ut.

Package Type

Functional Block Diagram

FOUT0

DGND

NEG

FOUT1

OSC2

OSC1

DVDD

HPF

AVDD

CH0+

CH0-

CH1-

CH1+

HFOUT

9G0

MCLR 15

11 G1

REFIN/OUT

AGND 13

12 F1

24-Pin SSOP

16-bit

ΔΣ ADC

MCLR

–

CH0+

CH0-

Reference

2.4V

–

CH1+

CH1-

HPF1

LPF1 E-to-F

conversion

REFIN/

FOUT1

HFOUT

G0 G1

F2 F1 FOUT0

OSC1 OSC2

OUT

NEG

HPF

Multi-level

16-bit

ΔΣ ADC

Multi-level

HPF1

PGA

POR

Energy-Me tering ICs wi th Active (Real) Power Pul se O utput

MCP3905/06
DS21948D-page 2 © 2007 Microchip Technology Inc.
1.0 ELECTRICAL 
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ...................................................................................7.0V
Digital inputs and outputs w.r. t. AGND........-0.6V to VDD +0.6V
Analog input w.r.t. AGND..... ............................ ........-6V to +6V
VREF input w.r.t. AGND........ .......................-0.6V to  VDD +0.6V
Storage temperature ................... .. .. .. .. .. .. ......-65°C to +150°C
Ambient temp. with power applied................-65°C to +125°C
Soldering temperature of leads (10 seconds).............+300°C
ESD on the analog inputs (HBM,MM).................5.0 kV, 500V
ESD on all other p in s ( H BM,MM)........ ....... ...... ...5.0 kV, 500V
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRIC AL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ. Max Units Comment
Overall Measurement Accuracy
Energy Measurement Error E — 0.1 — % FOUT Channel 0 swings 1:500 range, 
MCP39 05 onl y (Note 1, Note 4)
— 0.1 — % FOUT Channel 0 swings 1:1000 range, 
MCP39 06 onl y (Note 1, Note 4)
No-Load Threshold/ 
Minimum Load NLT — 0.0015 — % FOUT
Max Disabled when F2, F1, F0 = 0, 1, 1
(Note 5, Note 6)
Phase Delay Between 
Channels — — 1/M CLK s HPF = 0 and 1, < 1 MCLK
(Note 4, Note 6, Note 7)
AC Power Supply
Rejection Ratio
(Output Frequency Variation)
AC PSRR — 0 .01 — % FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
DC Power Supply
Rejection Ratio
(Output Frequency Variation)
DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3)
System Gain Error — 3 10 % FOUT Note 2, Note 5
ADC/PGA Specifications
Offset Error VOS — 2 5 mV Referred to Input
Gain Error Match — 0.5 — % FOUT Note 8
Internal Voltage Reference
Voltage — 2.4 — V
Tolerance — ±2 — %
Tempco — 15 — ppm/°C
Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is 
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. 
See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range.
2: Does not inclu de inte rna l VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between 
measured output frequency and expected transfer function.
3: Percent  of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 
50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV.
4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive).
5: Refer to Secti on 4 .0 “D evice Overview” for complete description.
6: Specified by characterization, not production tested.
7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
8: Gain error match is measured from CH0 G = 1 to any other gain setting.

MCP3905/06

TEMPERATURE CHARACTERISTICS

Reference Input

Input Range 2.2 — 2.6 V

Input Impedance 3.2 — — kΩ

Input Capacitance — — 10 pF

Analog Inputs

Maximum Signa l Level — — ±1 V CH0+,CH0-,CH1+,CH1- to AGND

Differential Input Voltage

Range Channel 0 — — ±470/G mV G = PGA Gain on Channel 0

Differential Input Voltage

Range Channel 1 ——±660mV

Input Impedance 390 — — kΩProportional to 1/MCLK frequency

Bandwidth

(Notch Frequency) — 14 — kHz Proportional to MCLK frequency,

MCLK/256

Oscillator Input

Frequ enc y Range MCLK 1 — 4 MHz

Power Specifica tions

Operati ng Volt age 4.5 — 5.5 V AVDD, DVDD

IDD,A IDD,A —2.7 3.0 mAAV

DD pin only

IDD,D IDD,D —1.2 2.0 mADV

DD pin only

Electrical Specifications: Unless otherwise indicated, VDD = 4.5V – 5.5V, AGND, DGND = 0V.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +85 °C

Operati ng Temperatu r e Range TA-40 — +125 °C Note

Storage Temperature Range TA-65 — +150 °C

Note: The MCP3905/06 operate over this extended temperature range, but with reduced performance. In any

case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,

Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter Sym Min Typ. Max Units Comment

Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is

measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.

See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range.

2: Does not inclu de inte rna l VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between

measured output frequency and expected transfer function.

3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @

50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV.

4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive).

5: Refer to Secti on 4 .0 “D evice Overview” for complete description.

6: Specified by characterization, not production tested.

7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.

8: Gain error match is measured from CH0 G = 1 to any other gain setting.

MCP3905/06

FIGURE 1-1: Output Timings for Pulse Outputs and Negative Power Pin.

TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,

AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter Sym Min Typ Max Units Comment

Frequency Ou tput

FOUT0 and FOUT1 Pulse Width

(Logic-Low) tFW —275 —ms 984376 MCLK periods

(Note 1)

HFOUT Pulse Width tHW —90 — ms 322160 MCLK periods

(Note 2)

FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s

HFOUT Pulse Period tHP Refer to Equation 4-2 s

FOUT0 to FOUT1 Falling-Edge Time tFS2 —0.5 tFP —

FOUT0 to FOUT1 Min Separation tFS —4/MCLK —

FOUT0 and FOUT1 Output High Voltage VOH 4.5 ——VI

OH = 10 mA, DVDD = 5.0V

FOUT0 and FOUT1 Output Low Voltage VOL ——0.5 V IOL = 10 mA, DVDD = 5.0V

HFOUT Output High Voltage VOH 4.0 ——VI

OH = 5 mA, DVDD = 5.0V

HFOUT Output Low Voltage VOL ——0.5 V IOL = 5 m A, D VDD = 5.0V

High-Level Input Voltage

(All Digital Input Pins) VIH 2.4 ——VDV

DD = 5.0V

Low-Level Input Voltage

(All Digital Input Pins) VIL ——0.85 V DVDD = 5.0V

Input Leakage Current ——±3 µA VIN = 0, VIN = DVDD

Pin Capacitance ——10 pF Note 3

Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.

2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP.

3: Specified by characterization, not production tested.

FOUT0

tFP

FOUT1

HFOUT

tFW

tHP

tHW

tFS

tFS2

NEG

MCP3905/06

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-1: Measurement Error,

Gain = 8, PF = 1.

FIGURE 2-2: Measurement Error,

Gain = 16, PF = 1.

FIGURE 2-3: Measurement Error,

Gain = 32, PF = 1.

FIGURE 2-4: Measurement Error,

Gain = 8 , PF = 0.5.

FIGURE 2-5: Measurement Error,

Gain = 16, PF = 0.5.

FIGURE 2-6: Measurement Error,

Gain = 32, PF = 0.5.

Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a statis tic al s umm ar y b as ed on a l im ite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude ( V)

Me asur ement Error

+85°C

+25°C

-40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Am plitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitud e (V)

Measuremen t Error

+85°C

+25°C

- 40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude ( V)

Measurement Error

+85°C

+25°C

-40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Am plitude (V)

Measurement Error

+85°C

+25°C

-40°C

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

MCP3905/06

Note: Unless otherwise specified, DVDD, AV DD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-7: Measurement Error,

Gain = 1, PF = 1.

FIGURE 2-8: Measurement Error,

Gain = 2, PF = 1.

FIGURE 2-9: Measurement Error,

Gain = 1, PF = + 0.5.

FIGURE 2-10: Measurement Error,

Gain = 2, PF = + 0.5.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Me asur ement Error

+85°C

+25°C

- 40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitud e (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH1 Vp-p Amplitude ( V)

Measurement Error

+85°C

+25°C

-40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

MCP3905/06

Note: Unless otherwise specified, DVDD, AV DD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-11: Measurement Error vs.

Input Frequency.

FIGURE 2-12: Channel 0 Offset Error

(DC Mode, HPF off), G = 1.

FIGURE 2-13: Channel 0 Offset Error

(DC Mode, HPF off), G = 8.

FIGURE 2-14: Channel 0 Offset Er ror

(DC Mode, HPF Off), G = 16.

FIGURE 2-15: Measurement Error vs. VDD

(G = 16).

FIGURE 2-16: Measurement Error vs. VDD,

G = 16, External VREF.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

45 50 55 60 65 70 75

Frequency (Hz)

% Error

PF = 1.0

PF = 0.5

500

1000

1500

2000

2500

3000

-1.75

-1.70

-1.65

-1.61

-1.56

-1.52

-1.47

-1.43

-1.38

Channel 0 Offset (mV)

Occurance

16384 Samples

Mean = -1.57 mV

Std. Dev = 52.5 µV

200

400

600

800

1000

1200

-1.71

-1.69

-1.68

-1.67

-1.66

-1.65

-1.64

-1.63

-1.62

-1.60

-1.59

Channel 0 Offset (mV)

Occurance

16384 Samples

Mean = -1.64 mV

Std. Dev = 17.4 µV

500

1000

1500

2000

2500

3000

3500

4000

-1.38E-03

-1.37E-03

-1.36E-03

-1.35E-03

-1.34E-03

-1.33E-03

-1.32E-03

-1.31E-03

-1.30E-03

-1.29E-03

-1.28E-03

-1.27E-03

-1.26E-03

-1.25E-03

-1.24E-03

-1.23E-03

-1.22E-03

Bin (mV)

Occurance

16384 Samples

Mean = - 1.28 mV

Std. dev = - 18.1 µV

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

VDD=4.75V

VDD=5.0V

VDD=4.5V

VDD=5.25V

VDD=5.5V

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

0.3

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

VDD=4.5V

VDD=4.75V

VDD=5.0V

VDD=5.25V

VDD=5.5V

MCP3905/06

Note: Unless otherwise specified, DVDD, AV DD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-17: Measurement Error

w/ External VREF, (G = 1).

FIGURE 2-18: Measurement Error

w/ External VREF, (G = 8).

FIGURE 2-19: Measurement Error

w/ External VREF (G = 16).

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp -p Amp litud e (V)

Measurement Error

+85°C

+25°C

-40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C +25°C

- 40°C

MCP3905/06

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Digital VDD (DV DD)

DVDD is the power supply pin for the digital circuitry

within the MCP3905/06.

DVDD requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Please refer to Sectio n 5.0 “Applications

Information”.

3.2 High-Pass Filter Input Logic Pin

(HPF)

HPF controls the state of the high-pass filter in both

input channels. A logic ‘1’ enables both filters,

removing a ny D C offset coming fro m the sy ste m or th e

device. A logic ‘0’ disables both filters, allowing DC

voltages to be measured.

3.3 Analog VDD (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP3905/06.

AVDD requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Please refer to Section 5.0 “Applications

Information”.

3.4 Current Channel (CH0-, CH0+)

CH0- and C H0+ are the ful ly dif fere ntial a nalog v olt age

input channels for the current measurement, containin g

a PGA for small-signal input, such as shunt current-

sensin g. The linear and spe cified region of this cha nnel

is dependant on the PGA gain. This corresponds to a

maximum differential voltage of ±470 mV/GAIN and

maximum absolute voltage, with respect to AGND, of

± 1V. Up to ± 6V can be applie d to these pins withou t the

risk of permanent damage.

Refer to Section 1.0 “Electrical Characte ristic s” .

Pin No. Symbol Function

1DV

DD Digital Power Supply Pin

2 HPF High-Pass Filters Control Logic Pin

3AV

DD Analog Power Supply Pin

4 NC No Connec t

5 CH0+ Non-Inverting Analog Input Pin for Channel 0 (Current Channel)

6 CH0- Inverting Analog Input Pin for Channel 0 (Current Channel)

7 CH1- Inverting Analog Input Pin for Channel 1 (Voltage Channel)

8 CH1+ Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)

9MCLR

Master Clear Logic Input Pin

10 REFIN/OUT Voltage Reference Input/Output Pin

11 AGND Analog Ground Pin, Return Path for internal analog circuitry

12 F2 Frequency Control for HFOUT Logic Input Pin

13 F1 Frequency Control for FOUT0/1 Logic Input Pin

14 F0 Frequency Control for FOUT0/1 Logic Input Pin

15 G1 Gain Control Logic Input Pin

16 G0 Gain Control Logic Input Pin

17 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin

18 OSC2 Oscillator Crystal Connection Pin or Clock Output Pin

19 NC No Connect

20 NEG Negative Power Logic Output Pin

21 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry

22 HFOUT High-Frequency Logic Output Pin (Intended for Calibration)

23 FOUT1 Differential Mechanical Counter Logic Output Pin

24 FOUT0 Differential Mechanical Counter Logic Output Pin

MCP3905/06

3.5 Voltage Channel (CH1-,CH1+)

CH1- and CH1+ are the ful ly dif fere ntial a nalog volt age

input c hannels fo r the volt age meas urement. The linear

and specified region of these channels have a

maximum differential voltage of ±660mV and a

maximum absolute voltage of ±1V, with respect to

AGND. Up to ±6V can be applied to these pins without

the risk of permanent damage.

Refer to Section 1.0 “Electrical Characteristics”.

3.6 Master Clear (MCLR)

MCLR controls the rese t for both del ta-sig ma ADCs, al l

digital registers, the SINC filters for each channel and

all accumulators post multiplier. A logic ‘0’ resets all

registers and holds both ADCs in a Reset condition.

The charge stored in both ADCs is flushed and their

output is maintained to 0x0000h. The only block

consuming power on the digital power supply during

Reset is the oscillator circuit.

3.7 Reference (REFIN/OUT)

REFIN/OUT is the output for the internal 2.4V

reference. This reference has a typical temperature

coefficient of 15 ppm/°C and a tolerance of ±2%. In

addition, an external reference can also be used by

applying voltage to this pin within the specified range.

REFIN/OUT requires appropriate bypass capacitors to

AGND, even when using the internal reference only.

Refer to Section 5.0 “Applications Information”.

3.8 Analog Ground (AGND)

AGND is the ground connection to the internal analog

circuitry (ADCs, PGA, band gap reference, POR). To

ensure accuracy and noise cancellation, this pin must

be connected to the same ground as DGND, preferably

with a star connection. If an analog ground plane is

available, it is recommended that this device be tied to

this plane of the Printed Circuit Board (PCB). This

plane sho ul d also reference all o the r a nalog ci rcu itry i n

the system.

3.9 Frequency Control Logic Pins

(F2, F1, F0)

F2, F1 and F0 select the high-frequency output and

low-frequency output pin ranges by changing the

value of the constants FC and HFC used in the device

transfer function. FC and HFC are the frequency

constants that define the period of the output pulses

for the device.

3.10 Gain Control Logic Pins (G1, G0)

G1 and G0 select the PGA gain on Channel 0 from

three different values: 1, 8 and 16.

3.11 Oscillator (OSC1, OSC2)

OSC1 and OSC2 provide the master clock for the

device. A resonant crystal or clock source with a similar

sinusoidal waveform must be placed across these pins

to ensure proper operati on. The typic al clock freque ncy

specified is 3.579545 MHz. However, the clock

frequency can be with the range of 1 MHz to 4 MHz

without disturbing measurement error. Appropriate

load c apaci tance should b e conne cted to th ese pin s for

proper operation.

A full-swing, single-ended clock source may be

connected to OSC1 with proper resistors in series to

ensure no ringing of the clock source due to fast

transient edges.

3.12 Negative Power Output Logic Pin

(NEG)

NEG detects the phase difference between the two

channel s an d wi ll go to a logi c ‘ 1’ state when the phase

difference is g r ea ter th an 9 0° (i. e., wh en th e m eas ure d

active (real) power is negative). T he output state i s syn-

chronous with the rising-edge of HFOUT and maintains

the logic ‘1’ until the active (real) power becomes posi-

tive again and HFOUT shows a pulse.

3.13 Ground Connection (DGND)

DGND is the ground connection to the internal digital

circuitry (SINC filters, multiplier, HPF, LPF, Digital-to-

Frequency (DTF) converter and oscillator). To ensure

accuracy and noise cancellation, DGND must be

connected to the same ground as AGND, preferably

with a star connection. If a digital ground plane is

available, it is recommended that this device be tied to

this pl ane of the PCB. This pl ane shou ld also r eference

all other digital circuitry in the system.

3.14 High-Frequency Output (HFOUT)

HFOUT is the high-frequency output of the device and

suppli es the inst ant aneous real- power informati on. The

output is a per iod ic pul se ou tput, wit h it s p eriod p ropor-

tional to the measured active (real) power, and to the

HFC const ant defined by F0, F1 and F2 pin logic states.

This output is the preferred output for calibration due to

faster output frequencies, giving smaller calibration

times. Since this output gives instantaneous active

(real) power, the 2ω ripple on the output should be

noted. However, the average period will show minimal

drift.

3.15 Frequency Output (FOUT0, FOUT1)

FOUT0 and FOUT1 are the frequency outputs of the

device that supply th e ave rage real-powe r info rma tio n.

The outputs are periodic pulse outputs, with its period

proportional to the measu red active (real) power , and to

the Fc constant, defined by the F0 and F1 pin logic

states. These pins include high-output drive capability

for direct use of electromechanical counters and 2-

phase stepper motors. Since this output supplies

average active (real ) power , any 2ω ripple on the output

pulse per iod is minimal.

MCP3905/06

4.0 DEVICE OVERVIEW

The MCP3905/06 is an energy-metering IC that

suppli es a frequenc y output propo rtional to act ive (real)

power, and higher frequency output proportional to the

instantaneous power for meter calibration. Both chan-

nels use 16-bit, second-order, delta-sigma ADCs that

oversample the input at a frequency equal to MCLK/4,

allowing for wide dynamic range input signals. A

Programmable Gain Amplifier (PGA) increases the

usable range o n the cu rrent input chann el (Chann el 0).

The calculation of the active (real) power , as well as the

filter ing assoc iated with th is calcul ation, is performe d in

the digital domain, ensuring better stability and drift

performance. Figure 4-1 represents the simplified

block diagram of the MCP3905/06, detailing its main

signal-processing blocks.

Two digit al high-p ass fi lters can cel the s ystem of fset on

both channels such that the real-power calculation

does not include any circuit or system offset. After

being hi gh-pass filte red, the voltage and current signals

are multiplied to give the instantaneous power signal.

This s ignal does n ot cont ain the DC offset component s,

such that the averaging technique can be efficiently

used to give the desired active (real) power output.

The instantaneous power signal contains the real-

power information; it is the DC component of the

instantaneous power. The averaging technique can be

used with both sinusoidal and non-sinusoidal wave-

forms, as well as for all power factors. The

instantaneous power is thus low-pass filtered in order

to produce the instantaneous real-power signal.

A DTF converter accumulates the instantaneous active

(real) power information to produce output pulses with a

frequency proportional to the average active (real)

power. The low-frequency pulses presented at the

FOUT0 and FOUT1 outputs are designed to drive electro-

mechanical counters and two-phase stepper motors

displaying the real-power energy consumed. Each pulse

corresponds to a fixed quantity of real energy, selected

by the F2, F1 and F0 logic settings. The HFOUT output

has a higher frequency setting and lower integration

period such that it can represent the instantaneous

active (real) power signal. Due to the shorter accumula-

tion time, it enables the user to proceed to faster calibra-

tion under steady load conditions (refer to Section 4.7

“FOUT0/1 and HFOUT Output Frequencies”).

FIGURE 4-1: Simplified MCP3905/06 Block Diagram with Frequency Contents.

HPF

...1010..

DTF

–

ADC

–

PGA

LPF

HPF

CH0+

CH0-

CH1+

CH1-

ADC

OUT0

OUT1

OUT

MCP3905/06

0 00

Frequency

Content

ΔΣ

ADC Output

Code Contains

System and

ADC Offset

DC Offset

Removed

by HPF

Instantaneous

Power

ANALOG DIGITAL

Instantaneous

Active (Real) Power

Input Signal

with System

Offset and

Line Frequency

MCP3905/06

4.1 Analog Inputs

The MCP3905/06 analog inputs can be connected

directly to the curre nt and volt age tran sducers (suc h as

shunts or current transformers). Each input pin is

protected by special ized El ectrost atic Disc harge (ESD)

structures that are certified to pass 5 kV HBM and

500V MM contact charge. These structures also allow

up to ±6V continuous voltage to be present at their

inputs without the risk of perma nen t dam age .

Both channels have fully differential voltage inputs for

better no ise performance. The absolute volt age at each

pin relative to AGND should be maintained in the ±1V

range du ring operati on in orde r to ensure the m easure-

ment error performance. The common mode signals

should be adapted to respect both the previous

conditions and the differential input voltage range. For

best performance, the common mode signals should

be referenced to AGND.

The current channel com prises a PG A on the fron t-end

to allow for smaller signals to be measured without

additional signal conditioning. The maximum differen-

tial voltage specified on Channel 0 is equal to

±470 mV/Gain (see Table 4-1). The maximum peak

voltage specified on Channel 1 is equal to ±660 mV.

4.2 16-Bit Delta-Sigma ADCs

The ADCs used in the MCP3905/06 for both current

and voltage channel measurements are delta-sigma

ADCs. They comprise a second-order, delta-sigma

modula tor using a multi -bit DAC and a t hird-order SINC

filter. The delta-sigma architecture is very appropriate

for the app lications t argeted by th e MCP3905, becaus e

it is a waveform-oriented converter architecture that

can offer both high linearity and low distortion perfor-

mance throughout a wide input dynamic range. It also

creates minimal requirements for the anti-aliasing filter

design. The multi-bit architecture used in the ADC

minimizes quantization noise at the output of the

converters without disturbing the linearity.

Both ADCs have a 16-bit resolution, allowing wide input

dynami c range sensing . The oversampli ng ratio of both

converters is 64. Both converters are continuously

converting during normal operation. When the MCLR

pin is low, both converters will be in Reset and output

code 0x 0000h. If the voltag e at the inpu ts of the ADC is

larger tha n the specified range, the l inearity is no longer

specified. However, the converters will continue to

produce output codes until their saturation point is

reached . The DC saturati on point is arou nd 700 mV for

Channe l 0 an d 1V for Chan nel 1, using intern al volt ag e

reference.

The clocking signals for the ADCs are equally distrib-

uted between the two channels in order to minimize

phase delays to less than 1 MCLK period (see

Section 3.2 “High-Pass Filter Input Logic Pin

(HPF)”). The SINC filters main notch is positioned at

MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing

the user to be able to measure wide harmonic content

on either channel. The magnitude response of the

SINC filter is shown in Figure 4-2.

FIGURE 4-2: SINC Filter Magnitude

Response (MCLK = 3.58 MHz).

4.3 Ultra-Low Drift VREF

The MCP3905/06 contains an internal voltage refer-

ence source specially designed to minimize drift over

temperature. This internal VREF supplies reference

volt age to both c urrent and vo lta ge channel AD Cs. The

typical value of this voltage reference is 2.4V , ± 100 mV .

The internal reference has a very low typical tempera-

ture coefficient of ±15 ppm/°C, allowing the output

frequencies to have minimal variation with respect to

temperature since they are proportional to (1/VREF)².

REFIN/ OUT is the outpu t pin for th e vo lt a ge re ference.

Appropriate bypass capacitors must be connected to

the REFIN/OUT pin for proper operation (see

Section 5.0 “Applications Information”). The

voltage reference source impedance is typically 4 kΩ,

which enables this voltage reference to be overdriven

by an external voltage reference source.

TABLE 4-1: MCP3905 GAIN SELECTIONS

G1 G0 CH0 Gain Maximum

CH0 Voltage

00 1±470mV

01 2±235mV

10 8±60mV

11 16 ±30 mV

TABLE 4-2: MCP3906 GAIN SELECTIONS

G1 G0 CH0 Gain Maximum

CH0 Voltage

00 1±470mV

01 32 ±15 mV

10 8±60mV

11 16 ±30 mV

-120

-100

-80

-60

-40

-20

0 5 10 15 20 25 30

Frequency (kHz)

Normal Mode Re je cti on (dB )

MCP3905/06

If an external voltage reference source is connected to

the REFIN/OUT pin, the external voltage will be used

as the reference for both current and voltage channel

ADCs. The voltage across the source resistor will then

be the difference between the internal and external

voltage. The allowed input range for the external volt-

age source goes from 2.2V to 2.6V for accurate mea-

surement error. A VREF value outside of this range will

cause additional heating and power consumption due

to the so urce re sisto r, which mi ght af fec t meas ureme nt

error.

4.4 Power-On Reset (POR)

The MCP3905/06 contains an internal POR circuit that

monitor s analo g supply v oltage AVDD during opera tion.

This circuit ensures correct device startup at system

power-up/power-down events. The POR circuit has

built-in hysteresis and a timer to give a high degree of

immunity to potential ripple and noise on the power

supplies, allowing proper settling of the power supply

during power-up. A 0.1 µF decoupling capacitor should

be mounted as close as possible to the AVDD pin,

providing additional transient immunity (see

Section 5.0 “Applications Information”).

The threshold voltage is typically set at 4V, with a

tolerance of about ±5%. If the supply voltage falls below

this threshold, the MCP3905/06 will be held in a Reset

conditi on (e quivale nt to a ppl yi ng l ogic ‘0’ on the M CLR

pin). The typical hysteresis value is approximately

200 mV in order to prevent glitches on the power

supply.

Once a powe r-up even t has occurred , an interna l timer

prevents the p art fro m outpu t tin g an y pulse for ap pro x-

imately 1s (with MCLK = 3.58 MHz), thereby prevent-

ing potential metastability due to intermittent resets

caused by an unsettled regulated power supply.

Figure 4-3 illustrates the different conditions for a

power-up and a power-down event in the typical

conditions.

FIGURE 4-3: Power-on Reset Operation.

4.5 High-Pass Filters and Multiplier

The active (real) power value is extracted from the DC

instantaneous power. Therefore, any DC offset

component present on Channel 0 and Channel 1

affects the DC component of the instantaneous power

and will cause the real-power calculation to be

erroneous. In order to remove DC offset components

from the instantaneous power signal, a high-pass filter

has been introduced on each channel. Since the high-

pass filtering introduces phase delay, identical high-

pass filters are implemented on both channels. The

filt ers a re cloc ked by the same dig ital si gnal, ensur ing

a phase difference between the two channels of less

than one MCLK period. Under typical conditions

(MCLK = 3.58 MHz), this phase difference is less than

0.005°, with a line frequency of 50 Hz. The cut-off

frequency of the filter (4.45 Hz) has been chosen to

induce minimal gain error at typical line frequencies,

allowing sufficient settling time for the desired applica-

tions. The two high-pass filters can be disabled by

applying a logic ‘0’ to the HPF pin.

FIGURE 4-4: HPF Magnit ude Respon se

(MCLK = 3. 58 MHz).

The multip li er output gives the prod uc t of the tw o hig h-

pass -filtered c hannels , correspondi ng to ins tant aneous

active (real) power. Multiplying two sine wave signals

by the sam e ω freq uency gives a D C compo nent an d a

2ω component. The instantaneous power signal con-

tains the activ e (real) power of its DC com ponent, while

also containing 2ω components coming from the line

frequency multiplication. These 2ω components come

for the line frequency (and its harmonics) and must be

removed in order to extrac t th e real-power info rma tio n.

This is a cc om pli shed us ing th e l ow -pass filter and DT F

converter.

AVDD

4.2V

DEVICE

MODE RESET PROPER

OPERATION RESET

PULSE

OUT

Time

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequen cy (Hz)

Normal Mode Rejection (dB)

MCP3905/06

4.6 Low-Pass Filter and DTF

Converter

The MCP3905/06 low-pass filter is a first-orde r IIR filter

that extracts the active (real) power information (DC

component) from the instantaneous power signal. The

magnitude response of this filter is detailed in Figure 4-

5. Due to the fac t that the instantaneous power signal

has harmonic content (coming from the 2ω components

of the inputs), and since the filter is not ideal , there will

be some ripple at the output of the low-pass filter at the

harmonics of the line frequency.

The cut-off frequency of the filter (8.9 Hz) has been

chosen to have sufficient rejection for commonly-used

line frequencies (50 Hz and 60 Hz). With a standard

input clock (MCLK = 3.58 MHz) and a 50 Hz line

frequency, the rejection of the 2ω component (100 Hz)

will be more than 20 dB. This equates to a 2ω

component containing 10 times less power than the

main DC component (i.e., the average active (real)

power).

FIGURE 4-5: LPF Magnitude Response

(MCLK = 3. 58 MHz).

The output of the low-pass filter is accumulated in the

DTF converter. This accumulation is compared to a

different digital threshold for FOUT0/1 and HFOUT,

representin g a q uantit y of real e nergy meas ured by the

part. Every time the digital threshold on FOUT0/1 or

HFOUT is crossed, the part will output a pulse (See

Section 4.7 “FOUT0/1 and HFOUT Output Frequen-

cies”).

The equivalent quantity of real energy required to

output a pulse is much larger for the FOUT0/1 outputs

than the H FOUT. This is such that the integration period

for the FOUT0/1 outputs is much larger. This larger

integration period acts as another low-pass filter so that

the outpu t rip ple due to th e 2ω components is mi nimal.

However, these components are not totally removed,

since realized low-pass filters are never ideal. This will

create a small jitter in the output frequency. Averaging

the output pulses with a counter or a Microcontroller

Unit (MCU) in the application wil l then remove the small

sinuso idal conte nt of the output freq uency and fi lter out

the remaining 2ω ripple.

HFOUT is intended to be used for calibration purposes

due to its instantaneous power content. The shorter

integration period of HFOUT demands that the 2ω

compon ent be give n more atten tion. Sinc e a sinuso idal

signal average is zero, averaging the HFOUT signal in

steady-sta te c ond iti ons w il l gi ve the p rop er rea l energy

value.

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequency (Hz)

Normal Mode Rejection (dB)

MCP3905/06

4.7 FOUT0/1 and HFOUT Output

Frequencies

The thresholds for the accumulated energy are differ-

ent for FOUT0/1 and HFOUT (i.e., they have different

transfer functions). The FOUT0/1 allowed output

frequencies are quite low in order to allow superior

integration time (see Section 4.6 “Low-Pass Filter

and DTF Converter”). The FOUT0/1 output frequency

can be calcu lat ed wi th the fol lowi ng equ ation:

EQUATION 4-1: FOUT FREQUENCY

OUTPUT EQUATION

For a given DC input V, the DC and RMS values are

equivalent. For a given AC input signal with peak-to-

peak amplitude of V, the equivalent RMS value is

V/sqrt(2), assuming pu rely sinusoidal signals . Note that

since th e act iv e (real ) power i s the product o f t wo R M S

inputs, the output frequencies of an AC signal is half

that of th e DC equival ent signal, a gain assum ing purely

sinusoidal AC signals. The constant FC depends on the

FOUT0 and FOUT1 digital settings. Table 4-3 shows

FOUT0/1 output frequencies for the different logic set-

tings.

FOUT Hz() 8.06 V0

×V1

×GF

××

VREF

()

-----------------------------------------------------------

Where:

V0=the RMS diff erential volt age on Channel 0

V1=the RMS diff erential volt age on Channel 1

G=the PGA gain on Channel 0

(current channel)

FC=the frequency constant selected

VREF =the voltage reference

TABLE 4-3: OUTPUT FREQUENCY CONSTANT FC FOR FOUT0/1 (VREF =2.4V)

F1 F0 FC (Hz) FC (Hz)

(MCLK = 3.58 MHz)

FOUT Frequency (Hz)

with Full-Scale

DC Inputs

FOUT Frequency (Hz)

with Full-Sca le

AC Inputs

00MCLK/221 1.71 0.74 0.37

01MCLK/220 3.41 1.48 0.74

10MCLK/219 6.83 2.96 1.48

11MCLK/218 13.66 5.93 2.96

MCP3905/06

The high-frequency output HFOUT has lower

integration times and, thus, higher frequencies. The

output frequency value can be calculated with the

following equation:

EQUATION 4-2: HFOUT FREQUENCY

OUTPUT EQUATION

The constant HFC depends on the FOUT0 and FOUT1

digital settings with the Table 4-4.

The detailed timings of th e outp ut pulse s are d escr ibed

in the Timing Characteristics table (see Section 1.0

“Electri cal Characte ristics” and Figure 1-1).

MINIMAL OUTPUT FREQUENCY FOR

NO-LOAD THRESHOLD

The MCP3905/06 also includes, on each output

frequenc y, a no-l oad thre shold ci rcuit t hat will elimi nate

any creep effects in the meter. The outputs will not

show any pulse if the output frequency falls below the

no-load threshold. The minimum output frequency on

FOUT0/1 and HFOUT is equal to 0.0015% of the

maximum output frequency (respectively FC and HFC)

for each of the F2 , F1 and F0 se lectio ns (se e Table 4-3

and Table 4-4); except when F2, F1, F0 = 011. In this

last configuration, the no-load threshold feature is

disabl ed. The selection of FC will determine the st art-up

current load. In order to respect the IEC standards

requirements, the meter will have to be designed to

allow start-up currents compatible with the standards

by choosing the FC value matching these

requirements. For additional applications information

on no-load threshold, startup current and other meter

design points, refer to AN994, "IEC Compliant Active

Energy Meter Design Using The MCP3905/6”,

(DS00994).

TABLE 4-4: OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF =2.4V)

HFOUT Hz() 8.06 V0

×V1G×× HFC

VREF

()

----------------------------------------------------------------

Where:

V0=the RMS differential voltage on Channel 0

V1=the RMS differential voltage on Channel 1

G=the PGA gain on Channel 0

(current channel)

FC=the frequency constant selected

VREF =the voltage reference

F2 F1 F0 HFCHFC (Hz) HFC (Hz)

(MCLK = 3.58 MHz) HFOUT Frequency (Hz) with

full-scale AC Inputs

000 64 x FCMCLK/215 109.25 27.21

001 32 x FCMCLK/215 109.25 27.21

010 16 x FCMCLK/215 109.25 27.21

0112048 x FCMCLK/2727968.75 6070.12

100128 x FCMCLK/216 219.51 47.42

101 64 x FCMCLK/216 219.51 47.42

110 32 x FCMCLK/216 219.51 47.42

111 16 x FCMCLK/216 219.51 47.42

MCP3905/06

5.0 APPLICATIONS INFORMATION

5.1 Meter Design using the

MCP3905/06

For all applications information, refer to AN994, "IEC

Compliant Active Energy Meter Design Using The

MCP3905/6” (DS00994). This application note

includes all required energy meter design information,

including the following:

• Meter rating and current sense choices

• Shunt design

• PGA selection

• F2, F1, F0 selection

• Meter calibration

• Anti-aliasing filter design

• Compensation for parasitic shunt inductance

• EMC design

• Power supply design

• No-load threshold

• Start-up cu rrent

• Accuracy testing results from MCP3905-based

meter

• EMC testing results from MCP3905-based meter

MCP3905/06

6.0 P ACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu meric tracea bil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

XXXXXXXXXXX

YYWWNNN

24-Lead SSOP Examples:

XXXXXXXXXXX MCP3905

0739256

I/SS^^

MCP3905/06

24-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 24

Pitch e 0.65 BSC

Overall Height A – – 2.00

Molded Package Thickness A2 1.65 1.75 1.85

Standoff A1 0.05 – –

Overall Width E 7.40 7.80 8.20

Molded Package Width E1 5.00 5.30 5.60

Overall Length D 7.90 8.20 8.50

Foot Length L 0.55 0 .75 0.95

Footprint L1 1.25 REF

Lead Thickness c 0.09 – 0.25

Foot Angle φ0° 4° 8°

Lead Width b 0.22 – 0.38

NOTE 1

A1 L1 L

A2 φ

Microchip Technology Drawing C04-132

MCP3905/06

NOTES:

MCP3905/06

APPENDIX A: REVISION HISTORY

Revision A (July 2005)

Original Release of this Document.

Revision B (August 2005)

Replace Figures 2-1 thru 2- 6 in Section 2.0 “Typical

Performance Curves”

Revision C (October 2005)

Added references to MCP3905/06 throughout

document.

Revision D (February 2007)

This revision includes updates to the packaging

diagrams.

MCP3905/06

NOTES:

MCP3905/06

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3905: Energy-Metering IC

MCP3905T: Energy-Metering IC (Tape and Reel)

MCP3906: Energy-Metering IC

MCP3906T: Energy-Metering IC (Tape and Reel)

Temperature Range: I = -40°C to +85°C

Package: SS = Plastic Shrink Small Outline (209 mil Body),

24-lead

PART NO. –X /XX

PackageTemperature

Range

Device

Examples:

a) MCP3905-I/SS: Industrial Temperature,

24LD SSOP.

b) MCP3905T-I/SS: Tape and Reel,

Industrial Temperature,

24LD SSOP.

a) MCP3906-I/SS: Industrial Temperature,

24LD SSOP.

b) MCP3906T-I/SS: Tape and Reel,

Industrial Temperature,

24LD SSOP.

MCP3905/06

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

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T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thail a nd - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhage n

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Sp ain - Madri d

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921- 5820

WORLDWIDE SALES AND SERVICE

12/08/06