SIEMENS
Pr~gramma~ble Controller
Programming Instructions Order No.: GWA 4NEB 810 2120-02 a
Fig.
1
S5-101U programmable controller
CONTENTS Page Page
THE PROGRAMMING LANGUAGE 4.2.1
STEP 5 programming language
1.1
4.2.2
Program structure
1.1
4.2.3
PRINCIPLE
OF
OPERATION 4.2.4
OF THE PC
Program processing 2.1
"RUN
and "STOP" modes 2.2 5.
Memor
i
es 2.2 5.1
5.1.1
NOTES
ON
PROGRAM
DEVELOPMENT 5.1.2
Power-up 3.1 5.1.3
Battery mon
i
tor
i
ng 3.2 5.1.4
Ren ten
tive/non-rententive 5.1.5
flags 3.2 5.1.6
Interrupt processing 3.2
Intercompatibi
l
i
ty between 5.1.7
LAD, CSF and STL 3.4 5.1.8
Operation in the SINEC L1 3.7 5.2
local area network 5.2.1
5.2.2
PROGRAM START-UP 5.2.3
Loading and dumping a 5.2.4
program
4.1
5.2.5
Program test 4.2 6.
Search function
Signal status display
Forcing of outputs and
flags
Forcing of timers and
counters
PROGRAMMING EXAMPLES
Basic operations
Binary logic operations
Setting/resetting operations
Load and transfer operations
Timer functions
Counter functions
Comparison (relational)
operations
Arithmetic operations
Other functions
Supplementary operations
Logic operations (word mode)
Conversion functions
Shift operations
Jump operations
Cond
i
t
i
on codes
OPERATION SET
1.
The
programming language
1.1
STEP
5
programming language
The user programs are written in the
STEP 5 programning language. The
statements of this
l
anguage permit
not only the programning of simple
binary functions but also the pro-
gramming of complex digital functions.
Depending on the programmer used, all
three methods of representation
statement list (STL)
1 adder d
i
agram (LAD)
control system flowchart (CSF)
are possible so that the method of
programming can be adapted to the
particular application. Only STL pro-
gramming is possible with the hand-
held 605U programmer. The machine
code generated by the 6701675 pro-
grammers is identical for all
three methods of representat ion
..
1.2
Program structure
The user program consists of up to
1024
statements and can be written as a pro-
gram block (PB) or function block (FB).
WFy
PBl
at
FBI
can
k
exwwted
on
%c
S5+1O1U
programable
contrallsr,
Program block
A program block can be programmed and
documented in
a11 three methods of re-
presentation (STL, LAD and CSF).
A
pro-
gram block can be translated from one
method of representation into the two
other methods with the 6701675 program-
mers provided certain programming rules
are observed (see Section
3.4).
For users famil far with contactors and
re1 ays, the LAD method is recommended
since the ladder diagram has very close
similarities with schematic circuit
diagrams.
Program blocks are used especially
when a CRT-based programmer is avail-
able and programming or documen-
tation is to be made in graphic form.
Fig.
2:
Methods of representation with
the STEP 5 programming language
to
3lN
19 239
idrcftl
Function block
Function blocks can only be written
and documented in STL form.
Jump operations make
it
possible to
enhance the structuring of the user
program and thus also its capabilities.
Short, constant response times to inter-
rupts can be implemented with load and
transfer operations in conjunction with
jump operations (see Section
3.4).
Note: Supplementary operations must
not be used in
PB1.
+o
2lh
19 239
Idrcctl
to
KC
117-15
DIN
L3
705
DIN
40
719
DIN
19
23i
,
lrrlfti
2.
Principle
of
operation
2.1
Program
processing
The control functions of the lOlU are
defined by a user program.
In order to be able to scan the user
program cyclically statement by state-
ment, the CPU has to perform the follow-
ing functions:
1.
In the case of a cold restart (power
switch from
"Off"
to "On" or mode
selector from "Stop" to "Run"), the
process output image* is erased,
i.e. all outputs are set to zero.
2.
The process input image* is updated,
i.e. all signal statuses of the in-
puts are scanned and written into
the process input image.
The user program (PB1 or FBI) is
scanned and processed statement by
statement. When scanning the signal
statuses of the inputs, the
CPU
ac-
cesses the process input image and
not the actual inputs. When latching
and unlatching the outputs (coils),
only the process output image is
overwritten to begin with.
4. Once the user program has been pro-
cessed, the process output image
is transferred to the actual out-
puts.
5.
Points 2,
3
and
4
are handled cycli-
cal
ly.
Cold restart
Cr>
Erase process
output image
I
Cycle checkpoint
Read process
input image
12nd statement
I
Last statement
H
Transfer process
I
output image to
the outputs
Fig.
3:
Principle of operation of the
S5-101U
A
scanning operation from cycle check-
point to cycle checkpoint takes approx.
70 ms for 1024 statements (binary).
If
a scanning cycle is not completed
within 300 ms due to program errors
*
Process 1/0 image:
or faults, an internal monitor responds, Internal memory area in which the
the PC enters the "Stop" status and signal status ("0" or "1") of the
all outputs (coils) are switched off. inputs/outputs is stored.
The
"Run"
and "Stop" modes
"RUN" mode
p-
In the "RUN" mode, the program is scanned
cyclically from cycle checkpoint to
cycle checkpoint. The PC is brought
into the "RUN" mode by
-
switching the mode selector to
"RUN1'
-
selecting the "PC RUN1' function of
the programner (mode selector in "RUN"
position)
-
and on recovery of the power supply
if
the mode selector is at "RUN" and
was in the "RUN" position prior to
the power failure.
Memories
The PC has an internal program memory,
the data of which can be supported for
three years by a backup battery.
There are also two different memory
submodules (see Fig. 4).
"STOP" mode
In the "STOP" mode, the program is not
scanned and the outputs (coils) are
disabled. While the PC is in the "STOP"
state, all timers and counters and the
process 1/0 image retain the values
or states they had in the last scanning
cycle prior to the PC entering the "STOP"
state.
If
the PC is switched to "RUN",
the timers and counters (0
...
7) are
reset. The non-retentive flags and the
process 1/0 image are erased.
The
PC
is brought into the "STOP" mode
by
-
switching the mode selector to "STOP"
-
selecting the "PC STOP" function on
the programmer
-
faults or errors in program scanning,
e.g. time-out or operations that can
not be interpreted by the PC.
The cause for the PC entering the 'STOP"
state can be traced with the aid of
the "DISPLAY ESTACK" function of the
programner (see Section 4.2 of Operating
Instructions).
The memory submodules are used for pro-
gram dumping or for copying the program
should only one memory submodule be
used for a number of PCs.
On
power-up or when the PC is switched
to
"RUN",
the contents of the memory
submodule are always copied into the
internal memory and processed there.
Fig. 4: Differences between the EPROM and EEPROM submodules.
Memory submodu
l
e
Program
dump
Program
erasure
Program mod
i
-
fication via
programmer
EPROM
PG
615 (with adapter 984-2UAll)
PG 670 (with adapter 984-OUAll)
PG 675
Only with special UV lamp
(erasure time: 30 min)
On
1~
erasure of entire
program possible
EEPROM
PG 615
PG 670 (without 984
adapter)
PG 675
Direct in the PC with
the above programmers
and the PG 605U pro-
9
r
amme
r
Programmer function:
PG PC)
possible
3.2
Battery
monitoring
Flag F 63.6 is used for monitoring the The PC must be in the "RUN" state.
battery. Flag F 63.6 is reset by the "ERASE PRO-
This flag is set by the operating system
GRAM"
function of the programner or by
of the PC on power recovery and during the user program. The user can therefore
the normal scanning cycle
if
failure determine how the PC is to react to
of the battery backup v01 tage is detected. backup battery fail ure.
The S5-101W has a total of 512 flags.
The flag area is subdivided as follows:
Retentive flags (F 0.0
...
F
31.7)
-
retain their last state prior to
-
power-down on power-up (with backup
battery only)
-
retain their last state when the
mode is changed from "STOP" to "RUN"
(with and without backup battery)
-
are reset like the non-retentive
flags on power-up (without backup
battery)
-
can also be reset by the user pro-
gram
(
"
ERASE PROGRAM" function
).
By using retentive flags, the last
status of the plant or machine prior
to the PC leaving the "RUN" mode can
be stored. On restart, the plant or
machine can resume operations at the
point at which
it
was stopped.
Interrupt processing
When an interrupt signal (e.g. emer-
gency off) from the process is re-
ceived by the PC, the latter inter-
rupts cyclic scanning of the user program
and inititates the processing of a
specific interrupt routine.
Interrupt processing with the S5-101U
is defined exclusively by the user pro-
gram so that each input and output can
be used for interrupt processing.
Non-retentive flags (F 32.0.. .F 63.7)
-
are reset when the PC mode changes
from "STOP" to "RUN" and on power-up.
Flags F 61.0
-
F 62.7 are reserved
as coordinating
fl
ags for operation
in the SINEC L1 local area network;
flags F 63.0
-
F 63.7 are reserved
as system flags. Since they are af-
fected by the PC operating system,
they must not be used as flags in
the normal sense.
In order to achieve minimum response
times, the inputs and outputs are re-
ferenced direct, i.e. outside cyclic
program scanning. The load/transfer
operations "LPB" (inputs) and "TPB"
(outputs) are available for this pur-
pose.
A
more or less constant response time
is achieved
if
the scanning of the in-
puts programmed by the user as interrupt
inputs is uniformly distributed over
the entire user program. Fig. 6 shows
a user program with interrupt processing.
Task: When input
I
0.0
becomes
"l",
outputs
Q
@.g.
..
Q
0.7
are to assume
the state of flags F 3.a
...
F3.7. In
order to keep the response time as
short and constant as possible, ten
interrupt scans should be written in
the user program.
User
program
STEP
5
program (STL)
Interrupt
routine
Expl
anat ions
1st interrupt scan: by loading PB
0,
I
0.0
is scanned direct, i.e. by-
passing the process image, and mapped
on F
@.a.
If
F
0.0
(and consequently
I
0.0)
is
"l",
a jump is made to the
interrupt routine.
F
10.0
defines the
return address.
2nd
i
nterrupt scan
10th interrupt scan
Flag byte FB3 is transferred direct into
peripheral byte PB
0,
i.e. direct to
the outputs. The process output image
is updated.
By scanning flags
F
10.0
...
F 11.0 (only
one flag is used), the user program is
continued at the return address last
defined.
Fig.
6:
Example of a user program with interrupt scanning
3.5
Intercompatibility between LAD, CSF and STL
General
Each of the methods of representa-
tion in the STEP
5
programming
languages has specific properties
and limitations.
Consequently, a program block written
in STL cannot simply be displayed as
an LAD or CSF and the graphic methods
of representation, LAD and CSFy may
not always be fully compatible.
In other words, one form cannot al-
ways be translated back into the
other form.
If
the program has been entered as Fig.
7:
Range and limitations of the
an LAD or CSF,
it
can always be trans- methods of representation in the
lated back into STL form. STEP
5
programming language
Input Output
The aim of this section is to establish
a number of rules, which,
if
adhered to,
will
ensure complete compatibility be-
tween the three methods of representation.
These rules are classified as follows:
-
Rules for compatibility between the
graphic methods of representation
(LAD and CSF)
.
If
these rules are followed, input is
possible in one graphic form and display
in the others.
Fig.
8:
Graphic input
I
nput Output
-
Rules for compatibility between the
statement list and the graphic methods
of representat ion.
If
these rules are observed,
it
is
possible to enter a program in any
if
the three methods of representation,
graphic or not, and to have
it
dis-
played in the other two forms.
Fig.
9:
Input in the form of a statement list
Input as LAD and dis~lav as CSF (STL)
Rule: Do not exceed the display
boundaries for LAD.
Excessive nesting may cause the LAD
display boundary to be exceeded
(8
levels)
max
.4
Example of maximum LAD nesting for display as CSF
Input as CSF and display as LAD (STL)
Rule
1:
Do not exceed the display
boundaries for LAD.
Too many inputs on a CSF box cause
the
l
adder diagram display boundary
to be exceeded.
CSF
Fig.
11:
Example of a maximum
AND
box in CSF form for display as an LAD
Rule 2: The output of a complex ele-
ment (memory, comparator, timer and
counter) must not be ored.
Fig. 12: Only AND boxes are allowed in.CSFs after a complex element.
In~ut as STL and display as LAD or CSF
Rule
1:
A
complex element must not have In addition, every unused input or out-
a preceed
i
ng operation. put must be assigned an NOP 0 operation.
Rule 2: The inputs and outputs of com- In the case of timers and counters, the
plex elements must be programmed in set input and the input for loading the
the order in which they are assigned time (TW) or count (ZW) must be dis-
parameters on the screen in graphic abled together.
mode.
Times and counts are exceptions since
the relevant value must first be stored
in the accumulator with a load operation.
STL
LAD
CSF
Fig. 13: Example for assigning NOP operations to unused inputs and outputs
3.6
Operation in the SINEC
L1
local area network
The SINEC L1 local area network is used
for interconnecting programnabl e con-
trol
l
ers of the
l
ow-end performance
range and operates on the Master-Slave
principle.
The CP 530 comrnun
i
cations processor
is always the Master, and the slaves
the CPUs of all small PCs. Each slave
is assigned a s1 ave number under which
it
is referenced. Data can be inter-
changed between the master and up to
30 slaves, as well as between the indi-
vidual slaves. In the case of the S5-101U,
the slave number, the coordinating flags
and the send and receive mailboxes are
defined as follows:
Slave numk
The slave number is stored at the beginning
of the user program (PBlIFB1) together
with an indentifier.
In addition to the actual data, control
and security information, which the
STEP 5 user program can access through
a coordinating flag word, is also trans-
mi
tted
.
The actual data are deposited in a receive
mailbox and a send mailbox which the
user can access with load and transfer
operations.
header
SF
63.0
LKF
..
Identifier
Nos.
1...30
RECEIVE coordinatinq
fl
aq b.yte (KME) SEND coordinating
fl
aq byte (KMS)
Flag byte FB
61
is used. Flag byte FB
62
is used.
M61.7
.
.
.
M 61.0
I
I
1-r~
Receive error in last transfer
ERROR with master
SLAVE FAIL
A
slave in the network has failed
BUS-RUN BUS is in RUN state
PG-BIT Programmer requests the bus access
INTERRUPT This message is accompanied by an interrupt
EMPF-ERK Operating system may accept data from the bus into
the receive mailbox
Bit from bus master
M62.7
.
M
62.0
Send error In last transfer
Slave permits programmer access
SEND-ERK User releases send mailbox for sending to the bus
Bit for bus master
The coordinating flags are affected by the operating system of the PC and
can therefore not be used as flags in the normal sense.
Receive mailbox
The receive mailbox is in data block
DB1 (DW 40
...
DW72) and has the following
structure
:
l) Slave No.
0
=
Master
DL 40
DL 41
DL 42
DL 71
DL 72
Send mailbox
The send mailbox is in data block DB
1
(DW88..
.DW
112) and has the
following structure:
LENGTH of net
(0.. .64)
1st
i
tern of data
3rd item of data
61st item of data
63rd item of data
l) Slave No.
0
=
Master
DR 40
DR
41
DR
42
DR 71
DR
72
DL 80
DL 81
DL 82
DL
111
Nett
data
Nett
data
SOURCE-SLAVE No.
(0.. .30)
2nd item of data
4th item of data
62nd
i
tem of data
64th itemof data
LENGTH of nett data
(0.. .64)
1st item of data
3rd item of data
61st item of data
For more detailed information on the SINEC L1 local area network, please refer to the
Instructions (4NEB 811-0545) and Programming Instructions (4NEB 811-0546) of the SINEC L1
network
.
DW 40
DW 41
DW 42
DW 71
DW 72
DL 112 63rd item of data
DR
112
DR
80
DR
81
DR 82
DR
111
p
p-
64th item of data DW 112
DESTINATION SLAVE No.
(0.. .30)
2nd item of data
4th
i
tern of data
62nd item of data
.-
DW 80
DW 81
DW 82
DW
111
4.
Program Start
=up
The hand-held PG 605U/615 programmer The following settings are necessary
and the CRT-based PG 670 and PG 675 on the PG 670 and PG 675 programners
programmers can be used for loading in conjunction with the S5-1101 U pro-
and testing programs. grammable controller:
PG 670: S5-150
AK
S5-130
W
PG 675: S5-150
S
NO
4.1
Loading and dumping a program
Fig. 14: Schematic of a program loading operation followed by the
dumping of the program in an EEPROM submodule 4.1
Before loading the program, the "ERASE When the program has been loaded,
it
PROGRAM"
function must be executed. is transferred from the programmer memory
This deletes to the internal memory of the
PC.
If
-
the internal program memory of the PC an EEPROM submodule is plugged in, the
-
the binary process
I/O
image program is automatically dumped.
-
all flags Once the program has been transferred
-
error identifiers and the causes of to the PC memory,
it
is no longer in
interrupts. the programner memory and must be brought
back into the latter before program
corrections can be made*
(output FBl/PBl)
.
Dumping of the program in an EPROM sub-
module is possible on the PG 615 (with
adapter), PG 670 (with 984 adapter)
and PG 675 programmers.
To dump the program
in
an EPROM sub-
module, proceed as shown in Fig. 14.
Put PC to STOP
r-------
*
I
I
Dump program
Erase program
I
t
I
\Ir
Load program
I
Put PC to STOP
into programmer
1
i
I
$
I
Transfer pmgram Carry out any pro-
I
from programmer gram corrections
Transfer program'
from
PC
to pro-
*
4
I
grammer
to
PC
JI
JI
-
Transfer program'
I
Plug EEPROM
from PC to pro-
I
submodule
in
Set
PC
to RUN grammer
L
*
JI
4
I
r
I
Tmnsfer pmg-am
I
from programmer
Test pmgram Set
PC
to STOP
+
JI
I
to
Pc
'b
2
T
I
\
.
I
.
r
Is program execu-
I
4
I
t
ing properly?
I
J
R
Necessary only in the case
of the
605U
progmmmer End
Wait until program-
ming is completed
4.2
Program
test
Faults causing the PC to enter the The following debugging functions are
"STOP" status can be identified with available for tracing logic errors in
the aid of the interrupt stack (see program scanning.
Instructions, Section
4.2)
4.2.1 Search function
The programmer "Search" function is Search runs are important in conjunction
available for locating points in the with the following functions:
user program.
-
Input/correction
In the test phase, for instance, all
-
Display
points in a program containing a de-
-
Program-dependent signal status display
finite operand can be displayed, e.g.
an output not acting as expected. For more details, please refer to the
The following search keys can be used: Operating Instructions of the programmers.
-
Statements, e.g.
AI
1.0
-
merands, e.g.
I
1.0
-
Labels (FB
1
only)
-
Addresses
4.2.2 Signal status display
The following programmer functions are
available for displaying the signal
statuses of binary and digital operands:
Direct signal status display Program-dependent signal status display
The status of any operands can be ob- This test function enables the signal
served at the cycle checkpoint (Sec- status of an operand and the result
tion
2.1)
with the aid of this function. of the logic operation to be observed
when the selected statement is processed.
4.2.3 Forcing of outputs and flags
The "FORCE" function enables definite
binary and digital operands to be in-
f
luenced with the PC in the
"RUN"
mode.
The desired statuses of the operands
are entered from the programmer byte
by byte and transferred to the PC.
The following can be forced:
-
QB
0..
.
QB
3
-
FB O...FB
63
In this way,
it
is possible to force
definite outputs on system startup without
the user program and check the correct
wiring of actuators and indicators etc.
When forcing while a user program is
executing, the operand statuses entered
are transferred once to the PC and program
scanning resumed with these statuses
entered may be modified by the current
program.
4.2.4
Forcing of timers and counters
Timers and counters can be forced
in both operating modes of the PC,
using
the
605U, 615 and OP
393
programmer on
l
y
.
Programming (from version
1
.l
onwards)
Data words
DW
0
to
DE
15 in data block
DB
1
are reserved for the preset values
for timers and counters.
In the user program, reference is made
to the associated data word when timers
and counters are started.
DWP
T
15
C
P
to
If
both timers counters are to
be forced, different numbers should
be used, e.g.
A
maximum of 16 timers/counters
in any combination can be forced.
The following program is required
in the PC:
Programming (from version 1.2 onwards)
Data words
DW
!l
to
DW
15 in data block
DB
1
are reserved for the preset values
for timers and counters.
In the user program, reference is made
to the associated data word when timers
and counters are started.
T
B-DW
0 to T 15-DW 15
C
0-DW 15 to
C
16-DW 31
16 timers and 16 counters can be forced.
-
The following program is required in
the
PC:
LKT is repl aced by
;
LDW
LD~
16
i
LKC is repl aced by
SC
1
LDW (16.. .31)
~DW
0
LIT is replaced
SIT
Q
by LDW
~MD
1
LKC is rep1 aced
S
C
1
by LDW
Make sure that there are meaningful
time values in the data words used when
changing from the "STOP" to the "RUN"
mode.
It
is advisable to force the timers/
counters (with the preset values) in
the "STOP" status of the PC.
Forcing with the programmer
The data word assigned to a timer For further information, p1 ease refer
or counter is loaded with the preset to the Programning Instructions of the
value, using the "Direct signal status 605U programmer in the Section entitled
d ispl ay" function of the programmer. "PROGRAM TEST-Forc ing of timers and
The data block for the preset value counters."
can be selected on the programmer
(but DB1 is mandatory for the S5-101U PC).
5.
Programming examples
5.1
Basic operations
5.1
.l
Binary logic operations
AND
logic
Original ISTEP
5
representation
Statement
A
I
1.1
A
I
1.3
A
I
1.7
=
a
1.0
A
"1"
signal appears at output
Q
1.0
There are no restrictions imposed
when all the inputs have
"1"
signals on the number of scans and the pro-
simultaneously. gr ammi ng sequence.
A
"0"
signal appears at output
Q
1.0
if
at least one of the inputs has a
"0"
signal.
OR
logic
Original
l
STEP
5
representation
A
"1"
signal appears at output
Q
1.2 There are no restrictions imposed
if
at least one of the inputs has a on the number of scans and the pro-
"1"
signal. grammi ng sequence.
I
l.Zl'J.5
.5
Q
1.2
A
"0"
signal appears at output
Q
1.2
when all inputs have
"0"
signals si-
mu1 taneously.
Statement
list
0
I
1.2
0
I
1.7
0
I
1.5
=
a
1.2
L
adder
(
Control system
diagram flowchart
Q
1.2
AND before
OR
logic
Original
A
"1"
signal appears at output
Q
1.1
when the output of at least
one of the AND gates is
"1".
STEP
5
representation
A
"On
signal appears at output
Q
1.1
when neither of the AND
gates has
"1"
at its output.
Statement
list
OR
before AND
logic
Original
Ladder
d iagram
ai.
I
ai.1
Control system
flowchart
Control system
flowchart
STEP
5
representation
A
"1"
signal appears at output
Q
1.1
if
input
I
1.0
or
I
1.1
and one of
the inputs
I
1.2 or
I
1.3 have a
"1"
signal.
Statement
list
A
"0"
signal appears at output
Q
1.1
when input
I
1.0
has a
"0"
signal
and the AND gate has a
"0"
at its output.
Ladder
diagram
OR
before
AND
logic
A
"1"
signal appears at output
Q
2.0
when both
OR
gates have
"1"
signals
at their outputs.
Original
A
"0"
signal appears at output
Q
2.0
when
at
least one of the
OR
gates
has a
"0"
signal at this output.
Scanning for
"0"
signal status
STEP
5
representation
A
"1"
signal appears at output
Q
2.6
only when input
I
1.5
has
a
"1"
signal and input
I
1.6
a
"0"
signal.
Control system
flowchart
Statement Ladder
Original
11.5 11.6
Q
2.0
list diagram
STEP
5
representation Control system
flowchart
11.5
a
11.6
aQ2.0
Statement
list
A
11.5
AN1
1.6
=
Q2.g
Ladder
diagram
11.6
5.1.2
Setting /resetting operations
RS
flip-flop for latched signal outputs
Original
I
STEP
5
representation
:'
....
:.:':.*..::'L,::.:
....
:..
A
"1"
at input
I
1.4 resets the
@$@E;:@:
...%..:.
S..:
is only necessary
if
program is
flip-flop. to be represented in
LAD
or
CSF
form
on the 670/675 programmer. When
If
the signal at input
I
1.4 changes programming
with
LAD or
CSF,
these
to
"OU,
this status is maintained.
NOP
@
operations are automat ical
ly
i
ncl uded.
Control system
flowchart
Statement
list
11
4
I17
Q1
5
RS
flip-flop with flags
Ladder
diagram
A
I17
I
1.7
Q
1
5
S
Q15
Q
15
R
Q15
HOP
#f
R
a
Original
I
A
"1"
at signal
I
1.7 sets the flip-
If
the set (input
I
1.7) and reset
flop. (input
I
1.4) signals are applied
simultaneously, the scan operation
If
the signal at input
I
1.7 changes last programmed (in this case AI 1.4)
to
"ON,
this status is maintained, i.e. remains effective during processing
the signal is latched. of the remaining program.
A
"1"
at input
I
1.6 sets the flip-
If
the signal at input
I
1.3 changes
flop. to
"OM,
this status is maintained.
If
the set (input
I
1.6) and reset
If
the signal at input
I
1.6 changes (input
I
1.3) signals are applied si-
to
"OM,
this status is maintained, mu1 taneously, the scanning operation
i.e. the signal is latched. last programmed (in this case AI 1.6)
remains effective during processing of
A
"1"
at input
I
1.3 resets the the remaining program, i.e. flag
F
1.7
flip-flop. is set (setting signal has priority over
the resetting signal
).
5.4
STEP
5
representation Control system
flowchart
Statement Ladder
A
113
=
0
14
I
list diagram
Implementation of a transition-sensitive pulse (pulse edge evaluation)
Original
l
STEP
5
representation
A
I
1.7
ANF
4.0
=
F
2.6
A
F
2.0
S
F
4.0
AN1
1.7
The AND logic condition (AI 1.7 and The AND logic condition
AI
1.7 and
AN F 4.0) is fulfilled at each posi- AN
F
4.0 is no longer fulfilled at
tive-going edge of the signal at in- the next program scan since flag
put
I
1.7 and flags F
4.0
and F 2.0 F 4.0 has been set.
("Pulse edge flags") are set
if
the
result of the logic operation
(RLO)
Flag 2.0 is reset, i.e.
it
is only
is
"1".
"1"
during a single program pass
or scan.
Control system
flowchart
-
Statement
list
Binary scaler
(T
or trigger flip-flop)
I I
Ladder
diagram
Original
l
STEP
5
representation
A 1l.d
ANF 1.6
S
0
1.0
A 11.0
A
F1.0
R
Q
1.0
.
....:
$g$&$$$
ANI
';
I.
a
A
Q
1.0
S
F
1.0
AN1 1.0
ANQ 1.0
Output
Q
1.0 changes its state on a po-
If
a defined frequency is applied to the
sitive-going transition at input
1.fl.
input, therefore, half the input frequency
A
negative-going change at the input has appears at the output.
no effect on the output.
Control system
flowchart
Statement
list Ladder
diagram
5.1.3
Load and transfer operations
Load and transfer
When loading/transferring FW,
IW
and
QW,
the following relationship between
the accumulator contents and the byte
belonging to a particular word applies:
contents
15
.........
@er-
ation
L
00
ff.
I
B
IW
Q
B
Q
W
F B
F
W
0
R
D L
DW
P
B
T
CT
C
K
ti3)
K F~)
K y3)
Ks3)
K T~)
K c3)
Note:
contents
15
.........
The progranable control
l
er has two
accumulators (16 bits) for relational
and arithmetic operations and for digital
logic.
Loading implies that the contents of
accumulator
1
are relocated
to
accu-
mulator 2 and that accumulator
1
is
reloaded in keeping with the operand
of the load operation.
After two load operations, therefore,
information can be obtained, for example,
on the contents of the accumulators
in connection with relational or com-
parison operations.
Function er-
ation
Load T
00
an input
!jte
(from PI1
)
ff
IB
an input word
(from PII)
IW
anoutput yte
P
(from
PI$
)
QB
an output word
(from PIO) QW
aflagbyte
a flag word FB
data FB
(right-hand byte) D
R
data
(
left-hand byte) D L
data
(word)
D
W
a peripheral byte
Parameters
0 to 5
0 to 4
0 to3
.
0 to 2
Oto63
0 to 62
1
to 255
I
to 255
1
to 255
0 to 5
0 to 15
0 to 15
0 to 15
0 to 15
random bit
(16 bits)
0 to FFFF
-
32768 to
+
32767
0 to 255
for each
byte
2random
alpha-
numeric
characters
0.0 to
999.3
0 to 999
When loading an FB, IB, QB or PB, the
byte is always loaded in the
low
byte
of the accumulator. 0 is written into
the high byte of the accumulator.
When transferring an FB, IB, QB or PB,
it
is always the low byte of the accumul-
ator that is transferred.
of the digital 1/0
modules (bypassing Load and transfer operations are ab-
the PIO) solute operations, i.e. they are carried
a time (binary) out independently of the result of
(BCD) the previous logic operation.
a count (binary)
(BC01 Graphics programming of load and transfer
a constant as operations is only possible indirectly
bit pattern in connection with timer and counter
a constant in operation, otherwise only in statement
hexadecimal code lists.
a constant as
fixed-point number
a constant,
2 bytes
aconstant,2ASCII
characters
a time (constant)
a count (constant)
Parameters
Oto5
Oto4
Oto3
Ot02
0 to 63
0 to 62
1
to 255
1
to 255
1
to 255
The transfer operation always transfers
the contents of accumulator
1
to the
operand specified in the transfer oper-
ation. The contents are not changed.
Function
Transfer
an input b e
(from PI1
Ij)
an input word
(from PII)
an output
(from PI0
$jF
an output word
(from PIO)
a flag byte
a flag word
data
(right-hand byte)
data (left-hand
byte)
data (word)
1) PI1 process image of inputs
2) PI0 process image of outputs
3) Four-byte instruction with the opcode
in bytes 0/1 and the constant in bytes
213
Loading and transferring a time
(see also under timer and counter operations)
During graphic input,
FW
20 was assigned Outputs
B1
and D1 are digital outputs.
to output
BI
of the timer. The time appears in binary code
(BCD
with time base) at output
B1
(DE).
The programmer automatically stores
the corresponding load and transfer
operation in the user program. In this
way, the contents of the memory location
addressed with T 10 are loaded into
accumul ator
1.
The contents of accumulator
1
are then
transferred to
FW
20.
Original
T1orpoy
FW20
Transfer
The time T10 in binary code in this
example can be traced at
FW
20.
STEP
5
representation Control system
flowchart
t(l!lk!~-~FW~o
Statement
list
A
I
2.0
i{iir.O
L
T10
T
FW20
MOP
Q
MOP
BI:
Ladder
diagram
pq-bFw20
5.1.4
Timer
functions
Pulse
Timers are restarted on power recovery
following a powerfail condition.
Original
The timer is started during the first
scanning cycle
if
the result of the
logic operation is
"l".
The timer re-
mains unaffected during subsequent scan-
ning resulting in
"1"
signal.
STEP
5
representation
The timer is set to "0" (reset)
if
the
result of the logic operation is "0".
diagram
The AT and OT scans result in a
"1"
signal as long as the timer is running.
Control system
flowchart
The timer is loaded with the specified
value (10). The number to the right
of the point indicates the time base:
0
5
0.01
S
251s
120.1
S
3GlOs
B1
and
DE
are digital outputs. The time
appears at output
B1
(DE)
in
BCD.
Extended pulse
Original
A
I20
L
KT10
2
S
ET1
NOPB
NOPQ
NOPQ
AT1
=
Q
1.0
STEP
5
representation
Statement Ladder Control system
The timer is started during the first
scanning cycle
if
the result of the
I
2.0
J-L--v-
logic operation is
"It1.
Q1.O
&k-A-&
list
The timer remains unaffected
if
the
result of the logic operation is "0".
The AT or OT scan results in a
"1"
signal
as long as the timer is running.
diagram flowchart
"ON"
delay
The timer is started during the first
scanning cycle
if
the result of the
logic operation is
"1".
The timer remains
6
1::
ge
unaffected during subsequent processing
if
the result of the logic operation The timer is loaded with the specified
is
"1".
value
(9).
The number to the right of
the point indicates the time base:
The timer is set to "0" (reset)
if
the 0
a
0.01
S
2e
1
S
result of the logic operation is "0".
12
0.1
S
3a10s
Original Statement
The AT or OT scan results in a
"1"
signal Outputs
B1
and
DE
are digital outputs.
when the time has elapsed and the result The time appears at output
B1
(DE) in
of the logic operation is still present BCD.
at the input.
STEP
5
representation
Latching
"ON"
delay
!list diagram flowchart
Ladder Control system
The timer is started during the first The AT or OT scans result in a
"1"
signal
scanning cycle
if
the result of the when the time has elapsed. The signal
logic operation is
"1".
status only becomes
"ON
if
the timer
is reset with the
RT
operation.
The timer is unaffected
if
the result
of the logic operation is "0".
I
1.6d
Q1.3
Original
STEP
5
representation
Statement Ladder Control system
list
I
I
diagram flowchart
"OFF"
delay
The timer is started during the first
scanning cycle
if
the result of the
logic operation is "0". The timer remains
unaffected during subsequent processing
if
the result of the logic operation
Original
The timer is set to "0" (reset)
if
the
result of the logic operation is
"1".
The
A
T
or OT scan results in a
"l"
signal
if
the timer is running or
if
the result of the logic operation is
still present at the input.
A
I14
L
KT1000
A
T5
004
=
a
0.4
Q
0.4
STEP
5
representation
The timer is loaded with the specified
value (9). The number to the right of
the point indicates the time base:
0
=^
0.01
S
221s
l?
0.1
S
3110s
Statement
list
Outputs B1 and
DE
are digital outputs.
The time appears at output B1 (OE) in
BCD
.
Ladder
diagram Control system
flowchart
Clock
pulse generator
A
clock pulse generator can be con-
structed from a self-clocking timer
F2
0
U
with a T flip-flop (binary scaler)
at its output.
Timer
T
7
is restarted with flag
F
2.0
each time its time elapses,
i.e. flag
F
2.0
has a
"1"
signal
for one cycle each time the time
e
l
apses
.
These pulses from flag
F
2.g
act on
the following T flip-flop with the
result that a pulse train with a
mark-space ratio of
1
:
1
appears
at output
Q
6.6.
The period dura-
tion of this pulse train is twice
as great as the time of the self-
clocking timer.
5.1.5
Counter functions
Set counter
Original
I
STEP
5
representation
Statement Ladder
/
list
I
diagram
/
Control system
flowchart
I
2.1
KC1
Sg
Ill
The counter is set during the first In the above example, the starting value
scanning cycle
if
the result of the of the counter is 150.
logic operation is
"1".
The counter B1 and DE are digital outputs. The count
remains unchanged during subsequent appears at output
B1
(DE) in
BCD.
processing (irrespective of whether
the result of the logic operation is
"1"
or
"0").
The counter is set again
(pulse edge evaluation) at the next
first scanning cycle
if
the result of
the logic operation is
"1".
Reset counter
Original
l
STEP
5
representation
The counter is reset when the result of
the logic operation is
"1".
The counter remains unchanged
if
the
logic operation becomes "0".
Control system
flowchart
Statement
list Ladder
diagram
The value of the addressed counter is
A
counter with two different inputs
incremented by
1.
The CU function is can be used as an upldown counter by
effective only on a positive-going means of the two separate pulse-edge
pulse edge (from
"0"
to
"l")
of the flags for CU and
CD.
result of the logic operation pro-
grammed before CU.
Original
I1 l
KCQl8
a1
0
Counting down
STEP
5
representation
Statement Ladder Control system
list diagram flowchart
A
I
2.1
LKC
918
AC1
=Q
10
Original STEP
5
representation
Statement Ladder Control system
list diagram flowchart
120KCfl25
A
L
10
CDC
1
SC
1
A
I
21
F
100
I21
F
10B
AC1
The value of the addressed counter is
A
counter with two different inputs
decremented by
1.
The
CD
function is can be used as an up/down counter by
effective only on a positive-going means of the two separate pulse-edge
pulse edge (from
"0"
to
"l")
of the flags for CU and
CD.
logic operation programmed before
CD.
5.1.6
Comparison (relational) operations
Comparing for equal to
The operand first specified is compared The numerical representation of the
with the subsequent operation in keeping operands is taken into account, i.e.
with the comparison function. The result the contents of the accumulators are
of the comparison is flagged by condition interpeted as being fixed-point numbers.
codes
CC0
and
CC1.
After a comparison for equal to, a jump
can be made to a label
(+
127
words)
with the jump operation
JZ
=
. ..
(if
RLO
=
1).
Original
IB0
IB1
Q
1.0
Comparing for not equal to
STEP
5
representation
for
IBO=IBl
IB
0
IB
1
IB
0
>
IB
1
The operand first specified is compared The numerical representation of the
with the subsequent operand in keeping operands is taken into account, i.e.
with the comparison function. The result the contents of the accumulators are
of the comparison is flagged by condition interpreted as being fixed-point numbers.
codes
CC0
and
CC1.
Following a comparison for not equal
to, a jump can be made to a label
(+
127
words) with the jump operation
JN
=
. .
.
(if
RLO
=
1).
Control system
flowchart
Statement
list
L
IB0
CC1
0
0
1
Original
IB0
IB1
Q1
l
Ladder
diagram
L
IB1
!
=F
=
(21.0
CC0
0
1
0
STEP
5
representat~on
IB1
IB1
RL 0
1
0
0
RLO
0
1
1
for
IB
0
=
IB
1
IB
0
c
IB
1
IB
0
>
IB
1
Control system
flowchart
Statement
list
L
180
Ladder
diagram
CC1
0
0
1
L
IB1
><F
=
Q1.l
CC0
0
1
0
I
B1
I
B
1
Comparing for greater than
The operand first specified is compared The numerical representation of the
with the subsequent operand in keeping operands is taken into account, i.e.
with the comparison function. The result the con tents of the accumulators are
of the comparison is flagged by condition interpreted as being fixed-point numbers.
codes
CC0
and
CC1.
After a comparison for greater than,
a
jump can be made to a label
(+
127
words) with the jump operation
3
=
.
.
.
(if RLO
=
1).
Or~glnal
180 IBI
Q1
2
for
lc~lc;lRio
IB
0
=
IB 1
IB
0
<
IB 1
IB
0
>
IB 1
STEP
5
representation
Comparing for
less
than
Control system
flowchart
1~o-j~~
IBI
c2
Q
a12
/Statement
i
Iis
t
L
IB0
L
IB1
>
F
=
81
2
Original
IB0 IB1
I
I
01.4
for
IB
0
=
IB 1
IB
0
<
IB
1
IB
0
>
1%
1
Ladder
diagram
1B017J
Q1
2
IB~
c2
The operand first specified is corn- The numerical representation of the
pared with the subsequent operand in operands is taken into account, i.e.
keeping with the comparison function. the con tents of the accumulators are
The result of the comparison is flagged interpreted as being fixed-point numbers.
by condition codes
CC0
and
CC1.
After comparing for less than, a jump
can be made to a label
(2
127
words)
with the jump operation
JM
=
...
(if
RLO
=
1).
STEP
5
representation
CC1
0
0
1
Control system
flowchart
IB0
-
IB1
-
-
Q1.4
Statement
\is
t
L
IBO
L
IB1
F
=
01.4
CC0
0
1
0
Ladder
diagram
1~0]7k.4 IB1
C2
RLO
0
1
0
Comparing for greater than or equal to
The operand first specified is compared The numerical representation of the
with the subsequent operand in keeping operands is taken into account, i.e.
with the comparison function. The result the con tents of the accumulators are
of the comparison is flagged by condition interpreted as being fixed-pobnt num-
codes
CC0
and
CC1.
bers.
After comparison for greater than or
equal to,
a
jump can be made to a label
(+
127
words) with the jump operation
Jr
(if RLO
=
1
).
Original
IB0
IB1
Q1
3
Comparing for
less
than or equal to
STEP
5
representation
RLO
1
0
1
for
IB
0
=
IB 1
IB 0
<
IB 1
IB 0
>
IB 1
The operand first specified is compared The numerical representation of. the
with the subsequent operand in keeping operands is taken into account, i.e.
with the comparison function. The result the contents of the accumulators are
of the comparison is flagged by condition interpreted as being fixed-point numbers.
codes
CC0
and
CC1.
After comparing for less than or equal
to, a jump can be made to a label
(+
-
127
words) with the jump operation
JC
=
.
.
.
(if
RLO
=
1).
Control system
flowchart
Statement
list
L
IB0
Or~ginal
IB0
IB1
0
01.5
Ladder
diagram
CC1
0
0
1
L
IB1
>=F
=
Q1
3
CC0
0
1
0
STEP
5
representation
I01
C2
for
IB 0
=
IB 1
IB 0
<
IB
1
IB
0
>
IB 1
Control system
flowchart
Statement
list
L
IB0
CC0
0
1
0
CC1
0
0
1
Ladder
diagram
RLO
1
1
0
L
IB1
<=F
=
Q1
5
IB1
Q
Cl1
5
5.2
Supplementary operations
Supplementary operations can only be
programmed in
FB
1.
5.2.1
Logic
operations
Accumulators
1
and
2
can be loaded by
two load operations in keeping with
the operands of these load operations.
The contents of both accumulators can
then be digi tal ly
gated.
Operation
AW
OW
XOW
Description
Digital ANDing of accumul-
ators
1
and
2
Digital ORing of accumul-
ators
1
and
2.
Digital EXORing of
accumulators
1
and
2.
Example
The hexadecimal number
3F84H
is to be ANDed
with input word
1
of
inputs
IW
1.
The
result is to appear in
Output word zero of the
outputs (QW
0).
3F84H
IW
3H
Result
AW
The two bit patterns
0101 1110 1000 1011
and
0111 0001 0111 1100
are to be ORed with
each other.
STL
L
KH
3F84
L ]IN1
AW
T
QW
0
L
KM
01...11
L
KM
01
...
00
Explanation
The hexadecimal number 3F84 is loaded
into accumulator
l;
at the same time,
the old contents of accumulator
1
are
shifted into accumulator
2.
Input word
1
(IW
1)
is loaded into ac-
cumulator
1
and the hexadecimal number
shifted into accumulator
2.
The con-
tents accumulator
1
are digitally ANDed
with those of accumulator
2
and the
result stored in accumulator
1.
The contents of accumulator
1
(result)
are transferred to out~ut word.
QW
0.
The first bit pattern is loaded into
accumulator
1;
at the same time, the
old contents of accumulator
1
are shifted
into accumulator
2.
The second bit pattern is loaded into
accumulator
1
and the first bit pattern
shifted into accumulator
2.
The contents of accumulator
1
are ORed
with those of accumulator
2
and the
result stored in accumulator
1.
The contents of accumulator
1
(result)
are transferred to flagword FW
13.
Data word DW
12
is loaded into accumulator
1;
at the same time, the old contents of
accumulator
1
are shifted into accumulator
2.
Input word
IW
0
is loaded into accumul-
ator
1
and data word
L
DW
12
shifted
into accumulator
2.
The contents of accumulator
1
are EXORed
with those of accumulator
2
and the
result stored in accumulator
1.
The contents of accumulator
1
(result)
are transferred to output word
QW
0.
0101 1110 1000 1011
0111 0001 0111 1100
Result
OW
Input word
IW
0
is to
be compared with data-
word
12
for equality.
The non-identical
bits of the word are
to appear in output
word
QW
0.
DW
12
EA83H
IW
0
68C5
Result
XCKTZR$
T
FW
13
L
DW
12
L
IW
0
xcu
l
TQW
0
5.2.4
Jump
operations
The jump destination for unconditional
and conditional jumps is specified as
a symbolic address (max.
4
characters).
In the case of the
PG
605U/ and
PG
615U
programmers, jump labels
MO...
M99
can
be assigned. The symbolic parameter
of the jump statement is identical to
the symbolic address of the statement
to which the jump is made. When pro-
gramming, make sure that the absolute
jump displacement does not exceed
+l27
words and note that a
STEP
5
statement
may consist of more than one word.
Jumps over segment boundaries are not
permissible.
All
jump operations (with the exception
of JU) depend on the RLO and the con-
di tion codes in the processor of the
programmable controller.
Operatian
JU
=
I]
JC
=
1-1
JZ
=
0
JN
1-1
JP
=
-1
JM
=
-1
JO
=
I
Description
Unconditional jump
The uncondi tional jump
i
S
executed independent-
ly
of any conditions.
Conditional jump
The condi tional jump
is executed
if
the
RLO is
"l".
If
the
result of the logic
operation is
"ON,
the
jump is not executed
and the RLO is set to
"l"
Jump
if
contents of
accumulator zero.
This jump is executed
if
the contents of
the accumulator are zero.
If
the contents are
not zero, the jump
is not executed. The
RLO is not changed.
Jump
'if
contents of
accumulator not zero.
This jump is executed
if
the contents of
the accumulator are
'
not zero.
If
the contents
are zero, the jump
is not executed. The
RLO is not changed.
Jump
if
contents of
accumulator positive.
The jump is executed
if
the contents of the ac-
cumul ator are greater
than zero.
If
the con-
tents of the accumulator
are zero or less than
zero, the jump is not
executed. The RLO is
not changed.
Jump
if
contents of
accumulator negative.
This jump is executed
if
the contents of
the accumulator are less
than zero.
If
the contents
are zero or greater
than zero, the jump is
not executed. The RLO is
not changed.
Jump on overflow
This jump is executed when
an overflow occurs.
If
there
is no overflow, the
jump is not executed. The
RLO is not changed.
Enter symbolic address
(max.
4
characters)
5.20
Example
If
none of the inputs of
input word
IW
1
is set,
a jump is made to label
"AN
1"
If
the input word
IW
1
and output word
'QW
0 are
not identical, a jump is
made back to label
"AN
0".
If
IW
1
and
QW
3
are iden-
tical,
IW
1
is compared
with data word
DW
12.
If
IW
1
is greater or
smaller than DW 12, a
jump is made to the
"Destination" label.
STL
AN0
:
IW
JZ.ANII
:
A
IW
AN]. :L
IW1
:L
QW
:XW
:
JP=ANO
m
:L
IW1
:L DW12
:
F
:JB=Destina-
tion
0
Desti-:A 112.2
nation
.
Explanation
Input word
IW
1
is loaded into
accumulator
1.
If
the contents
of accumulator
1
are equal to
zero, a jump is executed to label
"AN
l",
otherwise the next state-
rnent (AI 1.0) is executed.
Comparison of input word
IW
1
and output word QW3.
If
the two
words are not identical, individual
bits are set in accumulator
1.
If
the contents of accumulator
1
are not zero, a jump is made back
to the
"AN
0"
label, otherwise the
next statements are executed.
Input word
IW
1
is compared with
data word
W
12 for greater or less
than.
If
IW
1
is greater or less
than DW 12, the RLO is set to
"1".
If
RLO
=
"l",
a jump is made to the
"Destination" label.
If
RLO
=
"O",
the next statement is
executed.
6.
Operation set
Binary logic operations
Up
to
6
bracketing levels
:an
he
progranmed.
Settinghesetting operations
Aff-
ects
RLO
Opera-
ti
on Machine code
(hexadecimal)
Word 0
1
Word
1
B0
I
B1
1
B2
1
B3
Parameter Condition
codes
affected
CC1
I
CC0
I
OV
Dep-
ends
on
RLO
-
-
-
-
-
.E,
C).
X
c
rT(
0
E
.P
C)
=
VI
"
1
:.E
S
I
S
Q
S
F
R
I
R
Q
Timer and counter functions
Function
70
70
74
70
70
DO
DO
90
F0
F0
-
-
-
-
-
0.0 to 2.3
3.0 to
5.3
0.0 to 1.3
3.0 to 3.3
0.0t063.7
0.0 to 2.3
3.0 to 5.3
0.0 to 1.3
2.0 to 3.3
L
I
I
Setaninputto"ln
(in the' (PII)
Setanoutputto"1"
(in the PIO)
Setaflag
Reset an input to "0"
(in the PII)
Reset an output to "0"
(in the PIO)
Y
Y
Y
Y
Y
00
80
00
00
80
-
-
-
-
-
I I
I I
I
I I I
I
I
+
Relative address
Y
Y
Y
Y
Y
-
-
-
-
-
Load and transfer operations
+
Relative address
I
+
Opera-
tion Function
Aff-
Load an.input byte (from the PII)
Parameter (hexadecimal
)
Word 0
I
Word
1
B0
I
B1
(
B2
I
B3
Load an input word (from the PIO)
Load an output byte (from the PIO)
Load an output word (from the PIO)
Condition
Load a flaq byte
Maschine code
.-
I
-
&l.
ends
on
RLO
Load a flaq word
Dep-
Load data (left-hand byte)
Load data (right-hand byte)
ects
RLO
Load data (word)
Load a time
codes
affected
-eel
IOV
Load a count
Load a peripheral byte of the
inputs
S
g
.v
*
3
VI
0
1
a.,
Load a time (BCD)
Load a count (BCD)
Load and transfer operations (cont.)
Dep-
ends
on
RLO
N
Aff-
ects
RL
0
N
Opera-
tion
T IB
+F
-F
Parameter
0 to
5
Condition
codes
affected
79
59
.
*.
X
c
m
0
E
.-
-
W
U
1-
!.E
55
Maschine code
(hexadecimal)
CC1
Block calls
Function
Transfer to an input byte
(in the
PII)
00
00
CC0
-
Word
0
Function
Block end
Block end conditional
Block end unconditional
OV
-
Word 1
B0
48
-
-
'Z
7
X
a
0
E
-U
*
3
'4
U
I
:.E
42
46
42
B2
-
B1
00
B3
-
-
-
Dep-
ends
on
RLO
N
Y
Y
Opera-
tion
B E
BEC
BEU
Parameter Maschine code
(hexadecimal)
N
N
Aff-
ects
RL
0
Y
Y
Y
Word 0
N
N
B0
65
05
65
Word 1
Condition
codes
affected
B1
00
00
01
B2 CC~
Y
Y
B3
'CCO
-
-
-
Y
Y
'OV
-
-
-
Y
Y
58
54 Fixed-pointaddition
Fixed-point subtraction
Other operations
I
Logic operations (word mode) (supplementary operations)
I
I
Conversion operations (supplementary operations)
I
Dep-
ends
on
RLO
N
N
N
N
Opera-
ti
on
NOP
0
NOP
1
STP
BLD
1
Opera-
I
Parameter
1
Machine code
I
Dep-
I
Aff-
I
Condition
I
3,
l
Function
Parameter Machine code
(hexadecimal
)
AW
OW
XOW
Aff-
ects
RL 0
N
N
N
N
00
00
00
41
49
51
I
Shift operations (supplementary operations)
I
Word 0
ti
on
CFW
CSW
B0
00
FF
70
10
Word
1
N
N
I
Opera-
l
Parameter
I
Machine code
I
Dep-
1
Aff-
I
Condition
I
.g-
I
Function
1
+
Function
No operation
(all bits reset)
No operation
(all bits set)
STOP
Segment end for proqramminq
in statement list
Statement for constructing
displays in LAD form on
the programmer
B1
00
FF
03
00
B2
Opera-
tion
SLW
SIW
!,
+.
X
c
m
0
E
.F
*1
3
"7
U
I
2.5
40
40
44
40
Condition
codes
affected
B3
(hexadecimal)
I
+
Jump displacementl
CC1
N
N
ends
on
RLO
N
N
Parameter
0 to 15
0 to 15
tion
JU
=
JC
=
JZ
=
JN
=
JP
=
JM
=
JO
=
X
X
X
X
X
X
Word 0
+
Nurnh~r of shifts
CC0
-
-
-
-
ects
RL 0
N
N
B0
01
09
Word
1
10
X
Number nf shifts
Symbolic address
Symbolic address
Symbolic address
Symbolic address
Symbolic address
Symbolic address
SymbolicaddressOD
OV
-
-
-
-
-
-
-
B1
00
00
B2
-
-
Jump operations (supplementary operations)
Machine code
(hexadecimal
)
B3
-
-
Dep-
ends
on
RLO
N
55
55
55
codes
affected
Word 0
(hexadecimal)
ANDing of accumulators
1
and
2
ORing of accumulators
1
and 2
Exclusive-ORing of accumulators
1
and 2
Y.
X
S
2
.-
-
+
3
m
U
1
:.z
42
62
CC1
Y
Aff-
ects
RL 0
N
B0
61
69
Word
1
ends
on
RLO
N
Y
N
N
N
N
N
Formation of one's complement
(fixed point)
Formation of two's complement
(fixed point)
B1
00
00
B2
-
-
Word 0
CC0
-
Y
B3
-
-
N
ects
RL 0
N
Y
N
N
N
N
N
B0
2D
FA
45
35
15
25
Word
1
OV
~
-
Y
Condition
codes
affected
N
B1
00
00
00
00
00
00
00
B2
-
-
-
-
-
-
-
.E-
+.
X
c
m
0
E
.F
11
"7
U
I
;.E
49
CC1
Y
Y
B3
-
-
-
-
-
-
-
Function
Shift left (16 bits)
47
codes
af
f
ec ted
Shift right (16 bits)
1
CC0
Y
Y
W.
X
S
P
.P
+
3
V1
U
1
z.5
55
62
62
62
62
62
57
CC1
OV
-
-
Unconditional jump
Conditionaljump
(Jump condition: RLO)
Conditional jump
(Jump condition: CC
1,
CC 0)
Conditional jump
(Jump condition: CC
1,
CC 0)
Conditional jump
(Jump condition: CC
1,
CC 0)
Conditional jump
(Jump condition: CC
1,
CC 0)
Conditional jump
(Jump
rendition:
QV)
CC0
-
-
-
-
-
-
-
OV
'
-
-
-
-
-
-
-
SIEMENS AKTIENGESELLSCHAFT
Order
No.
EWA
4NEB
810
2119-02c
Printed in the Federal Republic
of
Germany