LTC3814-5
1
38145fc
60V Current Mode
Synchronous Step-Up Controller
The LTC3814-5 is a synchronous step-up switching regu-
lator controller that can generate output voltages up to
60V. The LTC3814-5 uses a constant off-time peak current
control architecture to deliver very high duty cycles with
accurate cycle-by-cycle current limit without requiring a
sense resistor.
A precise internal reference provides ±0.5% DC accuracy.
A high bandwidth (25MHz) error amplifi er provides very
fast line and load transient response. Large 1Ω gate driv-
ers allow the LTC3814-5 to drive large power MOSFETs
for higher current applications. The operating frequency
is selected by an external resistor and is compensated for
variations in VIN. A shutdown pin allows the LTC3814-5
to be turned off reducing the supply current to <230µA.
n 24V Fan Supplies
n 48V Telecom and Base Station Power Supplies
n Networking Equipment, Servers
n Automotive and Industrial Control Systems
n High Output Voltages: Up to 60V
n Large 1Ω Gate Drivers
n No Current Sense Resistor Required
n Dual N-Channel MOSFET Synchronous Drive
n ±0.5% 0.8V Voltage Reference
n Fast Transient Response
n Programmable Soft-Start
n Generates 5.5V Driver Supply
n Power Good Output Voltage Monitor
n Adjustable Off-Time/Frequency: tOFF(MIN) < 100ns
n Adjustable Cycle-by-Cycle Current Limit
n Undervoltage Lockout On Driver Supply
n Output Overvoltage Protection
n Thermally Enhanced 16-Pin TSSOP Package
High Effi ciency High Voltage Step-Up Converter Effi ciency vs Load Current
FEATURES DESCRIPTION
APPLICATIONS
TYPICAL APPLICATION
PGOOD
VOFF
PGOOD
VRNG
ITH
VFB SGND
RUN/SS
IOFF
1000pF
0.01µF
100pF
VIN
4.5V TO 14V
22µF
VOUT
24V
4A
VOUT
100k
100k
263k
LTC3814-5
EXTVCC
TG
SW
BG
PGND
INTVCC
NDRV
BOOST
38145 TA01
0.1µF M1
Si7848DP
M2
Si7848DP
1µF
29.4k
1k
270µF
× 2
4.7µH
+
+
D1
MBR1100
LOAD (A)
0
EFFICIENCY (%)
90
95
4
85
80 123
100
38145 TA01b
VIN = 12V
VIN = 5V
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No RSENSE
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5847554, 6304066, 6476589,
6580258, 6677210, 6774611.
LTC3814-5
2
38145fc
Supply Voltages
INTVCC ................................................... –0.3V to 14V
(INTVCC – PGND), (BOOST – SW) ......... –0.3V to 14V
BOOST (Continuous) ............................. –0.3V to 85V
BOOST (≤400ms) .................................. –0.3V to 95V
EXTVCC .................................................. –0.3V to 15V
(EXTVCC – INTVCC) .................................. –12V to 12V
(NDRV – INTVCC) Voltage ........................... –0.3V to 10V
SW Voltage (Continuous) .............................. –1V to 70V
SW Voltage (400ms) ..................................... –1V to 80V
IOFF Voltage (Continuous) .......................... –0.3V to 70V
IOFF Voltage (400ms) ................................. –0.3V to 80V
RUN/SS Voltage ........................................... –0.3V to 5V
PGOOD Voltage ............................................ –0.3V to 7V
VRNG, VOFF Voltages ................................... –0.3V to 14V
FB Voltage ................................................. –0.3V to 2.7V
TG, BG, INTVCC, EXTVCC RMS Currents .................50mA
Operating Junction Temperature Range
(Notes 2, 3, 7) ....................................... –40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 1)
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
IOFF
VOFF
VRNG
PGOOD
ITH
VFB
RUN/SS
SGND
BOOST
TG
SW
PGND
BG
INTVCC
EXTVCC
NDRV
17
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3814EFE-5#PBF LTC3814EFE-5#TRPBF 3814EFE-5 16-Lead Plastic TSSOP –40°C to 125°C
LTC3814IFE-5#PBF LTC3814IFE-5#TRPBF 3814IFE-5 16-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
LTC3814-5
3
38145fc
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
INTVCC INTVCC Supply Voltage l4.35 14 V
IQINTVCC Supply Current
INTVCC Shutdown Current
RUN/SS > 1.5V (Notes 4, 5)
RUN/SS = 0V
3
224
6
600
mA
µA
IBOOST BOOST Supply Current RUN/SS > 1.5V (Note 5)
RUN/SS = 0V
240
0
400
5
µA
µA
VFB Feedback Voltage (Note 4)
0°C to 85°C
–40°C to 85°C
–40°C to 125°C
l
l
l
0.796
0.794
0.792
0.792
0.800
0.800
0.800
0.800
0.804
0.806
0.806
0.808
V
V
V
V
∆VFB,LINE Feedback Voltage Line Regulation 5V < INTVCC < 14V (Note 4) l0.002 0.02 %/V
VSENSE(MAX) Maximum Current Sense Threshold VRNG = 2V, VFB = 0.76V
VRNG = 0V, VFB = 0.76V
VRNG = INTVCC, VFB = 0.76V
256
70
170
320
95
215
384
120
260
mV
mV
mV
VSENSE(MIN) Minimum Current Sense Threshold VRNG = 2V, VFB = 0.84V
VRNG = 0V, VFB = 0.84V
VRNG = INTVCC, VFB = 0.84V
–300
–85
–200
mV
mV
mV
IVFB Feedback Current VFB = 0.8V 20 150 nA
AVOL(EA) Error Amplifi er DC Open-Loop Gain 65 100 dB
fUError Amp Unity Gain Crossover
Frequency
(Note 6) 25 MHz
VRUN/SS Shutdown Threshold 0.6 0.9 1.2 V
IRUN/SS RUN/SS Source Current RUN/SS = 0V 0.7 1.4 2.5 µA
VVCCUV INTVCC Undervoltage Lockout INTVCC Rising
Hysteresis
l4.05 4.2
0.5
4.35 V
V
Oscillator
tOFF Off-Time IOFF = 100µA
IOFF = 300µA
1.55
515
1.85
605
2.15
695
µs
ns
tOFF(MIN) Minimum Off-Time IOFF = 2000µA 100 ns
tON(MIN) Minimum On-Time 350 ns
Driver
IBG,PEAK BG Driver Peak Source Current VBG = 0V 0.7 1 A
RBG,SINK BG Driver Pulldown RDS(ON) 1 1.5 Ω
ITG,PEAK TG Driver Peak Source Current VTG – VSW = 0V 0.7 1 A
RTG,SINK TG Driver Pulldown RDS(ON) 1 1.5 Ω
PGOOD Output
∆VFBOV PGOOD Upper Threshold
PGOOD Lower Threshold
VFB Rising
VFB Falling
7.5
–7.5
10
–10
12.5
–12.5
%
%
∆VFB,HYST PGOOD Hysteresis VFB Returning 1.5 3 %
VPGOOD PGOOD Low Voltage IPGOOD = 5mA 0.3 0.6 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V 0 2 µA
The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C (Note 2), INTVCC = VBOOST = VRNG = VEXTVCC = VNDRV = VOFF = 5V, unless
otherwise specifi ed.
ELECTRICAL CHARACTERISTICS
LTC3814-5
4
38145fc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3814-5 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3814E-5 is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3814I-5 is guaranteed
to meet performance specifi cations over the full –40°C to 125°C operating
junction temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3814-5: TJ = TA + (PD • 38°C/W)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PG Delay PGOOD Delay VFB Falling 125 µs
VCC Regulators
VEXTVCC EXTVCC Switchover Voltage
EXTVCC Rising
EXTVCC Hysteresis
l4.5
0.1
4.7
0.25 0.4
V
V
VINTVCC,1 INTVCC Voltage from EXTVCC 6V < VEXTVCC < 15V 5.2 5.5 5.8 V
∆VEXTVCC,1 VEXTVCC - VINTVCC at Dropout ICC = 20mA, VEXTVCC = 5V 75 150 mV
∆VLOADREG,1 INTVCC Load Regulation from EXTVCC ICC = 0mA to 20mA, VEXTVCC = 10V 0.01 %
VINTVCC,2 INTVCC Voltage from NDRV Regulator Linear Regulator in Operation 5.2 5.5 5.8 V
∆VLOADREG,2 INTVCC Load Regulation from NDRV ICC = 0mA to 20mA, VEXTVCC = 0 0.01 %
INDRV Current into NDRV Pin VNDRV – VINTVCC = 3V 20 40 60 µA
VCCSR Maximum Supply Voltage Trickle Charger Shunt Regulator 15 V
ICCSR Maximum Current into NDRV/INTVCC Trickle Charger Shunt Regulator,
INTVCC ≤ 16.7V (Note 8)
10 mA
Note 4: The LTC3814-5 is tested in a feedback loop that servos VFB to the
reference voltage with the ITH pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(QG • fSW).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
Note 8: ICC is the sum of current into NDRV and INTVCC.
Overcurrent Operation
The
l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C (Note 2), INTVCC = VBOOST = VRNG = VEXTVCC = VNDRV = VOFF = 5V, unless
otherwise specifi ed.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response Start-Up
VOUT
200mV/DIV
100μs/DIV
FRONT PAGE CIRCUIT
VIN = 12V
0A TO 4A LOAD STEP
38145 G01
IOUT
2A/DIV
VOUT
10V/DIV
1ms/DIV
FRONT PAGE CIRCUIT
VIN = 12V
ILOAD = 1A
38145 G02
RUN/SS
4V/DIV
IL
5A/DIV
VOUT
10V/DIV
200µs/DIV
FRONT PAGE CIRCUIT
VIN = 12V
VRNG = 1V
RSHORT = 1Ω
38145 G03
IL
5A/DIV
LTC3814-5
5
38145fc
Effi ciency vs Load Current Frequency vs Input Voltage Frequency vs Load Current
ITH Voltage vs Load Current Off-Time vs IOFF Current
Off-Time vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs Temperature
LOAD (A)
EFFICIENCY (%)
90
95
85
80
100
38145 G04
VIN = 12V
VIN = 24V
VIN = 36V
VOUT = 50V
04
123 5
INPUT VOLTAGE (V)
5
FREQUENCY (kHz)
260
280
300
13
240
220
200 7911 15
38145 G05
ILOAD = 0A
ILOAD = 1A
FRONT PAGE CIRCUIT
LOAD CURRENT (A)
0
FREQUENCY (kHz)
260
280
300
240
220
200 1234
38145 G06
VIN = 5V
VIN = 12V
FRONT PAGE CIRCUIT
LOAD CURRENT (A)
ITH VOLTAGE (V)
1
2
0
3
38145 G07
FRONT PAGE CIRCUIT
VIN = 12V
VRNG = 1V
04
123 5
ITH VOLTAGE (V)
0
–400
CURRENT SENSE THRESHOLD (mV)
–200
–300
–100
0
100
200
400
0.5 1 1.5 2
38145 G08
2.5 3
300
VRNG = 2V
1.4V
1V
0.7V
0.5V
IOFF CURRENT (µA)
10
10
OFF-TIME (ns)
100
1000
10000
100 1000 10000
38145 G09
VOFF = INTVCC
TEMPERATURE (°C)
–50
OFF-TIME (ns)
640
660
680
25 75
38145 G10
620
600
–25 0 50 100 125
580
560
IOFF = 300µA
VRNG VOLTAGE (V)
0.5
MAXIMUM CURRENT SENSE THRESHOLD (mV)
200
38145 G11
100
01 1.5
300
400
2
TEMPERATURE (°C)
–50 –25
190
MAXIMUM CURRENT SENSE THRESHOLD (mV)
210
240
050 75
38145 G12
200
230
220
25 100 125
VRNG = INTVCC
LTC3814-5
6
38145fc
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage
vs Temperature
Driver Pulldown RDS(ON)
vs Temperature
Driver Peak Source Current
vs Supply Voltage
Driver Pulldown RDS(ON)
vs Supply Voltage
EXTVCC Switch Resistance
vs Temperature
INTVCC Current vs Temperature
INTVCC Shutdown Current
vs Temperature
Driver Peak Source Current
vs Temperature
TEMPERATURE (°C)
–50 –25
0.797
REFERENCE VOLTAGE (V)
0.799
0.803
0.802
050 75
38145 G14
0.798
0.801
0.800
25 100 125
TEMPERATURE (°C)
–50
0.5
PEAK SOURCE CURRENT (A)
1.0
1.5
–25 0 25 50
38145 G15
75 100 125
VBOOST = VINTVCC = 5V
TEMPERATURE (°C)
–50
RDS(ON) (Ω)
1.25
1.50
1.75
25 75
38145 G16
1.00
0.75
–25 0 50 100 125
0.50
0.25
VBOOST = VINTVCC = 5V
DRVCC/BOOST VOLTAGE (V)
4 5 7 9 11 13
PEAK SOURCE CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
06 8 10 12
38145 G17
14
DRVCC/BOOST VOLTAGE (V)
4
RDS(ON) (Ω)
0.6
0.8
0.9
1.0
1.1
6891413
38145 G21
0.7
57 10 11 12
TEMPERATURE (°C)
–50
4
5
7
25 75
38145 G19
3
2
–25 0 50 100 125
1
0
6
RESISTANCE (Ω)
TEMPERATURE (°C)
–50 –25
0
INTVCC CURRENT (mA)
2
5
050 75
38145 G20
1
4
3
25 100 125
INTVCC = 5V
TEMPERATURE (°C)
–50
INTVCC CURRENT (µA)
25
38145 G21
200
100
–25 0 50
0
400
300
75 100 125
INTVCC = 5V
LTC3814-5
7
38145fc
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Current vs INTVCC Voltage
INTVCC Shutdown Current
vs INTVCC Voltage
RUN/SS Pull-Up Current
vs Temperature
Shutdown Threshold
vs Temperature
INTVCC VOLTAGE (V)
0
2.0
2.5
3.5
610
38145 G22
1.5
1.0
24 81214
0.5
0
3.0
INTVCC CURRENT (mA)
INTVCC VOLTAGE (V)
0
200
250
350
610
38145 G23
150
100
24 81214
50
0
300
INTVCC CURRENT (µA)
TEMPERATURE (°C)
–50
SS/TRACK CURRENT (µA)
2
3
25 75
38145 G24
1
–25 0 50 100 125
0
RUN/SS = 0V
TEMPERATURE (°C)
–50
SHUTDOWN THRESHOLD (V)
2.0
25
38145 G25
1.4
1.0
–25 0 50
0.8
0.6
2.2
1.8
1.6
1.2
75 100 125
LTC3814-5
8
38145fc
IOFF (Pin 1): Off-Time Current Input. Tie a resistor from
VOUT to this pin to set the one-shot timer current and
thereby set the switching frequency.
VOFF (Pin 2): Off-Time Voltage Input. Voltage trip point
for the on-time comparator. Tying this pin to an external
resistive divider from the input makes the off-time pro-
portional to VIN. The comparator defaults to 0.7V when
the pin is grounded and defaults to 2.4V when the pin is
connected to INTVCC.
VRNG (Pin 3): Sense Voltage Limit Set. The voltage at this
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive
divider from INTVCC. The nominal sense voltage defaults
to 95mV when this pin is tied to ground, and 215mV when
tied to INTVCC.
PGOOD (Pin 4): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 125µs before
the power good output is pulled to ground.
ITH (Pin 5): Error Amplifi er Compensation Point and Cur-
rent Control Threshold. The current comparator threshold
increases with control voltage. The voltage ranges from
0V to 2.6V with 1.2V corresponding to zero sense voltage
(zero current).
VFB (Pin 6): Feedback Input. Connect VFB through a resistor
divider network to VOUT to set the output voltage.
RUN/SS (Pin 7): RUN/Soft-Start Input. For soft-start, a
capacitor to ground at this pin sets the ramp rate of the
maximum current sense threshold. Pulling this pin below
0.9V will shut down the LTC3814-5, turn off both of the
external MOSFET switches and reduce the quiescent sup-
ply current to 224µA.
SGND (Pin 8): Signal Ground. All small-signal components
should connect to this ground and eventually connect to
PGND at one point.
NDRV (Pin 9): Drive Output for External Pass Device of
the Linear Regulator for INTVCC. Connect to the gate of an
external NMOS pass device and a pull-up resistor to the
input voltage VIN or the output voltage VOUT.
EXTVCC (Pin 10): External Driver Supply Voltage. When
this voltage exceeds 4.7V, an internal switch connects
this pin to INTVCC through an LDO and turns off the exter-
nal MOSFET connected to NDRV, so that controller and
gate drive are drawn from EXTVCC.
INTVCC (Pin 11): Main Supply and Driver Supply Pin. All
internal circuits and bottom gate output driver are powered
from this pin. INTVCC should be bypassed to SGND and
PGND with a low ESR (X5R or better) 1µF capacitor in
close proximity to the LTC3814-5.
BG (Pin 12): Bottom Gate Drive. The BG pin drives the
gate of the bottom N-channel main switch MOSFET. This
pin swings from PGND to INTVCC.
PGND (Pin 13): Bottom Gate Return. This pin connects
to the source of the pull-down MOSFET in the BG driver
and is normally connected to ground.
SW (Pin 14): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground
to VOUT.
TG (Pin 15): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true fl oating drive to the top MOSFET.
BOOST (Pin 16): Top Gate Driver Supply. The BOOST pin
supplies power to the fl oating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1µF
capacitor. An additional fast recovery diode from INTVCC
to the BOOST pin will create a complete fl oating charge-
pumped supply at BOOST.
GND (Exposed Pad Pin 17): Ground. The Exposed Pad
must be soldered to PCB ground.
PIN FUNCTIONS
LTC3814-5
9
38145fc
FUNCTIONAL DIAGRAM
–
+
1.4V
1.4µA
0.7V
RC
CC1
CC2
VRNG
3
ITH
–+
–
+
VVOFF
IIOFF
tOFF = (76pF)
R
SQ
20k
ICMP
×
SHDN SWITCH
LOGIC
BG
INTVCC
ON
OV
0.9V
4V
EA
0.8V
38145 FD
SGND
RFB1
RFB2
8
6
RUN
SHDN
FAULT
12
PGND
13
PGOOD
VFB
SW
14
TG
BOOST
CB
15
16
INTVCC
NDRV
11
9
–
+
–
+
UV
0.72V
OV
0.88V
CVCC
VOUT
M2
M1
M3
L
COUT
CIN
+
DB
4
+
+
VIN
VIN
–
+
OVERTEMP
SENSE
5V
REG
INTVCC
IOFF
1
VOUT
ROFF
VOFF
2
–
+
INTVCC
UV
–
+
–
+
OFF
ON
5.5V
4.7V
5.5V
4.2V
2.6V
EXTVCC
10
5
0.8V
REF
–
+
RUN/SS
7
Σ
VIN
LTC3814-5
10
38145fc
OPERATION
Figure 1. Floating TG Driver Supply and Negative BG Return
Main Control Loop
The LTC3814-5 is a current mode controller for DC/DC
step-up converters. In normal operation, the top MOSFET
is turned on for a fi xed interval determined by a one-shot
timer (OST). When the top MOSFET is turned off, the bot-
tom MOSFET is turned on until the current comparator
ICMP trips, restarting the one-shot timer and initiating the
next cycle. Inductor current is determined by sensing the
voltage between the PGND and SW pins using the bottom
MOSFET on-resistance. The voltage on the ITH pin sets
the comparator threshold corresponding to the inductor
peak current. The fast 25MHz error amplifi er EA adjusts
this voltage by comparing the feedback signal VFB to the
internal 0.8V reference voltage. If the load current increases,
it causes a drop in the feedback voltage relative to the
reference. The ITH voltage then rises until the average
inductor current again matches the load current.
The operating frequency is determined implicitly by the
top MOSFET on-time (tOFF) and the duty cycle required to
maintain regulation. The one-shot timer generates a top
MOSFET on-time that is inversely proportional to the IOFF
current and proportional to the VOFF voltage. Connecting
VOUT to IOFF and VIN to VOFF with a resistive divider keeps
the frequency approximately constant with changes in VIN.
The nominal frequency can be adjusted with an external
resistor ROFF.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 0.9V will turn on the device.
Fault Monitoring/Protection
Constant off-time current mode architecture provides ac-
curate cycle-by-cycle current limit protection—a feature
that is very important for protecting the high voltage
power supply from output overcurrent conditions. The
cycle-by-cycle current monitor guarantees that the induc-
tor current will never exceed the value programmed on
the VRNG pin.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 125µs power bad mask timer expires. Furthermore,
in an overvoltage condition, M2 is turned off and M1 is
turned on immediately and held on until the overvoltage
condition clears.
The LTC3814-5 provides an undervoltage lockout com-
parator for the INTVCC supply. The INTVCC UV threshold
is 4.2V to guarantee that the MOSFETs have suffi cient
gate drive voltage before turning on. If INTVCC is under
the UV threshold, the LTC3814-5 is shut down and the
drivers are turned off.
Strong Gate Drivers
The LTC3814-5 contains very low impedance drivers ca-
pable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
60V fl oating high side driver drives the topside MOSFET
and a low side driver drives the bottom side MOSFET
(see Figure 1). The bottom side driver is supplied directly
from the INTVCC pin. The top MOSFET drivers are biased
from fl oating bootstrap capacitor CB, which normally is
recharged during each off cycle through an external diode
from INTVCC when the top MOSFET turns off. In an output
overvoltage condition, where it is possible that the bot-
tom MOSFET will be off for an extended period of time,
an internal timeout guarantees that the bottom MOSFET
is turned on at least once every 25µs for one top MOSFET
on-time period to refresh the bootstrap capacitor.
BOOST
TG
SW
BG
PGND
INTVCC
INTVCC
LTC3814-5
M2
+
+
VIN
CIN
VOUT
COUT
DB
CB
38145 F01
M1
L
LTC3814-5
11
38145fc
The basic LTC3814-5 application circuit is shown on the
fi rst page of this data sheet. External component selection
is primarily determined by the maximum input voltage and
load current and begins with the selection of the power
MOSFET switches. The LTC3814-5 uses the on-resistance
of the synchronous power MOSFET for determining the
inductor current. The desired amount of ripple current and
operating frequency largely determines the inductor value.
Next, COUT is selected for its ability to handle the large RMS
current and is chosen with low enough ESR to meet the
output voltage ripple and transient specifi cation. Finally,
loop compensation components are selected to meet the
required transient/phase margin specifi cations.
Duty Cycle Considerations
For a boost converter, the duty cycle of the main switch
is:
D=1−VIN
VOUT
;D
MAX =1−VIN(MIN)
VOUT
The maximum VOUT capability of the LTC3814-5 is inversely
proportional to the minimum desired operating frequency
and minimum off-time:
VOUT(MAX) =VIN(MIN)
fMIN•t
OFF(MIN)
≤60V
Maximum Sense Voltage and the VRNG Pin
The control circuit in the LTC3814-5 measures the input
current by using the RDS(ON) of the bottom MOSFET or
by using a sense resistor in the bottom MOSFET source,
so the output current needs to be refl ected back to the
OPERATION
input in order to dimension the power MOSFET properly
and to choose the maximum sense voltage. Based on the
fact that, ideally, the output power is equal to the input
power, the maximum average input current and average
inductor current is:
IIN(MAX) =IL,AVG(MAX) =IO(MAX)
1−DMAX
The current mode control loop will not allow the induc-
tor peak to exceed VSENSE(MAX)/RSENSE. In practice, one
should allow some margin for variations in the LTC3814-
5 and external component values, and a good guide for
selecting the maximum sense voltage when VDS sensing
is used is:
VSENSE(MAX) =1.7 •RDS(ON) •I
O(MAX)
1−DMAX
VSENSE is set by the voltage applied to the VRNG pin. Once
VSENSE is chosen, the required VRNG voltage is calculated
to be:
V
RNG = 5.78 • (VSENSE(MAX) + 0.026)
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.
IC/Driver Supply Power
The LTC3814-5’s internal control circuitry and top and bot-
tom MOSFET drivers operate from a supply voltage (INTVCC
pin) in the range of 4.5V to 14V. If the input supply voltage
or another available supply is within this voltage range it
can be used to supply IC/driver power. If a supply in this
range is not available, two internal regulators are available
to generate a 5.5V supply from the input or output. An
internal low dropout regulator is good for voltages up to
15V, and the second, a linear regulator controller, controls
the gate of an external NMOS to generate the 5.5V supply.
Since the NMOS is external, the user has the fl exibility to
choose a BVDSS as high as necessary.
APPLICATIONS INFORMATION
LTC3814-5
12
38145fc
Power MOSFET Selection
The LTC3814-5 requires two external N-channel power
MOSFETs, one for the bottom (main) switch and one for
the top (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BVDSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), Miller
capacitance and maximum current IDS(MAX).
Since the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resis-
tance. MOSFET on-resistance is typically specifi ed with
a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =RSENSE
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the signifi cant variation in on-resistance
with
temperature (see Figure 2) and typically varies
from 0.4%/
°
C to 1.0%/
°
C depending on the particular
MOSFET used.
ing its off-time and must be chosen with the appropriate
breakdown specifi cation. The LTC3814-5 is designed to
be used with a 4.5V to 14V gate drive supply (INTVCC pin)
for driving logic-level MOSFETs (VGS(MIN) ≥ 4.5V).
For maximum effi ciency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 3).
Figure 2. RDS(ON) vs Temperature
Figure 3. Gate Charge Characteristic
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The fl at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is fl at) is specifi ed for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying by the ratio of the application VDS to the curve
specifi ed VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
VDS voltage specifi ed. CMILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specifi ed on MOSFET
data sheets. CRSS and COS are specifi ed sometimes but
defi nitions of these parameters are not included.
The most important parameter in high voltage applications
is breakdown voltage BVDSS. Both the top and bottom
MOSFETs will see full output voltage plus any additional
ringing on the switch node across its drain-to-source dur-
JUNCTION TEMPERATURE (°C)
–50
ρT NORMALIZED ON-RESISTANCE
1.0
1.5
150
38145 F02
0.5
0050 100
2.0
+
–VDS
VOUT
VGS
MILLER EFFECT
QIN
ab
CMILLER = (QB – QA)/VDS
VGS V
+
–
38145 F03
APPLICATIONS INFORMATION
LTC3814-5
13
38145fc
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT −VIN
VOUT
Synchronous Switch Duty Cycle =VIN
VOUT
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN =DMAX
IO(MAX)
1DMAX
2
(T)RDS(ON)
+1
2VOUT2IO(MAX)
1DMAX
(RDR )(CMILLER)
•1
INTVCC –V
TH(IL)
+1
VTH(IL)
(f)
PSYNC =1
1DMAX
(IO(MAX))2(T)R
DS(0N)
where ρT is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER). VTH(IL) is the data sheet specifi ed typical
gate threshold voltage specifi ed in the power MOSFET
data sheet at the specifi ed drain current. CMILLER is the
calculated capacitance using the gate charge curve from
the MOSFET data sheet and the technique described above.
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses.
Both top and bottom MOSFET I2R losses are greatest at
lowest VIN, and the top MOSFET I2R losses also peak
during an overcurrent condition when it is on close to
100% of the period. For most LTC3814-5 applications,
the transition loss and I2R loss terms in the bottom
MOSFET are comparable, so best effi ciency is obtained
by choosing a MOSFET that optimizes both RDS(ON) and
CMILLER. Since there is no transition loss term in the syn-
chronous MOSFET, however, optimal effi ciency is obtained
by minimizing RDS(ON)—by using larger MOSFETs or
paralleling multiple MOSFETs.
Multiple MOSFETs can be used in parallel to lower
RDS(ON) and meet the current and thermal requirements
if desired. The LTC3814-5 contains large low impedance
drivers capable of driving large gate capacitances without
signifi cantly slowing transition times. In fact, when driv-
ing MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (10Ω or less) to reduce noise and EMI caused
by the fast transitions.
Operating Frequency
The choice of operating frequency is a tradeoff between
effi ciency and component size. Low frequency operation
improves effi ciency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3814-5 applications is
determined implicitly by the one-shot timer that controls
the on-time tOFF of the synchronous MOSFET switch.
The on-time is set by the current into the IOFF pin and the
voltage at the VOFF pin according to:
tOFF =VVOFF
IIOFF
76pF
()
Tying a resistor ROFF from VOUT to the IOFF pin yields a syn-
chronous MOSFET on-time inversely proportional to VOUT.
This results in the following operating frequency and also
keeps frequency constant as VOUT ramps up at start-up:
f=VIN
VVOFF •ROFF (76pF) (Hz)
The VOFF pin can be connected to INTVCC or ground or
can be connected to a resistive divider from VIN. The VOFF
pin has internal clamps that limit its input to the one-shot
timer. If the pin is tied below 0.7V, the input to the one-
shot is clamped at 0.7V. Similarly, if the pin is tied above
2.4V, the input is clamped at 2.4V. Note, however, that
if the VOFF pin is connected to a constant voltage, the
operating frequency will be proportional to the input
voltage VIN. Figures 4a and 4b illustrate how ROFF relates
to switching frequency as a function of the input voltage
and VOFF voltage. To hold frequency constant for input
APPLICATIONS INFORMATION
LTC3814-5
14
38145fc
voltage changes, tie the VOFF pin to a resistive divider from
VIN, as shown in Figure 5. Choose the resistor values so
that the VRNG voltage equals about 1.55V at the mid-point
of VIN as follows:
VIN,MID =
VIN(MAX) +VIN(MIN)
2=1.55V • 1+R1
R2
With these resistor values, the frequency will remain
relatively constant at:
f=1+R1/ R2
ROFF(76pF) (Hz)
for the range of 0.45VIN to 1.55 • VIN, and will be propor-
tional to VIN outside of this range.
Changes in the load current magnitude will also cause
a frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By shortening the off-time slightly
as current increases, constant-frequency operation can be
maintained. This is accomplished with a resistor connected
from the ITH pin to the IOFF pin to increase the IOFF current
slightly as VITH increases. The values required will depend
on the parasitic resistances in the specifi c application. A
good starting point is to feed about 10% of the ROFF cur-
rent with RITH as shown in Figure 6.
APPLICATIONS INFORMATION
Figure 4a. Switching Frequency vs ROFF (VOFF = INTVCC)Figure 4b. Switching Frequency vs ROFF
(VOFF Connected to a Resistor Divider from VIN)
Figure 6. Correcting Frequency Shift with Load Current Changes
Figure 5. VOFF Connection to Keep the Operating
Frequency Constant as the Input Supply Varies
ROFF (kΩ)
10
100
SWITCHING FREQUENCY (kHz)
1000
100 1000
38145 F04a
VIN = 5V VIN = 24V
VIN = 12V
ROFF (kΩ)
10
100
SWITCHING FREQUENCY (kHz)
1000
100 1000
38145 F04b
1+R1/R2 = 3.2
(VIN,MID = 5V)
1+R1/R2 = 7.7
(VIN,MID =12V)
1+R1/R2 = 15.5
(VIN,MID = 24V)
R2
R1
VIN
VOFF
LTC3814-5
38145 F05
1000pF
ROFF
RITH
VOUT IOFF
ITH
LTC3814-5
38145 F06
10ROFF
VOUT
RITH =
LTC3814-5
15
38145fc
Minimum On-Time and Dropout Operation
The minimum on-time tON(MIN) is the smallest amount of
time that the LTC3814-5 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 350ns. The
minimum on-time limit imposes a minimum duty cycle
of tON(MIN)/(tON(MIN) + tOFF). If the minimum duty cycle is
reached, due to a rising input voltage for example, then
the output will rise out of regulation. The maximum input
voltage to avoid dropout is:
VIN(MAX) =VOUT
tOFF
tON(MIN) +tOFF
A plot of maximum duty cycle vs switching frequency is
shown in Figure 7.
The required saturation of the inductor should be chosen
to be greater than the peak inductor current:
IL(SAT) ≥IO(MAX)
1−DMAX
+ΔIL
2
Once the value for L is known, the type of inductor must
be selected. High effi ciency conver
ters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ
®
cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the synchronous MOSFET from turning on
and storing charge during the dead time, which can cause
a modest (about 1%) effi ciency loss. The diode can be
rated for about one half to one fi fth of the full load current
since it is on for only a fraction of the duty cycle. The peak
reverse voltage that the diode must withstand is equal to
the regulator output voltage. In order for the diode to be
effective, the inductance between it and the synchronous
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can
be omitted if the effi ciency loss is tolerable.
Output Capacitor Selection
In a boost converter, the output capacitor requirements
are demanding due to the fact that the current waveform
is pulsed. The choice of component(s) is driven by the
acceptable ripple voltage which is affected by the ESR,
ESL and bulk capacitance as shown in Figure 8e. The total
output ripple voltage is:
VOUT =IO(MAX)
1
f•C
OUT
+ESR
1–DMAX
where the fi rst term is due to the bulk capacitance and
second term due to the ESR.
APPLICATIONS INFORMATION
Figure 7. Maximum Switching Frequency vs Duty Cycle
Inductor Selection
An inductor should be chosen that can carry the maximum
input DC current which occurs at the minimum input volt-
age. The peak-to-peak ripple current is set by the inductance
and a good starting point is to choose a ripple current of
at least 40% of its maximum value:
ΔIL=40% • IO(MAX)
1−DMAX
The required inductance can then be calculated to be:
L=VIN(MIN) •D
MAX
f•ΔIL
2.0
1.5
1.0
0.5
0
0 0.25 0.50 0.75
38145 F07
1.0
DROPOUT
REGION
VIN/VOUT
SWITCHING FREQUENCY (MHz)
LTC3814-5
16
38145fc
For many designs it is possible to choose a single capacitor
type that satisfi es both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved signifi cantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance
have been determined, the overall ripple voltage wave-
form should be verifi ed on a dedicated PC board (see PC
Board Layout Checklist section for more information on
component placement). Lab breadboards generally suffer
from excessive series inductance (due to inter-component
wiring), and these parasitics can make the switching
waveforms look signifi cantly worse than they would be
on a properly designed PC board.
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 8d. The RMS
output capacitor ripple current is:
IRMS(COUT) IO(MAX) •VO–V
IN(MIN)
VIN(MIN)
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, Nippon Chemi-con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon-
ductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic
at a somewhat higher price. An additional ceramic capaci-
tor in parallel with OS-CON capacitors is recommended
to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
APPLICATIONS INFORMATION
Figure 8. Switching Waveforms for a Boost Converter
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have signifi cantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs. In applications with VOUT > 30V,
however, choices are limited to aluminum electrolytic and
ceramic capacitors.
VIN
LD
SW
8a. Circuit Diagram
8b. Inductor and Input Currents
COUT
VOUT
RL
IIN
IL
8c. Switch Current
ISW
tON
8d. Diode and Output Currents
8e. Output Voltage Ripple Waveform
IO
ID
VOUT
(AC)
tOFF
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
38145 F08
LTC3814-5
17
38145fc
Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure 8b). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of 10µF to 100µF. A low
ESR capacitor is recommended though not as critical as
for the output capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
IRMS(CIN) =0.3 • VIN(MIN)
L•f •D
MAX
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
Output Voltage
The LTC3814-5 output voltage is set by a resistor divider
according to the following formula:
VOUT =0.8V 1+RFB1
RFB2
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifi er. The internal reference has a guaranteed
tolerance of less than ±1%. Tolerance of the feedback
resistors will add additional error to the output voltage.
0.1% to 1% resistors are recommended.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VOUT and the BOOST pin rises
to approximately VOUT + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1µF to 0.47µF, X5R
or X7R dielectric capacitor is adequate.
The reverse breakdown of the external diode, DB, must
be greater than VOUT. Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
current to fl ow at full reverse voltage. If the reverse
current times reverse voltage exceeds the maximum al-
lowable power dissipation, the diode may be damaged.
For best results, use an ultrafast recovery diode such as
the MMDL770T1.
IC/MOSFET Driver Supplies (INTVCC)
The LTC3814-5 drivers and the LTC3814-5 internal circuits
are supplied from the INTVCC pin (see Figure 1). These
pins have an operating range between 4.2V and 14V. If
the input voltage or another supply is not available in
this voltage range, two internal regulators are provided
to simplify the generation of this IC/driver supply voltage
as described in the next sections.
The NDRV Pin Regulator
The NDRV pin controls the gate of an external NMOS as
shown in Figure 9b and can be used to generate a regu-
lated 5.5V supply from VIN or VOUT. Since the NMOS is
external, it can be chosen with a BVDSS or power rating
as high as necessary to safely derive power from a high
voltage input or output voltage. In order to generate an
INTVCC supply that is always above the 4.2V UV threshold,
the supply connected to the drain must be greater than
4.2V + RNDRV • 40µA + VT.
The EXTVCC Pin Regulator
A second low dropout regulator is available for voltages
≤ 15V. When a supply that is greater than 4.7V is con-
nected to the EXTVCC pin, the internal LDO will regulate
5.5V on INTVCC from the EXTVCC pin voltage and will also
disable the NDRV pin regulator. This regulator is disabled
when the IC is shut down, when INTVCC < 4.2V, or when
EXTVCC < 4.7V.
APPLICATIONS INFORMATION
LTC3814-5
18
38145fc
Using the INTVCC Regulators
One, both or neither of these regulators can be used to
generate the 5.5V IC/driver supply depending on the
circuit requirements, available supplies, and the voltage
range of VIN or VOUT. Deriving the 5.5V supply from VIN
is more effi cient, however deriving it from VOUT has the
advantage of maintaining regulation of VOUT when VIN
drops below the UV threshold. Four possible confi gurations
are shown in Figures 9a through 9d, and are described
as follows:
1. Figure 9a. If the VIN voltage or another low voltage
supply between 4.5V and 14V is available, the sim-
plest approach is to connect this supply directly to the
INTVCC and DRVCC pins. The internal regulators are
disabled by shorting NDRV and EXTVCC to INTVCC.
2. Figure 9b. If VIN(MAX) > 14V, an external NMOS con-
nected to the NDRV pin can be used to generate 5.5V
from VIN. VIN(MIN) must be > 4.5V + RNDRV • 40µA + VT
to keep INTVCC above the UV threshold and the BVDSS
of the external NMOS must be chosen to be greater
than VIN(MAX). The EXTVCC regulator is disabled by
grounding the EXTVCC pin.
3. Figure 9c. If the VIN(MAX) < 14.7V and VIN is allowed to
fall below 4.2V without disrupting the boost converter
operation, use this confi guration. The INTVCC supply
is derived from VIN until the VOUT > 4.7V. Once INTVCC
is derived from VOUT, VIN can fall below the 4V UV
threshold without losing regulation of VOUT. Note that
in this confi guration, VIN must be > ~5V at least long
enough to start up the LTC3814-5 and charge VOUT >
4.7V. Also, since VOUT is connected to the EXTVCC pin,
this confi guration is limited to VOUT < 15V.
4. Figure 9d. Similar to confi guration 3 except that VOUT
is allowed to be >15V since VOUT is connected to an
external NMOS with appropriately rated BVDSS. VIN has
same start-up requirement as 3.
APPLICATIONS INFORMATION
Figure 9. Four Possible Ways to Generate INTVCC Supply
VOUT ≤ 15V
(a) 4.2V to 14V
Supply Available
(b) INTVCC from VIN,
VIN > 14V
(c) INTVCC from VOUT,
VOUT ≤ 15V
(d) INTVCC from VOUT,
VOUT > 15V
38145 F09
NDRV
EXTVCC
INTVCC +
VIN < 14.7V
5.5V
NDRV
EXTVCC
INTVCC
LTC3814-5
VIN
5.5V
NDRV
RNDRV
EXTVCC
INTVCC +
VOUT
5.5V
RNDRV
+
LTC3814-5
LTC3814-5
+
–4.5V to
14V
NDRV
EXTVCC
INTVCC +
LTC3814-5
VIN < 14.7V
LTC3814-5
19
38145fc
Power Dissipation Considerations
Applications using large MOSFETs and high frequency
of operation may result in a large DRVCC /INTVCC supply
current. Therefore, when using the linear regulators, it is
necessary to verify that the resulting power dissipation
is within the maximum limits. The DRVCC /INTVCC supply
current consists of the MOSFET gate current plus the
LTC3814-5 quiescent current:
I
CC = (f)(QG(TOP) + QG(BOTTOM)) + 3mA
When using the internal LDO regulator, the power dissipa-
tion is internal so the rise in junction temperature can be
estimated from the equation given in Note 2 of the Electrical
Characteristics as follows:
T
J = TA + IEXTVCC • (VEXTVCC – VINTVCC)(38°C/W)
and must not exceed 125°C.
Likewise, if the external NMOS regulator is used, the worst
case power dissipation is calculated to be:
P
MOSFET = (VDRAIN(MAX) – 5.5V) • ICC
and can be used to properly size the device.
FEEDBACK LOOP/COMPENSATION
Introduction
In a typical LTC3814-5 circuit, the feedback loop consists of
two sections: the modulator/output stage and the feedback
amplifi er/compensation network. The modulator/output
stage consists of the current sense component and in-
ternal current comparator, the power MOSFET switches
and drivers, and the output fi lter and load. The transfer
function of the modulator/output stage for a boost con-
verter consists of an output capacitor pole, RLCOUT, and
an ESR zero, RESRCOUT, and also a “right-half plane” zero,
(RL/L)(VIN2/VOUT2). It has a gain/phase curve that is typi-
cally like the curve shown in Figure 10 and is expressed
mathematically in the following equation.
H(s)=VOUT(s)
VITH (s) =RL•V
IN •V
SENSE(MAX)
2.4 • VOUT •R
DS(ON)
•1+s•R
ESR •C
OUT
1+s•R
L•C
OUT
•1s• L
RL
•VOUT2
VIN2
s=j2f
This portion of the power supply is pretty well out of the
user’s control since the current sense is chosen based on
maximum output load, and the output capacitor is usually
chosen based on load regulation and ripple requirements
without considering AC loop response. The feedback am-
plifi er, on the other hand, gives us a handle on which to
adjust the AC response. The goal is to have an 180° phase
shift at DC so the loop regulates and less than 360° phase
shift at the point where the loop gain falls below 0dB, i.e.,
the crossover frequency, with as much gain as possible
at frequencies below the crossover frequency. Since the
feedback amplifi er adds an additional 90° phase shift to
the phase shift already present from the modulator/output
stage, some phase boost is required at the crossover
frequency to achieve good phase margin. The design
procedure (described in more detail in the next section) is
to (1) obtain a gain/phase plot of modulator/output stage,
(2) choose a crossover frequency and the required phase
boost, and (3) calculate the compensation network.
APPLICATIONS INFORMATION
Figure 10. Bode Plot of Boost Modulator/Output Stage
(1)
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEG)
38145 F10
00
–90
–180
90
180
GAIN
PHASE
LTC3814-5
20
38145fc
The two types of compensation networks, Type 2 and Type
3 are shown in Figures 11 and 12. When component values
are chosen properly, these networks provide a “phase
bump” at the crossover frequency. Type 2 uses a single
pole-zero pair to provide up to about 60° of phase boost
while Type 3 uses two poles and two zeros to provide up
to 150° of phase boost.
The compensation of boost converters are complicated
by two factors: the RHP zero and the dependence of the
loop gain on the duty cycle. The RHP zero adds additional
phase lag and gain. The phase lag degrades phase margin
and the added gain keeps the gain high typically in the
frequency region where the user is trying the roll off the
gain below 0dB. This often forces the user to choose a
crossover frequency at a lower frequency than originally
desired. The duty cycle effect of gain (see above transfer
function) causes the phase margin and crossover frequency
to be dependent on the input supply voltage which may
cause problems if the input voltage varies over a wide range
since the compensation network can only be optimized
for a specifi c crossover frequency. These two factors
usually can be overcome if the crossover frequency is
chosen low enough.
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or
Type 3 loop is a nontrivial task. The applications shown
in this data sheet show typical values, optimized for the
power components shown. They should give acceptable
performance with similar power components, but can be
way off if even one major power component is changed
signifi cantly. Applications that require optimized transient
response will require recalculation of the compensation
values specifi cally for the circuit in question. The underly-
ing mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
Modulator gain and phase can be obtained in one of
three ways: measured directly from a breadboard, or if
the appropriate parasitic values are known, simulated or
generated from the modulator transfer function. Mea-
surement will give more accurate results, but simulation
or transfer function can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3814-5
and the actual MOSFETs, inductor and input and output
capacitors that the fi nal design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3814-5, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifi er with a 0.1µF feedback capacitor from ITH to FB
and a 10k to 100k resistor from VOUT to FB. Choose the
bias resistor (RB) as required to set the desired output
voltage. Disconnect RB from ground and connect it to
a signal generator or to the source output of a network
analyzer to inject a test signal into the loop. Measure the
gain and phase from the ITH pin to the output node at the
positive terminal of the output capacitor. Make sure the
analyzer’s input is AC coupled so that the DC voltages
present at both the ITH and VOUT nodes don’t corrupt the
measurements or damage the analyzer.
APPLICATIONS INFORMATION
Figure 11. Type 2 Schematic and Transfer Function Figure 12. Type 3 Schematic and Transfer Function
GAIN (dB)
38145 F11
0
PHASE
–6dB/OCT
–6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
VREF
R1
R2
FB
C2
IN
OUT
+
–
C1
GAIN (dB)
38145 F12
0
PHASE
–6dB/OCT
+6dB/OCT –6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
VREF
R1
R2
FB
C2
IN
OUT
+
–
C1
C3
R3
LTC3814-5
21
38145fc
If breadboard measurement is not practical, mathemat-
ical software such as MATHCAD or MATLAB can be used
to generate plots from the transfer function given in
Equation 1. A SPICE simulation can also be used to gener-
ate approximate gain/phase curves. Plug the expected
capacitor, inductor and MOSFET values into the following
SPICE deck and generate an AC plot of VOUT/V
ITH with gain
in dB and phase in degrees. Refer to your SPICE manual
for details of how to generate this plot.
*This fi le simulates a simplifi ed model of
the 3814-5 for generating a v(out)/(vith) or
a v(out)/v(outin) bode plot
.param vout=24
.param vin=12
.param L=10u
.param cout=270u
.param esr=.018
.param rload=24
*
.param rdson=0.02
.param Vrng=1
.param vsnsmax={0.173*Vrng-0.026}
.param K={vsnsmax/rdson/1.2}
.param wz={1/esr/cout}
.param wp={2/rload/cout}
*
* Feedback Amplifi er
rfb1 outin vfb 29k
rfb2 vfb 0 1k
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 100p
cc2 ith x1 0.01p
rc x1 vfb 100k
*
* Modulator/Output Stage
eout out 0 laplace {v(ith)} =
{0.5*K*Rload*vin/vout *(1+s/wz)/(1+s/wp)
*(1-s*L/Rload*vout*vout/vin/vin)}
rload out 0 {rload}
*
vstim out outin dc=0 ac=10m; ac stimulus
.ac dec 100 10 10meg
.probe
.end
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 10. Choose the crossover frequency about 25%
of the switching frequency for maximum bandwidth. Al-
though it may be tempting to go beyond fSW/4, remember
that signifi cant phase shift occurs at half the switching
frequency that isn’t modeled in the above H(s) equation
and PSPICE code. Note the gain (GAIN, in dB) and phase
(PHASE, in degrees) at this point. The desired feedback
amplifi er gain will be –GAIN to make the loop gain at 0dB
at this frequency. Now calculate the needed phase boost,
assuming 60° as a target phase margin:
BOOST = – (PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
Finally, choose a convenient resistor value for R1 (10k
is usually a good value). Now calculate the remaining
values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
APPLICATIONS INFORMATION
LTC3814-5
22
38145fc
TYPE 2 Loop:
K=tanBOOST
2+45°
C2 =1
2•f•G•K•R1
C1=C2 K21
()
R2 =K
2•f•C1
RB=VREF(R1)
VOUT VREF
TYPE 3 Loop:
K=tan2BOOST
4+45°
C2 =1
2•f•G•R1
C1=C2 K 1
()
R2 =K
2•f•C1
R3 =R1
K1
C3 =1
2fK•
R3
RB=VREF(R1)
VOUT VREF
SPICE or mathematical software can be used to generate
the gain/phase plots for the compensated power supply to
do a sanity check on the component values before trying
them out on the actual hardware. For software, use the
following transfer function:
T(s) = A(s)H(s)
where H(s) was given in equation 2 and A(s) depends on
compensation circuit used:
Type 2:
A (s)=1+s•R2•C1
s•R1• C1+C2
()
•1+s•R2• C1• C2
C1+C2
⎛
⎝
⎜⎞
⎠
⎟
Type 3:
A (s)=1
s•R1• C1+C2
()
•
1+s• R1+R3
()
•C3
()
•1+s•R2•C1
()
1+s•R3•C3
()
•1+s•R2• C1• C2
C1+C2
⎛
⎝
⎜⎞
⎠
⎟
For SPICE, simulate the previous PSPICE code with
calculated compensation values entered and generate a
gain/phase plot of VOUT/VOUTIN.
Fault Conditions: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3814-5, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With peak current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
ILIMIT =VSNS(MAX)
RDS(ON) ρT
−1
2ΔIL
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs at the lowest VIN at the highest ambient
temperature, conditions that cause the largest power loss
in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
APPLICATIONS INFORMATION
LTC3814-5
23
38145fc
A reasonable assumption is that the minimum RDS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN.
For hard shorts, the inductor current is limited only by the
input supply capability.
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provides a soft-
start function and a means to shut down the LTC3814-5.
Soft-start reduces the input supply’s surge current by
controlling the ramp rate of the ITH voltage, eliminates
output overshoot and can also be used for power supply
sequencing.
Pulling RUN/SS below 0.9V puts the LTC3814-5 into a low
quiescent current shutdown (IQ = 224µA). This pin can be
driven directly from logic as shown in Figure 14. Releasing
the RUN/SS pin allows an internal 1.4µA current source to
charge up the soft-start capacitor, CSS. When the voltage
on RUN/SS reaches 0.9V, the LTC3814-5 turns on and
begins ramping the ITH voltage at VITH = VSS – 0.9V. As the
RUN/SS voltage increases from 0.9V to 3.3V, the current
limit is increased from 0% to 100% of its maximum value.
The RUN/SS voltage continues to charge until it reaches
its internally clamped value of 4V.
If RUN/SS starts at 0V, the delay before starting is
approximately:
tDELAY,START =0.9V
1.4µA CSS =0.64s/µF
()
CSS
plus an additional delay, before the current limit reaches
its maximum value of:
tDELAY,REG ≥2.4V
1.4µA CSS
The start delay can be reduced by using diode D1 in
Figure 13.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3814-5 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the effi ciency to drop at high input currents. The input
current is maximum at maximum output current and
minimum input voltage. The average input current fl ows
through L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same RDS(ON), then the resistance of one MOSFET can
simply be summed with the resistances of L and the
board traces to obtain the DC I2R loss. For example, if
RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range
from 15mW to 1.5W as the input current varies from
1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the bottom MOSFET spends in the saturated
region during switch node transitions. It depends upon
the output voltage, load current, driver strength and
MOSFET capacitance, among other factors. The loss
is signifi cant at output voltages above 20V and can be
estimated from the second term of the PMAIN equa-
tion found in the Power MOSFET Selection section.
When transition losses are signifi cant, effi ciency can
be improved by lowering the frequency and/or using a
bottom MOSFET(s) with lower CRSS at the expense of
higher RDS(ON).
3. INTVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
APPLICATIONS INFORMATION
Figure 13. RUN/SS Pin Interfacing
3.3V
OR 5V RUN/SS
D1
CSS
38145 F13
RUN/SS
CSS
LTC3814-5
24
38145fc
about 3mA and driver current can be calculated by:
IGATE = f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT)
are the gate charges of the top and bottom MOSFETs.
This loss is proportional to the supply voltage that
INTVCC is derived from, i.e., VIN, VOUT or an external
supply connected to INTVCC.
4. COUT loss. The output capacitor has the diffi cult job
of fi l
tering the large RMS input current out of the synchro-
nous MOSFET. It must
have a very low ESR to minimize
the AC I2R loss
.
Other losses, including CIN ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve effi ciency, the input cur-
rent is the best indicator of changes in effi ciency. If you
make a change and the input current decreases, then the
effi ciency has increased. If there is no change in input
current, then there is no change in effi ciency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
charge COUT generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
Design Example
As a design example, take a supply with the following speci-
fi cations: VIN = 12V ±20%, VOUT = 24V ±5%, IOUT(MAX) =
5A, f = 250kHz. Since VIN can vary around the 12V nominal
value, connect a resistive divider from VIN to VOFF to keep
the frequency independent of VIN changes:
R1
R2 =12V
1.55V −1=6.74
Choose R1 = 133k and R2 = 20k. Now calculate timing
resistor ROFF:
ROFF =1+133k / 20k
250kHz • 76pF =402.6k
The duty cycle is:
D=1−12V
24V =0.5
and the maximum input current is:
IIN(MAX) =5A
1−0.5 =10A
Choose the inductor for about 40% ripple current at the
maximum VIN:
L=12V
250kHz • 0.4 •10A 112V
24V
=6μH
The peak inductor current is:
IL(PEAK) =5A
1−0.5 +1
2(4A)=12A
so, choose the CDEP147 5.9µH inductor with ISAT = 16.4A
at 100°C.
Next, choose the bottom MOSFET switch. Since the drain
of the MOSFET will see the full output voltage plus any
ringing, choose a 40V MOSFET to provide a margin of
safety. The Si7848DP has:
BVDSS = 40V
R
DS(ON) = 9mΩ(max)/7.5mΩ(nom),
δ
= 0.006/°C,
C
MILLER = (14nC – 6nC)/20V = 400pF,
V
GS(MILLER) = 3.5V,
θJA= 20°C/W.
This yields a nominal sense voltage of:
VSNS(NOM) =1.7 • 0.0075Ω•5A
1−0.5 =128mV
APPLICATIONS INFORMATION
LTC3814-5
25
38145fc
To guarantee proper current limit at worst-case conditions,
increase nominal VSNS by 50% to 190mV. To check if the
current limit is acceptable at VSNS = 190mV, assume a
junction temperature of about 30°C above a 70°C ambient
(ρ100°C = 1.4):
IIN(MAX) ≥190mV
1.4 • 0.009Ω−1
2•4A=13A
I
OUT(MAX) = IIN(MAX) • (1-DMAX) = 6.5A
and double-check the assumed TJ in the MOSFET:
PTOP =1
10.5
6.5A
()
2(1.4)(0.009)=1.06W
T
J = 70°C + 1.06W • 20°C/W = 91°C
Verify that the Si7848DP is also a good choice for the
bottom MOSFET by checking its power dissipation at
current limit and minimum input voltage, assuming a
junction temperature of 30°C above a 70°C ambient
(ρ100°C = 1.4):
P
BOT =0.5 6.5A
10.5
2
(1.4) (0.009)
+1
2(24V)26.5A
10.5
(2)(400pF)
•1
12V 3.5V +1
3.5V
(250kHz)
=1.06W +0.30W =1.36W
T
J = 70°C + 1.36W • 20°C/W = 97°C
The junction temperature will be signifi cantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
Since VIN is always between 4.5V and 14V, it can be con-
nected directly to the INTVCC and DRVCC pins.
COUT is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
VOUT(RIPPLE) =(5A) 1
250kHz • 330μF+0.018
10.5
=0.25V (about 1%)
A 0A to 5A load step will cause an output change of up to:
∆VOUT(STEP) = ∆ILOAD • ESR = 5A • 0.018Ω
= 90mV
An optional 10µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 14.
APPLICATIONS INFORMATION
LTC3814-5
26
38145fc
Figure 14. 12V Input Voltage to 24V/5A
PGOOD
VOFF
PGOOD
VRNG
ITH
SGND
VFB
SGND PGND
PGND
RUN/SS
IOFF
COFF
100pF
CSS
1000pF
VIN
12V
VOUT
VOUT
24V
5A
CC2
470pF
RC
250k
RFB2
1k RFB1, 29.4k
LTC3814-5
EXTVCC
TG
SW
BG
PGND
INTVCC
NDRV
BOOST
38145 F14
CB
0.1µF
CDRVCC
0.1µF
CVCC
1µF
ROFF
403k
133k
DB
BAS19
M2
Si7848DP
COUT1
330µF
35V × 2 COUT2
10µF
50V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
47pF
20k
CIN1
68µF
20V
CIN2
1µF
20V
M1
Si7848DP
L1
5.9µH
D1
B1100
APPLICATIONS INFORMATION
LTC3814-5
27
38145fc
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi-
cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
•
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3814-5.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
fi ltering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
•
Connect the input capacitor(s) CIN close to the pow-
er MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and SGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the bottom driver decoupling capacitor CINTVCC
closely to the INTVCC and PGND pins.
APPLICATIONS INFORMATION
LTC3814-5
28
38145fc
PACKAGE DESCRIPTION
FE16 (BA) TSSOP REV H 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 – 0.30
(.0077 – .0118)
TYP
2
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation BA
LTC3814-5
29
38145fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 01/11 Updated Description section
Changed Operating Junction Temperature Range in Absolute Maximum Ratings and Order Information sections
Remove Lead Based Part Numbers from Order Information
Updated Note 2
Updated Fault Monitoring/Protection section
Updated Equations
Updated Related Parts
1
2
2
4
10
22
30
(Revision history begins at Rev C)
LTC3814-5
30
38145fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0111 REV C • PRINTED IN USA
TYPICAL APPLICATION
24V Input Voltage to 50V/5A
PART NUMBER DESCRIPTION COMMENTS
LTC3786 Low IQ Synchronous Boost Controller 2.5V ≤ VIN ≤ 38V, VOUT up to 60V, Fixed Operating Frequency 50kHz to
900kHz, MSOP-16E, 3mm × 3mm QFN-16
LTC3787 2-Phase, Single Output Synchronous Step-Up
Controller
2.5V ≤ VIN ≤ 38V, VOUT up to 60V, 50kHz to 900kHz, SSOP-28,
4mm × 5mm QFN-28
LTC3788/LTC3788-1 2-Phase, Dual Output Synchronous Step-Up Controller 2.5V ≤ VIN ≤ 38V, VOUT up to 60V, 50kHz to 900kHz, SSOP-28
LTC3862/LTC3862-1 2-Phase Current Mode Step-Up DC/DC Controller 4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz
LTC3813 100V Maximum VOUT Synchronous Step-Up DC/DC
Controller
No RSENSE, Large 1 Gate Driver, Adjustable Off-Time, SSOP-28
LTC1871, LTC1871-1,
LTC1871-7
Wide Input Range, No RSENSE Low Quiescent Current
Flyback, Boost and SEPIC Controller
Adjustable Switching Frequency, 2.5V ≤ VIN ≤ 36V, Burst Mode Operation
at Light Load, MSOP-10
LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
3mm × 3mm DFN-10 and MSOP-10E
LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operation Frequency,
3mm × 3mm DFN-10 and MSOP-10E
PGOOD
PGOOD
VRNG
ITH
SGND
VFB
SGND PGND
PGND
RUN/SS
IOFF
VOFF
COFF
100pF
CSS
1000pF
VIN
12V* TO 40V
*IOUT(MAX) = 2A AT VIN = 12V
VOUT
50V
5A
M3
ZXMN10A07F
CC2
330pF
RC
300k
RFB2
499Ω
RFB1
30.9k
LTC3814-5
EXTVCC
TG
SW
BG
PGND
INTVCC
NDRV
BOOST
38145 TA02
CB
0.1µF
CDRVCC
0.1µF
CVCC
1µF
150k
100k
10k
RNDRV
100k
DB
BAS19
M2
Si7850DP
COUT1
220µF
63V
× 2 COUT2
10µF
100V
× 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
150pF
CIN1
68µF
50V
CIN2
1µF
50V
M1
Si7850DP
L1
10µH
D1
B1100
VOUT
VIN
ROFF
806k
143k
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