© Semiconductor Components Industries, LLC, 2015
March, 2018 − Rev. 25
1Publication Order Number:
CAT24C32/D
CAT24C32
32-Kb I2C CMOS Serial
EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus.
Features
•Supports Standard, Fast and Fast−Plus I2C Protocol
•1.7 V to 5.5 V Supply Voltage Range
•32−Byte Page Write Buffer
•Hardware Write Protection for Entire Memory
•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial and Extended Temperature Range
•PDIP, SOIC, TSSOP, UDFN, WLCSP 4−ball and 5−ball Packages
•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
SOIC−8
W SUFFIX
CASE 751BD
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
For the location of Pin 1, please consult the
corresponding package drawing.
UDFN8
HU4 SUFFIX
CASE 517AZ
WLCSP4
C4C SUFFIX
CASE 567JY
* For serial EEPROM in the US8 package, please
consult the N24C32 datasheet.
WLCSP5
C5A SUFFIX
CASE 567JQ
VCC
SDA
VSS
SCL
1
WLCSP4 (C4C)
WLCSP5 (C5A)
WP SCL
VCC VSS
SDA
132
A
B
C
PIN CONFIGURATIONS (Top Views)
SDA
WP
VCC
VSS
A2
A1
A0
1
SCL
PDIP (L), SOIC (W), TSSOP (Y),
UDFN (HU4)
2
A
B
CAT24C32
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2
(PDIP−8)
DEVICE MARKINGS
(SOIC−8)
(TSSOP−8) (UDFN−8)
C5U = Specific Device Code
A = Assembly Location
XX = Last Two Digits of Assembly Lot Number
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
C5U
AXX
YM
C32F
AYMXXX
C32F = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
24C32F = Specific Device Code
A = Assembly Location
XXX = Last Three Digits of Assembly Lot Number
YY = Production Year (Last Two Digits)
WW = Production Week (Two Digits)
G = Pd−Free designator
24C32F
AXXX
YYWWG
24C32F = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
24C32F
AYMXXX
2 = Specific Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
2
YM
(WLCSP−5)
B = Specific Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
B
YM
(WLCSP−4)
Figure 1. Functional Symbol
SDA
SCL
WP
CAT24C32
VCC
VSS
A2, A1, A0
Device AddressA0, A1, A2
Serial DataSDA
Serial ClockSCL
Write ProtectWP
Power SupplyVCC
GroundVSS
FunctionPin Name
PIN FUNCTION
CAT24C32
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3
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature –65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 2 mA
ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C
VCC ≤ 3.3 V
1mA
TA = −40°C to +85°C
VCC > 3.3 V
3
TA = −40°C to +125°C 5
ILI/O Pin Leakage Pin at GND or VCC 2mA
VIL Input Low Voltage −0.5 VCC x 0.3 V
VIH Input High Voltage SCL, SDA Inputs VCC x 0.7 6.5 V
WP, A0, A1, A2 Inputs VCC x 0.7 VCC + 0.5
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V, TA = 25°C, f = 1.0 MHz 8 pF
CIN (Note 4) Input Capacitance (other pins) VIN = 0 V, TA = 25°C, f = 1.0 MHz 6 pF
IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA
VIN < VIH, VCC = 3.3 V 120
VIN < VIH, VCC = 1.7 V 80
VIN > VIH 2
IA (Note 5) Address Input Current
(A0, A1, A2)
Product Rev F
VIN < VIH, VCC = 5.5 V 50 mA
VIN < VIH, VCC = 3.3 V 35
VIN < VIH, VCC = 1.7 V 25
VIN > VIH 2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
CAT24C32
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4
Table 5. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)
Symbol Parameter
Standard
VCC = 1.7 V − 5.5 V
Fast
VCC = 1.7 V − 5.5 V
Fast−Plus (Note 9)
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Units
Min Max Min Max Min Max
FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.25 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.40 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms
tHD:DAT Data In Hold Time 0 0 0 ms
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 7) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms
tBUF Bus Free Time Between STOP
and START
4.7 1.3 0.5 ms
tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms
tDH (Note 7) Data Out Hold Time 100 100 50 ns
Ti (Note 7) Noise Pulse Filtered at SCL and
SDA Inputs
100 100 100 ns
tSU:WP WP Setup Time 0 0 0 ms
tHD:WP WP Hold Time 2.5 2.5 1 ms
tWR Write Cycle Time 5 5 5 ms
tPU (Notes 7, 8) Power−up to Ready Mode 1 1 1 ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
9. Fast−Plus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code
on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Time ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Level 0.5 x VCC
Output Test Load Current Source IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
CAT24C32
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5
Power−On Reset (POR)
Each CAT24C32 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally. The Address inputs are not available for use with
WLCSP 4−ball and 5−ball.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally. The WP input is not available for the
WLCSP 4−ball, therefore all write operations are allowed
for the device in this package.
Functional Description
The CAT24C32 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C32
operates as a Slave device. Both Master and Slave can transmit
or receive, but only the Master can assign those roles.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C32, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP (C5A and C4C) respond only to the Slave
Address with A2 A1 A0 = 0 0 0. The R/W bit tells the Slave
whether the Master intends to read (1) or write (0) data
(Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
Figure 3. Slave Address Bits
1010
DEVICE ADDRESS*
A2A1A0R/W
* The devices in WLCSP 4−ball and 5−ball respond only to Slave Address byte with A2 A1 A0 = 0 0 0
CAT24C32
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6
Figure 4. Acknowledge Timing
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 5. Bus Timing
SCL
SDA IN
SDA OUT
tBUF
tSU:STO
tSU:DAT
tR
tAA tDH
tLOW
tHIGH
tLOW
tSU:STA
tHD:SDA
tHD:DAT
tF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24C32 is shipped erased, i.e., all bytes are FFh.
CAT24C32
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7
SLAVE
ADDRESS
S
A
****
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
Figure 6. Byte Write Sequence
*a15 − a12 are don’t care bits
a15 − a8a7 − a0d7 − d0
Figure 7. Write Cycle Timing
STOP
CONDITION START
CONDITION ADDRESS
ACK8th Bit
Byte n
SCL
SDA
tWR
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
P
A
C
K
BUS
ACTIVITY:
MASTER
SLAVE
n = 1
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
Figure 8. Page Write Sequence
P ≤ 31
Figure 9. WP Timing
189
18
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
tSU:WP
tHD:WP
a7a0d7d0
CAT24C32
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8
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
Figure 10. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOP
NO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY
MASTER
SLAVE
Figure 11. Selective Read Sequence
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
SLAVE
S
A
C
K
S
T
A
R
T
P
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE ADDRESS
N
O
A
C
K
DATA
BYTE
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
CAT24C32
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9
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
Package
Type Temperature Range
Lead
Finish Shipping
CAT24C32HU4I−GT3 C5U UDFN8 I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32HU4E−GT3
(Note 12)
C5U UDFN8 E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32C5ATR 2 WLCSP5 I = Industrial
(−40°C to +85°C)
SnAgCu Tape & Reel, 5,000 Units / Reel
CAT24C32C5CTR P WLCSP5 with
Die Coat
I = Industrial
(−40°C to +85°C)
SnAgCu Tape & Reel, 5,000 Units / Reel
CAT24C32C4CTR B WLCSP4 with
Die Coat
I = Industrial
(−40°C to +85°C)
SnAg Tape & Reel, 5,000 Units / Reel
CAT24C32LI−G 24C32F PDIP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 50 Units / Tube
CAT24C32WI−G 24C32F SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT24C32WI−GT3 24C32F SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32WE−GT3
(Note 12)
24C32F SOIC−8,
JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32YI−G C32F TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tube, 100 Units / Tube
CAT24C32YI−GT3 C32F TSSOP−8I = Industrial
(−40°C to +85°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32YE−GT3
(Note 12)
C32F TSSOP−8E = Extended
(−40°C to +125°C)
NiPdAu Tape & Reel, 3,000 Units / Reel
CAT24C32USI−T3
(In Development)
TBD US8 I = Industrial
(−40°C to +85°C)
Matte−Tin Tape & Reel, 3,000 Units / Reel
10.All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12.Please contact your nearest ON Semiconductor Sales office for availability.
13.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light
the EEPROM cells lose their stored data.
CAT24C32
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10
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT24C32
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11
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT24C32
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PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
CAT24C32
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PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE O
0.065 REF
Copper Exposed
E2
D2
L
E
PIN #1 INDEX AREA
PIN #1
IDENTIFICATION
DAP SIZE 1.8 x 1.8
DETAIL A
D
A1
be
A
TOP VIEW SIDE VIEW
FRONT VIEW
DETAIL A
BOTTOM VIEW
A3
0.065 REF
0.0 - 0.05A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
SYMBOL MIN NOM MAX
A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
b 0.20 0.25 0.30
D 1.95 2.00 2.05
D2 1.35 1.40 1.45
E 3.00
E2 1.25 1.30 1.35
e
2.95
0.50 REF
3.05
L 0.25 0.30 0.35
A
CAT24C32
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14
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
DIM
A
MIN MAX MIN MAX
INCHES
1.90 2.10 0.075 0.083
MILLIMETERS
B2.20 2.40 0.087 0.094
C0.60 0.90 0.024 0.035
D0.17 0.25 0.007 0.010
F0.20 0.35 0.008 0.014
G0.50 BSC 0.020 BSC
H0.40 REF 0.016 REF
J0.10 0.18 0.004 0.007
K0.00 0.10 0.000 0.004
L3.00 3.20 0.118 0.126
M0 6 0 6
N5 10 5 10
P0.23 0.34 0.010 0.013
R0.23 0.33 0.009 0.013
S0.37 0.47 0.015 0.019
U0.60 0.80 0.024 0.031
V0.12 BSC 0.005 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
LB
A
PG
41
58
C
K
D
SEATING
J
S
R
U
DETAIL E
V
F
H
N
R 0.10 TYP
M
−Y−
−X−
−T−
DETAIL E
T
M
0.10 (0.004) XY
T0.10 (0.004)
____
____
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ǒmm
inchesǓ
SCALE 8:1
3.8
0.15
0.50
0.0197
1.0
0.0394
0.30
0.012
1.8
0.07
CAT24C32
www.onsemi.com
15
PACKAGE DIMENSIONS
WLCSP5, 1.34x0.91
CASE 567JQ
ISSUE A
SEATING
PLANE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
2X
DIM
A
MIN MAX
−−−
MILLIMETERS
A1
D1.34 BSC
E
b0.16 0.20
e0.40 BSC
0.35
ÈÈ
ÈÈ
E
D
AB
PIN A1
REFERENCE
e
A0.05 BC
0.03 C
0.05 C
5X b
13
C
B
A
0.10 C
A
A1
A2
C
0.08 0.12
0.91 BSC
e1 0.693 BSC
0.18
5X
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.69
0.10 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 3
e1
A2 0.23 REF
RECOMMENDED
A1
PACKAGE
OUTLINE
PITCH
0.40
PITCH
2
DETAIL A
DIE COAT A3
(OPTIONAL)
DETAIL A
A2
A3 0.025 REF
CAT24C32
www.onsemi.com
16
PACKAGE DIMENSIONS
ÈÈ
ÈÈ
WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O
SEATING
PLANE
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
2X DIM
A
MIN MAX
−−−
MILLIMETERS
A1
D0.76 BSC
E
b0.15 0.16
e0.40 BSC
0.35
D
E
AB
PIN A1
REFERENCE
e
A0.05 BC
0.03 C
0.05 C
4X b
12
B
A
0.05 C
A
A1
A2
C
0.0415 0.0715
0.76 BSC
0.05 C
2X TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 3
e
A2 0.255 REF
PITCH 0.16
4X
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.40
0.40
RECOMMENDED
A1 PACKAGE
OUTLINE
PITCH
DIE COAT
DETAIL A
(OPTIONAL) A2
A3
A3 0.025 REF
DETAIL A
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