PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
1
Document Title
128K x8 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
Remark
Design target
Preliminary
Final
Final
History
Initial draft
First revision
- Seperate read and write at ICC, ICC1
ICC = ICC1 → Read : 15mA, Write : 35mA
Finalized
- Add 70ns speed bin for commercial product and 85ns speed
bin for industrial.
Revised
- Improved operating current
Add typical value.
ICC Read : 15mA → 10mA(Remove write current)
ICC2 : 90mA → 60mA
- Speed bin change
Remove 45ns from commercial part
Remove 55ns and 100ns from industrial part.
Draft Date
November 22, 1995
April 15, 1996
September 5, 1996
November 5, 1997
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
2
128K x8 bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
The K6T1008C2C families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
• Process Technology: TFT
• Organization: 128K x8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F/R
PIN DESCRIPTION
PRODUCT FAMILY
Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2, Max)
K6T1008C2C-L Commercial(0~70°C)
4.5~5.5V
55/70ns 50µA
10µA60mA
32-DIP, 32-SOP
32-TSOP1-F/R
K6T1008C2C-B
K6T1008C2C-P Industrial(-40~85°C) 70ns 50µA
15µA32-SOP
32-TSOP1-F/R
K6T1008C2C-F
FUNCTIONAL BLOCK DIAGRAM
32-TSOP
Type1 - Reverse
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP
Type1 - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
32-DIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-SOP
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
1024 rows
128×8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0 A1 A2 A3 A9 A11A10
A4
A5
A6
A7
A8
A12
A14
I/O1Data
cont
I/O8
A13
A15
A16
VCC
VSS
CS1
WE
OE
Control
logic
CS2
Data
cont
Name Function Name Function
CS1,CS2Chip Select Inputs I/O1~I/O8Data Inputs/Outputs
OE Output Enable Vcc Power
WE Write Enable Input Vss Ground
A0~A16 Address Inputs N.C No Connection
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
3
PRODUCT LIST
Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
K6T1008C2C-DL55
K6T1008C2C-DL70
K6T1008C2C-DB55
K6T1008C2C-DB70
K6T1008C2C-GL55
K6T1008C2C-GL70
K6T1008C2C-GB55
K6T1008C2C-GB70
K6T1008C2C-TB55
K6T1008C2C-TB70
K6T1008C2C-RB55
K6T1008C2C-RB70
32-DIP, 55ns, L-pwr
32-DIP, 70ns, L-pwr
32-DIP, 55ns, LL-pwr
32-DIP, 70ns, LL-pwr
32-SOP, 55ns, L-pwr
32-SOP, 70ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 55ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
K6T1008C2C-GP70
K6T1008C2C-GF70
K6T1008C2C-TF70
K6T1008C2C-RF70
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don′t care(Must be in high or low status.)
CS1CS2OE WE I/O Pin Mode Power
HX1) X1) X1) High-Z Deselected Standby
X1) LX1) X1) High-Z Deselected Standby
LH H H High-Z Output Disable Active
LHLHDout Read Active
LHX1) LDin Write Active
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN, VOUT -0.5 to 7.0 V-
Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CK6T1008C2C-L
-40 to 85 °CK6T1008C2C-P
Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
4
RECOMMENDED DC OPERATING CONDITIONS1)
Note
1. Commercial Product : TA=0 to 70°C and Industrial Product :TA=-40 to 85°C, otherwise specified.
2. Overshoot : Vcc+3.0V for≤30ns pulse width.
3. Undershoot : -3.0V for≤30ns pulse width.
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Min Typ Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 -Vcc+0.52) V
Input low voltage VIL -0.53) -0.8 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled not, 100% tested.
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -6pF
Input/Output capacitance CIO VIO=0V -8pF
DC AND OPERATING CHARACTERISTICS
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 -1µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read -510 mA
Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V,
CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Read -2 5 mA
Write 20 35
ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,VIN=VIL or VIH -45 60 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other input=VIL or VIH - - 3mA
Standby
Current
(CMOS)
K6T1008C2C-L
ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V
or CS2≤0.2V
Other input =0~Vcc
Low Power -150
µA
K6T1008C2C-B Low Low Power -0.3 10
K6T1008C2C-P Low power -150
K6T1008C2C-F Low Low Power -0.3 15
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
5
CL1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
AC CHARACTERISTICS
Parameter List Symbol
Speed Bins
Units
55ns 70ns
Min Max Min Max
Read
Read cycle time tRC 55 -70 -ns
Address access time tAA -55 -70 ns
Chip select to output tCO1, tCO2 -55 -70 ns
Output enable to valid output tOE -25 -35 ns
Chip select to low-Z output tLZ 10 -10 -ns
Output enable to low-Z output tOLZ 5-5-ns
Chip disable to high-Z output tHZ 020 025 ns
Output disable to high-Z output tOHZ 020 025 ns
Output hold from address change tOH 10 -10 -ns
Write
Write cycle time tWC 55 -70 -ns
Chip select to end of write tCW 45 -60 -ns
Address set-up time tAS 0-0-ns
Address valid to end of write tAW 45 -60 -ns
Write pulse width tWP 40 -50 -ns
Write recovery time tWR1,tWR2 0-0-ns
Write to output high-Z tWHZ 020 025 ns
Data to write time overlap tDW 25 -30 -ns
Data hold from write time tDH 0-0-ns
End write to output low-Z tOW 5-5-ns
DATA RETENTION CHARACTERISTICS
1. CS1≥Vcc-0.2v, CS2≥Vcc-0.2V or CS2≤0.2V
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS11)≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V 2.0 -5.5 V
Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V,
CS2≥Vcc-0.2V or CS2≤0.2V
K6T1008C2C-L -120
µA
K6T1008C2C-B -110
K6T1008C2C-P - - 25
K6T1008C2C-F - - 10
Data retention set-up tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
6
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
CS1
Address
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
CS2
tOH
tAA
tOLZ
tLZ tOHZ
tHZ(1,2)
tRC
tCO2tOE
tCO1
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
7
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS1
tCW(2) tWR(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
Address
CS1
tWC
tWR(4)
tAS(3)
CS2tCW(2)
tWP(1)
tDW tDH
tOW
tWHZ
Data Undefined
Data Valid
WE
Data in
Data out
tDW tDH
Data Valid
WE
Data in
Data out High-Z High-Z
CS2
tWC
tAW
tAS(3)
tCW(2)
tWP(1)
tAW
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
8
DATA RETENTION WAVE FORM
CS1 controlled
VCC
4.5V
2.2V
VDR
CS1
GND
Data Retention Mode
CS1≥VCC-0.2V
tSDR tRDR
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
CS2
tCW(2)
WE
Data in Data Valid
Data out High-Z High-Z
tCW(2) tWR(4)
tWP(1)
tDW tDH
tAS(3)
tWC
CS2 controlled
VCC
4.5V
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR tRDR
CS2≤0.2V
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
9
PACKAGE DIMENSIONS Units: millimeter(inch)
0~15°
1.91
#1
32 DUAL INLINE PACKAGE (600mil)
#32
13.60±0.20
0.535±0.008
41.91±0.20
1.650±0.008
( )
0.075
15.24
0.600
+0.10
MAX
42.31
1.666
0.25 -0.05
+0.004
0.010
-0.002
2.54
0.100
MAX
3.81±0.20
0.150±0.008
5.08
0.200
MIN
0.015
0.38 0.130±0.012
3.30±0.30
#16
#17
1.52±0.10
0.060±0.004
0.46±0.10
0.018±0.004
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
20.47±0.20
0.806±0.008
MAX
20.87
0.822 MAX
2.74±0.20
0.108±0.008
3.00
0.118
MIN
0.002
0.05
0.004 MAX
0.10 MAX
#1
0.71
( )
0.028
13.34
0.525
11.43±0.20
0.450±0.008
0.80±0.20
0.031±0.008
+0.10
0.20 -0.05
+0.004
0.008
-0.002
14.12±0.30
0.556±0.012
#17
#16
1.27
0.050
+0.100
0.41 -0.050
+0.004
0.016 -0.002
PRELIMINARY
K6T1008C2C Family CMOS SRAM
Revision 2.0
November 1997
10
32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820F)
#32
1.00±0.10
0.039±0.004
MAX
8.40
0.331
0.10
0.004
#1
0.50
( )
0.020
18.40±0.10
0.724±0.004
0.45 ~0.75
0.018 ~0.030
20.00±0.20
0.787±0.008
#17
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS Units: millimeter(inch)
32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820R)
#32
1.00±0.10
0.039±0.004
MAX
8.40
0.331
#1
0.50
( )
0.020
18.40±0.10
0.724±0.004
0.45 ~0.75
0.018 ~0.030
20.00±0.20
0.787±0.008
#17
+0.10
0.15 -0.05
+0.004
0.006 -0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
MAX
0.10
0.004 MAX
