Data Sheet 1 of 10 Rev. 03.1, 2009-02-20
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
PTFA043002E
Description
The PTFA043002 is a 300-watt, internally-matched, laterally-diffused,
GOLDMOS® push-pull FET intended for analog and digital broadcast,
including 8VSB and COFDM applications from 470 to 860 MHz. The
thermally-enhanced package provides the coolest operation available. Full
gold metallization ensures excellent device lifetime and reliability. PTFA043002E
Package H-30275-4
Thermally-Enhanced High Power RF LDMOS FET
300 W, 470 – 860 MHz
ATSC 8VSB Characteristics (broadband fixture, push-pull configuration)
(VDD = 32 V, POUT = 100 WAVG, IDQ = 1.55 A, ƒ = 800 MHz)
Characteristic Symbol Min Typ Max Unit
Common Source Power Gain Gps 16 dB
Drain Efficiency ηD28 %
FIrst Adjacent IMD –33 dBc
RF Characteristics
Two-tone Drive-up at 800 MHz
(in broadband circuit)
VDD = 32 V, IDQ = 1.55 A,
ƒ1 = 799.5 MHz, ƒ2 = 800.5 MHz
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 50 100 150 200 250 300 350
Output Power (W PEP)
IM3, 5, 7 (dBc)
0
5
10
15
20
25
30
35
40
45
Drain Efficiency (%)
3rd Order
7th
5th
Efficiency
*See Infineon distributor for future availability.
Features
Thermally-enhanced package
Broadband internal matching
Typical 8VSB performance
- Average output power = 100 W
- Gain = 16 dB
- Adjacent < –33 dBc
Integrated ESD protection: Human Body
Model, Class 2 (minimum)
Excellent thermal stability
Low HCI drift
Pb-free and RoHS compliant
Capable of handling 5:1 VSWR at 32 V,
300 W (CW) output power
PTFA043002E
Data Sheet 2 of 10 Rev. 03.1, 2009-02-20
RF Characteristics (cont.)
Two-tone Measurements (tested in narrowband test fixture)
VDD = 32 V, IDQ = 1.55 A, POUT = 300 WPEP, ƒ = 860 MHz, tone spacing = 1 MHz
Characteristic Symbol Min Typ Max Unit
Gain Gps 16 17.5 dB
Drain Efficiency ηD38 41 %
Intermodulation Distortion IMD –29 –28 dBc
DC Characteristics (one side)
Characteristic Conditions Symbol Min Typ Max Unit
Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA/side V(BR)DSS 65 V
Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS 1.0 µA
VDS = 63 V, VGS = 0 V IDSS ——10.0 µA
On-State Resistance VGS = 10 V, VDS = 0.1 V RDS(on) 0.08 W
Operating Gate Voltage VDS = 28 V, IDQ = 0.75 A/side VGS 2.0 2.5 3.0 V
Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS 1.0 µA
Maximum Ratings
Parameter Symbol Value Unit
Drain-Source Voltage VDSS 65 V
Gate-Source Voltage VGS –0.5 to +12 V
Junction Temperature TJ200 °C
Total Device Dissipation PD761 W
Above 25°C derate by 4.35 W/°C
Storage Temperature Range TSTG –40 to +150 °C
Thermal Resistance (TCASE = 70°C, 300 W CW) RθJC 0.23 °C/W
Ordering Information
Type Package Outline Package Description Marking
PTFA043002E H-30275-4 Thermally-enhanced, flange mount PTFA043002E
*See Infineon distributor for future availability.
PTFA043002E
Data Sheet 3 of 10 Rev. 03.1, 2009-02-20
Typical Performance (data taken in a broadband test fixture)
Analog NTSC Performance
VDD = 32 V, IDQ = 1.55 A
0
50
100
150
200
250
300
350
400 500 600 700 800 900
Frequency (MHz)
Output Power, 25% Sync
Compression (W, Pk, Sync.)
20
25
30
35
40
45
50
55
Drain Efficiency (%)
Output Power
Efficiency
Two-tone IMD Performance
VDD = 32 V, IDQ = 1.55 A, IMD = –28 dBc
0
100
200
300
400
400 500 600 700 800 900
Frequency (MHz)
Output Power, PEP (W)
20
30
40
50
60
Drain Efficiency (%)
Drain Efficiency
Output Power (PEP)
8VSB Performance vs. Frequency
@ 100 W Average Power
VDD = 32 V, IDQ = 1.55 A, IMD = –28 dBc
-40
-38
-36
-34
-32
-30
400 500 600 700 800 900
Frequency (MHz)
Adjacent (dBc)
10
14
18
22
26
30
Drain Efficiency (%)
Efficiency
Adjacent
Gain vs. Frequency
VDD = 32 V, IDQ = 1.55 A
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
400 500 600 700 800 900
Frequency (MHz)
Small Signal Gain (dB)
PTFA043002E
Data Sheet 4 of 10 Rev. 03.1, 2009-02-20
Two-tone Drive-up at 800 MHz
(in narrowband circuit)
VDD = 32 V, IDQ = 1.55 A, ƒ1 = 799.5 MHz, ƒ2 = 800.5 MHz
-80
-70
-60
-50
-40
-30
-20
-10
0
050 100 150 200 250 300 350
Output Power, PEP (W)
IM3, 5, 7 (dBc)
0
5
10
15
20
25
30
35
40
Gain (dB), Efficiency (%)
3rd Order
7th
5th
Drain Efficiency
Gain
Typical Performance (cont.)
Bias Voltage vs. Temperature
Voltage normalized to typical gate voltage,
series show current
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
-20 020 40 60 80 100
Case Temperature (°C)
Normalized Bias Voltage (V)
0.29 A
0.88 A
1.47 A
2.20 A
4.41 A
6.61 A
8.81 A
11.02 A
DVB Adjacent Channel Power
VDD = 32 V, IDQ = 1.55 A,
63 W DVB signal
-75
-70
-65
-60
-55
-50
450 500 550 600 650 700 750 800 850 900
Frequency (MHz)
ACP (±4.2 MHz) (dBc)
0
5
10
15
20
25
Drain Efficiency (%)
+4.2 MHz
Efficiency
–4.2 MHz
PTFA043002E
Data Sheet 5 of 10 Rev. 03.1, 2009-02-20
Broadband Circuit Impedance Data
VDD = 28 V, IDQ = 2.0A, POUT = 30 W AVG Two-carrier WCDMA
Frequency Z Source Z Load
MHz RjX RjX
450 3.00 –4.61 1.78 –3.26
475 3.02 –3.71 1.85 –2.63
500 3.18 –2.96 1.99 –2.09
525 3.43 –2.36 2.18 –1.64
550 3.75 –1.90 2.41 –1.28
575 4.10 –1.61 2.64 –1.03
600 4.42 –1.47 2.85 –0.87
625 4.66 –1.44 3.01 –0.77
650 4.79 –1.47 3.10 –0.70
675 4.84 –1.50 3.15 –0.63
700 4.84 –1.50 3.17 –0.53
725 4.82 –1.46 3.20 –0.42
750 4.82 –1.42 3.24 –0.31
775 4.83 –1.41 3.30 –0.22
800 4.80 –1.46 3.33 –0.18
825 4.69 –1.54 3.30 –0.16
850 4.43 –1.61 3.17 –0.13
875 4.04 –1.54 2.95 –0.01
900 3.57 –1.27 2.67 0.27
0.1
0.2
0.1
0.1
0.3
0
.2
N
E
A
<-
--
W
AV
E
LE
N
G
TH
S
T
O
W
AR
D
L
OA
D
-
0
.0
900 MHz
450 MHz
Z Source
450 MHz
900 MHz
Z Load
Z0 = 50
Z Source Z Load
G
D
G
S
D
PTFA043002E
Data Sheet 6 of 10 Rev. 03.1, 2009-02-20
l17 l19
l16 l18
a043002e_bd-02_070212
C9
R8
R9
10µF
35V
C11
0.1µF
C10
TB2
5.1KV
10V
QQ1
1.2K V
R11
LM7805
3.3K V
R7
R13
2K V
0.001µF
C35
BCP56
1.3K V
Q1
R10
R12
22V
C34
0.001µF
0.001µF
C33
R14
100 V
VBIAS
2.7pF
C32
6.2pF
C31
75pF
C16
2.4pF
C15
4.8pF
C14
DUT
75pF
C17
0.01µF
C22
10µF
50V
C21
10µF
50V
C20
1µF
C19
1µF
C18
75pF
C17
75pF
C8
R5
8.2pF
C5
75pF
C12
R6
10µF
35V
C7
0.1µF
C6
75pF
C3
75pF
15pF
C2
2.7pF
C1
TB3
TB4
TB1
5.1KV
10 V
3.3K V
R4
R1
R2
R3
100 V
2KV
22V
RF_IN
L1
C4
2.4pF
L2
1µF
C25
75pF
C24
1µF
C26 10µF
50V
C27 10µF
50V
C28
0.01µF
C29
VDD
l9
l3
l2
l8
l13
l15
l7
l1
Sl1
RF_OUTl26
Sl2
l14
l10
l4
l11
l5
l12
l6
VDD
VDD
VBIAS
VBIAS
C13
8.2pF
6.8pF
C30
l21
l20
l23
l22
l25
l24
Reference Circuit
Reference circuit schematic for 470 to 860 MHz—rated for 300 W (PEP) only
Circuit Assembly Information
DUT PTFA043002E LDMOS transistor
Circuit board 0.25 mm [.010”] over .635 mm [.025”] thick, εr = 10.2 Rogers 3010, multilayer
copper: 10 mils top 25 mils bottom
Microstrip Electrical Characteristics at 860 MHz1Dimensions: L x W (mm) Dimensions: L x W (in.)
TB1, TB2, TB3, Broadside coupled striplines 14.63 x 1.70 0.576 x 0.067
TB4
Sl1, Sl20.017 λ, 15.6 33.02 x 1.32 0.075 x 0.067
l1, l26 0.250 λ, 39.0 0.51 x 2.54 1.300 x 0.052
l2, l8, l24, l25 0.004 λ, 26.0 5.59 x 15.24 0.020 x 0.100
l3, l90.049 λ, 6.1 4.45 x 15.24 0.220 x 0.600
l4, l10 0.038 λ, 6.1 7.62 x 22.86 0.175 x 0.600
l5, l11 0.067 λ, 4.2 6.25 x 25.40 0.300 x 0.900
l6, l12 0.055 λ, 3.8 28.45 x 1.22 0.246 x 1.000
l7, l13 0.216 λ, 41.0 40.39 x 1.22 1.120 x 0.048
l14, l15 0.307 λ, 41.0 5.08 x 25.40 1.590 x 0.048
l16, l17 0.045 λ, 3.8 12.70 x 25.40 0.200 x 1.000
l18, l19 0.112 λ, 3.8 2.74 x 25.40 0.500 x 1.000
l20, l21 0.024 λ, 3.8 2.54 x 20.32 0.108 x 1.000
l22, l23 0.022 λ, 4.7 2.54 x 20.32 0.100 x 0.800
1Electrical characteristics are rounded.
PTFA043002E
Data Sheet 7 of 10 Rev. 03.1, 2009-02-20
a043002e_cd-dtl_0702212
R12
Q1
QQ1
R9
R8
R7
R14 R10
R11
R13
C35
C33
C10 C12
C34
VDD
C11
a043002e_cd-02_070212
RF_OUT
VDD
RF_IN
R12
Q1
QQ1
R9
R8R7
R14 R10
R11
R1
R3
R4
R5
R6
C5
C4
C9
C2
C3
R2
C1
C6 C8
R13
C35
C33
C10 C12
C34
C13 C17
C15
C16
C31
C32
C29
C25
C26
C24
C19
C20
C18
C21
C23
C22
C28
C27
L2
L1
VDD
VDD
VDD
C14
C30
C7
C11
Reference circuit assembly diagram* (not to scale)—rated for 300 W (PEP) only
Reference Circuit (cont.)
*Gerber Files for this circuit available on request.
PTFA043002E
Data Sheet 8 of 10 Rev. 03.1, 2009-02-20
Reference Circuit (cont.)
Component Description Suggested Manufacturer P/N or Comment
C1, C32 Ceramic capacitor, 2.7 pF ATC 100B 2R7
C2 Capacitor, 15 pF ATC 100B 150
C3, C8, C9, C12, Ceramic capacitor, 75 pF ATC 100B 750
C16, C17, C18, C24
C4, C15 Ceramic capacitor, 2.4 pF ATC 100B 2R4
C5, C13 Ceramic capacitor, 8.2 pF ATC 100B 8R2
C6, C10 Capacitor, 0.1 µF Digi-Key PCC104BCT-ND
C7, C11 Tantalum capacitor, 10 µF, 35 V Digi-Key PCS6106TR-ND
C14 Ceramic capacitor, 4.8 pF ATC 100B 4R8
C19, C20, C25, C26 Capacitor, 1 µF ATC 920C105
C21, C22, C27, C28 Tantalum capacitor, 10 µF, 50 V Garrett Electronics TPS106K050R0400
C23, C29 Ceramic capacitor, 0.01 µF ATC 200B 103
C30 Ceramic capacitor, 6.8 pF ATC 100B 6R8
C31 Ceramic capacitor, 6.2 pF ATC 100B 6R2
C33, C34, C35 Capacitor, 0.001 µF Digi-Key PCC1772CT-ND
L1, L2 Ferrite, 8.9 mm Elna Magnetics BDS 4.6/3/8.9-4S2
Q1 Transistor Infineon Technologies BCP56
QQ1 Voltage regulator National Semiconductor LM7805
R1, R14 Chip Resistor 100 ohms Digi-Key P100ECT-ND
R2, R13 Potentiometer 2 k-ohms Digi-Key 3224W-202ETR-ND
R3, R12 Chip Resistor 22 ohms Digi-Key P22KECT-ND
R4, R7 Chip Resistor 3.3 k-ohms Digi-Key P3.3KECT-ND
R5, R8 Chip Resistor 10 ohms Digi-Key P10ECT-ND
R6, R9 Chip Resistor 5.1 k-ohms Digi-Key P5.1KECT-ND
R10 Chip Resistor 1.0 k-ohms Digi-Key P1KGCT-ND
R11 Chip Resistor 1.1 k-ohms Digi-Key P1.1KGCT-ND
See next page for package information
PTFA043002E
Data Sheet 9 of 10 Rev. 03.1, 2009-02-20
C
L
S
41.15
[1.620]
1.63
[.064]
2.18
[.086] SPH
31.24±0.28
[1.230±.011]
35.56
[1.400]
D
G
D
16.61±0.51
[.654±.020]
2X R 1.59
[.063]
2X 3.18
[.125]
9.40
[.370 ]
0.038 [.0015] -A-
2X 45°±5° X 1.19
[.047]
4.55±0.38
[.179±.015]
Flange 10.16
[.400]
4X 3.23±0.25
[.127±.010]
G
H-30275-4
[.360 ]
+.004
–.006
LID 9.14 +0.10
–0.15
4X 11.68
[.460]
13.72
[.540]
C
L
C
L
+0.10
–0.15
+.004
–.006
Package Outline Specifications
Package H-30275-4
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.13 +0.051/–0.025 [.005 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S - flange: 2.54 micron [100 microinch] (min)
D, G - leads: 11.14 micron ± 0.38 micron [45 microinch ± 15 microinch]
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/products
Data Sheet 10 of 10 Rev. 03.1, 2009-02-20
PTFA043002E
Confidential, Limited Internal Distribution
Revision History: 2009-02-20 Data Sheet
Previous Version: 2005-11-18, Data Sheet
Page Subjects (major changes since last revision)
6Revise circuit board information.
1, 2, 9 Update package designation.
8Fixed typing error
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GOLDMOS® is a registered trademark of Infineon Technologies AG.
Edition 2009-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
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