Integrated
Circuit
Systems, Inc.
ICS950810
0472F—01/12/04
Block Diagram
Recommended Application:
CK-408 clock for BANIAS processor/ ODEM and
MONTARA-G chipsets.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%. (CPU, 3V66, PCI)
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Frequency Generator with 200MHz Differential CPU Clocks
Functionality
* These inputs hav e 150K internal pull-up resistor to VDD.
2SF1SF0SF UPC )zHM( )0:5(66V3 )zHM(
F_ICP ICP )zHM(
X00 66.66166.6633.33
X01 00.00166.6633.33
X10 00.00266.6633.33
X11 33.33166.6633.33
diM00 etatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT8/KLCT
diM10 devreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseR
PLL2
PLL1
Spread
Spectrum
3V66_5
3V66_3
3V66_(4,2)
48MHz_USB
48MHz_DOT
X1
X2 XTAL
OSC
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
3V66_0
CPU
DIVDER
3
3CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
VDDREF 156
REF
X1 255
FS1
X2 354
FS0
GND 453
CPU_STOP#*
PCICLK_F0 552
CPUCLKT0
PCICLK_F1 651
CPUCLKC0
PCICLK_F2 750
VDDCPU
VDDPCI 849
CPUCLKT1
GND 948
CPUCLKC1
PCICLK0 10 47 GND
PCICLK1 11 46 VDDCPU
PCICLK2 12 45 CPUCLKT2
PCICLK3 13 44 CPUCLKC2
VDDPCI 14 43 MULTSEL0*
GND 15 42 IREF
PCICLK4 16 41 GND
PCICLK5 17 40 FS2
PCICLK6 18 39 48MHz_USB
VDD3V66 19 38 48MHz_DOT
GND 20 37 VDD48
3V66_2 21 36 GND
3V66_3 22 35 3V66_1/VCH_CLK
3V66_4 23 34 PCI_STOP#*
3V66_5 24 33 3V66_0
*PD# 25 32 VDD3V66
VDDA 26 31 GND
GND 27 30 SCLK
Vtt_PWRGD# 28 29 SDATA
ICS950810
2
ICS950810
0472F—01/12/04
NIP REBMUN EMANNIPEPYTNOITPIRCSED
1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR
21XNI.zHM813.41yllanimon,tupnilatsyrC
32XTUO.zHM813.41yllanimon,tuptuolatsyrC
4
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61F_KLCICPTUO.#POTS_ICPybdetceffatonkcolcICPgninnureerF
72F_KLCICPTUO.#POTS_ICPybdetceffatonkcolcICPgninnureerF
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9DNGRWP.stuptuoV3rofnipdnuorG
010KLCICPTUO.stuptuokcolcICP
111KLCICPTUO.stuptuokcolcICP
212KLCICP
TUO.stuptuokcolcICP
313KLCICP
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V3.3lanimon,KLCICPdnaF_KLCICProfylppusrewoP
51DNGRWP.stuptuoV3rofnipdnuorG
614KLCICPTUO.stuptuokcolcICP
715KLCICPTUO.stuptuokcolcICP
816KLCICPTUO.stuptuokcolcICP
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02DNGRWP.stuptuoV3rofnipdnuorG
122_66V3TUO.V3.3tastuptuozHM66
223_66V3TUO.V3.3tastuptuozHM66
324_66V3TUO.V3.3tastuptuozHM66
425_66V3TUO.V3.3tatuptuo/tupnizHM66
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72DNGRWP.stuptuoV3rofnipdnuorG
Pin Configuration
3
ICS950810
0472F—01/12/04
Pin Configuration (Continued)
NIP REBMUN EMANNIPEPYTNOITPIRCSED
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2366V3DDVRWP.skcolc66V3ehtrofniprewoP
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53KLC_HCV/1_66V3TUOtuptuokcolcCSSzHM66roCSS-nonzHM84elbatceleS
63DNGRWP.stuptuoV3rofnipdnuorG
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83TOD_zHM84TUOkcolctuptuozHM84
93BSU_zHM84TUOkcolctuptuozHM84
042SFNI.niptcelesycneuqerF
14DNGRWP.stuptuoV3rofnipdnuorG
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340LESTLUMNI stuptuoUPCrofreilpitlumtnerrucehtnoitcelesroftupniLTTVLV3.3
442CKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"yratnemelpmoC" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuoedom
542TKLCUPCTUO edomtnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuo
64UPCDDVRWPlanimonV3.3,skcolcUPCrofylppuS
74DNGRWP.stuptuoV3rofnipdnuorG
841CKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"yratnemelpmoC" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuoedom
941TKLCUPCTUO edomtnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuo
05UPCDDVRWPlanimonV3.3,skcolcUPCrofylppuS
150CKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"yratnemelpmoC" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuoedom
250TKLCUPCTUO edomtnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqererasrotsiserlanretxE.stuptuo
35#POTS_UPCNI .wolnevirdnehwlevelwolevitcaotstlahtupnisuonorhcnysasihT
450SFNI.niptcelesycneuqerF
551SFNI.niptcelesycneuqerF
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4
ICS950810
0472F—01/12/04
Host Swing Select Functions
0LESITLUM tegraTdraoB ZmreT/ecarT
,RecnerefeR =ferI
V
DD
)rR*3(/
tuptuO tnerruC Z@hoV
0- - --
1smho05 ,%1574=rR Am23.2=ferI FERI*6=hoI05@V7.0
Truth Table
Maximum Allowed Current
noitidnoC
noitpmusnocylppusV3.3xaM ,sdaolpacetercsidxaM V564.3=ddV DNGroddV=stupnicitatsllA
edoMnwodrewoP )0=#NWDRWP( Am52
evitcAlluF Am063
2SF1SF0SF UPC )zHM( 66V3 )0:5( )zHM(
F_ICP ICP )zHM( 0FER )zHM( TOD/BSU )zHM(
X00 66.66166.6633.33813.4100.84
X01 00.00166.6633.33813.4100.84
X10 00.00266.6633.33813.4100.84
X11 33.33166.6633.33813.4100.84
diM00 etatsirTetatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT8/KLCTKLCT2/KLCT
diM10 devreseRdevreseRdevreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseRdevreseR
P ower Gr oups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD f or Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
NO TE: MUL TSEL0 = 0 not supported in ICS950810. Refer to ICS950805 f or Buffered Mode support.
5
ICS950810
0472F—01/12/04
Power Management
PD# CPU_STOP# PCI_STOP# VCO CPU CPU# PCICLK 3v66 48MHz REF
0 X X STOP Iref*2 FLOAT LOW LOW LOW LOW
1 1 1 RUN RUN RUN RUN RUN RUN RUN
1 0 1 RUN Iref*2 FLOAT RUN RUN RUN RUN
1 1 0 RUN RUN RUN LOW RUN RUN RUN
1 1 1 RUN RUN RUN RUN RUN RUN RUN
Note: PCI_F is not affected by PCI_ STO P# and CPU_STO P#
State Byte0 bit6
PD# Byte1bit6
C
p
u_sto
p
#Pin
PD# Pin
C
p
u_Sto
p
#Stoppable
CPU out
p
uts Free-Running
CPU out
p
uts
0 0 0 1 1 Runnin
g
Runnin
g
1 0 0 1 0 Irefx6 Runnin
g
2 0 0 0 1 Irefx2 Irefx2
3 0 0 0 0 Irefx2 Irefx2
4 0 1 1 1 Runnin
g
Runnin
g
5 0 1 1 0 Hi-Z Runnin
g
60 1 0 1 Hi-Z Irefx2
70 1 0 0 Hi-Z Irefx2
8 1 0 1 1 Runnin
g
Runnin
g
9 1 0 1 0 Irefx6 Runnin
g
10 1 0 0 1 Hi-Z Hi-Z
11 1 0 0 0 Hi-Z Hi-Z
12 1 1 1 1 Runnin
g
Runnin
g
13 1 1 1 0 Hi-Z Runnin
g
14 1 1 0 1 Hi-Z Hi-Z
15 1 1 0 0 Hi-Z Hi-Z
Tri-State Control of CPU Outputs
6
ICS950810
0472F—01/12/04
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2VDD +0.3 V
Input Low Voltage VIL VSS -0.3 0.8 V
Input High Current IIH VIN = VDD -5 5
IIL1 VIN = 0 V; Inpu ts with no pull-up
resistors -5
IIL2 VIN = 0 V; Inputs with pu l l - up
resistors -200
IDD3.3OP CL = Full load; Select @ 100 MHz 229 230 360 mA
IDD3.3OP CL =Full load; Select @ 133 MHz 220 233 360 mA
Powerdown Current IDD3.3PD IREF=2. 32 mA 22 25 mA
Input F r equency FiVDD = 3.3 V 14.318 MHz
Pin Induct ance Lpin 7nH
CIN Logic Input s 5 pF
COUT Output pin capacitance 6 pF
CINX X1 & X2 pins 27 30 45 pF
Clk Stabilization1,2 TSTAB From Power Up or deass ertion of
PowerDown to 1st clock. 11.8 ms
tPZH,tPZL Output enable delay (all outputs) 1 10 ns
tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
2See timin
g
dia
g
rams for buffered and un-buffered timin
g
re
q
uirements.
Delay1
Input Capacitance1
Input Low Current µA
Operating Supply Current
7
ICS950810
0472F—01/12/04
El ect r i ca l Character i st ics - CPU ( 0. 7 V Sel e ct )
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unl e ss ot h erwi se specifie d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current So urce Ou t pu t
Impedance Zo1 VO = Vx3000 Ω
V ol t age Hi gh V Hi gh 660 810 850
V oltage Low VLow -150 20 150
M ax V o ltage V ovs 850 1150
M i n Voltage V uds -450 -15
Crossin g Voltag e (abs) V cross(a bs) 250 380 5 50 m V
Crossin g Voltag e (var) d-V cross V ariat ion of cross i ng ov er all
edges 22 140 mV
Ri se T i m e trVOL = 0.175V, VOH = 0.52 5V 175 290 7 00 ps
Fall Time t fVOH = 0 . 52 5V VOL = 0. 175V 175 3 10 700 ps
Rise T i m e Vari at i on d-t r10 125 ps
Fall Time V ari ation d-tf10 125 ps
Duty Cycle dt3 Meas urement f rom dif f erenti al
wavefrom 45 51 55 %
Skew tsk3 V
T
= 5 0% 16 100 ps
Jitter, Cy cle to cycle tjcyc-cyc1VT = 5 0% 48 150 ps
1Guaranteed by desi g n, not 10 0% teste d i n p roduct i o n.
2 IOW
T
can be vari ed a nd i s selectabl e thru t h e M ULT SEL pi n.
Statist ica l measurem ent on
si n gl e en ded sign al using mV
M easurem ent on sin gl e e nded
signal u sing absolu te val ue. mV
El ect r i cal Chara ct er i st ics - PCI CLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unl e ss ot h erwi se specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Outp ut Imp edance RDSP11VO = VDD*(0.5) 12 33 55 W
Output High Voltage VOH1IOH = -1 mA 2.4 3.28 V
Out put Low Voltage VOL1IOL = 1 m A 0.08 0.55 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -3 3 mA
VOL @MIN = 1.9 5 V 30 110
VOL @MA X = 0.4 V 37 3 8 m A
Ri se T i m e tr11VOL = 0.4 V , VOH = 2. 4 V 0.5 1. 28 2 ns
Fall Time tf11VOH = 2.4 V, V OL = 0. 4 V 0.5 1. 37 2 ns
Duty Cycle dt11VT = 1.5 V 45 51.1 55 %
Skew tsk11VT = 1.5 V 127 500 ps
Jitter,cy cle to cyc tjcyc-cyc1VT = 1. 5 V 164 250 ps
1Guaranteed by desi g n, not 10 0% teste d i n p roduct i o n.
Output High Current IOH1
Out put Low Current IOL1
8
ICS950810
0472F—01/12/04
Electrical Characteristics - 3V66 Mode: 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Im pedance RDSP11VO = VDD*(0.5) 12 33 55 Ω
Output High Voltage VOH1IOH = -1 m A 2.4 3.28 V
Output Low Voltage VOL1IOL = 1 mA 0.08 0.55 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -33 mA
VOL @MIN = 1.95 V 30 110
VOL @MAX = 0.4 V 37 38 mA
Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.15 2 ns
Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 1.53 2 ns
Duty Cycle dt11VT = 1.5 V 45 51.3 55 %
Skew tsk11VT = 1.5 V 67 250 ps
Jitter t
c
c-c
c1VT = 1.5 V 3V6 6 175 250 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH1
IOL1
O utput Low C urren t
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Im pedance RDSP11VO = VDD*(0.5) 20 48 60 Ω
Output High Voltage VOH1IOH = -1 m A 2.4 3.27 V
Output Low Voltage VOL1IOL = 1 mA 0.08 0.4 V
V OH@MIN = 1.0 V -29 -61
V OH@MAX = 3.135 V -12 -23 mA
VOL @MIN = 1.95 V 29
VOL @MAX = 0.4 V 27 mA
48DOT Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 0.69 1 ns
48DOT Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 0.81 1 ns
VCH 48 USB Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 11.372 ns
VCH 48 USB Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 11.472 ns
48 DOT Duty Cycle dt11VT = 1.5 V 45 51.2 55 %
VCH 48 USB Duty Cycle dt11VT = 1.5 V 45 53.5 55 %
48 DOT Jitter t
c
c-c
c1VT = 1.5 V 111 350 ps
48 USB Jitter t
c
c-c
c1VT = 1.5 V 99 350 ps
USB to DOT Skew tsk11VT = 1.5 V (0 OR 180 degrees) 1ns
VCH Jitter t
c
c-c
c1VT = 1.5 V 147 350 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH1
O utput Low C urren t IOL1
9
ICS950810
0472F—01/12/04
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Im pedance RDSP11VO = VDD*(0.5) 20 48 60 Ω
Output High Voltage VOH1IOH = -1 m A 2.4 3.28 V
Output Low Voltage VOL1IOL = 1 mA 0.08 0.4 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -33 mA
VOL @MIN = 1.95 V 30 110
VOL @MAX = 0.4 V 37 38 mA
Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 11.692 ns
Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 11.562 ns
Duty Cycle dt11VT = 1. 5 V 45 53 55 %
Jitter t
c
c-c
c1VT = 1.5 V 152 1000 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH1
O utput Low C urren t IOL1
10
ICS950810
0472F—01/12/04
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface , the protocol is set to use only "Block-Writes" from the controller . The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown abov e must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H)
AC
K
Du mmy Command C ode
AC
K
Dummy Byte Count
ACK
By te 0
AC
K
By te 1
AC
K
By te 2
ACK
By te 3
AC
K
By te 4
AC
K
By te 5
ACK
By te 6
AC
K
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H)
AC
K
Byte Coun
t
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte
4
ACK
Byte
5
ACK
Byte
6
ACK
Stop Bit
How to Read:
11
ICS950810
0472F—01/12/04
I2C Tables
P in # Name 0 1 P WD
B i t 7 - Spread Enab l ed S prea d S pe c trum Control RW OF F O N 0
Bit 6 - CPU_T(2:0)
P ower do wn m ode o ut pu t
level
0= CP U driven i n power
down
1= und riven
RW HIGH LOW 0
B it 5 35 3V 66_1/ VCH_CLK V CH/66. 66 S elect RW 66. 66 48. 00 0
Bit 4 53 CPU_STOP#* Reflec ts value of pin R Stop Active X
Bit 3 34 PCI_STOP#* Reflect s v alue of pi n a t
power up. Also can be set. R/RW Stop Active 1
B i t 2 40 FS2 F req uency S e l ec ti on RW - - X
B i t 1 55 FS1 F req uency S e l ec ti on RW - - X
B i t 0 54 FS0 F req uency S e l ec ti on RW - - X
Cont rol Func t i on
Affect ed Pin
BYTE
0T
y
pe Bit Control
P in # Nam e 0 1 PWD
Bit 7 43 MULTSEL0* Reflects value of pin R - - x
B i t 6 - CPU_T(2:0) CP U_St op m o de ou t p ut level
0= CPU driv en when s t opped
1 = undriven RW HIGH LOW 0
B i t 5 45, 44 CPUCLKT2
CPUCLKC2 Al low c ont rol of out put with
as sert ion of CPU_S TOP #. RW Not
Freerun Freerun 0
B i t 4 49, 48 CPUCLKT1
CPUCLKC1 Al low c ont rol of out put with
as sert ion of CPU_S TOP #. RW Not
Freerun Freerun 0
B i t 3 52, 51 CPUCLKT0
CPUCLKC0 Al low c ont rol of out put with
as sert ion of CPU_S TOP #. RW Not
Freerun Freerun 0
B i t 2 45, 44 CPUCLKT2
CPUCLKC2 Out put cont rol RW Dis able Enable 1
B i t 1 49, 48 CPUCLKT1
CPUCLKC1 Out put cont rol RW Dis able Enable 1
B i t 0 52, 51 CPUCLKT2
CPUCLKC2 Out put cont rol RW Dis able Enable 1
BYTE
1Control F unct i on
Affect ed Pin Type Bit Control
12
ICS950810
0472F—01/12/04
P in # Nam e 0 1 P WD
Bit 7 - - (Reserved) - - - 0
Bit 6 18 PCICLK6 Output control RW Disable Enable 1
Bit 5 17 PCICLK5 Output control RW Disable Enable 1
Bit 4 16 PCICLK4 Output control RW Disable Enable 1
Bit 3 13 PCICLK3 Output control RW Disable Enable 1
Bit 2 12 PCICLK2 Output control RW Disable Enable 1
Bit 1 11 PCICLK1 Output control RW Disable Enable 1
Bit 0 10 PCICLK0 Output control RW Disable Enable 1
BYTE
2Control F unct i on
Affect ed Pin Type Bit Cont rol
P in # Nam e 0 1 PWD
B i t 7 38 48M Hz_DOT O utpu t control RW Disabl e E na bl e 1
B i t 6 39 48M Hz_US B O ut pu t control RW Disabl e E na bl e 1
Bit 5 7 PCICLK_F2 A ll ow c ont rol of out put wit h
ass erti on of PCI_ S T OP#. RW Freerun Not
Freerun 0
Bit 4 6 PCICLK_F1 A ll ow c ont rol of out put wit h
ass erti on of PCI_ S T OP#. RW Freerun Not
Freerun 0
Bit 3 5 PCICLK_F0 A ll ow c ont rol of out put wit h
ass erti on of PCI_ S T OP#. RW Freerun Not
Freerun 0
B i t 2 7 P CI CLK_F 2 Out put c on t rol RW Disabl e E nabl e 1
B i t 1 6 P CI CLK_F 1 Out put c on t rol RW Disabl e E nabl e 1
B i t 0 5 P CI CLK_F 0 Out put c on t rol RW Disabl e E nabl e 1
Control F unct i on
BYTE
3Affect ed Pin Bit Control
Type
P in # Nam e 0 1 P WD
B i t 7 - - (Reserved ) RW Disabl e E nable 0
B i t 6 - - (Reserved ) RW Disabl e E nable 0
B i t 5 33 3V 66 _0 O utpu t control RW Disabl e E nabl e 1
B i t 4 35 3V 6 6_1/VCH_CLK O ut pu t control RW Disabl e E nable 1
B i t 3 24 3V 66 _5 O utpu t control RW Disabl e E nabl e 1
B i t 2 23 3V 66 _4 O utpu t control RW Disabl e E nabl e 1
B i t 1 22 3V 66 _3 O utpu t control RW Disabl e E nabl e 1
B i t 0 21 3V 66 _2 O utpu t control RW Disabl e E nabl e 1
Type Bit Control
Control F unct i on
Affect ed PinBYTE
4
13
ICS950810
0472F—01/12/04
Pin # Name 0 1 PWD
Bit 7 X - (Reserved) - - - 0
Bit 6 X - (Reserved) - - - 0
Bit 5 X - (Reserved) - - - 0
Bit 4 X - (Reserved) - - - 0
Bit 3 X - (Reserved) - - - 0
Bit 2 X - (Reserved) - - - 0
Bit 1 X - (Reserved) - - - 0
Bit 0 X - (Reserved) - - - 0
Affected Pin Type B i t Cont rolBYTE
5Control Function
P in # Nam e 0 1 P WD
Bit 7 X Revision ID Bit 3 (Reserved) R - - 1
Bit 6 X Revision ID Bit 2 (Reserved) R - - 1
Bit 5 X Revision ID Bit 1 (Reserved) R - - 1
Bit 4 X Revision ID Bit 0 (Reserved) R - - 1
Bit 3 X Vendor ID Bit 3 (Reserv ed) R - - 1
Bit 2 X Vendor ID Bit 2 (Reserv ed) R - - 1
Bit 1 X Vendor ID Bit 1 (Reserv ed) R - - 1
Bit 0 X Vendor ID Bit 0 (Reserv ed) R - - 1
Affect ed Pin Type Bit ControlBYTE
6Control F unct i on
14
ICS950810
0472F—01/12/04
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH cloc k, there
is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the
standard skew described below as Tpci.
3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0) Tpci
Skews at Common Transition Edges
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
PCI PCI ts
k
1VT = 1.5 V 127 500 ps
3V66 3V66 ts
k
1VT = 1.5 V 67 250 ps
3V66 to PCI S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 3.5 ns
1Guarenteed b
y
desi
g
n, not 100% tested in
p
roduction.
15
ICS950810
0472F—01/12/04
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is progr ammed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output dri ve
current v alues. The CPU will be driv en high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I2C Bit 6 of Byte 1 is prog rammed to '1' then final state of the stopped CPU signals is Low , both CPU
and CPU# outputs will not be driven.
CPU_STOP#
CPUT
CPUC
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the
de-assertion to activ e outputs is to be defined to be tetw een 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit
6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
16
ICS950810
0472F—01/12/04
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held lo w on their ne xt high to low tr ansitions. When the I2C Bit 6 of Byte 0 is progr ammed to '0' CPU clocks m ust
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
Power Down Assertion of Waveforms
0ns
PD #
CPUT 100MHz
CPUC 100MHz
3V66MHz
PCI 33MHz
USB 48MHz
REF 14.318MHz
25ns 50ns
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the pow er supply until the time that stable clocks are output from the cloc k chip . If the I2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
17
ICS950810
0472F—01/12/04
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
PCI_S TOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their ne xt high to low transition. The PCI_ST OP# setup time tsu is 10 ns, f or transitions to be recognized b y the next
rising edge.
18
ICS950810
0472F—01/12/04
300 mil SSOP Pack age
INDEX
AREA
INDEX
AREA
1 2
N
Dh x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α
0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Ordering Information
ICS950810yFLF-T
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y F LF- T
19
ICS950810
0472F—01/12/04
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (20 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α
0° 8° 0° 8°
aaa -- 0.10 -- .004
V
ARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
SYMBOL In Millimeters In Inches
COMMON DIM EN SIONS COMMON DIMENSIONS
SEE VARIATION S SEE VARIATIONS
8.10 BASIC 0.319 BASI C
0.50 BASIC 0.020 BASI C
SEE VARIATION S SEE VARIATIONS
ND mm . D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
Ordering Information
ICS950810yGLF-T
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Packag e Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y G LF- T
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Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Clock Synthesizer by Chipset Vendor > Notebook Chipsets > 950810
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950810 (Notebook Chipsets)
Description
CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets.
Market Group
PC CLOCK
Additional Info
• 3 Differential CPU Clock Pairs @ 3.3V • 7 PCI (3.3V) @ 33.3MHz • 3 PCI_F (3.3V) @ 33.3MHz • 1 USB (3.3V) @ 48MHz • 1 DOT (3.3V) @
48MHz • 1 REF (3.3V) @ 14.318MHz • 5 3V66 (3.3V) @ 66.6MHz • 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
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Related Orderable Parts
Attributes 950810CFLF 950810CFLFT 950810CGLF 950810CGLFT
Voltage 3.3 V (PVG56) 3.3 V (PVG56) 3.3 V (PAG56) 3.3 V (PAG56)
Package SSOP 56 SSOP 56 TSSOP 56 TSSOP 56
Speed NA NA NA NA
Temperature C C C C
Status Active Active Active Active
Sample Yes No Yes No
Minimum Order Quantity 104 1000 102 1000
Factory Order Increment 26 1000 34 1000
Related Documents
Type Title Size Revision Date
Datasheet 950810 Datasheet 167 KB 11/08/2006
Product Change Notice PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed 202 KB 12/13/2005
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