HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Typical Applications Features The HMC1190ALP6NE is Ideal for: Broadband Operation with no external matching High-side and Low-side LO injection Operation High Input IP3 of +24 dBm Power Conversion Gain of 8.9 dB Input P1dB of 11 dBm SSB Noise Figure of 9 dB 55 dBc Channel-to-Channel Isolation Enable/Disable Mixer and PLLVCO independently Single-ended RF input ports Maximum Phase Detector Rate: 100 MHz Low Phase Noise: -110 dBc/Hz in Band Typical PLL FOM: -230 dBc/Hz Integer Mode, -227 dBc/Hz Fractional Mode < 180 fs Integrated RMS Jitter (1 kHz to 20 MHz) LO Low Noise Floor: -165 dBc/Hz Mixer Low Noise Floor: -161 dBc/Hz Integrated VCO External VCO Input, differential LO output Exact Frequency Mode: 0 Hz Fractional Frequency Error Programmable RF Output Phase Output Phase Synchronous Frequency Changes Output Phase Synchronization LO Output Mute Function Compact Solution, 6x6 mm Leadless QFN Package * GSM & 3G & LTE/WiMAX/4G * MIMO Infrastructure Receivers * Wideband Radio Receivers * Multiband Basestations & Repeaters General Description IN AR Y DA TA SH EE T Functional Diagram M TRANSCEIVERS - Rx RFICs * M ultiband/Multi-standard Cellular BTS Diversity Receivers PR EL I The HMC1190ALP6NE is a high linearity broadband dual channel downconverting mixer with integrated PLL and VCO optimized for multi-standard receiver applications that require a compact, low power design. Integrated wideband limiting LO amplifiers enable the HMC1190ALP6NE to achieve an unprecedented RF bandwidth of 700 MHz to 3500 MHz for applications including Cellular/3G, LTE/WiMAX/4G. Unlike conventional narrow-band downconverters, the HMC1190ALP6NE supports both high-side and low-side LO injection over all RF frequencies. The RF and LO input ports are internally matched to 50 Ohms. The HMC1190ALP6NE features an integrated LO and RF baluns, enable control of IF and LO amplifiers and bias control interface to high linearity passive mixer cores. Balanced passive mixer combined with high-linearity IF amplifier architecture provides excellent LO-to-RF, LO-to-IF, and RF-to-IF isolations. Low noise figure of 9 dB, and high IIP3 of +24 dBm allow the HMC1190ALP6NE to be used in most demanding applications. External bias control pins enable optimization of already low power dissipation of 2.34 W (typical). Fast enable control interface reduces power consumption further in TDD applications. External VCO input allows the HMC1190ALP6NE to lock external VCOs, and enables cascaded LO architectures for MIMO applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase features can further phase adjust and synchronize multiple HMC1190ALP6NE's enabling scalable MIMO and beam-forming radio architectures. Additional features include configurable LO output mute function, Exact Frequency Mode that enables the HMC1190ALP6NE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing phase of the output signal that increases efficiency of digital pre-distortion loops. The HMC1190ALP6NE is housed in RoHS compliant compact 6x6 mm leadless QFN package. 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190A* PRODUCT PAGE QUICK LINKS Last Content Update: 12/18/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. * HMC1190A Material Declaration * PCN-PDN Information EVALUATION KITS * Quality And Reliability * HMC1190A Evaluation Board and Kit * Symbols and Footprints DOCUMENTATION DISCUSSIONS Data Sheet View all HMC1190A EngineerZone Discussions. * HMC1190ALP6NE: Broadband High IP3 Dual Channel DownConverter w/Fractional-N PLL & VCO, 0.7-3.8 GHz Data Sheet SAMPLE AND BUY User Guides * UG-899: Evaluating the HMC1190A Multiband Dual Channel Downconverter with Integrated PLL and VCO REFERENCE MATERIALS Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. Product Selection Guide DOCUMENT FEEDBACK * RF, Microwave, and Millimeter Wave IC Selection Guide 2017 Submit feedback for this data sheet. Quality Documentation * HMC1190ALP6NE Qualification Report This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz TA = +25C, IF Frequency = 150 MHz, LO Power is set to `3' [1], RF Input Power = -5 dBm, LOVDD=3VRVDD=DVDD3V=CHIPEN= 3.3V, VDDCP=VCS1=VCS2=VBIASIF1=VBIASIF2=LOBIAS1=LOBIAS2=VCC1=VCC2=VGATE1=VGATE2=5V unless otherwise noted. Typical Units Mixer Core RF Input Frequency Range Parameter 700 - 3800 MHz Mixer Core IF Output Frequency Range 50 - 350 MHz LSB 1900 2200 USB LSB USB 9.1 8.7 8.3 8.5 IIP3 25.2 23.4 26.3 Noise Figure (SSB) 8.6 8.7 9.1 Input 1 dB Compression 11 10.8 12.3 Conversion Gain[3] LO Leakage at RF Port -42 LSB 3500 MHz LSB USB LSB USB 8 8.1 7.2 7.4 6.1 6.2 dB 25.4 27.2 26.7 26.7 27.2 27.2 28.3 dB 9 9.8 9.3 10.6 10 12.1 12.8 12.6 13.7 13.6 15.3 15.2 dBm -52 dBm -44 -46 43.5 47.6 37.6 46.3 40.5 Channel to Channel Isolation[4] 49.1 51.9 47.2 45.6 46 +2RF-2LO Response 79.3 77.5 84.6 73.4 80.2 +3RF-3LO Response 79.2 74.8 77.1 69.1 80.5 -47 dB 38.7 50.5 46.9 59.9 53.9 dBc 44.7 44.9 44.7 40.1 40.6 dBc 80.5 77.2 73.2 70.8 71.6 dBc 75.5 72.9 76.1 81 69.7 dBc DA TA RF to IF Isolation [1] LO Power Level can be adjusted using Reg 16h. 2700 USB EE T 900 Side Band[2] SH RF Frequency [2] LSB stands for lower side band and refers to RF<LO. USB stands for upper side band and refers to RF>LO. IN AR Y [3] Balun losses at IF output ports are de-embedded. [4] RF1 input power= -5 dBm, measurement taken from IF2 output. RF2 and IF1 ports are terminated with 50 Ohms TRANSCEIVERS - Rx RFICs Table 1. Electrical Specifications Table 2. DC Power Supply Specifications Parameter Min. Typ. Max. Units. +4.5 +5 +5.5 V 200 [1] 330 556 [2] mA +3 +3.3 +3.6 V 142 [1] 193 246 [2] mA VDDIF-0.2 +5 VDDIF V 5V Supply Rails [4] (VDDCP, VCS1, VCS2, VDDLS, VBIASIF1, VBIASIF2, LOBIAS1, LOBIAS2, VCC1, VCC2) (5V) 324 330 338 mA 3.3V Supply Voltage [4] (LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF) (3.3V) 185 193 200 mA PR EL I M 5V Supply Rails (VDDCP, VCS1, VCS2, VDDLS, VBIASIF1, VBIASIF2, LOBIAS1, LOBIAS2, VCC1, VCC2) 3.3V Supply Voltage (LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF) VGATE1, VGATE2[3] [1] LO Frequency=2400 MHz, LO_MIX is enabled in single ended mode, LO_OUT is disabled. LO_MIX power setting = 0, divide ratio = 1, divider stage high gain = 0 [2] LO Frequency=2400 MHz, LO_MIX and LO_OUT are both enabled in differential mode. LO_MIX and LO_OUT power setting = 3, divide ratio = 62, divider stage high gain = 1 [3] VGATE1 and VGATE2 are obtained through resistors which are connected to VDDIF [4] LO Frequency=2400 MHz, LO_MIX is enabled in differential mode, LO_OUT is disabled. LO_MIX power setting = 3. When LO_OUT is enabled in differential mode the bias current increases by 34 mA (Typ.). For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 2 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 2. DC Power Supply Specifications (Continued) Typ. Max. Units. 139 146 152 mA VCS1 + VCS2 (5V) 2.7 3 3.1 mA VBIASIF1 + VBIASIF2 (5V) 20 21.5 23 mA VGATE1 + VGATE2 3 3 3 mA LOBIAS1 + LOBIAS2 (5V) VDDIF (5V) mA mA 0 mA 3.2 3.45 3.6 mA 1.3 1.6 1.9 mA 0 0 0 mA 4.5 4.9 5.2 mA 3.2 3.45 3.6 mA LO_OUT differential, LO_MIXER off [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 144 44.5 149 47 154 49.5 mA mA LO_OUT single-ended, LO_MIXER off [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 126 44.5 130 47 133 49.5 mA mA 154 49.5 mA mA VBIASIF1 + VBIASIF2 (5V) SH VGATE1 + VGATE2 (5V) DA TA LOVDD (3.3V) 144 44.5 LO_OUT off, LO_MIXER single-ended [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 127 44.5 130 47 132.5 49.5 mA mA LO_OUT differential, LO_MIXER differential [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 179 44.5 184 47 189 49.5 mA mA LO_OUT single-ended, LO_MIXER single-ended [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 146 44.5 150 47 154 49.5 mA mA VCCPD, VCCPS, VCCHF, DVDD3V, 3VRVDD (+3.3V) 44.5 47 49.5 mA VDDCP, VCC1, VCC2, VDDLS (5V) [1] 1 1 1 mA 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF (3.3V) [1] 5 5 5 mA M LO_OUT off, LO_MIXER differential [1] 5V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) PR EL I PLL/VCO Core Supply Currents when CHIPEN is Disabled 4 150 0 LOBIAS1 + LOBIAS2 (5V) PLL/VCO Core Supply Currents when CHIPEN is Enabled 4 143 0 VCS1 + VCS2 (5V) Mixer Core Supply Currents when IF1EN and IF2EN are Disabled 4 136 EE T LOVDD (3.3V) IN AR Y TRANSCEIVERS - Rx RFICs Parameter Mixer Core Supply Currents when IF1EN and IF2EN are Enabled Min. VDDIF (5V) 149 47 [1] LO Frequency=2400 MHz, LO_MIX and LO_OUT outputs set to maximum gain. 3 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 3. PLL & VCO Specifications Conditions Min. Typ. Max. Units Logic High 1.2 V Logic Low Input Current Input Capacitance 0.6 V 1 uA 2 EE T LO Output Characteristics 50 4100 MHz VCO Frequency at PLL Input 2000 4100 MHz VCO Fundamental Frequency 2000 4100 MHz VCO Output Divider VCO Output Divider Range 1, 2, 4, ... 60, 62 SH LO Output Frequency pF 1 62 Integer 16 524287 Fractional 20 524283 Fractional Mode DC 100 MHz Integer Mode DC 100 MHz DA TA PLL RF Divider Characteristics 19-Bit N Divider Range Phase Detector (PD) IN AR Y PD Frequency Harmonics fo Mode at 4000 MHz 2nd / 3rd / 4th VCO Output Divider VCO RF Divider Range 1,2,4,6,8,... 62 M PLL RF Divider Characteristics PR EL I 19-Bit N-Divider Range (Integer) 19-Bit N-Divider Range (Fractional) -30/-22/-32 TRANSCEIVERS - Rx RFICs Parameter Logic Inputs dBc 1 62 Max = 219 - 1 16 524,287 Fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 REF Input Characteristics Max Ref Input Frequency Ref Input Voltage AC Coupled 1 2 Ref Input Capacitance 14-\Bit R-Divider Range 1 350 MHz 3.3 Vpp 5 pF 16,383 VCO Open Loop Phase Noise at fo @ 4 GHz 10 kHz Offset -78 dBc/Hz 100 kHz Offset -108 dBc/Hz 1 MHz Offset -134.5 dBc/Hz 10 MHz Offset -156 dBc/Hz 100 MHz Offset -167 dBc/Hz For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 4 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 3. PLL & VCO Specifications (Continued) Parameter Conditions Min. Typ. Max. Units 10 kHz Offset 100 kHz Offset -83 dBc/Hz -113 dBc/Hz 1 MHz Offset -139.5 dBc/Hz 10 MHz Offset -165.5 dBc/Hz 100 MHz Offset -167 dBc/Hz Normalized to 1 Hz Floor Fractional Mode Normalized to 1 Hz Flicker (Both Modes) Normalized to 1 Hz VCO Characteristics VCO Tuning Sensitivity at 3862 MHz Measured at 2.5 V VCO Tuning Sensitivity at 3643 MHz Measured at 2.5 V VCO Tuning Sensitivity at 3044 MHz VCO Tuning Sensitivity at 2558 MHz VCO Tuning Sensitivity at 2129 MHz VCO Supply Pushing -230 dBc/Hz -227 dBc/Hz -268 dBc/Hz 15 MHz/V 14.5 MHz/V 16.2 MHz/V Measured at 2.5 V 14.6 MHz/V Measured at 2.5 V 15.4 MHz/V Measured at 2.5 V 14.8 MHz/V Measured at 2.5 V 2 MHz/V DA TA VCO Tuning Sensitivity at 3491 MHz SH Floor Integer Mode EE T Figure of Merit Measured at 2.5 V IN AR Y TRANSCEIVERS - Rx RFICs VCO Open Loop Phase Noise at fo @ 3 GHz/2 = 1.5 GHz Table 4. Enable/Disable Settling Time Specifications PR EL I Disable Settling Time Conditions M Parameter Enable Settling Time 5 Min. Typ. Max. Units Mixer Core Enabled 140 ns Mixer Core Disabled 110 ns For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 1. Low Side LO Conversion Gain vs. VGATE [1] [2] Figure 2. Low Side LO Input IP3 vs. VGATE [1] 12 29 10 27 IIP3 (dBm) 8 6 4 25 23 21 0 0.7 17 1.1 1.5 1.9 2.2 2.6 3 3.4 15 0.7 3.8 1.1 2.2 SH 4.8V 5V 2.6 3 3.4 3.8 4.9V 5V Figure 4. High Side LO Input IP3 vs. VGATE [1] 31 12 29 10 4 1.1 1.5 1.9 2.2 2.6 3 3.4 M 0 0.7 IN AR Y 6 IIP3 (dBm) 27 8 2 25 23 21 19 17 15 0.7 3.8 1.1 1.5 4.9V PR EL I 4.8V 16 2.6 3 3.4 3.8 4.9V 5V Figure 6. High Side LO Noise Figure vs. VGATE [1] 18 16 NOISE FIGURE (dB) 14 12 10 8 6 4 0.7 2.2 4.8V 5V Figure 5. Low Side LO Noise Figure vs. VGATE [1] 18 1.9 FREQUENCY (GHz) FREQUENCY (GHz) NOISE FIGURE (dB) 1.9 DA TA 4.9V Figure 3. High Side LO Conversion Gain vs. VGATE [1] [2] CONVERSION GAIN (dB) 1.5 FREQUENCY (GHz) FREQUENCY (GHz) 4.8V EE T 19 2 TRANSCEIVERS - Rx RFICs 31 14 12 10 8 6 1.1 1.5 1.9 2.3 2.7 3.1 3.5 4 0.7 1.1 FREQUENCY (GHz) 4.8V 4.9V 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) 5V 4.8V 4.9V 5V [1] VGATE is bias voltage for passive mixer cores (VGATE1 and VGATE2 pins). Refer to pin description table. [2] Balun losses at IF output ports are de-embedded. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 6 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 7. Conversion Gain vs. High Side LO & Low Side LO [1][2] Figure 8. Input IP3 vs. High Side LO & Low Side LO[2] 29 10 27 8 25 6 23 21 4 19 0 0.7 17 1.1 1.5 1.9 2.2 2.6 3 3.4 15 0.7 3.8 1.1 1.5 FREQUENCY (GHz) EE T CONVERSION GAIN (dB) 31 2 2.2 2.6 3 SH Low Side LO 3.4 3.8 Low Side LO DA TA High Side LO Figure 9. RF/IF Isolation vs. Temperature[2][3] 80 Figure 10. LO Leakage vs. Frequency[2][3] 0 70 -20 50 40 1.1 1.5 1.9 2.2 2.6 3 3.4 -40 -60 -80 0.7 3.8 1.1 M 20 0.7 IN AR Y 60 30 1.5 FREQUENCY (GHz) 2.2 2.6 3 At IF PR EL I 12 1.9 3.4 3.8 FREQUENCY (GHz) Figure 11. Low Side LO Conversion Gain vs. LO Drive [1][2] At RF Figure 12. Low Side LO Input IP3 vs. LO Drive[2] 31 29 10 27 8 IIP3 (dBm) CONVERSION GAIN (dB) 1.9 FREQUENCY (GHz) High Side LO ISOLATION (dBc) TRANSCEIVERS - Rx RFICs 12 6 4 25 23 21 19 2 0 0.7 17 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 15 0.7 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 FREQUENCY (GHz) FREQUENCY (GHz) LO Power Setting 0 LO Power Setting 1 LO Power Setting 2 LO Power Setting 3 LO Power Setting 0 LO Power Setting 1 LO Power Setting 2 LO Power Setting 3 [1] Balun losses at IF output ports are de-embedded. [3] For low side LO [2] VGATE=5V 7 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 14. +3RF -3LO Response vs. Frequency over Temperature[1][2][3] Figure 13. +2RF -2LO Response vs. Frequency over Temperature[1][2][3] 70 60 50 40 0.7 1.1 1.5 1.9 2.2 2.6 3 3.4 80 70 60 50 40 0.7 3.8 1.1 EE T 80 1.5 0 -20 -25 1.2 1.8 2.3 2.9 3.4 M 0.7 RETURN LOSS (dB) -15 -30 3.4 3.8 -5 -10 -15 -20 0.1 4 0.2 0.3 0.4 FREQUENCY (GHz) +85C PR EL I +25C -40C +25C 14 P1dB (dBm) 14 12 10 8 8 2.3 2.7 3.1 3.5 6 0.7 1.1 1.5 FREQUENCY (GHz) +25C +85C 0.8 0.9 1 +85C -40C 12 10 1.9 0.7 18 16 1.5 0.6 Figure 18. Low Side LO Input P1dB vs. Frequency over Temperature[3] 16 1.1 0.5 FREQUENCY (GHz) Figure 17. High Side LO Input P1dB vs. Frequency over Temperature[3] P1dB (dBm) 3 Figure 16. IF Output Return Loss vs. Frequency over Temperature [3][4] IN AR Y RETURN LOSS (dB) -5 6 0.7 2.6 0 -10 18 2.2 DA TA Figure 15. RF Input Return Loss vs. Frequency over Temperature[3][4] -35 0.1 1.9 FREQUENCY (GHz) SH FREQUENCY (GHz) TRANSCEIVERS - Rx RFICs 90 +3RF-3LO RESPONSE (dBc) +2RF-2LO RESPONSE (dBc) 90 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) -40C +25C +85C [1] Balun losses at IF output ports are de-embedded. [3] VGATE=5V [2] Low side LO [4] LO input Frequency = 1900MHz, LO power setting is 3. -40C For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 8 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 19. Low Side LO Conversion Gain vs. Frequency @ VGATE=5V [1][2] Figure 20. Low Side LO Input IP3 vs. Frequency @ VGATE=5V[2] 31 29 10 27 8 25 23 6 21 4 0 0,7 17 1,1 1,5 1,9 2,2 2,6 3 3,4 15 0,7 3,8 1,1 1,5 1,9 2,2 2,6 3 3,4 3,8 FREQUENCY (GHz) FREQUENCY (GHz) +25C -40C Figure 21. High Side LO Conversion Gain vs. Frequency @ VGATE=5V [1][2] 12 +85C SH +85C -40C Figure 22. High Side LO Input IP3 vs. Frequency @ VGATE=5V[2] DA TA +25C EE T 19 2 31 29 10 27 8 6 4 2 1,1 1,5 1,9 2,2 2,6 3 3,4 M 0 0,7 25 IN AR Y TRANSCEIVERS - Rx RFICs 12 23 21 19 17 15 0,7 3,8 1,1 1,5 FREQUENCY (GHz) +85C PR EL I +25C 3 3,4 3,8 +85C -40C 18 16 14 12 10 8 6 4 0.7 2,6 Figure 24. High Side LO Noise Figure vs. Temperature @ VGATE=5V NOISE FIGURE (dB) NOISE FIGURE (dB) 16 2,2 +25C -40C Figure 23. Low Side LO Noise Figure vs. Temperature @ VGATE=5V 18 1,9 FREQUENCY (GHz) 14 12 10 8 6 1.1 1.5 1.9 2.3 2.7 3.1 FREQUENCY (GHz) 3.5 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) [1] Balun losses at IF output ports are de-embedded. [2] At room temperature 9 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 25. Low Side LO Conversion Gain vs. Frequency @ VGATE=4.9V [1][2] Figure 26. Low Side LO Input IP3 vs. Frequency @ VGATE=4.9V[2] 29 10 27 8 25 23 6 21 4 0 0,7 17 1,1 1,5 1,9 2,2 2,6 3 3,4 15 0,7 3,8 1,1 1,5 1,9 2,2 2,6 3 3,4 3,8 FREQUENCY (GHz) FREQUENCY (GHz) +25C -40C Figure 27. High Side LO Conversion Gain vs. Frequency @ VGATE=4.9V [1][2] 12 +85C SH +85C -40C Figure 28. High Side LO Input IP3 vs. Frequency @ VGATE=4.9V[2] DA TA +25C EE T 19 2 31 29 10 27 6 4 2 1,1 1,5 1,9 2,2 2,6 3 3,4 M 0 0,7 25 IN AR Y 8 23 21 19 17 15 0,7 3,8 1,1 1,5 FREQUENCY (GHz) +85C PR EL I +25C 2,6 3 3,4 3,8 +85C -40C Figure 30. High Side LO Noise Figure vs. Temperature @ VGATE=4.9V 18 16 14 12 10 8 6 4 0.7 2,2 +25C -40C NOISE FIGURE (dB) NOISE FIGURE (dB) 16 1,9 FREQUENCY (GHz) Figure 29. Low Side LO Noise Figure vs. Temperature @ VGATE=4.9V 18 TRANSCEIVERS - Rx RFICs 31 12 14 12 10 8 6 1.1 1.5 1.9 2.3 2.7 3.1 FREQUENCY (GHz) 3.5 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) [1] Balun losses at IF output ports are de-embedded. [2] At room temperature For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 10 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 31. Low Side LO Conversion Gain vs. Frequency @ VGATE=4.8V [1][2] Figure 32. Low Side LO Input IP3 vs. Frequency @ VGATE=4.8V[2] 31 29 10 27 8 25 6 23 21 4 0 0,7 17 1,1 1,5 1,9 2,2 2,6 3 3,4 15 0,7 3,8 1,1 1,5 FREQUENCY (GHz) 1,9 2,2 2,6 3 3,4 3,8 FREQUENCY (GHz) -40C Figure 33. High Side LO Conversion Gain vs. Frequency @ VGATE=4.8V [1][2] 12 SH +85C +25C +85C -40C Figure 34. High Side LO Input IP3 vs. Frequency @ VGATE=4.8V[2] DA TA +25C EE T 19 2 31 29 10 27 8 6 4 2 1,1 1,5 1,9 2,2 2,6 3 3,4 M 0 0,7 25 IN AR Y TRANSCEIVERS - Rx RFICs 12 23 21 19 17 15 0,7 3,8 1,1 1,5 FREQUENCY (GHz) +85C PR EL I +25C -40C 3 3,4 3,8 +85C -40C 18 16 14 12 10 8 6 4 0.7 2,6 Figure 36. High Side LO Noise Figure vs. Temperature @ VGATE=4.8V NOISE FIGURE (dB) NOISE FIGURE (dB) 16 2,2 +25C Figure 35. Low Side LO Noise Figure vs. Temperature @ VGATE=4.8V 18 1,9 FREQUENCY (GHz) 14 12 10 8 6 1.1 1.5 1.9 2.3 2.7 3.1 FREQUENCY (GHz) 3.5 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) [1] Balun losses at IF output ports are de-embedded. [2] At room temperature 11 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 70 70 65 65 60 60 55 50 45 55 50 45 High Side LO 35 35 30 1.1 1.5 1.9 2.2 2.6 3 3.4 0.7 3.8 1.1 1.5 2.6 3 SH 3.4 3.8 IF=50MHz IF=100MHz IF=150MHz IF=200MHz Figure 40. Low Side LO Input IP3 Mismatch @ VGATE=5V 5 IN AR Y 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 IIP3 MISMATCH (dBm) 4 0.6 M CONVERSION GAIN MISMATCH (dB) 1 0.8 3 2 1 0 -1 -2 -3 -4 -5 0.7 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 FREQUENCY (GHz) PR EL I FREQUENCY (GHz) Figure 41. Low Side LO Conversion Gain vs. VGATE=Vdd[1] 12 2.2 DA TA Low Side LO Figure 39. Low Side LO Conversion Gain Mismatch @ VGATE=5V [1] -1 0.7 1.9 FREQUENCY (GHz) FREQUENCY (GHz) High Side LO EE T 40 40 30 0.7 Low Side LO TRANSCEIVERS - Rx RFICs Figure 38. Channel to Channel Isolation vs. IF Frequency ISOLATION (dB) ISOLATION (dB) Figure 37. Channel to Channel Isolation vs. Frequency Figure 42. Low Side LO Input IP3 vs. VGATE=Vdd 31 29 10 27 8 25 23 6 2 0 0.7 21 VDDIF=4.5V, LOVDD=3V VDDIF=4.75V, LOVDD=3.15V VDDIF=5V, LOVDD=3.3V VDDIF=5.25V, LOVDD=3.45V VDDIF=5.5V, LOVDD=3.6V 4 1.1 1.5 1.9 2.2 2.6 VDDIF=4.5V, LOVDD=3V VDDIF=4.75V, LOVDD=3.15V VDDIF=5V, LOVDD=3.3V VDDIF=5.25V, LOVDD=3.45V VDDIF=5.5V, LOVDD=3.6V 19 17 3 3.4 FREQUENCY (GHz) 3.8 15 0.7 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 FREQUENCY (GHz) [1] Balun losses at IF output ports are de-embedded. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 12 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 43. Conversion Gain vs. IF Frequency @ RF=900 MHz, VGATE=5V [1] Figure 44. IIP3 vs. IF Frequency @ RF=900 MHz, VGATE=5V 30 10 28 8 IIP3 (dBm) 6 4 26 24 22 20 EE T CONVERSION GAIN (dB) 32 2 18 0 16 50 100 150 200 50 100 FREQUENCY (MHz) +85C -40C +25C 200 +85C -40C Figure 46. IIP3 vs. IF Frequency @ RF=1900 MHz, VGATE=5V DA TA Figure 45. Conversion Gain vs. IF Frequency @ RF=1900 MHz, VGATE=5V [1] 12 32 30 10 4 0 100 150 M 50 IN AR Y 6 IIP3 (dBm) 28 8 2 26 24 22 20 18 16 200 50 100 FREQUENCY (MHz) +85C PR EL I +25C 12 150 200 FREQUENCY (MHz) -40C Figure 47. Conversion Gain vs. IF Frequency @ RF=2400 MHz, VGATE=5V [1] +25C +85C -40C Figure 48. IIP3 vs. IF Frequency @ RF=2400 MHz, VGATE=5V 32 30 10 28 8 IIP3 (dBm) CONVERSION GAIN (dB) 150 FREQUENCY (MHz) SH +25C CONVERSION GAIN (dB) TRANSCEIVERS - Rx RFICs 12 6 4 26 24 22 20 2 18 0 16 50 100 150 200 50 100 FREQUENCY (MHz) +25C +85C 150 200 FREQUENCY (MHz) -40C +25C +85C -40C [1] Balun losses at IF output ports are de-embedded. 13 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 50. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @3600 MHz with various divider ratios [1] Figure 49. Auxiliary LO Output, Open Loop Phase Noise @ 3600 MHz -40 -100 PHASE NOISE(dBc/Hz) -80 -120 -100 -120 -140 -140 -160 -160 -180 -180 1 10 100 1000 10000 100000 1 10 EE T PHASE NOISE(dBc/Hz) -60 100 SH Div1 Div2 Div4 10000 100000 Div8 Div16 Div32 Div62 Figure 52. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @4100 MHz with various divider ratios [1] DA TA Figure 51. Auxiliary LO Output, Open Loop Phase Noise @ 4100 MHz -40 -80 -60 -100 -120 -140 -160 -180 10 100 1000 10000 M 1 PHASE NOISE(dBc/Hz) -100 -80 -120 IN AR Y PHASE NOISE(dBc/Hz) 1000 OFFSET (KHz) OFFSET (KHz) TRANSCEIVERS - Rx RFICs -80 -140 -160 -180 100000 1 10 100 1000 10000 100000 OFFSET (KHz) OFFSET (KHz) PR EL I Div1 Div2 Div4 Div8 Div16 Div32 Div62 Figure 53. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @ 3300 MHz with various divider ratios [2] -80 PHASE NOISE(dBc/Hz) -100 -120 -140 -160 -180 1 10 100 1000 10000 100000 OFFSET (KHz) Div1 Div2 Div4 Div8 Div16 Div32 Div62 [1] Using 122.88 MHz clock input, 61.44 MHz PFD, 2.5 mA CP, 174 uA Leakage. [2] Using 100 MHz clock input, 50MHz PFD, 2.5 mA CP, 174 uA Leakage For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 14 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz -100 -60 -110 -100 -120 -140 -160 100 kHz Offset -120 -130 1 MHz Offset -140 -150 -160 EE T -80 PHASE NOISE (dBc/Hz) PHASE NOISE(dBc/Hz) Figure 55. Auxiliary LO Output, Open Loop Phase Noise vs. Temperature -40 -170 -180 100 MHz Offset -180 1 10 100 1000 10000 100000 30 100 SH 3044 MHz 2558 MHz 2129.4 MHz 27 C Figure 56. Auxiliary LO Output Power vs Temperature [1] 4000 -40 C 85 C Figure 57. Integrated RMS Jitter [2] 10 IN AR Y 5 0 -5 -10 100 INTEGRATED JITTER (ps) 0.3 15 0.25 0.2 0.15 0.1 0.05 0 1000 0 500 1000 OUTPUT FREQUENCY (MHz) M 85C -40C 70 60 2000 2500 3000 3500 4000 -40 C 27 C 85 C Figure 59. Reference Input Sensitivity, Square Wave, 50 [3] Figure 58. Typical VCO Sensitivity 80 1500 OUTPUT FREQUENCY (MHz) PR EL I 27C -220 -222 -224 50 FOM (dBc/Hz) KVCO (MHz/V) 1000 DA TA 3862.4 MHz 3643.33 MHz 3491.74 MHz 40 30 -226 -228 -230 20 -232 10 0 300 FREQUENCY (MHz) OFFSET (KHz) OUTPUT POWER (dBm) TRANSCEIVERS - Rx RFICs Figure 54. Auxiliary LO Output, Open Loop Phase Noise vs. Frequency 0 1 2 3 4 5 TUNING VOLTAGE (V) ML core, Tuning Cap 15 H core, Tuning Cap 7 MH core, Tuning Cap 7 CL core, Tuning Cap 15 L core, Tuning Cap 15 CH core, Tuning Cap 15 -234 -15 -12 -9 -6 -3 0 3 REFERENCE POWER (dBm) 14 MHz Square Wave 25 MHz Square Wave 50 MHz Square Wave 100 MHz Square Wave [1] Both Aux. LO and MOD LO Gain Set to `3' (Max Level), both Aux. LO and MOD LO Buffer Enabled, measured from Auxiliary LO Port. [2] RMS Jitter data is measured in fractional mode using 50 MHz reference frequency, from 1 kHz to 100 MHz integration bandwidth. [3] Measured from a 50 source with a 100 external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage. 15 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 60. Reference Input Sensitivity, Sinusoid Wave, 50 [1] Figure 61. Figure of Merit for PLL/VCO FOM (dBc/Hz) -210 -215 -220 -225 -230 -15 -10 -5 0 Typ FOM vs Offset -220 FOM Floor FOM 1/f Noise -230 -240 2 10 -235 -20 -210 5 50 MHz sin 100 MHz sin 10 4 10 5 10 6 Figure 63. Fractional-N Spurious Performance @ 2646.96 MHz Exact Frequency Mode OFF [2] DA TA Figure 62. Fractional-N Spurious Performance @ 2646.96 MHz Exact Frequency Mode ON [2] -40 -40 -60 -120 -140 -160 10 100 1000 10000 100000 M 1 IN AR Y -80 -100 PHASE NOISE(dBc/Hz) -60 -80 -100 -120 -140 -160 -180 1 10 100 Figure 64. Forward Transmission Gain [3] 100000 -40 S21 EXT-IN LO OUT DIFFERENTIAL OUTPUT 15 10000 Figure 65. Closed Loop Phase Noise With External VCO HMC384LP4E @ 2200 MHz -60 PHASE NOISE(dBc/Hz) 20 1000 OFFSET (KHz) PR EL I OFFSET (KHz) FORWARD TRANMISSION GAIN (dB) 3 SH 14 MHz sin 25 MHz sin PHASE NOISE(dBc/Hz) 10 OFFSET (Hz) REFERENCE POWER (dBm) -180 EE T NORMALIZED PHASE NOISE (dBc/Hz) -205 TRANSCEIVERS - Rx RFICs -200 -200 -80 -100 10 -120 5 -140 0 S21 EXT-IN LO OUT SINGLE-ENDED OUTPUT -160 -180 -5 400 800 1200 1600 2000 OUTPUT FREQUENCY (MHz) 2400 2800 1 10 100 1000 10000 OFFSET (KHz) [1] Measured from a 50 source with a 100 external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage. [2] 122.88 MHz clock input, PFD = 61.44 MHz, Channel Spacing = 240 KHz. [3] S21 from Ext_VCO (pin 43, 44) in and LO (pin32, 33) out. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 16 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 67. Auxiliary LO Single Ended Output Return Loss 0 0 -5 -5 -10 -15 -20 -25 -10 -15 -20 -25 -30 -30 100 1000 EE T RETURN LOSS (dB) RETURN LOSS (dB) 100 1000 OUTPUT FREQUENCY (MHz) DA TA SH OUTPUT FREQUENCY (MHz) Table 5. Loop Filter Configuration Loop Filter BW (kHz) C2 (nF) C3 (pF) 180 6.8 47 C4 (pF) R2 (k) R3 (k) R4 (k) 47 2.2 1 Loop Filter Design 1 PR EL I M 156 C1 (pF) IN AR Y TRANSCEIVERS - Rx RFICs Figure 66. Auxiliary LO Differential Output Return Loss 17 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 6. Harmonics of LO Table 7. MxN Spurious @ IF Port nLO Spur @ RF Port 1 2 3 4 mRF 0 1 2 3 4 0.7 -65 -45 -67 -63 0 xx -44 -52 -52 -55 1.1 -80 -55 -64 -67 1 -49 0 -44 -17 -52 1.5 -59 -58 -65 -62 2 -87 -45 -72 -50 -80 1.9 -59 -54 -72 -64 3 -88 -62 -88 -71 -87 -63 4 -85 -85 -88 -88 -87 -60 -59 -73 2.7 -59 -58 -82 -55 3.1 -60 -58 -77 -48 3.5 -53 -63 -73 -48 RF Freq. = 0.9 GHz @-5 dBm LO Freq. = 0.8 GHz @ Max. level All values in dBc below IF power level (1RF - 1LO). EE T 2.3 Table 8. MxN Spurious @ IF Port DA TA SH LO = Max. level All values in dBm measured at RF port. Table 9. MxN Spurious @ IF Port nLO mRF 0 1 2 3 4 0 xxx -44 -49 -64 -49 1 -54 0 -43 2 -83 -49 -76 3 -87 -72 -86 4 -83 -83 -85 0 1 2 3 4 0 xxx -44 -47 -65 -53 -65 1 -58 0 -46 -40 -68 -84 2 -80 -60 -75 -67 -85 -88 -85 3 -82 -82 -86 -83 -85 -85 -87 4 -84 -82 -85 -85 -87 IN AR Y -28 -57 M RF Freq. = 1.9 GHz @-5 dBm LO Freq. = 1.8 GHz @ Max. level All values in dBc below IF power level (1RF - 1LO). PR EL I nLO mRF TRANSCEIVERS - Rx RFICs nLO LO Freq. (GHz) RF Freq. = 2.5 GHz @-5 dBm LO Freq. = 2.4 GHz @Max. level All values in dBc below IF power level (1RF - 1LO). Table 10. Truth Table [1] CHIPEN (V) PLL/VCO LOW OFF HIGH ON [1] IF and LO amplifiers can be disabled through SPI bus. See Enabling/Disabling Mixer Features application section. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 18 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Recommended Operating Conditions 6V VGATE1,2, VDDCP, VCS1, VCS2, LOVDD -0.3V to +5.5V 3VRVDD, DVDD3V -0.3V to +3.6V Max. Channel Temperature 150C Thermal Resistance (channel to ground paddle) 3.3C/W Storage Temperature -65 to 150C Operating Temperature -40 to +85C ESD Sensitivity (HBM) Class 1B ESD Sensitivity (FICDM) Class C1 5.0 V LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF +3.3 V Operating Temperature -40 to +85C EE T VBIASIF1,2, LOVDD VDDCP, VCS1, VCS2, VBIASIF1, VBIASIF2,LOBIAS1,LOBIAS2,VCC1,VCC2,VGATE1,VGATE2,VDDLS SH +20 dBm DA TA RF Input Power (VBIASIF1,2= +5V, LOVDD=3.0V) IN AR Y Outline Drawing PR EL I M TRANSCEIVERS - Rx RFICs Absolute Maximum Ratings NOTES: 1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. 2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. 3. LEAD AND GROUND PADDLE PLATING: NiPdAu. 4. DIMENSIONS ARE IN INCHES [MILLIMETERS]. 5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE. 6. CHARACTERS TO BE HELVETICA MEDIUM, .025 HIGH, WHITE INK, OR LASER MARK LOCATED APPROX. AS SHOWN. 7. PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.25mm MAX. 8. PACKAGE WARP SHALL NOT EXCEED 0.05mm 9. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. 10. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. Package Information Part Number Package Body Material Lead Finish MSL Rating [2] Package Marking [1] HMC1190ALP6NE RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn MSL1 H1190A XXXX [1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260 C 19 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Pin Descriptions 1 VDDCP Power Supply for charge pump analog section. 2 BIAS External bypass decoupling for precision bias circuits. 3,4 CP1,CP2 Charge Pump Outputs. 5 3VRVDD Reference supply, 3.3 V nominal. 6 XREFP Reference Input. DC bias is generated internally. Normally AC coupled externally. 7 DVDD3V DC Power Supply for Digital (CMOS) Circuitry, 3.3 V nominal. 8,23 VCS1, VCS2 Bias control pins for IF amplifiers. Connect to 5V supply through 590 Ohms resistors. Refer to application section for proper values of resistors to adjust IF amplifier current. 9 IF1N IF1P IF2P SH 10 21 Description Differential IF outputs. Connect to 5V supply through choke inductors. See application circuit. 22 IF2N 11, 20 VBIASIF1, VBIASIF2 12, 19 VGATE1, VGATE2 Bias pins for mixer cores. Set from 4.7V to 5.0V for operating frequency band. 13, 18 RF1, RF2 RF input pins of the mixer, internally matched to 50 Ohms. RF input pins require off chip DC blocking capacitors. See application circuit. 14, 17 LOBIAS2, LOBIAS1 Bias control pins for LO Amplifiers. Connect to 5V supply through 270 Ohms resistors. Refer to application section for proper values of resistors to adjust LO amplifier current. 15,24 RSV 16 LOVDD CHIP_EN LO_N 27 LO_P 31 32 DA TA Chip Enable. Connect to logic high for normal operation. Negative LO output used for single-ended, differential, or dual output mode. Positive LO output used for differential or dual outputs only. While it can drive a separate load from LO_N, it cannot be used when LO_N is disabled. PR EL I 29 3V bias supply for LO Drive stages. Refer to application circuit for appropriate filtering and bias generation information. M 25 30 IN AR Y Reserved for internal use.Should be left floating. 26 28 Supply voltage pin for IF amplifier's bias circuits. Connect to 5V supply through filtering. TRANSCEIVERS - Rx RFICs Function EE T Pin Number VCC1 VCO Analog supply1, 5.0V nominal. VCC2 VCO Analog Supply 2, 5.0V nominal. VTUNE VCO Varactor. Tuning Port Input. SEN PLL Serial Port Enable (CMOS) Logic Input. SDI PLL Serial Port Data (CMOS) Logic Input. 33 SCK PLL Serial Port Clock (CMOS) Logic Input. 34 LD/SDO Lock Detect, or Serial Data, or General Purpose (CMOS) Logic Output (GPO). 35 EXT_VCO_N External VCO negative input 36 EXT_VCO_P External VCO positive input. 37 VCCHF Analog supply, 3.3 V nominal 38 VCCPS Analog supply, Prescaler, 3.3 V nominal 39 VCCPD Analog supply, Phase Detector, 3.3 V nominal 40 VDDLS Analog supply, Charge Pump, 5.0 V nominal For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 20 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz IN AR Y DA TA SH EE T TRANSCEIVERS - Rx RFICs Evaluation PCB PR EL I M The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. Evaluation PCB Schematic To view this Evaluation PCB Schematic please visit www.hittite.com and choose HMC1190ALP6NE from the "Search by Part Number" pull down menu to view the product splash page. Evaluation Order Information Item Contents Part Number Evaluation PCB Only HMC1190ALP6NE Evaluation PCB EV1HMC1190ALP6N [1] Evaluation Kit HMC1190ALP6NE Evaluation PCB USB Interface Board 6' USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software, Hittite PLL Design Software) EK1HMC1190ALP6N [2] [1] Reference this number when ordering Evaluation PCB Only [2] Reference this number when ordering an HMC1190ALP6NE Evaluation KIt 21 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 1.0 Theory of Operation Figure 66. HMC1190ALP6NE PLL VCO Block Diagram 1.1 PLL Overview TRANSCEIVERS - Rx RFICs IN AR Y DA TA SH EE T The block diagram of HMC1190ALP6NE PLL with Integrated VCO is shown in Figure 66 PR EL I M The PLL divides down the VCO output to the desired comparison frequency via the N-divider (integer value set in Reg 03h, fractional value set in Reg 04h), compares the divided VCO signal to the divided reference signal (reference divider set in Reg 02h) in the Phase Detector (PD), and drives the VCO tuning voltage via the Charge Pump (CP) (configured in Reg 09h) to the VCO subsystem. Some of the additional PLL subsystem functions include: * Delta Sigma configuration (Reg 06h) * Exact Frequency Mode (Configured in Reg 0Ch, Reg 06h,Reg 03h, and Reg 04h) * Lock Detect (LD) Configuration (Reg 07h to configure LD, and Reg 0Fh to configure LD_SDO output pin) * External CEN pin used as hardware enable pin. Typically, only writes to the divider registers (integer part Reg 03h, fractional part Reg 04h,VCO Divide Ratio part Reg 04h) are required for HMC1190ALP6NE output frequency changes. Divider registers of the PLL (Reg 03h, and Reg 04h), set the fundamental frequency (2050 MHz to 4100 MHz) of the VCO. Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the appropriate fundamental VCO frequency (2050 MHz to 4100 MHz) by programming N divider (Reg 03h, and Reg 04h), and programming the output divider (divide by 1/2/4/6.../60/62, programmed in Reg 16h) in the VCO register. For detailed frequency tuning information and example, please see "1.3.7 Frequency Tuning" section. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 22 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz VCO Overview The VCO consists of a capacitor switched step tuned VCO and an output stage. In typical operation, the VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL AutoCal state machine if AutoCal is enabled (Reg 0Ah[11] = 0, see section "1.2.1 VCO Calibration" for more information). The VCO tunes to the fundamental frequency (2050 MHz to 4100 MHz), and is locked by the CP output from the PLL subsystem. The VCO controls the output stage of the HMC1190ALP6NE enabling configuration of: * Mute when unlock (Reg 17h[7]) EE T * * * VCO Output divider settings configured in Reg 16h (divide by 2/4/6...60/62 to generate frequencies from 33 MHz to 2050 MHz, or divide by 1 to generate fundamental frequencies between 2050 MHz and 4100 MHz) Output gain settings (Reg 16h[7:6], Reg 16h[9:8]) Single-ended or differential output operation (Reg 17h[9:8]) Always Mute (Reg 16h[5:0]) SH * VCO Calibration 1.1.1.1 VCO Auto-Calibration (AutoCal) DA TA 1.1.1 The HMC1190ALP6NE uses a step tuned type VCO. A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or `stepped' by switching in/out VCO tank capacitors. A step tuned VCO allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the HMC1190ALP6NE's charge pump. This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). IN AR Y TRANSCEIVERS - Rx RFICs 1.1 PR EL I M The VCO switches are normally controlled automatically by the HMC1190ALP6NE using the AutoCalibration feature. The Auto-Calibration feature is implemented in the internal state machine. It manages the selection of the VCO sub-band (capacitor selection) when a new frequency is programmed. The VCO switches may also be controlled directly via register Reg 15h for testing or for other special purpose operation. To use a step tuned VCO in a closed loop, the VCO must be calibrated such that the HMC1190ALP6NE knows which switch position on the VCO is optimum for the desired output frequency. The HMC1190ALP6NE supports Auto-Calibration (AutoCal) of the step tuned VCO. The AutoCal fixes the VCO tuning voltage at the optimum mid-point of the charge pump output, then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency. This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor. A typical tuning curve for a step tuned VCO is shown in Figure 67.Note how the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency hopping. 23 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 3 2 1 fmin fmax 0 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 VCO FREQUENCY(MHz) SH Calibrated at 85C, Measured at 85C Calibrated at 85C, Measured at -40C Calibrated at -40C, Measured at -40C Calibrated at -40C, Measured at 85C Calibrated at 27C, Measured at 27C Figure 67.Typical VCO Tuning Voltage After Calibration DA TA The calibration is normally run automatically once for every change of frequency. This ensures optimum selection of VCO switch settings vs. time and temperature. The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine. The accuracy required in the calibration affects the amount of time required to tune the VCO. The calibration routine searches for the best step setting that locks the VCO at the current programmed frequency, and ensures that the VCO will stay locked and perform well over it's full temperature range without additional calibration, regardless of the temperature that the VCO was calibrated at. IN AR Y Auto-Calibration can also be disabled allowing manual VCO tuning. Refer to section 1.2.1.5 for a description of manual tuning. TRANSCEIVERS - Rx RFICs 4 EE T TUNE VOLTAGE AFTER CALIBRATION (V) 5 1.1.1.2 Auto-reLock on Lock Detect Failure M It is possible by setting Reg 0Ah[17] to have the VCO subsystem automatically re-run the calibration routine and re-lock itself if Lock Detect indicates an unlocked condition for any reason. With this option the system will attempt to re-Lock only once. PR EL I 1.1.1.3 VCO AutoCal on Frequency Change Assuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change is requested. If it is desired to rerun the AutoCal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency. 1.1.1.4 VCO AutoCal Time & Accuracy The VCO frequency is counted for Tmmt, the period of a single AutoCal measurement cycle. n Tmmt = Txtal * R * 2 (EQ 1) n is set by Reg 0Ah[2:0] and results in measurement periods which are multiples of the PD period, TxtalR. R is the reference path division ratio currently in use, Reg 02h Txtal is the period of the external reference (crystal) oscillator. The VCO AutoCal counter will, on average, expect to register N counts, rounded down (floor) to the nearest integer, every PD cycle. N is the ratio of the target VCO frequency, fvco, to the frequency of the PD, fpd, where N can For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 24 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz be any rational number supported by the N divider. N is set by the integer (Nint = Reg 03h) and fractional (Nfrac = Reg 04h) register contents 24 (EQ 2) The AutoCal state machine runs at the rate of the FSM clock, TFSM, where the FSM clock frequency cannot be greater than 50 MHz. m TFSM = Txtal * 2 m (EQ 3) is 0, 2, 4 or 5 as determined by Reg 0Ah[14:13] EE T The expected number of VCO counts, V, is given by n V = floor (N * 2 ) n fvcom = V * fxtal / (2 * R) where the worst case measurement error, ferr , is: n+1 DA TA ferr fpd / 2 SH The nominal VCO frequency measured, fvcom, is given by (EQ 4) (EQ 5) (EQ 6) IN AR Y TRANSCEIVERS - Rx RFICs N = Nint + Nfrac / 2 Figure 68. VCO Calibration PR EL I M A 5-bit step tuned VCO, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 VSPI data transfers of 20 clock cycles each. Total calibration time, worst case, is given by: n Tcal = k128TFSM + 6TPD 2 + 7 * 20TFSM (EQ 7) or equivalently n m Tcal = Txtal (6R * 2 + (140+(3 * 128)) * 2 ) (EQ 8) For guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8th the frequency step caused by a VCO sub-band switch change. Better resolution settings will show no improvement. 1.1.0.0.1 VCO AutoCal Example The HMC1190ALP6NE must satisfy the maximum fpd limited by the two following conditions: a. N 16 (fint), N 20.0 (ffrac), where N = f VCO/ fpd b. fpd 100 MHz 25 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 Suppose the HMC1190ALP6NE output frequency is to operate at 2.01 GHz. Our example crystal frequency is fxtal = 50 MHz, R=1, and m=0 (Figure 68), hence TFSM = 20 ns (50 MHz). Note, when using AutoCal, the maximum AutoCal Finite State Machine (FSM) clock cannot exceed 50 MHz (see Reg 0Ah[14:13]). The FSM clock does not affect the accuracy of the measurement, it only affects the time to produce the result. This same clock is used to clock the 16 bit VCO serial port. If time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. Using an input crystal of 50 MHz (R=1 and fpd=50 MHz) the times and accuracies for calibration using (EQ 6) and (EQ 8) are shown in Table 11 Where minimal tuning time is 1/8th of the VCO band spacing. SH EE T Across all VCOs, a measurement resolution better than 800 kHz will produce correct results. Setting m = 0, n = 5, provides 781 kHz of resolution and adds 8.6 s of AutoCal time to a normal frequency hop. Once the AutoCal sets the final switch value, 8.64 s after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. Hence as shown in this example that AutoCal typically adds about 8.6 s to the normal time to achieve frequency lock. Hence, AutoCal should be used for all but the most extreme frequency hopping requirements. Control Value Reg0Ah[2:0] n 2n 0 0 1 1 1 2 2 2 4 3 4 5 6 Tcal (s) Ferr Max 0.02 4.92 25 MHz 0.04 5.04 12.5 MHz 5.28 6.25 MHz 8 0.16 5.76 3.125 MHz 5 32 0.64 8.64 781 kHz 6 64 1.28 12.48 390 kHz 7 128 2.56 20.16 195 kHz 8 256 5.12 35.52 98 kHz M 7 Tmmt (s) 0.08 IN AR Y 3 DA TA Table 11. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0 TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz PR EL I 1.1.0.1 Manual VCO Calibration for Fast Frequency Hopping If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host. This can be done by initially locking the HMC1190ALP6NE on each desired frequency using AutoCal, then reading, and storing the selected VCO switch settings. The VCO switch settings are available in Reg 15h[8:1] after every AutoCal operation. The host must then program the VCO switch settings directly when changing frequencies. Manual writes to the VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled. Hence frequency changes with manual control and AutoCal disabled, requires a minimum of two serial port transfers to the HMC1190ALP6NE, once to set the VCO switches, and once to set the PLL frequency. If AutoCal is disabled Reg 0Ah[11]=1, the VCO will update its registers with the value written via Reg 15h[8:1] immediately. 1.1.2 Registers required for Frequency Changes in Fractional Mode A large change of frequency, in fractional mode (Reg 06h[11]=1), may require Main Serial Port writes to: 1. The integer register intg, Reg 03h (only required if the integer part changes) 2. Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal disabled) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 26 HMC1190ALP6NE v00.0615 Registers Required for Frequency Changes in Integer Mode SH 1.1.3 EE T 3. VCO Divide Ratio and Gain Register * Reg 16h[5:0] is required to change the VCO Output Divider value if needed. * Reg 16h[10:6] is required to change the Output Gain if needed. 4. The fractional register, Reg 04h. The fractional register write triggers AutoCal if Reg 0Ah[11]=0, and is loaded into the Delta Sigma modulator automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the fractional frequency change is loaded into the Delta Sigma modulator immediately when the register is written with no adjustment to the VCO. Small steps in frequency in fractional mode, with AutoCal enabled (Reg 0Ah[11]=0), usually only require a single write to the fractional register. Worst case, 3 Main Serial Port transfers to the HMC1190ALP6NE could be required to change frequencies in fractional mode. If the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. In all cases, in fractional mode, it is necessary to write to the fractional register Reg 04h for frequency changes. A change of frequency, in integer mode (Reg 06h[11]=0), requires Main Serial Port writes to: DA TA 1. VCO register * Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal disabled) * Reg 16h is required to change the VCO Output Divider value if needed 2. The integer register Reg 03h. * In integer mode, an integer register write triggers AutoCal if Reg 0Ah[11]=0, and is loaded into the prescaler automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the VCO. Normally changes to the integer register cause large steps in the VCO frequency, hence the VCO switch settings must be adjusted. AutoCal enabled is the recommended method for integer mode frequency changes. If AutoCal is disabled (Reg 0Ah[11]=1), a prior knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change. 1.1.4 IN AR Y TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz VCO Output Mute Function PR EL I M The HMC1190ALP6NE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional. The mute function is automatically controlled by the HMC1190ALP6NE, and provides a number of mute control options including: 1. Always mute (Reg 16h[5:0] = 0d). This mode is used for manual mute control. 2. Automatically mute the outputs during VCO calibration (Reg 17h[7] = 1) that occurs during output frequency changes. This mode can be useful in eliminating any out of band emissions during freqeuncy changes, and ensuring that the system emits only desired frequencies. It is enabled by writing Reg 17h[7] = 1. Typical isolation when the HMC1190ALP6NE is muted is always better than 60 dB, and is ~ 30 dB better than disabling the output buffers of the HMC1190ALP6NE via Reg 17h[5:4]. 27 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 1.2 PLL Overview 2.1.1 Charge Pump (CP) & Phase Detector (PD) The Phase detector (PD) has two inputs, one from the reference path divider and one from the RF path divider. When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other. We refer to the frequency of operation of the PD as fpd. Most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the PD, fpd. fpd is also referred to as the comparison frequency of the PD. EE T The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. The output current varies linearly over a full 2 radians (360) of input phase difference. SH 2.1.1.1 Charge Pump DA TA A simplified diagram of the charge pump is shown in Figure 69. The CP consists of 4 programmable current sources, two controlling the CP Gain (Up Gain Reg 09h[13:7], and Down Gain Reg 09h[6:0]) and two controlling the CP Offset, where the magnitude of the offset is set by Reg 09h [20:14], and the direction is selected by Reg 09h [21]=1 for up and Reg 09h [22]=1 for down offset. PR EL I M IN AR Y CP Gain is used at all times, while CP Offset is only recommended for fractional mode of operation. Typically the CP Up and Down gain settings are set to the same value (Reg 09h[13:7] = Reg 09h[6:0]). TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 69. Charge Pump Gain & Offset Control 2.1.1.1.1 Charge Pump Gain Charge pump Up and Down gains are set by Reg 09h[13:7] and Reg 09h[6:0] respectively. The current gain of the pump in Amps/radian is equal to the gain setting of this register divided by 2. Typical CP gain setting is set to 2 to 2.5 mA, however lower values can also be used. Values < 1 mA may result in degraded Phase Noise performance. For example, if both Reg 09h[13:7] and Reg 09h[6:0] are set to `50d' the output current of each pump will be 1 mA and the phase frequency detector gain kp = 1 mA/2 radians, or 159 A/rad. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 28 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz In Integer Mode, the phase detector operates with zero offset. The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time. Integer mode does not require any CP Offset current. When operating in Integer Mode simply disable CP offset in both directions (Up and down), by writing Reg 09h[22:21] = `00'b and set the CP Offset magnitude to zero by writing Reg 09h[20:14]= 0. In Fractional Mode CP linearity is of paramount importance. Any non-linearity degrades phase noise and spurious performance. EE T In fractional mode, these non-linearities are eliminated by operating the PD with an average phase offset, either positive or negative (either the reference or the VCO edge always arrives first at the PD ie. leads). A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset. Positive current causes the VCO to lead, negative current causes the reference to lead. SH The CP offset is controlled via Reg 09h[20:14]. The phase offset is scaled from 0 degrees, that is the reference and the VCO path arrive in phase, to 360 degrees, where they arrive a full cycle late. DA TA The specific level of charge pump offset current Reg 09h[20:14] is provided in (EQ 9). It is also plotted in Figure 70 vs. PD frequency for typical CP Gain currents. ( ) (EQ 9) Required CP Offset = min 4.3 x 10-9 x FPD x ICP ,0.25 x ICP where: FPD: Comparison frequency of the Phase Detector (Hz) ICP: is the full scale current setting (A) of the switching charge pump (set in Reg 09h[6:0], [13:7] IN AR Y TRANSCEIVERS - Rx RFICs 2.1.1.1.2 Charge Pump Phase Offset CP Current = 2.5 mA 600 500 400 M RECOMMENDED OFFSET CURRENT (uA) 700 CP Current = 2 mA PR EL I 300 200 CP Current = 1 mA 100 0 0 20 40 60 80 100 PHASE DETECTOR FREQUENCY (MHz) Recommended CP offset current CP gain currents. Calculated using (EQ 9) vs PD frequency for typical The required CP offset current should never exceed 25 % of the programmed CP current. It is recommended to enable the Up Offset and disable the Down Offset by writing Reg 09h[22:21] = `10'b. Operation with CP offset influences the required configuration of the Lock Detect function. Refer to the description of Lock Detect function in section 1.3.5. When operating with PD frequency >=80MHz, the CP Offset current should be disabled for the frequency change and then re-enabled after the PLL has settled. If the CP Offset current is enabled during a frequency change it may not lock. 29 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 2.1.1.2 Phase Detector Functions Setting Reg 0Bh[5] = 0, masks the PD up output, which prevents the charge pump from pumping up. Setting (Reg 0Bh[6]) = 0, masks the PD down output, which prevents the charge pump from pumping down. Clearing both Reg 0Bh[5] and Reg 0Bh[6] tri-states the charge pump while leaving all other functions operating internally. SH Reference Input Stage IN AR Y DA TA 2.1.2 EE T PD Force UP Reg 0Bh[9] = 1 and PD Force DN Reg 0Bh[10] = 1 allows the charge pump to be forced up or down respectively. This will force the VCO to the ends of the tuning range which can be useful in VCO testing. TRANSCEIVERS - Rx RFICs Phase detector register Reg 0Bhallows manual access to control special phase detector features. Figure 70. Reference Path Input Stage PR EL I M The reference buffer provides the path from an external reference source (generally crystal based) to the R divider, and eventually to the phase detector. The buffer has two modes of operation controlled by Reg 08h[21]. High Gain (Reg 08h[21] = 0), recommended below 200 MHz, and High frequency (Reg 08h[21] = 1), for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 internal termination. For 50 match, an external 100 resistor to ground should be added, followed by an AC coupling capacitor (impedance < 1 ), then to the XREFP pin of the part. At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher frequencies, a square or sinusoid can be used. The following table shows the recommended operating regions for different reference frequencies. If operating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 30 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 12. Reference Sensitivity Table Reference Input Frequency Slew > 0.5V/ns Sinusoidal Input Recommended Swing (Vpp) Recommended Power Range (dBm) Recommended Min Max Recommended Min Max < 10 YES 0.6 2.5 x x x (MHz) 10 YES 0.6 2.5 x x x 25 YES 0.6 2.5 ok 8 15 YES 0.6 2.5 YES 6 15 YES 0.6 2.5 YES 5 15 150 ok 0.9 2.5 YES 4 12 200 ok 1.2 2.5 YES 3 8 SH EE T 50 100 2.1.3 Reference Path 'R' Divider DA TA Input referred phase noise of the PLL when operating at 50 MHz is between -148 and -150 dBc/Hz at 10 kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better than this floor to avoid degradation of the PLL noise contribution. It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals. The reference path "R" divider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled via Reg 02h. 2.1.4 IN AR Y TRANSCEIVERS - Rx RFICs Square Input RF Path 'N' Divider 2.1.5 Lock Detect M The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional mode, and 219-1 (524,287) to 16 in integer mode. PR EL I The Lock Detect (LD) function indicates that the HMC1190ALP6NE is indeed generating the desired frequency. It is enabled by writing Reg 07h[11]=1. The HMC1190ALP6NE provides LD indicator in one of two ways: * As an output available on the LD_SDO pin of the HMC1190ALP6NE, (Configuration is required to use the LD_SDO pin for LD purpose, for more information please see "1.8 Serial Port Open Mode" and "1.3.5.3 Configuring LD_SDO Pin for LD Output" section). * Or reading from Reg 12h[1], where Reg 12h[1] = 1 indicates locked and Reg 12h[1] = 0 indicates an unlocked condition. The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period (window), repeatedly. Either signal may arrive first, only the difference in arrival times is significant. The arrival of the two edges within the designated window increments an internal counter. Once the count reaches and exceeds a user specified value (Reg 07h[2:0]) the HMC1190ALP6NE declares lock. Failure in registering the two edges in any one window resets the counter and immediately declares an un-locked condition. Lock is deemed to be reestablished once the counter reaches the user specified value (Reg 07h[2:0]) again. 2.1.5.1 Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section "1.3.1". 31 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz ICP Offset ( A) 1 + 2.66 x 10-9 ( sec ) + FPD ( Hz ) x ICP ( A) FPD ( Hz ) LD Window ( seconds ) = in Fractional Mode 2 1 LD Window ( seconds ) = in Integer Mode 2 x FPD (EQ 10) EE T where: FPD: is the comparison frequency of the Phase Detector ICP Offset : is the Charge Pump Offset Current Reg 09h[20:14] ICP: is the full scale current setting of the switching charge pump Reg 09h[6:0], or Reg 09h[13:7] SH If the result provided by (EQ 10) is equal to 10 ns Analog LD can be used (Reg 07h[6] = 0). Otherwise Digital LD is necessary Reg 07h[6] = 1. provides the required Reg 07h settings to appropriately program the Digital LD window size. From simply select the closest value in the "Digital LD Window Size" columns to the one calculated in (EQ 10) and program Reg 07h[9:8] and Reg 07h[7:5] accordingly. Table 13 DA TA Table 13, Table 13. Typical Digital Lock Detect Window Digital Lock Detect Window Size Nominal Value (ns) Fastest 00 01 11 17 29 53 100 195 IN AR Y LD Timer Speed Reg07[9:8] 6.5 8.9 12.8 21 36 68 130 255 7 10 Slowest 11 7.1 9.2 13.3 22 38 72 138 272 7.6 10.2 15.4 26 47 88 172 338 000 001 010 011 100 101 110 111 M LD Timer Divide Setting Reg07[7:5] 8 TRANSCEIVERS - Rx RFICs These settings in Reg 09h impact the required LD window size in fractional mode of operation. To function, the required lock detect window size is provided by (EQ 10). 2.1.5.2 Digital Window Configuration Example PR EL I Assuming, fractional mode, with a 50 MHz PD and * Charge Pump gain of 2 mA (Reg 09h[13:7] = 64h, Reg 09h[6:0] = 64h), * Down Offset (Reg 09h[22:21] = `10'b) * Offset current magnitude of +400 A (Reg 09h[20:14] = 50h) Applying (EQ 11), the required LD window size is: LD Window ( seconds ) 0.4 x10-3 ( A) 1 + 2.66 x 10-9 ( sec ) + 6 50 x 106 ( Hz ) x 2 x10-3 ( A) x 50 10 Hz ( ) = 13.33 nsec 2 (EQ 11) Locating the Table 13 value that is closest to the (EQ 11) result, in this case 13.3 13.33. To set the Digital LD window size, simply program Reg 07h[9:8] = `10'b and Reg 07h[7:5] = `010'b according to Table 13. There is always a good solution for the lock detect window for a given operating point. The user should understand however that one solution does not fit all operating points. As observed from (EQ 11), If charge pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 32 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Setting Reg 0Fh[4:0]=1 will display the Lock Detect Flag on LD_SDO pin of the HMC1190ALP6NE. If locked, LD_SDO will be high. As the name suggests, LD_SDO pin is multiplexed between LD and SDO (Serial Data Out) signals. Hence LD is available on the LD_SDO pin at all times except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data Out pin, and returns to the Lock Detect Flag after the read is completed. LD can be made available on LD_SDO pin at all times by writing Reg 0Fh[6] = 1. In that case the HMC1190ALP6NE will not provide any read-back functionality because the SDO signal is not available. Cycle Slip Prevention (CSP) EE T 2.1.6 DA TA SH When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than 2 radians. Since the gain of the PD varies linearly with phase up to 2, the gain of a conventional PD will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency. The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis. IN AR Y TRANSCEIVERS - Rx RFICs 2.1.5.3 Configuring LD_SDO Pin for LD Output The HMC1190ALP6NE PD features an ability to reduce cycle slipping during frequency tunning. The Cycle Slip Prevention (CSP) feature increases the PD gain during large phase errors. 2.1.7 Frequency Tuning PR EL I M HMC1190ALP6NE VCO subsystem always operates in fundamental frequency of operation (2050 MHz to 4100 MHz). The HMC1190ALP6NE generates frequencies below its fundamental frequency (33 MHz to 2050 MHz) by tuning to the appropriate fundamental frequency and selecting the appropriate Output Divider setting (divide by 2/4/6.../60/62) in Reg 16h[5:0]. The HMC1190ALP6NE automatically controls frequency tuning in the fundamental band of operation, for more information see "1.2.1 VCO Calibration". To tune to frequencies below the fundamental frequency range (<2050 MHz) it is required to tune the HMC1190ALP6NE to the appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6.../60/62) in Reg 16h[5:0]. 2.1.7.1 Integer Mode The HMC1190ALP6NE is capable of operating in integer mode. For Integer mode set the following registers a. Disable the Fractional Modulator, Reg 06h[11]=0 b. Bypass the Modulator circuit, Reg 06h[7]=1 In integer mode the VCO step size is fixed to that of the PD frequency. Integer mode typically has 3 dB lower phase noise than fractional mode for a given PD operating frequency. Integer mode, however, often requires a lower PD frequency to meet step size requirements. The fractional mode advantage is that higher PD frequencies can be used, hence lower phase noise can often be realized in fractional mode. Charge Pump offset should be disabled in integer mode Reg 09h[22:14] = 0h. 33 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz In integer mode the digital modulator is shut off and the N divider (Reg 03h) may be programmed to any integer value in the range 16 to 219-1. To run in integer mode configure Reg 06h as described, then program the integer portion of the frequency as explained by (EQ 12), ignoring the fractional part. 2.1.7.2 Fractional Mode EE T a. Disable the Fractional Modulator, Reg 06h[11] = 0 b. Bypass the delta-sigma modulator Reg 06h[7] = 1 c. To tune to frequencies (<2050 MHz), select the appropriate output divider valueReg 16h[5:0]. The HMC1190ALP6NE is placed in fractional mode by setting the following registers: SH a. Enable the Fractional Modulator, Reg 06h[11]=1 b. Connect the delta sigma modulator in circuit, Reg 06h[7]=0 2.1.7.2.1 Fractional Frequency Tuning DA TA This is a generic example, with the goal of explaining how to program the output frequency. Actual variables are dependant upon the reference in use. The HMC1190ALP6NE in fractional mode can achieve frequencies at fractional multiples of the reference. The frequency of the HMC1190ALP6NE, fvco, is given by fxtal R (Nint + Nfrac) = fint + ffrac IN AR Y fvco = fout = fvco / k fout is the output frequency after any potential dividers. is 1 for fundamental, or k = 2,4,6,...58,60,62 depending on the selected output divider value (Reg 16h[5:0]) PR EL I k (EQ 13) M Where: (EQ 12) TRANSCEIVERS - Rx RFICs 1.2.0.1.1 Integer Frequency Tuning Nint is the integer division ratio, Reg 03h, an integer number between 20 and 524,284 Nfrac is the fractional part, from 0.0 to 0.99999...,Nfrac=Reg 04h/224 R is the reference path division ratio, Reg 02h fxtal is the frequency of the reference oscillator input fpd is the PD operating frequency, fxtal /R As an example: fout 1402.5 MHz k 2 fvco 2,805 MHz fxtal = 50 MHz R =1 fpd = 50 MHz Nint = 56 Nfrac = 0.1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 34 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz = round(0.1 x 224) = round(1677721.6) = 1677722 f VCO = 50e6 1 (56 + f VCO 2 224 ) = 2805 MHz + 1.192 Hz error = 1402.5 MHz + 0.596 Hz error (EQ 14) (EQ 15) EE T fout = 1677722 2.1.7.2.2 SH In this example the output frequency of 1402.5 MHz is achieved by programming the 19-bit binary value of 56d = 38h into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah into frac_reg in Reg 04h. The 0.596 Hz quantization error can be eliminated using the exact frequency mode if required. In this example the VCO output fundamental 2805 MHz is divided by 2 (Reg 16h[5:0] = 2h) = 1402.5 MHz. Exact Frequency Tuning DA TA Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency resolution set by the phase detector (PD ) comparison rate divided by 224. The value 224 in the denominator is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large fixed modulus. Normally, the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD rate, a modulus of 224 would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is necessary to have exact frequency steps, and even an error of 3 Hz cannot be tolerated. IN AR Y TRANSCEIVERS - Rx RFICs Reg 04h PR EL I M Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common frequencies cannot be exactly represented. For example, Nfrac = 0.1 = 1/10 must be approximated as round((0.1 x 224)/ 224 ) 0.100000024. At fPD = 50 MHz this translates to 1.2 Hz error. Hittite's exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to FPD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever the desired frequency, f VCO, can be exactly represented on a step plan where there are an integer number of steps (<224) across integer-N boundaries. Mathematically, this situation is satisfied if: fPD 24 2 fVCOk = mod fgcd 0= where fgcd gcd(fVCO1, fPD ) and fgcd (EQ 16) Where: gcd stands for Greatest Common Divisor fN = maximum integer boundary frequency < f VCO1 fPD = frequency of the Phase Detector and f VCOk are the channel step frequencies where 0 < k < 224-1, As shown in Figure 71. 35 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 DA TA Some fractional PLLs are able to achieve this by adjusting (shortening) the length of the Phase Accumulator (the denominator or the modulus of the Delta-Sigma modulator) so that the Delta-Sigma modulator phase accumulator repeats at an exact period related to the interval frequency (f VCOk - f VCO(k-1)) in Figure 71. Consequently, the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f VCOk - f VCO(k-1). For example, in some applications, these intervals might represent the spacing between radio channels, and the spurious would occur at multiples of the channel spacing. IN AR Y The Hittite method on the other hand is able to generate exact frequencies between adjacent integer-N boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector comparison rate, which allows Hittite PLLs to maintain excellent phase noise and spurious performance in the Exact Frequency Mode. TRANSCEIVERS - Rx RFICs SH Figure 71. Exact Frequency Tuning EE T BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 2.1.7.2.3Using Hittite Exact Frequency Mode PR EL I M If the constraint in (EQ 16) is satisfied, HMC1190ALP6NE is able to generate signals with zero frequency error at the desired VCO frequency. Exact Frequency Mode may be re-configured for each target frequency, or be set-up for a fixed fgcd which applies to all channels. 2.1.7.2.4 Configuring Exact Frequency Mode For a Particular Frequency 1. Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO/fPD), where the floor function is the rounding down to the nearest integer. Then the integer boundary frequency fN = NINT fPD 2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd, where fgcd = gcd(f VCO,fPD) 24 3. Calculate and program the fractional register setting Reg 04h NFRAC = ceil is the ceiling function meaning "round up to the nearest integer." 2 ( fVCOk - fN ) fPD , where ceil Example: To configure the HMC1190ALP6NE for exact frequency mode at f VCO = 2800.2 MHz where Phase Detector (PD) rate fPD = 61.44 MHz Proceed as follows: Check (EQ 16) to confirm that the exact frequency mode for this f VCO is possible. fPD 224 = fgcd gcd(fVCO , fPD ) and fgcd ( ) fgcd = gcd 2800.2 x 106 ,61.44 x 106 = 120 x 103 > 61.44 x 106 = 3750 224 Since (EQ 16) is satisfied, the HMC1190ALP6NE can be configured for exact frequency mode at f VCO = 2800.2 MHz as follows: For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 36 HMC1190ALP6NE v00.0615 f 2800.2 x 106 45 = = d 2Dh 61.44 x 106 1. NINT = Reg 03h = floor 2. Reg 0Ch = 3. To program Reg 04h, the closest integer-N boundary frequency fN that is less than the desired VCO frequency f VCO must be calculated. fN = fPD NINT. Using the current example: 1 VCO = floor fPD 61.44 x 106 61.44 x 106 d C00h = = = 3072 = 3 6 20000 gcd 100 x 10 ,61.44 x 10 gcd ( fVCOk +1 - fVCOk ) , fPD ( ) ) ( fN =fPD x NINT =45 x 61.44 x 106 =2764.8 MHz. ) ( EE T fPD ( ) 3.1.7.2.1 Hittite Exact Frequency Channel Mode SH 24 224 f 2800.2 x 106 - 2764.8 x 106 2 VCO - fN = ceil = = d 938000h 9666560 fPD 61.44 x 106 Then= Reg04h ceil DA TA If it is desirable to have multiple, equally spaced, exact frequency channels that fall within the same interval (ie. fN f VCOk < fN+1) where f VCOk is shown in Figure 71 and 1 k 224, it is possible to maintain the same integer-N (Reg 03h) and exact frequency register (Reg 0Ch) settings and only update the fractional register (Reg 04h) setting. The Exact Frequency Channel Mode is possible if (EQ 16) is satisfied for at least two equally spaced adjacent frequency channels, i.e. the channel step size. IN AR Y To configure the HMC1190ALP6NE for Exact Frequency Channel Mode, initially and only at the beginning, integer (Reg 03h) and exact frequency (Reg 0Ch) registers need to be programmed for the smallest f VCO frequency (f VCO1 in Figure 71), as follows: Calculate and program the integer register setting Reg 03h = NINT = floor(f VCO1/fPD), where f VCO1 is shown in Figure 71 and corresponds to minimum channel VCO frequency. Then the lower integer boundary frequency is given by fN = NINT fPD. 2. Calculate and program the exact frequency register value Reg 0Ch = fPD/fgcd, where fgcd = gcd((f VCOk+1 - f VCOk),fPD) = greatest common divisor of the desired equidistant channel spacing and the PD frequency ((f VCOk+1 - f VCOk) and fPD). M 1. PR EL I TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Then, to switch between various equally spaced intervals (channels) only the fractional register (Reg 04h) needs to be programmed to the desired VCO channel frequency f VCOk in the following manner: ( ) 224 f VCOk - fN fPD Reg 04h = NFRAC = ceil where fN = floor(f VCO1/fPD), and f VCO1, as shown in Figure 71, represents the smallest channel VCO frequency that is greater than fN. Example: To configure the HMC1190ALP6NE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel (Channel 1) = f VCO1 = 2800.200 MHz and Phase Detector (PD) rate fPD = 61.44 MHz proceed as follows: First check that the exact frequency mode for this f VCO1 = 2800.2 MHz (Channel 1) and f VCO2 = 2800.2 MHz + 100 kHz = 2800.3 MHz (Channel 2) is possible. fPD 224 = fgcd1 gcd(fVCO1, fPD ) and fgcd1 f and= fgcd2 gcd(fVCO2 , fPD ) and fgcd2 PD 224 ) ( =gcd ( 2800.3 x 10 ,61.44 x 10 ) =20 x 10 61.44 x 106 = 3750 224 61.44 x 106 > =3750 224 fgcd1 = gcd 2800.2 x 106 ,61.44 x 106 = 120 x 103 > fgcd 2 37 6 6 3 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 1. Reg 03h = 2. Reg 0Ch = 6 VCO 1 floor 2800.2 x 10= 45 = = d 2Dh fPD 61.44 x 106 f floor 61.44 x 106 61.44 x 106 d C00h = = = 3072 = 3 6 20000 gcd 100 x 10 ,61.44 x 10 gcd ( fVCOk +1 - fVCOk ) , fPD fPD ( ) ) ( where (f VCOk+1 - f VCOk) is the desired channel spacing (100 kHz in this example). To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest channel VCO frequency f VCO1 must be calculated. fN = floor(f VCO1/fPD). Using the current example: 2800.2 x 106 =45 x 61.44 x 106 =2764.8 MHz 61.44 x 106 Then SH fN =fPD x floor EE T 3. PD 24 2800.2 x 106 - 2764.8 x 106 2 d 938000h = ceil = = 9666560 61.44 x 106 ( ) To change from channel 1 (f VCO1 = 2800.2 MHz) to channel 2 (f VCO2 = 2800.3 MHz), only Reg 04h needs to be programmed, as long as all of the desired exact frequencies f VCOk (Figure 71) fall between the same integer-N boundaries (fN < f VCOk < fN+1). In that case IN AR Y 4. DA TA 224 f ( VCO1 - fN ) for channel 1 where f Reg 04h ceil = = VCO1 2800.2 MHz f ( ) 24 2800.3 x 106 - 2764.8 x 106 2 = = d 93EAABh 9693867 61.44 x 106 Seed Register PR EL I 4.1.1 , and so on. M Reg 04h = ceil TRANSCEIVERS - Rx RFICs If (EQ 16) is satisfied for at least two of the equally spaced interval (channel) frequencies f VCO1,f VCO2 ,f VCO3 ,... f VCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies, and can be configured as follows: The start phase of the fractional modulator digital phase accumulator (DPA) may be set to any desired phase relative to the reference frequency, The phase is programmed in Reg 1Ah, and Exact Frequency Mode is required. Phase = 2 x Reg1Ah/(224) via the seed register Reg 1Ah[23:0]. The HMC1190ALP6NE will automatically reload the start phase (seed value) into the DPA every time a new fractional frequency is selected. Certain zero or binary seed values may cause spurious energy correlation at specific frequencies. For most cases a random, or non zero, non-binary start seed is recommended. 4.1 Soft Reset & Power-On Reset The HMC1190ALP6NE features a hardware Power on Reset (POR). All chip registers will be reset to default states approximately 250 s after power up. The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg 00h. 4.2 Power Down Mode Power down the HMC1190ALP6NE by pulling CEN pin (pin 17) low (assuming no SPI overrides(Reg 01h[0]=1)). This will result in all analog functions and internal clocks disabled. Current consumption will typically drop below 10 A in Power Down state. The serial port will still respond to normal communication in Power Down mode. It is possible to ignore the CEN pin, by setting Reg 01h[0]=0. Control of Power Down Mode then comes from the serial port register Reg 01h[1]. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 38 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz a. Internal Bias Reference Sources Reg 01h[2] b. PD Block Reg 01h[3] c. CP Block Reg 01h[4] d. Reference Path Buffer Reg 01h[5] e. VCO Path buffer Reg 01h[6] f. Digital I/O Test pads Reg 01h[7] 4.3 EE T To mute the output but leave the PLL and VCO locked please refer to 1.2.4 section. General Purpose Output (GPO) Pin DA TA SH The PLL shares the LD_SDO (Lock-Detect/Serial Data Out) pin to perform various functions. While the pin is most commonly used to read back registers from chip via the SPI, it is also capable of exporting a variety of signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOS driver with ~200 Rout. It has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. In its default configuration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus. The pin driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle = `000'b before the rising edge of SEN. If SEN rises before SCK has clocked in an `invalid' (non-zero) chip -address, the HMC1190ALP6NE will start to drive the bus. IN AR Y TRANSCEIVERS - Rx RFICs It is also possible to leave various blocks on when in Power Down (see Reg 01h), including: The BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER will naturally switch away from the GPO data and export the SDO during an SPI read. To prevent this automatic data selection, and always select the GPO signal, set "Prevent AutoMux of SDO" (Reg 0Fh[6] = 1). The phase noise performance at this output is poor and uncharacterized. The GPO output should not be toggling during normal operation because it may degrade the spectral performance. M Note that there are additional controls available, which may be helpful if sharing the bus with other devices: To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else). * To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 1 or Reg 0Fh[9] = 1 respectively. PR EL I * Example Scenarios: * Drive SDO during reads, tri-state otherwise (to allow bus-sharing) * No action required. * Drive SDO during reads, Lock Detect otherwise * Set GPO Select Reg 0Fh [4:0] = `00001'b (which is default) * Set "Prevent GPO driver disable" (Reg 0Fh[7] = 1) * Always drive Lock Detect * Set " Prevent AutoMux of SDO" Reg 0Fh[6] = 1 * Set GPO Select Reg 0Fh[4:0]= 00001 (which is default) * Set "Prevent GPO driver disable" (Reg 0Fh[7] = 1)) The signals available on the GPO are selected in Reg 0Fh[4:0]. 39 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Chip Identification The chip id information may be read by reading the content of read only register, chip_ID in Reg 00h. For HMC1190ALP6NE, chip id is C7701Ah. 4.5 SERIAL PORT Overview The SPI protocol has the following general features: Serial Port WRITE Operation AVDD = DVDD = 3V, AGND = DGND = 0V Parameter DA TA Table 14. SPI WRITE Timing Characteristics SH 4.5.1 EE T a. 3-bit chip address , enable the use of up to 8 devices connected to the serial bus b. Simultaneous Write/Read during the SPI cycle c. 5-bit address space d. 3 wire for Write Only capability, 4 wire for Read/Write capability Typical serial port operation can be run with SCLK at speeds up to 50 MHz. Conditions Min. Typ. Max Units SDI setup time to SCLK Rising Edge 3 ns t2 SCLK Rising Edge to SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns t6 Recovery Time 10 IN AR Y t1 Max Serial port Clock Speed TRANSCEIVERS - Rx RFICs 4.4 ns 50 MHz A typical WRITE cycle is shown in Figure 72. PR EL I M a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK. b. the slave (HMC1190ALP6NE) shifts in data on SDI on the first 24 rising edges of SCLK c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK (25-29) d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29). e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite reserves chip address a2:a0 = 000 for HMC1190ALP6NE. f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32). g. Master asserts SEN after the 32nd rising edge of SCLK. h. Slave registers the SDI data on the rising edge of SEN. i. Master clears SEN to complete the WRITE cycle. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 40 HMC1190ALP6NE v00.0615 EE T SH 4.5.2 Serial Port READ Operation A typical READ cycle is shown in Figure 73. DA TA Figure 72. Serial Port Timing Diagram - WRITE In general, the LD_SDO line is always active during the WRITE cycle. During any SPI cycle LD_SDO will contain the data from the current address written in Reg 00h[4:0]. If Reg 00h[4:0] is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress. If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the desired address to Reg 00h[4:0], then in the next SPI cycle the desired data will be available on LD_SDO. IN AR Y TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz An example of the two cycle procedure to read from any address follows: PR EL I M a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI as shown in Figure 73. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on the next cycle. b. the slave (HMC1190ALP6NE) shifts in data on SDI on the first 24 rising edges of SCK c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5 falling edges of SCK (25-29). r4:r0=00000. d. Slave shifts the register bits on the next 5 rising edges of SCK (25-29). e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCK (30-32). Chip address is always `000'b. f. Slave shifts the chip address bits on the next 3 rising edges of SCK (30-32). g. Master asserts SEN after the 32nd rising edge of SCK. h. Slave registers the SDI data on the rising edge of SEN. i. Master clears SEN to complete the the address transfer of the two part READ cycle. j. If one does not wish to write data to the chip during the second cycle, then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle. k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK. l. Slave (HMC1190ALP6NE) shifts the SDI data on the next 32 rising edges of SCK. On these same edges, the slave places the desired read data (ie. data from the address specified in Reg 00h[4:0] of the first cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the LD output. m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO. 41 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 15. SPI Read Timing Characteristics Conditions Min. Typ. Max Units t1 SDI setup time to SCK Rising Edge 3 ns t2 SCK Rising Edge to SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 t5 SCK Rising Edge to SDO time t6 Recovery TIme 10 ns t7 SCK 32 Rising Edge to SEN Rising Edge 10 ns ns ns PR EL I M IN AR Y DA TA SH EE T 8.2ns+0.2ns/pF TRANSCEIVERS - Rx RFICs Parameter For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 42 HMC1190ALP6NE v00.0615 EE T SH DA TA IN AR Y PR EL I M TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Figure 73. Serial Port Timing Diagram - READ For more information on using the GPO pin while in SPI Mode please see section 1.8 Serial Port Overview 43 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 2.0 PLL Register Map 2.1 Reg 00h ID Register (Read Only) DEFAULT C7701A h Bit Type [23:0] RO Width Default 24 C7701A Description Chip ID Number Reg 00h Open Mode Read Address/RST Strobe Register (Write Only) Bit Type [4:0] WO Read Address [5] WO [23:6] WO Width Default 5 - (WRITE ONLY) Read Address for next cycle Description Soft Reset 1 - (WRITE ONLY) Soft Reset - (set to 0 during operation) Not Defined 18 - Not Defined (set to write 0h) Bit [0] Type R/W Name Chip Enable Pin Select 0 keeps internal bias generators on, ignores Chip enable control 1 0 keeps PFD circuit on, ignores Chip enable control 1 0 keeps Charge Pump on, ignores Chip enable control Keep Reference Buffer ON 1 0 keeps Reference buffer block on, ignores Chip enable control R/W Keep VCO on 1 0 keeps VCO divider buffer on, ignores Chip enable control R/W Keep GPO Driver ON 1 0 keeps GPO output Driver ON, ignores Chip enable control R/W Reserved 2 0 reserved R/W Keep Bias On [3] R/W Keep PFD Pn [4] R/W Keep CP On [5] R/W [6] [13:0] 2.5 Bit 1 PR EL I M IN AR Y [2] Bit 0 = Chip enable via SPI - Reg 01h[0] = 0, CHIP_EN pin ignored (see Power Down Mode description for more details) 1 SPI Chip Enable 2.4 1 Description 1 = Chip enable via CHIP_EN pin, Reg 01h[0]=1 and CHIP_EN pin low places the HMC1190ALP6NE in Power Down Mode 1 R/W [9:8] 1 Default Controls Chip Enable (Power Down) if Reg 01h[0] =0 Reg 01h[0]=0 and Reg 01h[1]=1 - chip is enabled, CHIP_ EN pin don't care Reg 01h[0]=0 and Reg 01h[1]=0 - chip disabled, CHIP_EN pin don't care (see Power Down Mode description for more information) [1] [7] Width SH Reg 01h Chip Enable Register DEFAULT 3h DA TA 2.3 Name EE T 2.2 Name chip_ID TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Reg 02h REFDIV Register DEFAULT 1h Type R/W Name rdiv Width 14 Default 1 Description Reference Divider 'R' Value (EQ 8) min 1 max max 214-1 = 3FFFh = 16383d Reg 03h Frequency Register - Integer Part DEFAULT 19h Type Name Width Default Description Divider Integer part, used in all modes, see (EQ 10) [18:0] R/W Integer Setting 19 25d 19h Fractional Mode min 20d max 219 - 4 = 7FFFCh = 524,284d Integer Mode min 16d max 219-1 = 7FFFFh = 524,287d For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 44 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 2.6 [23:0] Type R/W Name Width Fractional Setting 24 Default 0 Description Divider Fractional part (24 bit unsigned) see Fractional Frequency Tuning Fractional Division Value = Reg4[23:0]/2^24 Used in Fractional Mode only 2.7 Reg 05h Reserved Type R/W 2.8 Name Reserved Width Default 24 0 Description Reserved SH Bit [23:0] EE T min 0 max 224-1 = FFFFFFh = 16,777,215d Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah TYPE NAME Width Default [1:0] R/W Reserved 2 2 Reserved, Program to 0h 2 Select the Delta Sigma Modulator Type 0: 1st order 1: 2nd Order 2: 3rd Order - Recommended 3: Reserved [3:2] R/W DSM Order 2 Synchronous SPI Mode 1 0 [5] [6] [7] PR EL I M [4] R/W DA TA BIT IN AR Y TRANSCEIVERS - Rx RFICs Bit Reg 04h Frequency Register - Fractional Part DEFAULT 0h DESCRIPTION 0: Normal SPI Load - all register load on rising edge of SEN 1: Synchronous SPI - registers Reg 03h, Reg 04h , Reg 1Ah wait to load synchronously on the next internal clock cycle. Normally (When this bit is 0) SPI writes into the internal state machines/counters happen asynchronously relative to the internal clocks. This can create freq/phase disturbances if writing register 3, 4 or 1A. When this bit is enabled, the internal SPI registers are loaded synchronously with the internal clock. This means that the data in the SPI shifter should be held constant for at least 2 PFD clock periods after SEN is asserted to allow this retiming to happen cleanly. R/W Exact Frequency Mode Enable 1 0 1: Exact Frequency Mode Enabled 0: Exact Frequency Mode Disabled R/W Reserved 1 0 Reserved 0 0: Use Modulator, Required for Fractional Mode, 1: Bypass Modulator, Required for Integer Mode Note: When enabled fractional modulator output is ignored, but fractional modulator continues to be clocked if Reg 06h[11] =1. This feature can be used to test the isolation of the digital fractional modulator from the VCO output in integer mode. R/W Fractional Bypass 1 1: loads the modulator seed (start phase) whenever the fractional 45 [8] R/W [10:9] register (Reg 04h) is written Autoseed EN 1 1 R/W Reserved 2 3 Reserved [11] R/W Delta Sigma Modulator Enable 1 1 0: Disable DSM, used for Integer Mode 1: Enable DSM Core, required for Fractional Mode [23:12] R/W Reserved 12 48d 30h 0: when fractional register (Reg 04h) write changes frequency, modulator starts at previous value (phase) Reserved For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Bit Reg 07h Lock Detect Register DEFAULT 200844 h Type Name Width Default Description R/W lkd_wincnt_max 3 4 [10:3] R/W Reserved 8 8 Reserved [11] R/W LD Enable 1 1 0: LD disable 1: LD enable [19:12] R/W Reserved 8 0 Reserved Lock Detect Training [21] R/W CSP Enable [23:22] R/W Reserved Bit Type [4:0] R/W [9:6] [10] [20:11] R/W Name Reserved GPO(General Purpose Output Pin Enable) PR EL I [5] 0 SH After changing PD frequency a toggle Reg 07h[20] from 0 to 1 retrains the Lock Detect. 1 1 Cycle Slip Prevention enable. When enabled, if the phase error becomes larger than approx 70% of the PFD period, the charge-pump gain is increased by approx 6mA for the duration of the cycle.. 2 0 Reserved Reg 08h Analog EN Register DEFAULT 1BFFF h M 2.10 9 0 to 1 transition triggers the training. Lock Detect Training is only required after changing Phase Detector frequency. DA TA R/W IN AR Y [20] EE T [2:0] lock detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 TRANSCEIVERS - Rx RFICs 2.9 Width Default 5 31d 1 Description Reserved 0 - Pin LD_SDO disabled 1d 1 - and RegFh[7]=1 , Pin LD_SDO is always driven, this is required for use of GPO port 1 - and RegFh[7]=0 LDO_SPI is off if chip address not equal to `000'b, allowing a shared SPI with other compatible parts R/W Reserved 4 15d Reserved R/W VCO Buffer and Prescaler Bias Enable 1 1d 0: VCO Buffer and Prescaler Bias Disable 1: VCO Buffer and Prescaler Bias Enable Only applies to External VCO R/W Reserved 10 55d [21] R/W High Frequency Reference 1 0 Reserved Program to 1 for XTAL > 200 MHz, 0 otherwise [22] R/W SDO Output Level 1 0d Output Logic Level on LD/SDO pin 0: 1.8 V Logic Levels 1: DVDD3V Logic Level [23] R/W Reserved 1 0d Reserved For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 46 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz [6:0] R/W R/W Name CP DN Gain Width Description 100d 64h Charge Pump DN Gain Control 20 Astep Affects fractional phase noise and lock detect settings 0d = 0 A 1d = 20 A 2d = 40 A ... 127d = 2.54mA Default 2mA 100d 64h Charge Pump UP Gain Control 20 A per step Affects fractional phase noise and lock detect settings 0d = 0 A 1d = 20 A 2d = 40 A ... 127d = 2.54mA Default 2mA 7 81d Charge Pump Offset Control 5 A/step Affects fractional phase noise and lock detect settings 0d = 0 A 1d = 5 A 2d = 10 A ... 127d = 635 A Default 405A 1 0 Sets Direction of Reg 09h[20:14] Up, 0- UP Offset Off 1 1 Sets Direction of Reg 09h[20:14] Down, 0- DN Offset Off 0 Only recommended with external VCOs and Active Loop Filters. When enabled the HMC1190ALP6NE increases CP current by 3 mA, thereby improving phase noise performance, and increasing loop bandwidth 7 CP UP Gain Default 7 [20:14] R/W Offset Magnitude R/W Offset UP enable R/W Offset DN enable [23] R/W HiK charge pump Mode IN AR Y [21] [22] DA TA SH [13:7] Type 1 PR EL I M TRANSCEIVERS - Rx RFICs Bit Reg 09h Charge Pump Register DEFAULT 547264 h EE T 2.11 47 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Bit Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h Type Name Width Default Description R/W Vtune Resolution 3 6d [10:3] R/W Reserved 8 16d Reserved [11] R/W AutoCal Disable 1 0 0 = AutoCal Enabled 1 = AutoCal disabled [12] R/W Reserved 1 0 Reserved FSM/VSPI Clock Select [16:15] R/W Reserved [17] R/W Auto relock - one Try [23:18] R/W Reserved SH DA TA R/W 2 1 Set the AutoCal FSM and VSPI Clock (50 MHz maximum) 0: Input Crystal Reference 1: Input Crystal Reference/4 2: Input Crystal Reference/16 3: Input Crystal Reference/32 2 0 Reserved 1 0 0: Does not attempt to relock if lock is lost 1: Attempts to relock if Lock Detect fails for any reason. Only tries once. 5 0 Reserved PR EL I M IN AR Y [14:13] EE T [2:0] Used by internlan AutoCal state machine R Divider Cycles 0-1 1-2 2-4 3-8 4 - 32 5 - 64 6 - 128 7 - 256 div cycles for frequency measurement. Measurement should last > 4 sec. Note: 1 does not work if R divider = 1. TRANSCEIVERS - Rx RFICs 2.12 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 48 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Reg 0Bh PD/CP Register DEFAULT 78061 h BIT TYPE NAME Width Default [3:0] R/W Reserved 4 1 Reserved R/W PD Phase Select 1 0 [5] R/W PD Up Output Enable 1 1 Enables the PD UP output, see also Reg 0Bh[9] 0Bh[10] EE T [4] [6] R/W PD Down Output Enable 1 1 Enables the PD DN output, see also Reg [8:7] R/W Reserved 2 0 Reserved, Program to 0d. R/W Force CP UP 1 0 Forces CP UP output on if CP is not forced down - Use for Test only R/W Force CP DN 1 0 Forces CP DN output on if CP is not forced up - Use for Test only [11] R/W Force CP Mid Rail 1 0 Force CP MId Rail - Use for Test only (if Force CP UP or Force CP DN are enabled they have precedence) [23:12] R/W Reserved 12 120d 78h 2.14 DA TA Reserved. Reg 0Ch Exact Frequency Register TYPE R/W NAME Number of Channels per Fpd PR EL I M [23:0] SH [9] [10] BIT 49 DESCRIPTION Inverts the PD polarity (program to 0) 0- Use with a positive tuning slope VCO and Passive Loop Filter (default when using internal VCO) 1- Use with a Negative Slope VCO or with an inverting Active Loop Filter with a Positive Slope VCO (Only recommended when using an External VCO, and an active loop filter) IN AR Y TRANSCEIVERS - Rx RFICs 2.13 Width 24 Default DESCRIPTION 0 Comparison Frequency divided by the correction rate. Must be an integer. Frequencies at exactly the correction rate will have zero frequency error. Only works in modulator Mode B(3rd order recommended modulator type in Reg06[3:2]). Reg 0Ch must be 0 if using ohter DSM type 0: Disabled 1: Invalid 2 valid max 224-1 = FFFFFFh = 16,777,215d For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz BIT Reg 0Fh GPO Register TYPE NAME Width Default DESCRIPTION Select signal to be output to SDO pin when enabled DEFAULT LOCK DETECT R/W GPO 5 [5] R/W GPO Test Data [6] R/W Prevent Automux SDO 1 [8] [9] [23:10] 2.16 M PR EL I [7] IN AR Y DA TA [4:0] SH EE T 0: Data from Reg0F[5] 1: Lock Detect Output 2. Lock Detect Trigger 3: Lock Detect Window Output 4: Ring Osc Test 5. Pullup Hard from CSP 6. PullDN hard from CSP 7. Reserved 8: Reference Buffer Output 9: Ref Divider Output 10: VCO divider Output 11. Modulator Clock from VCO divider 12. Auxiliary Clock 13. Aux SPI Clock 14. Aux SPI Enable 15. Aux SPI Data Out 16. PD DN 17. PD UP 18. SD3 Clock Delay 19. SD3 Core Clock 20. AutoStrobe Integer Write 21. Autostrobe Frac Write 22. Autostrobe Aux SPI 23. SPI Latch Enable 24. VCO Divider Sync Reset 25. Seed Load Strobe 26.-29 Not Used 30. SPI Output Buffer En 31. Soft RSTB R/W Reserved 1 0 1 - GPO Test Data when GPO_Select = 0 1 0 1- Outputs GPO data only 0- Automuxes between SDO and GPO data 1 0 TRANSCEIVERS - Rx RFICs 2.15 Reserved R/W Disable PFET 1 0 Program to 1 if external pull-ups are used on the SDO line (Prevents conflicts on the SPI bus) R/W Disable NFET 1 0 Program to 1 if external pull-downs are used on the SDO line (Prevents conflicts on the SPI bus) R/W Reserved 14 0 Reserved Reg 10h Tuning Register DEFAULT 80 h BIT TYPE NAME Width Default [7:0] R VCO Tune Curve 8 16d 10h [8] R VCO Tuning Busy 1 0 DESCRIPTION VCO selection resulting from AutoCalibration. 0- maximum frequency `1111 1111'b- minimum frequency Indicates if the VCO tuning is in process 1- Busy 0- Not Busy For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 50 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 2.17 TYPE NAME Width Default DESCRIPTION [18:0] R SAR Error Magnitude Count 19 219 - 1d 7FFFFh [19] R SAR Error Sign 1 0 SAR Error Sign 0: positive 1: negative [23:20] R Reserved 4 0 Reserved [0] [1] [23:2] BIT Width Default DESCRIPTION R GPO Out 1 0 GPO Output R Lock Detect Out 1 0 Lock Detect Output R Reserved 22 7h Reserved Reg 13h BIST Register (Read Only) TYPE R NAME Reserved Width Default 16 4697d 1259h DESCRIPTION Reserved IN AR Y [16:0] NAME SH TYPE 2.19 EE T Reg 12h GPO/LD Register (Read Only) BIT DA TA 2.18 SAR Error Magnitude Count PR EL I M TRANSCEIVERS - Rx RFICs BIT Reg 11h SAR Register (Read Only) 51 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz BIT Reg 14h Auxiliary SPI Register TYPE NAME Width Default DESCRIPTION [0] R/W Aux SPI Mode 1 0 1- Use the 3 outputs as an SPI port 0- Use the 3 outputs as a static GPO port along with Reg 14h[3:1] [3:1] R/W Aux GPO Values 3 0 3 Output values can be set indivually when Reg [4] R/W Aux GPO 3.3 V 1 0 [8:5] R/W Reserved 4 1 10h [0] = 1 0- 1.8 V output out of the Auxiliary GPO pins when Reg 1- 3.3 V output out of the Auxiliary GPO pins when Reg 10h [0] = 1 10h [0] = 1 EE T Reserved When set, CHIP_EN pin is used as a trigger for phase synchronization. Can be used to synchronize multiple R/W Phase Sync Aux SPI GPO Output R/W Aux SPI Outputs [23:14] R/W Reserved 2.21 2 2 1 0 0 IN AR Y [13:12] 1 10 HMC1190ALP6NE, or to along with the Reg 1Ah value to phase step the output. (Exact Frequency Mode must be enabled) SH [11:10] R/W Option to send GPO multiplexed data (ex Lock Detect) to one of the auxiliary outputs 0- None 1 - to [0] 2 - to [1] 3 - to [2] DA TA [9] 0 When disabled: 0 - Outputs Hi Z 1 - Outputs stay driven 2 - Outputs driven to high 3 - Outputs driven to low Reserved Reg 15h Manual VCO Config Register Default F48A0 h TYPE NAME [0] R/W Manual Calibration Mode M BIT Width Default 1 0 DESCRIPTION 1- VCO subsystem manual calibration enabled 0- VCO subsystem manual calibration disabled Capacitor Switch Setting 5 16d 10h R/W Manual VCO Selection 3 2 selects the VCO core sub-band R/W Manual VCO Tune Enable 1 0 1- Manual VCO tuning enabled 0- Manual VCO tuning disabled R/W Reserved 6 18d 12h [16] R/W Enable Auto-Scale CP current 1 1 1 - Automatically scale CP current based on VCO frequency and capacitor setting 0- Don't scale CP current [23:17] R/W Reserved 7 7d Reserved [8:6] [9] [15:10] PR EL I R/W [5:1] TRANSCEIVERS - Rx RFICs 2.20 capacitor switch setting Reserved For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 52 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz R/W RF Divide Ratio 6 [7:6] R/W LO Output Buffer Gain Control 2 [9:8] R/W LO2 Output Buffer gain Control 2 [10] R/W Divider Output Stage Gain Control 1 [23:11] R/W Reserved 13 Default DESCRIPTION 1 0 - Mute, VCO and PLL buffer On, RF output stages Off 1 - Fo 2 - Fo/2 3 - invalid, defaults to 2 4 - Fo/2 5 - invalid, defaults to 4 6 - Fo/6 ... 60 - Fo/60 61 - invalid, defaults to 60 62 - Fo/62 > 62 - invalid, defaults to 62 3 3 - Max Gain 2 - Max Gain - 3 dB 1 - Max Gain - 6 dB 0 - Max Gain - 9 dB EE T Width SH NAME 2 3 - Max Gain 2 - Max Gain - 3 dB 1 - Max Gain - 6 dB 0 - Max Gain - 9 dB 1 1 - Max Gain 0 - Max Gain - 3 dB 0 Reserved IN AR Y [5:0] TYPE PR EL I M TRANSCEIVERS - Rx RFICs BIT Reg 16h Gain Divider Register Default 6C1 h DA TA 2.22 53 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz BIT Reg 17h Modes Register Default 1AB h TYPE NAME Width Default DESCRIPTION Master enable for the entire VCO Subsystem 1 - Enable 0 - Disable Chip Enable is also required to set as enable mode. R/W VCO SubSys Master Enable 1 1 [1] R/W VCO Enable 1 1 [2] R/W External VCO Buffer Enable 1 0 External VCO Buffer to output stage enable. Only used when locking an external VCO. [3] R/W PLL Buffer Enable 1 1 PLL Buffer Enable. Used when using an internal VCO. EE T [0] R/W LO1 Output Buffer Enable 1 0 Enables LO1 (LO_P & LO_N pins) output buffer. R/W LO2 Output Buffer Enable 1 1 Enables the LO2 (LO2_N & LO2_P pins) output buffer [6] R/W External Input Enable 1 0 Enables External VCO input [7] R/W Pre Lock Mute Enable 1 1 Mute both output buffers until the PLL is locked R/W LO1 Output Single-Ended Enable [9] R/W LO2 Output Single-Ended Enable [10] R/W Reserved [11] R/W [23:12] R/W DA TA 0 Enables Single-Ended output mode for LO2 output 1- Single-ended mode, LO2_N pin is enabled, and LO2_P pin is disabled 0- Differential mode, both LO2_N and LO2_P pins enabled Please note that single-ended output is only available on LO2_N pin. IN AR Y 1 1 0 Reserved Charge Pump Output Select 1 0 Connects CP to CP1 or CP2 output. 0: CP1 1: CP2 Reserved 12 0 Reserved M 2.24 1 Enables Single-Ended output mode for LO output 1- Single-ended mode, LO_N pin is enabled, and LO_P pin is disabled 0- Differential mode, both LO_N and LO_P pins enabled Please note that single-ended output is only available on LO_N pin. 1 Reg 18h Bias Register Default 54C1 h PR EL I [8] SH [4] [5] BIT TYPE NAME Width Default [18:0] R/W Reserved 19 21697d 54C1h 1 0 External Input buffer BIAS bit0 1 0 External Input buffer BIAS bit1 3 0 Reserved [19] R/W [20] R/W [23:21] R/W 2.25 TRANSCEIVERS - Rx RFICs 2.23 External Input buffer BIAS bit0 External Input buffer BIAS bit1 Reserved DESCRIPTION Reserved Reg 19h Cals Register Default AAA h BIT TYPE NAME Width Default [23:0] R/W Reserved 2 2730d AAAh DESCRIPTION Reserved. Program to AB2h. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 54 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 2.26 R/W NAME Width Delta Sigma Modulator Seed 24 Default DESCRIPTION 11705611d B29D0Bh Used to program output phase relative to the reference frequency. (Exact Frequency Mode required). When not using Exact Frequency Mode and Auto seed Enable Reg06h[8] =1, Reg1Ah sets the start phase of output signal. If AutoSeed disable Reg06h[8] =0, Reg1Ah is the start phase of the signal after every frequency changel. (LO Phase = 2 x Reg1Ah/(224) IN AR Y DA TA SH EE T [23:0] TYPE PR EL I M TRANSCEIVERS - Rx RFICs BIT Reg 1Ah Seed Register Default B29D0Bh 55 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Application Information The HMC1190ALP6NE is a broadband dual channel, high dynamic range, high gain, low noise, highlinearity down converting mixer with integrated Fractional-N Integer-N PLL and VCO, designed to cover RF frequencies from 700 MHz to 3.5 GHz. The HMC1190ALP6NEs low noise and high linearity performance makes it suitable for a wide range of transmission standards, including TDD, FDD, LTE, WiMAX, CDMA,GSM, MC-GSM, W-CDMA, UMTS, TD-SCDMA applications. The HMC1190ALP6NE offers an easy-to-use and complete frequency conversion solution for diversity and MIMO receiver applications in a highly compact 6x6 mm plastic QFN package. The HMC1190ALP6NE greatly simplifies the design of diversity and MIMO receiver applications by increasing the integration level 3.1 EE T and reducing the number of required circuit elements thereby reducing cost, area, and power consumption. Principle of Operation SH HMC1190ALP6NE's single-ended RF inputs are converted into differential through the on-chip integrated baluns. The single-ended RF inputs are internally broadband matched to 50 and require only standard DC-blocking capacitors. DA TA HMC1190ALP6NE's RF inputs can be externally matched for narrow band application frequencies with a simple matching network including a series inductor, and a shunt capacitor to further improve the performance. Please refer to the application circuit for narrow band RF input matching for the detailed information. IN AR Y The HMC1190ALP6NE's IF amplifiers are designed for differential 200 output load impedance. A few external components are required at these IF outputs for the broadband frequency response as recommended in the application circuit. TRANSCEIVERS - Rx RFICs 3.0 Refer to the IF output interface section for detailed information. M The HMC1190ALP6NE requires 5V, 3.3V and 3V supply voltages and external bias voltages. Bias voltages generate reference currents for the IF and LO amplifiers. 3.3V supply voltage and the external bias voltages can be generated from 5V supply voltage to operate with a single supply. Please refer to the single supply operation section for more information. The reference currents to the IF and LO amplifiers can be disabled through SPI interface. See Enabling / 3.2 PR EL I Disabling Mixer Features section for details. Supply Number Reduction The LOVDD, VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1 and VGATE2 pins of HMC1190ALP6NE requires different supply voltages. Except LOVDD, other pin voltages i.e. VGATE1, VGATE2, LOBIAS1, LOBIAS2, VCS1, VCS2 voltages are already generated from 5.5V supply voltage on evaluation board (see application circuit). These bias voltages can be optimized by external resistors (VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1, and VGATE2). The resistor values of VCS1, VCS2 on evaluation board are 590 Ohms. LOBIAS1 and LOBIAS2 series resistor values are 270 Ohms. Refer to the VCS Interface and LOBIAS Interface section for more information. On the evaluation board, VGATE1, VGATE2 pin voltages are 5V; however VGATE1, VGATE2 pin voltages can be tuned between 4.7V and 5V for optimization of Input IP3 and conversion gain performances. After VGATE1,VGATE2 pin voltages are optimized, these pin voltages can be generated from 5V supply by changing the values of series resistors, R14 and R15. Refer to the VGATE interface section for more information. The 3 V supply voltage for the LO amplifiers can be generated from 5 V or 3.3 V supply voltages by adding For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 56 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz a series resistor (R_LOVDD) between LOVDD pin and supply voltage in the configuration shown in Figure 74. DA TA SH EE T If using a 3.3 V supply, R_LOVDD = 2.15 , and minimum power of R_LOVDD is 0.05 W Figure 74. Interface to generate 3 V for LOVDD pin from 3.3V or 5V Supply. 3.3 VGATE Interface IN AR Y TRANSCEIVERS - Rx RFICs If using a 5 V supply R_LOVDD = 14 , and minimum power rating of R_LOVDD is 0.3 W M The VGATE1, VGATE2 pins are bias pins for mixer cores. On evaluation board VGATE1, VGATE2 pin voltages are set to 5V. However voltage can be tuned between 4.7V and 5V for optimizing input IP3 and conversion gain performances for desired frequency band. Higher IIP3 values can be obtained by increasing the VGATE1, VGATE2 pin voltages but this will reduce HMC1190ALP6NEs conversion gain. Figure 77 shows the measured conversion gain and IIP3 for four values of VGATE1, VGATE2 pin voltages. Input IP3 vs. VGATE 10 8 6 31 29 27 IIP3(dBm) CONVERSION GAIN (dB) 12 PR EL I Conversion Gain vs. VGATE [1] 4 2 0 0.7 25 23 21 19 17 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) 4.7 V 4.9 V 4.8 V 5.0 V 15 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) 4.7 V 4.9 V 4.8 V 5 .0V Figure 75. Conversion Gain & IIP3 vs. RF Frequency over VGATE Pin Voltage @25C, IF =150 MHz After the VGATE voltage is tuned for optimized IIP3 and conversion gain performance, the VGATE pin [1] Balun losses at IF output ports are de-embedded. 57 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz voltage can be generated from 5V supply voltage by changing the value of series resistors, R54 and R56 from 0 Ohm to an appropriate value. shows the typical resistor values that need to be added in series with VGATE1, VGATE2 pins for different VGATE voltages.A fine tune for R54 and R56 resistors can be used if a better fit is required. Table 16. Resistor values for Different VGATE Pin Voltages 4.8 V 120 Ohms 4.9 V 56 Ohms 5.0 V 0 Ohm VCS Interface and LOBIAS Interface EE T R54=R56 174 Ohms SH 3.4 VGATE1=VGATE2 4.7 V DA TA VCS1, VCS2 pins are bias pins for IF amplifiers on each channel and set the reference currents to these IF amplifiers.The VCS voltage is generated from the 5V supply by series resistors. Higher IIP3 values can be obtained by changing the values of these series resistors R61 and R73, which will change the total supply current of the IF amplifiers which can be seen on Table 17. IN AR Y LOBIAS1, LOBIAS2 pins are bias pins for LO amplifiers and set the reference currents to these LO amplifiers. The LOBIAS voltage is generated from the 5V supply by series resistors R71 and R57. Changing LOBIAS2 voltage, changes current consumed by LOVDD pin, which can be seen at Table 18. HMC1190ALP6NEs flexible design allows users to choose best configuration for their needs. For higher power consumption, better OIP3 values can be achieved. M 8 7 6 5 4 3.2 3.5 3.6 3.9 4 VCS (V) +3.35V +3.70V +4.05V +4.40V +4.75V 28 26 24 IIP3(dBm) 9 PR EL I CONVERSION GAIN (dB) 10 TRANSCEIVERS - Rx RFICs Table 16 22 20 18 4.2 16 3.2 3.5 3.6 3.9 4 4.2 VCS (V) +3.35V +3.7V +4.05V +4.4V +4.75V Figure 76.Conversion Gain, IIP3 vs. VCS1, VCS2 and LOBIAS2 voltages at 1900 MHz RF Input. [1] shows the measured conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz. Conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz. Figure 76 [1] Balun losses at IF output ports are de-embedded. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 58 HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Table 17. VCS voltage vs IF Amplifier Currents 5.0 V IF Amp (mA) R61=R73 4.25 181 440 Ohms 4.0 159 590 Ohms 3.75 135 740 Ohms 3.5 110 880 Ohms 3.25 86 1 KOhms Table 18. LOBIAS2 voltage vs LO Amplifier Currents LOBIAS2 Pin (V) 5.0 V LO Amp (mA) 4.75 157 4.4 150 4.05 3.7 110 Ohms External RF Matching 270 Ohms 143 420 Ohms 135 580 Ohms 128 740 Ohms DA TA 3.36 3.5 R71=R57 SH LOBIAS Jumper, J12 (V) EE T VCS Pin (V) The HMC1190ALP6NEs RF inputs are internally broadband matched to 50. RF inputs can be externally matched for a specific RF frequency band of interest to further improve Input IP3 (IIP3). Matching RF inputs to a specific RF frequency band can be easily accomplished by adding a series inductor and a shunt capacitor. See Table 3 for values of the external matching components for corresponding RF frequency bands. Application circuit with the external components on RF input pins can be seen at Figure 80. IN AR Y TRANSCEIVERS - Rx RFICs VCS Jumper, J13 (V) VGATE1, VGATE2 pin voltages can be optimized for a specific RF frequency band by changing the resistor values in series with these pins. Table-1 shows the resistor values (R54, R56) for corresponding VGATE pin voltage. 12 9 6 INPUT IP3 40 38 25 36 34 20 15 CONVERSION GAIN 10 IIP3 (dBm) CONVERSION GAIN (dB) 15 30 OIP3(dBm) 18 M and Figure 79 show the measured conversion gain, IIP3 and OIP3 for 900MHz, 1900MHz and 2500MHz RF frequency bands. PR EL I Figure 77, Figure 78, 32 30 28 26 24 3 5 0 0 22 20 700 800 900 1000 1100 18 0.7 0.8 FREQUENCY (MHz) +25C +85C 0.9 1 1.1 FREQUENCY (GHz) -40C +25C +85C -40C Figure 77.Conversion gain, IIP3 and OIP3 for 900MHz RF frequency band. [1] [1] Balun losses at IF output ports are de-embedded. 59 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 30 40 25 12 20 9 15 6 10 38 36 34 OIP3(dBm) 15 IIP3 (dBm) 3 5 0 0 1800 30 28 26 24 CONVERSION GAIN 1700 32 1900 2000 2100 22 20 18 1.7 2200 FREQUENCY (MHz) 1.8 1.9 2 2.1 2.2 FREQUENCY (GHz) +85C -40C +25C +85C -40C SH +25C EE T CONVERSION GAIN (dB) INPUT IP3 Figure 78.Conversion Gain, IIP3 and OIP3 for 1900MHz RF frequency band. [1] 30 12 20 9 15 6 10 CONVERSION GAIN 3 38 36 34 OIP3(dBm) 25 IN AR Y 15 40 IIP3 (dBm) CONVERSION GAIN (dB) INPUT IP3 DA TA 18 2400 2500 2600 FREQUENCY (MHz) +85C 26 20 18 2.3 2700 2.4 2.5 2.6 2.7 FREQUENCY (GHz) -40C +25C +85C -40C M +25C 28 22 0 2300 30 24 5 0 32 TRANSCEIVERS - Rx RFICs 18 PR EL I Figure 79. Conversion Gain, IIP3 and OIP3 for 2500MHz RF frequency bands. [1] Table 19. Components for Selected Frequency Bands Tune Frequency C82 C81 C80 R55 Recommended VGATE1,2 Voltages 900 MHz 2.7 pF 8.2 nH Open 0 Ohm 5.0V 1900 MHz 1 pF 2.7 nH Open 120 Ohms 4.8V 2500MHz Open 1 nH 1 pF 120 Ohms 4.8V [1] Balun losses at IF output ports are de-embedded. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 60 HMC1190ALP6NE v00.0615 EE T SH DA TA Figure 80. Application Circuit for Narrowband RF Input Matching It is recommended to use high side LO injection for RF frequencies below 1.2 GHz for better IIP3. For instance, higher IIP3 can be obtained if LO input is driven with high side at RF=900 MHz. Please refer to Figure 81. IN AR Y TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz 31 29 27 25 M 23 PR EL I 21 19 17 15 0.7 1.1 1.5 1.9 2.2 2.6 3 3.4 3.8 FREQUENCY (GHz) High Side LO Low Side LO Figure 81. Input IP3 vs. High Side LO & Low Side LO @ VGATE=5V 61 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com HMC1190ALP6NE v00.0615 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz Input IP3 Dependence on RF Input Power The HMC1190ALP6NE accepts a wide range of RF input power. Figure 82 shows the IIP3 vs. RF input power for 1900 MHz RF and 150 MHz IF. 31 29 25 23 EE T IIP3 (dBm) 27 21 19 15 -10 -8 -6 -4 RF POWER (dBm) SH 17 -2 0 DA TA 1900 MHz Figure 82. IIP3 vs. RF Input Power, RF= 1900 MHz, IF= 150 MHz, VGATE= 4.8V 3.7 Enabling / Disabling Mixer Features IN AR Y HMC1190ALP6NE has a dual channel down converter core but it can also be configured as a single channel one. When single channel option is desired, HMC1190ALP6NEs unused IF amplifier can be disabled through SPI interface. TRANSCEIVERS - Rx RFICs 3.6 M HMC1190ALP6NE can also be used as standalone PLL/VCO. In this case all IF and LO buffer amplifiers at mixer side can be disabled through SPI interface. Value of Reg14 should be changed in order to make necessary enable/disable changes. See Table 20 for details. Table 20. Mixer Enable / Disable Function 3F4 IF2 disabled, IF1 and LO_Mixer enabled PR EL I REG14h value 3.8 3F2 IF1 disabled, IF2 and LO_Mixer enabled 3F6 IF1, IF2 and LO_Mixer disabled 3F0 IF1, IF2 and LO_Mixer enabled Using an External VCO In order to configure HMC1190ALP6NE to use with an external VCO, Register 17 needs to be configured to disable the on chip VCO and VCO to PLL path. Enable External Buffer, second CP link and External I/O switch. To make these changes Reg 17 [0:11] should be configured as 3157d. shows HMC1190ALP6NE configured as PLL alone used with External VCO HMC384LP4E. Loop Filter components are used as below. Figure 83 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com 62 HMC1190ALP6NE v00.0615 EE T SH Figure 83. Loop filter components for HMC1190ALP6NE is configured as PLL alone used with external VCO HMC384LP4E -40 DA TA -60 PHASE NOISE(dBc/Hz) -80 -100 -120 -140 IN AR Y TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.8 GHz -160 -180 1 10 100 1000 10000 M OFFSET (KHz) Figure 84. Closed Loop Phase Noise with External HMC384LP4E VCO @ 2200 MHz. PR EL I For detailed theory of operation of PLL/VCO, please refer to the "PLLs with Integrated VCOs - RF VCOs Operating Guide". 63 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or RFMG-apps@hittite.com