1
LTC1740
1740f
APPLICATIO S
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DESCRIPTIO
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FEATURES
BLOCK DIAGRA
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14-Bit, 6Msps,
Sampling ADC
The LTC
®
1740 is a 6Msps, 14-bit sampling A/D converter
that draws only 245mW from either a single 5V or dual
±5V supplies. This easy-to-use device includes a high
dynamic range sample-and-hold and a programmable
precision reference.
The LTC1740 has a flexible input circuit that allows differ-
ential full-scale input ranges of ±2.5V and ±1.25V with the
internal reference, or any full-scale input range up to
±2.5V with an external reference. The input common
mode voltage is arbitrary, though a 2.5V reference is
provided for single supply applications.
DC specifications include 1LSB typical INL, 0.5LSB typical
DNL and no missing codes over temperature. Outstanding
AC performance includes 79dB S/(N␣ +␣ D) and 91dB SFDR
at an input frequency of 2.5MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 80MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.
■
6Msps Sample Rate
■
79dB S/(N + D) and 91dB SFDR at 2.5MHz f
IN
■
Single 5V Supply or ±5V Supplies
■
Integral Nonlinearity Error: <1LSB
■
Differential Nonlinearity: <0.5LSB
■
80MHz Full-Power Bandwidth Sampling
■
±2.5V and ±1.25V Bipolar Input Ranges
■
2.5V Signal Ground Available
■
Out-of-Range Indicator
■
True Differential Inputs with 75dB CMRR
■
Power Dissipation: 245mW
■
36-Pin SSOP Package (0.209 Inch Width)
■
Telecommunications
■
Multiplexed Data Acquisition Systems
■
High Speed Data Acquisition
■
Spectral Analysis
■
Imaging Systems
4096-Point FFT
, LTC and LT are registered trademarks of Linear Technology Corporation.
DIGITAL CORRECTION
LOGIC
1740 TA01
MODE SELECT
PIPELINED 14-BIT ADCS/H
1µF
1µF0V OR –5V
1µF
1000pF
+
–
V
IN
V
CM
1µF
5V 3V TO 5V
V
DD
1µF
OV
DD
OGND
OF
D13 (MSB)
6MHz CLK
DIGITAL
OUTPUT
SENSE
V
REF
–A
IN
+
A
IN
V
SS
GND
2.250V
2.5V
REFERENCE
1
1932
V
DD
33
1µF
5V
V
DD
8
V
DD
9
2
3
4
5
30
V
SS
29 6
GND
7
GND
10
GND
34
GND
31 11
OGND
CLK
28
35
36
12
D7
D6
18
20
D0 (LSB)
BUSY
26
27
OUTPUT
BUFFERS
FREQUENCY (MHz)
0
–120
AMPLITUDE (dB)
–100
–80
–60
–40
0
0.5 1.0 1.5 2.0
1740 TA02
2.5 3.0
–20
fSMPL = 6MHz
fIN = 2.5MHz, 5VP-P
5V SUPPLY
2
LTC1740
1740f
0VDD = VDD (Notes 1, 2)
Supply Voltage (V
DD
)................................................. 6V
Negative Supply Voltage (V
SS
) ................................ –6V
Total Supply Voltage (V
DD
to V
SS
) ........................... 12V
Analog Input Voltage
(Note 3) .........................(V
SS
– 0.3V) to (V
DD
+ 0.3V)
Digital Input Voltage
(Note 3) .........................(V
SS
– 0.3V) to (V
DD
+ 0.3V)
Digital Output Voltage........ (V
SS
– 0.3V) to (V
DD
+ 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1740C ............................................... 0°C to 70°C
LTC1740I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●14 Bits
Integral Linearity Error (Note 6) 1 ±2.5 LSB
Differential Linearity Error ●–1 0.5 1.25 LSB
Offset Error (Note 7) ±15 ±60 LSB
●±80 LSB
Full-Scale Error ±30 ±75 LSB
Full-Scale Tempco I
OUT(REF)
= 0 ±15 ppm/°C
ORDER PART
NUMBER
LTC1740CG
LTC1740IG
T
JMAX
= 125°C, θ
JA
= 95°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
+AIN
–AIN
VCM
SENSE
VREF
GND
GND
VDD
VDD
GND
OGND
D13 (MSB)
D12
D11
D10
D9
D8
D7
OF
CLK
GND
VDD
VDD
GND
VSS
VSS
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
OVDD
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal 4.500V reference. Specifications are guaranteed for both
dual supply and single supply operation. (Notes 4, 5)
ABSOLUTE MAXIMUM RATINGS
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PACKAGE/ORDER INFORMATION
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CO VERTER CHARACTERISTICS
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Consult LTC Marketing for parts specified with wider operating temperature
ranges.
3
LTC1740
1740f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio 1MHz Input Signal 79.1 dB
2.5MHz Input Signal 79.0 dB
THD Total Harmonic Distortion 1MHz Input Signal, First 5 Harmonics –90 dB
2.5MHz Input Signal, First 5 Harmonics –89 dB
SFDR Spurious Free Dynamic Range 1MHz Input Signal 92 dB
2.5MHz Input Signal 91 dB
Full-Power Bandwidth 80 MHz
Input Referred Noise 0.45 LSB
RMS
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 2.475 2.500 2.525 V
V
CM
Output Tempco I
OUT
= 0 ±15 ppm/°C
V
CM
Line Regulation 4.75V ≤ V
DD
≤ 5.25V 0.6 mV/V
–5.25V ≤ V
SS
≤ –4.75V 0.03 mV/V
V
CM
Output Resistance 0.1mA ≤ I
OUT
≤ 0.1mA 8 Ω
V
REF
Output Voltage SENSE = GND, I
OUT
= 0 4.500 V
SENSE = V
REF
, I
OUT
= 0 2.250 V
SENSE = V
DD
Drive V
REF
with V
External Reference
V
REF
Output Tempco ±15 ppm/°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range V
REF
= 4.5V (SENSE = 0V) ●±2.50 V
V
REF
= 2.25V (SENSE Tied to V
REF
)●±1.25 V
External V
REF
(SENSE = 5V) ●±V
REF
/1.8 V
I
IN
Analog Input Leakage Current ●±10 µA
C
IN
Analog Input Capacitance Between Conversions 12 pF
During Conversions 4 pF
t
ACQ
Sample-and-Hold Acquisition Time 67 ns
t
AP
Sample-and-Hold Aperture Delay Time –900 ps
t
jitter
Sample-and-Hold Aperture Delay Time Jitter 0.6 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio V
SS
< (–A
IN
= +A
IN
) < V
DD
75 dB
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4)
VDD = OVDD = 5V, VSS = 0V, VREF = 4.5V, AIN = –0.1dBFS, AC coupled differential input.
TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4)
A ALOG I PUT
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DY A IC ACCURACY
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I TER AL REFERE CE CHARACTERISTICS
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4
LTC1740
1740f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V, V
SS
= 0V ●2.4 V
V
DD
= 5.25V, V
SS
= –5V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V, V
SS
= 0V ●0.8 V
V
DD
= 4.75V, V
SS
= –5V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 1.8 pF
V
OH
High Level Output Voltage 0V
DD
= 4.75V, I
O
= –10µA 4.74 V
0V
DD
= 4.75V, I
O
= –200µA●4.0 4.71 V
0V
DD
= 2.7V, I
O
= –10µA 2.6 V
0V
DD
= 2.7V, I
O
= –200µA●2.3 V
V
OL
Low Level Output Voltage 0V
DD
= 4.75V, I
O
= 160µA 0.05 V
0V
DD
= 4.75V, I
O
= 1.6mA ●0.10 0.4 V
0V
DD
= 2.7V, I
O
= 160µA 0.05 V
0V
DD
= 2.7V, I
O
= 1.6mA ●0.10 0.4 V
I
SOURCE
Output Source Current V
OUT
= 0V, 0V
DD
= 5V 50 mA
I
SINK
Output Sink Current V
OUT
= V
DD
, 0V
DD
= 5V 35 mA
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single
supply operation. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage (Note 9) 4.75 5.25 V
OV
DD
Output Supply Voltage (Note 9) 2.7 V
DD
V
V
SS
Negative Supply Voltage Dual Supply Mode –5.25 –4.75 V
Single Supply Mode 0 V
I
DD
Positive Supply Current ●47 60 mA
I
SS
Negative Supply Current ●2.3 2.6 mA
P
D
Power Dissipation ●245 300 mW
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE
Sampling Frequency ●0.05 6 MHz
t
CONV
Conversion Time ●100 135 ns
t
ACQ
Acquisition Time (Note 9) ●31 67 ns
t
H
CLK High Time (Note 9) ●20 83.3 ns
t
L
CLK Low Time (Note 9) ●20 83.3 ns
t
AP
Aperature Delay of Sample-and-Hold –900 ps
t
1
CLK↑ to BUSY↓3.5 ns
t
2
BUSY↑ to Outputs Valid 1.5 ns
Data Latency 3 Cycles
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 4)
DIGITAL I PUTS A D DIGITAL OUTPUTS
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POWER REQUIRE E TS
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TI I G CHARACTERISTICS
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5
LTC1740
1740f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4: V
DD
= 5V, V
SS
= –5V or 0V, f
SAMPLE
= 6MHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 5: Linearity, offset and full-scale specifications apply for a
single-ended +A
IN
input with –A
IN
tied to V
CM
for single supply and 0V for
dual supply.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
TI I G CHARACTERISTICS
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TYPICAL PERFOR A CE CHARACTERISTICS
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Typical INL at 6Msps Typical DNL at 6Msps S/(N + D) vs Input Frequency
and Amplitude
CODE
0
INL (LSB)
0
0.5
1.0
16384
1740 G01
–0.5
–1.0
–2.0 4096 8192 12288
–1.5
2.0
1.5
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
1740 G02
–0.6
0.6
0.8
0.2
12288 16384
INPUT FREQUENCY (MHz)
0.1
50
S/(N + D) (dBc)
55
60
65
70
80
110
1740 G03
100
75
VIN = 0dBFS
VIN = –6dBFS
VIN = –20dBFS
DUAL SUPPLIES
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
S/(N + D) vs Input Frequency
and Amplitude
INPUT FREQUENCY (MHz)
0.1
50
S/(N + D) (dBc)
55
60
65
70
80
110
1740 G04
100
75
VIN = 0dBFS
VIN = –6dBFS
VIN = –20dBFS
SINGLE SUPPLY
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
SFDR and THD
vs Input Frequency
INPUT FREQUENCY (MHz)
0.1
50
AMPLITUDE (dB)
55
65
70
75
10
95
1740 G05
60
1 100
80
85
90 SFDR
–THD
DUAL SUPPLIES
5V INPUT RANGE
A
IN
= 0dBFS
DIFFERENTIAL INPUT
6Msps
INPUT FREQUENCY (MHz)
0.1
50
AMPLITUDE (dB)
55
65
70
75
10
95
1740 G06
60
1 100
80
85
90 SFDR
–THD
SINGLE SUPPLY
5V INPUT RANGE
A
IN
= 0dBFS
DIFFERENTIAL INPUT
6Msps
SFDR and THD
vs Input Frequency
6
LTC1740
1740f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Spurious-Free Dynamic Range
vs Input Amplitude S/(N + D) and SFDR
vs Sample Frequency
INPUT AMPLITUDE (dBFS)
–50
0
SFDR (dBc AND dBFS)
50
60
70
80
90
100
dBFS
dBc
–40 –30 –20 –10
1740 G07
0
DUAL SUPPLIES
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
Spurious-Free Dynamic Range
vs Input Amplitude
INPUT AMPLITUDE (dBFS)
–50
0
SFDR (dBc AND dBFS)
50
60
70
80
90
100
dBFS
dBc
–40 –30 –20 –10
1740 G08
0
SINGLE SUPPLY
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
SAMPLE FREQUENCY (MHz)
1
AMPLITUDE (dBc)
75
80
85
56780
1740 G09
70
65
50 234
55
60
95
90
DUAL SUPPLIES
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
SFDR
S/(N + D)
S/(N + D) and SFDR
vs Sample Frequency Nonaveraged 4096 Point FFT
SAMPLE FREQUENCY (MHz)
1
AMPLITUDE (dBc)
75
80
85
56780
1740 G10
70
65
50 234
55
60
95
90
SINGLE SUPPLY
5V INPUT RANGE
DIFFERENTIAL INPUT
6Msps
SFDR
S/(N + D)
FREQUENCY (MHz)
0
0
–20
–40
–60
–80
–100
–120
–140 1.5 2.5
1740 G11
0.5 1 23
AMPLITIDE (dB)
DUAL SUPPLIES
6Msps
f
IN
= 2.5MHz, 5V
P-P
DIFFERENTIAL INPUT
Nonaveraged 4096 Point FFT
FREQUENCY (MHz)
0
0
–20
–40
–60
–80
–100
–120
–140 1.5 2.5
1740 G12
0.5 1 23
AMPLITIDE (dB)
SINGLE SUPPLY
6Msps
f
IN
= 2.5MHz, 5V
P-P
DIFFERENTIAL INPUT
IDD vs Clock Frequency ISS vs Clock Frequency
CLOCK FREQUENCY (MHz)
0
49
47
45
43
41
39
37
35 35
1740 G13
12 46
I
DD
(mA)
V
REF
= 4.5V
V
REF
= 2.25V
CLOCK FREQUENCY (MHz)
0
0
ISS (mA)
0.5
1.0
1.5
2.0
2.5
1234
1740 G14
56
7
LTC1740
1740f
OV
DD
(Pin 19): Positive Supply for the Output Logic. Can
be 2.7V to 5.25V. Bypass to GND with a 1µF to 10µF
ceramic capacitor.
BUSY (Pin 27): BUSY is low when a conversion is in
progress. When a conversion is finished and the ADC is
acquiring the input signal, BUSY is high. Either the falling
edge of BUSY or the rising edge of CLK can be used to
latch the output data.
V
SS
(Pins 29, 30): Negative Supply. Can be –5V or 0V. If
V
SS
is not shorted to GND, bypass to GND with a 1µF
ceramic capacitor.
V
DD
(Pins 32, 33): Analog 5V Supply. Bypass to GND with
a 1µF to 10µF ceramic capacitor (do not share a capacitor
with Pins 8, 9).
CLK (Pin 35): Conversion Start Signal. This active high
signal starts a conversion on its rising edge.
OF (Pin 36): Overflow Output. This signal is high when the
digital output is 01 1111 1111 1111 or 10 0000 0000 0000.
+A
IN
(Pin 1):
Positive Analog Input.
–A
IN
(Pin 2): Negative Analog Input.
V
CM
(Pin 3): 2.5V Reference Output. Optional input com-
mon mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic capacitor.
SENSE (Pin 4): Reference Programming Pin. Ground
selects V
REF
= 4.5V. Short to V
REF
for V
REF
= 2.25V.
Connect SENSE to V
DD
to drive V
REF
with an external
reference. Connect SENSE directly to V
DD
, V
REF
or GND.
Do not drive SENSE with a logic signal.
V
REF
(Pin 5): DAC Reference. Bypass to GND with a 1µF to
10µF ceramic capacitor.
GND (Pins 6, 7, 10, 31, 34): Analog Power Ground.
V
DD
(Pins 8, 9): Analog 5V Supply. Bypass to GND with a
1µF to 10µF ceramic capacitor. (Do not share a capacitor
with Pins 32 and 33.)
OGND (Pins 11, 28): Output Logic Ground. Connect to
GND.
D13 to D0 (Pins 12 to 18, 20 to 26): Data Outputs. The
output format is two’s complement.
PIN FUNCTIONS
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8
LTC1740
1740f
DIGITAL CORRECTION
LOGIC
OUTPUT
BUFFERS
1740 FBD
MODE SELECT
PIPELINED 14-BIT ADCS/H
0V OR –5V
3V TO 5V
V
CM
OV
DD
5V
V
DD
OGND
OF
D13 (MSB)
D0 (LSB)
CLK
SENSE
V
REF
–A
IN
+
A
IN
BUSY
GNDV
SS
GND
2.5V
REFERENCE
CLK
BUSY
1740 TD
ANALOG
INPUT
DATA
OUTPUT
t
CONV
t
CLOCK
t
H
t
L
NN + 1
N-3 N-2 N-1 N
N + 2 N + 3
t
ACQ
t
1
t
2
FUNCTIONAL BLOCK DIAGRA
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TI I G DIAGRA
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LTC1740
1740f
APPLICATIO S I FOR ATIO
WUUU
Conversion Details
The LTC1740 is a high performance 14-bit A/D converter
that operates up to 6Msps. It is a complete solution with
an on-chip sample-and-hold, a 14-bit pipelined CMOS
ADC and a low drift programmable reference. The digital
output is parallel, with a 14-bit two’s complement format
and an out-of-range (overflow) bit.
The rising edge of the CLK begins the conversion. The
differential analog inputs are simultaneously sampled and
passed on to the pipelined A/D. After two more conversion
starts (plus a 100ns conversion time) the digital outputs
are updated with the conversion result and will be ready for
capture on the third rising clock edge. Thus even though
a new conversion is begun every time CLK goes high, each
result takes three clock cycles to reach the output.
The analog signals that are passed from stage to stage in
the pipelined A/D are stored on capacitors. The signals on
these capacitors will be lost if the delay between conver-
sions is too long. For accurate conversion results, the part
should be clocked faster than 50kHz.
In some pipelined A/D converters if there is no clock present,
dynamic logic on the chip will droop and the power con-
sumption sharply increases. The LTC1740 doesn’t have
this problem. If the part is not clocked for 1ms, an internal
timer will refresh the dynamic logic. Thus the clock can be
turned off for long periods of time to save power.
Power Supplies
The LTC1740 will operate from either a single 5V or dual
±5V supply, making it easy to interface the analog input to
single or dual supply systems. The digital output drivers
have their own power supply pin (OV
DD
) which can be set
from 3V to 5V, allowing direct connection to either 3V or
5V digital systems. For single supply operation, V
SS
should
be connected to analog ground. For dual supply operation,
V
SS
should be connected to –5V. All V
DD
pins should be
connected to a clean 5V analog supply. (Don’t connect V
DD
to a noisy system digital supply.)
Analog Input Range
The LTC1740 has a flexible analog input with a wide
selection of input ranges. The input range is always
differential and is set by the voltage at the V
REF
pin
(Figure␣ 1). The input range of the A/D core is fixed at
±V
REF
/1.8. The reference voltage, V
REF
, is either set by the
on-chip voltage reference or directly driven by an external
voltage.
Internal Reference
Figure 2 shows a simplified schematic of the LTC1740
reference circuitry. An on-chip temperature compensated
bandgap reference (V
CM
) is factory trimmed to 2.500V.
The voltage at the V
REF
pin sets the input span of the ADC
to ±V
REF
/1.8. An internal voltage divider converts V
CM
to
2.250V, which is connected to a reference amplifier. The
reference programming pin, SENSE, controls how the
V
REF
–A
IN
+A
IN
1740 F01
V
IN
+
–
±V
REF
1.8 ADC
CORE
Figure 1. Analog Input Circuit
V
CM
SENSE
V
REF
1740 F02
–
+
R1
5k
LOGIC
2.5V
REFERENCE
2.250V
1µF
1µF
1k
TO
ADC
R2
5k
Figure 2. Reference Circuit
10
LTC1740
1740f
APPLICATIO S I FOR ATIO
WUUU
reference amplifier drives the V
REF
pin. If SENSE is tied to
ground, the reference amplifier feedback is connected to
the R1/R2 voltage divider, thus making V
REF
= 4.500V. If
SENSE is tied to V
REF
, the reference amplifier feedback is
connected to SENSE thus making V
REF
= 2.250V. If SENSE
is tied to V
DD
, the reference amplifier is disconnected from
V
REF
and V
REF
can be driven by an external voltage. With
additional resistors between V
REF
and SENSE, and SENSE
and GND, V
REF
can be set to any voltage between 2.250V
and 4.5V.
An external reference or a DAC can be used to drive V
REF
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the V
REF
pin is 1kΩ, so a buffer may be
required for high accuracy. Driving V
REF
with a DAC is
useful in applications where the peak input signal ampli-
tude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.
V
OUT
V
IN
LT1019A-2.5
5V
1740 F03a
1µF
1µF
V
REF
SENSE5V
V
CM
LTC1740
Figure 3a. Using the LT1019-2.5 as an
External Reference; Input Range = ±1.39V
1740 F03b
1µF
1µF
V
REF
LTC1740
SENSE
V
CM
2.250V
–
+
5k
5k
LTC1450
Figure 3b. Driving VREF with a DAC
Both the VCM and VREF pins must be bypassed with
capacitors to ground. For best performance, 1µF or larger
ceramic capacitors are recommended. For the case of
external circuitry driving VREF, a smaller capacitor can be
used at VREF so the input range can be changed quickly.
In this case, a 0.2µF or larger ceramic capacitor is
acceptable.
The V
CM
pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
applications it is convenient to connect A
IN–
directly to the
V
CM
pin.
Driving the Analog Inputs
The differential inputs of the LTC1740 are easy to drive.
The inputs may be driven differentially or single-ended
(i.␣ e., the A
IN–
input is held at a fixed value). The A
IN–
and
A
IN+
inputs are simultaneously sampled and any common
mode signal is reduced by the high common mode rejec-
tion of the sample-and-hold circuit. Any common mode
input value is acceptable as long as the input pins stay
between V
DD
and V
SS
. During conversion the analog
inputs are high impedance. At the end of conversion the
inputs draw a small current spike while charging the
sample-and-hold.
For superior dynamic performance in dual supply mode,
the LTC1740 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. For the best dynamic perfor-
mance, the analog inputs can be driven differentially via a
transformer or differential amplifier.
DC Coupling the Input
In many applications the analog input signal can be
directly coupled to the LTC1740 inputs. If the input signal
is centered around ground, such as when dual supply op
amps are used, simply connect A
IN–
to ground and con-
nect V
SS
to –5V (Figure 4). In a single power supply
system with the input signal centered around 2.5V, con-
nect A
IN–
to V
CM
and V
SS
to ground (Figure 5). If the input
signal is not centered around ground or 2.5V, the voltage
for A
IN–
must be generated externally by a resistor divider
or a voltage reference (Figure 6).
11
LTC1740
1740f
APPLICATIO S I FOR ATIO
WUUU
1740 F07
+A
IN
V
SS
V
IN
1µF
0V
C
C
RR
LTC1740
5V
–A
IN
V
CM
Figure 7. AC Coupling to the LTC1740. Note That the Input Signal
Can Almost Always Be Directly Coupled with Better Performance
1740 F06
+A
IN
V
SS
V
IN
1µF
2.500V
0V
5V 1.25V LTC1740
5V
–A
IN
V
REF
SENSE
Figure 6. DC Coupling a 0V to 2.5V Signal
AC Coupling the Input
The analog inputs to the LTC1740 can also be AC coupled
through a capacitor, though in most cases it is simpler to
directly couple the input to the ADC. Figure 7 shows an
example where the input signal is centered around ground
and the ADC operates from a single 5V supply. Note that
the performance would improve if the ADC was operated
from a dual supply and the input was directly coupled (as
in Figure 4). With AC coupling the DC resistance to ground
should be roughly matched for A
IN+
and A
IN–
to maintain
offset accuracy.
1740 F05
1µF
+A
IN
V
SS
V
IN
2.5V
LTC1740
5V
–A
IN
V
CM
Figure 5. DC Coupling a Signal Centered Around
2.5V (Single Supply System)
1405 F04
1µF
+A
IN
V
SS
V
IN
0V
LTC1740
5V
–5V
–A
IN
V
CM
Figure 4. DC Coupling a Ground Centered Signal
(Dual Supply System)
Differential Operation
The THD and SFDR performance of the LTC1740 can be
improved by using a center tap RF transformer to drive the
inputs differentially. Though the signal can no longer be
DC coupled, the improvement in dynamic performance
makes this an attractive solution for some applications.
Typical connections for single and dual supply systems
are shown in Figures 8a and 8b. Good choices for trans-
formers are the Mini Circuits T1-1T (1:1 turns ratio) and
T4-6T (1:4 turns ratio). For best results the transformer
should be located close to the LTC1740 on the printed
circuit board.
1740 F08a
+A
IN
V
SS
V
IN
1000pF
15Ω
15Ω
MINI CIRCUITS
T1-1T
1µF
LTC1740
5V
–A
IN
V
CM
Figure 8a. Single Supply Transformer Coupled Input
1740 F08b
+A
IN
V
SS
V
IN
MINI CIRCUITS
T1-1T
1µF
LTC1740
5V
–5V
–A
IN
V
CM
1000pF
15Ω
15Ω
Figure 8b. Dual Supply Transformer Coupled Input
12
LTC1740
1740f
APPLICATIO S I FOR ATIO
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Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of␣ 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth
must be greater than 50MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
The best choice for an op amp to drive the LTC1740 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica-
tions are most critical and time domain applications where
DC accuracy and settling time are most critical.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1740 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 80MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
For example, Figure 9 shows a 1000pF capacitor from
+A
IN
to –A
IN
and a 30Ω source resistor to limit the input
bandwidth to 5.3MHz. The 1000pF capacitor also acts as
a charge reservoir for the input sample-and-hold and iso-
lates the amplifier driving V
IN
from the ADC’s small current
glitch. In undersampling applications, an input capacitor
this large may prohibitively limit the input bandwidth.
If this is the case, use as large an input capacitance as
possible. High quality capacitors and resistors should be
+AIN
VIN
LTC1740
1740 F09
–AIN
1000pF
30Ω
Figure 9. RC Input Filter
INPUT VOLTAGE (V)
–(FS – 1LSB) FS – 1LSB
OUTPUT CODE
1740 F10
011…111
011…110
011…101
100…010
100…001
100…000
OVERFLOW
BIT
1
0
Figure 10. LTC1740 Transfer Characteristics
used since these components can add distortion. NPO and
silver mica type dielectric capacitors have excellent linear-
ity. Carbon surface mount resistors can generate distor-
tion from self-heating and from damage that may occur
during soldering. Metal film surface mount resistors are
much less susceptible to both problems.
Digital Outputs and Overflow Bit (OF)
Figure 10 shows the ideal input/output characteristics for
the LTC1740. The output data is two’s complement binary
for all input ranges and for both single and dual supply
operation. One LSB = V
REF
/(0.9 • 16384). To create a
straight binary output, invert the MSB (D13). The overflow
bit (OF) indicates when the analog input is outside the
input range of the converter. OF is high when the output
code is 10 0000 0000 0000 or 01 1111 1111 1111.
13
LTC1740
1740f
Full-Scale and Offset Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,
5.00V input range application. For zero offset error apply
–0.15mV (i.␣ e., –0.5LSB) at +A
IN
and adjust R1 until the
output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111. For full-scale adjustment, apply an input
voltage of
2.49954V (FS – 1.5LSBs) at +A
IN
and adjust R2
until the output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Digital Output Drivers
The LTC1740 output drivers can interface to logic operat-
ing from 3V to 5V by setting OV
DD
to the logic power
supply. OV
DD
requires a 1µF decoupling capacitor. To
prevent digital noise from affecting performance, the load
capacitance on the digital outputs should be minimized. If
large capacitive loads are required, (>30pF) external buff-
ers or 100Ω resistors in series with the digital outputs are
suggested.
Timing
The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 100ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 100ns after the convert
start. Thus output data can be latched on the third CLK
rising edge after the rising edge that samples the input.
Clock Input
The LTC1740 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
up with a logic gate. The clock can be driven with 5V
CMOS, 3V CMOS or TTL logic levels.
APPLICATIO S I FOR ATIO
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R2
1k
10k1µF
1740 F11
+A
IN
V
SS
V
IN
5V
–5V
–5V
LTC1740
5V
–A
IN
SENSE
V
REF
10k
24k
100Ω
R1
50k
Figure 11. Offset and Full-Scale Adjust Circuit
14
LTC1740
1740f
As with all fast ADCs, the noise performance of the
LTC1740 is sensitive to clock jitter when high speed inputs
are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
SNR = –20log (2πf
IN
t
J
)dB
where f
IN
is the frequency of an input sine wave and t
J
is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
Board Layout
To obtain the best performance from the LTC1740, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins␣ 6, 7, 10, 31, 34 (GND), Pins 11, 28 (OGND) and all
other analog grounds should be connected to this ground
plane. In single supply mode, Pins 29, 30 (V
SS
) should
also be connected to this ground plane. All bypass capaci-
tors for the LTC1740 should also be connected to this
ground plane (Figure 12). The digital system ground
DIGITAL
SYSTEM
–AIN
+AIN
1
2
1000pF
1740 F12
LTC1740
ANALOG GROUND PLANE
1µF
34
32
GNDVDD
33
VDD
31
GND
1µF
19
OVDD
1µF
5
VREF
1µF
3
VCM
11
OGND
10
GND
7
GND
6
GND
1µF
8
VDD
9
VDD
1µF
29
VSS
30
VSS
28
OGND
+
–
ANALOG
INPUT
CIRCUITRY
Figure 12. Power Supply Grounding
should be connected to the analog ground plane at only
one point, near the OGND pin (Pin 28).
The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac-
complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Supply Bypassing
High quality, low series resistance ceramic 1µF capacitors
should be used at the V
DD
pins, V
CM
and V
REF
. If V
SS
is
connected to –5V it should also be bypassed to ground
with 1µF. In single supply operation V
SS
should be shorted
to the ground plane as close to the part as possible. OV
DD
requires a 1µF decoupling capacitor to ground. Surface
mount capacitors such as the AVX 0805ZC105KAT pro-
vide excellent bypassing in a small board space. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
APPLICATIO S I FOR ATIO
WUUU
AVOID BREAKING GROUND PLANE
IN THIS AREA
PLACE NON-GROUND
VIAS AWAY FROM
GROUND PLANE AND
BYPASS CAPACITORS
ANALOG
GROUND
PLANE
BYPASS
CAPACITOR
1740 F13
LTC1740
Figure 13. Cross Section of the LTC1740 Printed Circuit Board
15
LTC1740
1740f
PACKAGE DESCRIPTION
U
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
G36 SSOP 0802
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 14 15 16 17 1813
12.50 – 13.10*
(.492 – .516)
2526 22 21 20 19232427282930313233343536
2.0
(.079)
0.05
(.002)
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
16
LTC1740
1740f
PART NUMBER DESCRIPTION COMMENTS
LTC1405 12-Bit, 5Msps Sampling ADC with Parallel Output Pin Compatible with the LTC1420
LTC1406 8-Bit, 20Msps ADC Undersampling Capability up to 70MHz
LTC1411 14-Bit, 2.5Msps ADC 5V, No Pipeline Delay, 80dB SINAD
LTC1412 12-Bit, 3Msps, Sampling ADC ±5V, No Pipeline Delay, 72dB SINAD
LTC1414 14-Bit, 2.2Msps ADC ±5V, 81dB SINAD and 95dB SFDR
LTC1420 12-Bit, 10Msps ADC 71dB SINAD and 83dB SFDR at Nyquist
LT1461 Micropower Precision Series Reference 0.04% Max Initial Accuracy, 3ppm/°C Drift
LTC1666 12-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1667
LTC1667 14-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1666
LTC1668 16-Bit, 50Msps DAC 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
LTC1741 12-Bit, 65Msps ADC Pin Compatible with the LTC1748
LTC1742 14-Bit, 65Msps ADC Pin Compatible with the LTC1748
LTC1743 12-Bit, 50Msps ADC Pin Compatible with the LTC1748
LTC1744 14-Bit, 50Msps ADC Pin Compatible with the LTC1748
LTC1745 12-Bit, 25Msps ADC Pin Compatible with the LTC1748
LTC1746 14-Bit, 25Msps ADC Pin Compatible with the LTC1748
LTC1747 12-Bit, 80Msps ADC Pin Compatible with the LTC1748
LTC1748 14-Bit, 80Msps ADC 76.3dB SNR and 90dB SFDR
LT1807 325MHz, Low Distortion Dual Op Amp Rail-to-Rail Input and Output
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPO RATION 2003
LT/TP 0603 1K • PRINTED IN USA
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