USB Battery Charger Detectors
MAX14578E/MAX14578AE
EVALUATION KIT AVAILABLE
19-5821; Rev 4; 5/14
Ordering Information/Selector Guide
General Description
The MAX14578E/MAX14578AE are USB charger detec-
tors compliant with USB Battery Charging Revision 1.1.
The USB charger-detection circuitry detects USB stan-
dard downstream ports (SDPs), USB charging down-
stream ports (CDPs), or dedicated charger ports (DCPs),
and controlS an external lithium-ion (Li+) battery charger.
The devices implement USB Battery Charging Revision
1.1-compliant detection logic including data contact
detection, D+/D- short detection, charging downstream
port identification. The MAX14578AE features an enable
(EN) input and an LDO output.
In addition, the internal USB switch is compliant to
Hi-Speed USB, full-speed USB, and low-speed USB
signals. The devices feature low on-resistance, low
on-resistance flatness, and very low capacitance. The
devices also feature high-ESD protection up to Q15kV
Human Body Model on the CD+ and CD- pins.
In addition, the MAX14578E/MAX14578AE feature Apple
and Sony charger detection that allows identification of
resistor-divider networks on D+/D-.
The MAX14578E/MAX14578AE are available in 12-bump,
0.4mm pitch, 1.3mm x 1.68mm WLP and 16-pin TQFN
packages and operate over the -40NC to +85NC extended
temperature range.
Features
S Compliant to USB Battery Charging Revision 1.1
S Data Contact Detection for Foolproof Connector
Insertion Detection
S Charging Downstream Detection
S Apple/Sony Charger Detection
S Dedicated Charger Detection
S China YD/T1591-Compliant Charger Detection
S Internal Switches Isolate the USB Transceiver
During the Charger Detection Process
S VBUS Connection Capable of 28V
S Device Status Change Interrupt
S Low Supply Current
S High-ESD Protection on CD+ and CD-
±15kV Human Body Model
±8kV IEC 6100-4-2 Contact Discharge
Applications
DSC and Camcorder
Media Players
Cell Phones
e-Book Readers
Mobile Internet Devices (MIDs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed Pad
T = Tape and reel.
PART I2CEN LDO TEMP RANGE PIN-PACKAGE TOP MARK
MAX14578EEWC+T Yes No No -40NC to +85NC12 WLP +ABW
MAX14578AEEWC+T No Yes Yes -40NC to +85NC12 WLP +ABX
MAX14578EETE+T Yes No No -40NC to +85NC16 TQFN AJA
MAX14578AEETE+T No Yes Yes -40NC to +85NC16 TQFN AJB
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
2 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
BAT, INT, SDA, SCL, CE0, CE1, CE2, EN .......... -0.3V to +6.0V
LOUT ........................................... -0.3V to (VB + 0.3V, 6V) (min)
VB ..........................................................................-0.3V to +30V
Switch Disabled or CP_ENA = 1 (Note 1)
CD+, CD- ........................................-2.1V to (VSWPOS + 0.3V)
TD+, TD- ......................................... -0.3V to (VSWPOS + 0.3V)
Switch Enabled or CP_ENA = 0 (Note 2)
CD+, CD-, TD+, TD- .......................-0.3V to (VVCCINT + 0.3V)
Continuous Current into LOUT ..................................... ±150mA
Continuous Current into Any Other Terminal .................. ±50mA
Continuous Power Dissipation (TA = +70NC)
WLP (derate 13.7mW/NC above +70NC) ................. 1096mW
TQFN (derate 20.8mW/NC above +70NC) ............... 1667mW
Operating Temperature Range ........................ -40NC to +85NC
Junction Temperature .................................................. +150NC
Storage Temperature Range ......................... -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
WLP
Junction-to-Ambient Thermal Resistance (BJA) ..........73°C/W
TQFN
Junction-to-Ambient Thermal Resistance (BJA) ..........48°C/W
Junction-to-Case Thermal Resistance (BJC) ...............10°C/W
ELECTRICAL CHARACTERISTICS
(VBAT = +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = +3.6V,
VB = +5.0V, TA = +25NC.) (Note 4)
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL CHARACTERISTICS (Note 3)
Note 1: VSWPOS = (VVCCINT or 3.3V) (min)
Note 2: VVCCINT = (VBAT, [(VB or 4.2V)(min)]) (max)
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Supply Voltage Range VBAT 2.8 5.5 V
VB3.5 28
Internal Positive Switch
Regulator VSWPOS 3.25 3.4 3.6 V
Internal Negative Switch
Regulator VSWNEG -2.06 -1.90 -1.76 V
VBAT UVLO VBATUVLO VBAT = 4.2V, VB = 0V 0.90 1.65 2.45 V
VBUS UVLO VBUSUVLO VBAT = 0V, VB = 5.5V 1.0 1.33 3.30 V
3Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
ELECTRICAL CHARACTERISTICS (continued)
(VBAT = +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = +3.6V,
VB = +5.0V, TA = +25NC.) (Note 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BAT Supply Current IBAT
MAX14578E
VBAT = +3.6V,
VB = 0V, CP_ENA = 0,
USBSWC = 0
1 2.5
FA
VBAT = +4.2V,
VB = 0V, CP_ENA = 1,
USBSWC = 1,
VSDA = VSCL = 1.8V
34.5 59
MAX14578AE
VBAT = +3.6V,
VB < VVBRAW, VEN =
+3.6V
1 2.5
VBAT = +4.2V,
VB = 0V, VEN = 0V 1.3 30
Supply current increase
when VEN = 1.6V,
VBAT = +4.2V
1.3 3.5
VB Supply Current IVB
MAX14578E
VB = +5.5V,
CP_ENA = 0,
USBSWC = 0
87 140 FA
MAX14578AE
VB = +5.5V,
VEN = 0V 190 295 FA
VB = +5.0V,
VEN = 0V 4.1 mA
VB = +5.5V,
VEN = +5.5V 75 125 FA
LOUT (LDO OUT) (MAX14578AE ONLY)
LOUT Current Limit ILOUT 95 mA
LOUT Voltage VLOUT ILOUT = 10mA, VB = 5.0V 4.87 4.94 V
ILOUT = 0mA, VB = 6.0V 4.0 5.3 5.5
LOUT Debounce Time tLOUT_DEB VB = 5.0V to VLOUT = 4.5V 20 ms
LOUT Turn-On Time 100 Fs
Themal Shutdown +141 NC
Themal Shutdown Hysteresis 20 NC
CHARGER DETECTION
VDP_SRC Voltage VDP_SRC 0.5 0.7 V
VDAT_REF Voltage VDAT_REF 0.25 0.4 V
VLGC Voltage VLGC 0.8 2.0 V
IDP_SRC Current IDP_SRC 6.6 11 FA
CD+ and CD- Sink Current ICD+_SINK
ICD-_SINK 50 150 FA
RCD Resistance RCD 200 330 500 kI
TD+ Pulldown Resistor RTD+_DWN 15 20 25 kI
4 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
ELECTRICAL CHARACTERISTICS (continued)
(VBAT = +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = +3.6V,
VB = +5.0V, TA = +25NC.) (Note 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TD- Pulldown Resistor RTD-_DWN 14.25 24.8 kI
Charger Detection Weak Sink IWEAK 0.18 FA
VBUS25 Ratio VBUS25 Reference ratio for special charger as a
percentage of VBUS voltage, VB = 5V 24 26 29 %
VBUS47 Ratio VBUS47 Reference ratio for special charger as a
percentage of VBUS voltage, VB = 5V 44 47 50 %
VBUS60 Ratio VBUS60 57.5 60.3 63.5 %
DCD M Time tMDEB All comparators 20 30 40 ms
DCD C Time tCDEB All comparators 5 ms
DCD Timer 2 s
Charger-Detect Source Time tDP_SRC_ON DCHK = 0 40 ms
DCHK = 1 625
Charger-Detect-Type
Detection Time tDP_RES_ON 120 ms
Charger-Detect Delay Time tDP_SRC_HICRNT 40 80 ms
VB Attach to CE1 and CE2
Output Time tVBSW
From VB > VVBDET or CHG_TYP_M = 1
(DCHK = 0) to CE1 and/or CE2 change 520
ms
From VB > VVBDET or CHG_TYP_M = 1
(DCHK = 1) to CE1 and/or CE2 change 1450
VB Raw-Detect Threshold VVBRAW 1.7 2.6 3.5 V
VB-Detect Threshold VVBDET 3.2 3.5 3.3 V
VB-Detect Threshold
Hysteresis VVBDET_HYS 38 50 mV
USB ANALOG SWITCHES (CD-, CD+)
Analog-Signal Range VDN2, VDP2 CP_ENA = 0 (MAX14578E) 0 VVCCINT V
CP_ENA = 1 VSWNEG VSWPOS
On- Resistance RONUSB VBAT = +3.0V, ICD+ = ICD- = 10mA,
VCD+, VCD- = 0 to +3.0V 3.3 6 I
On -Resistance Match
Between Channels DRONUSB VBAT = +3.0V, ICD+ = ICD- = 10mA,
VCD+, VCD- = +400mV 0.5 I
On -Resistance Flatness RFLATUSB VBAT = +3.0V, ICD+ = ICD- = 10mA,
VCD+, VCD- = 0 to +3.3V 0.06 0.26 I
Off-Leakage Current ILUSB(OFF)
VBAT = 4.2V, switch open, VCD+ =
VCD- = +0.3V or +2.5V; VTD+ or VTD- =
+2.5V or +0.3V
-360 +360 nA
On-Leakage Current ILUSB(ON) VBAT = 4.2V, switch closed, VCD+ or
VCD- = +0.3V or +2.5V -360 +360 nA
DIGITAL SIGNALS (INT, SCL, SDA, EN, CE0, CE1, CE2)
Input Logic-High VIH 1.4 V
Input Leakage Current IINLEAK -1 +1 FA
Input Logic-Low VIL 0.4 V
5Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Note 4: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
design and not production tested.
Note 5: Guaranteed by design; not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VBAT = +2.8V to +5.5V, VB = +3.5V to +5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = +3.6V,
VB = +5.0V, TA = +25NC.) (Note 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Open-Drain Low VODOL ISINK = 1mA 0.4 V
Output Logic-High VOH ISOURCE = 1mA VIO -
0.2 V
Output Logic-Low VOL ISINK = 1mA 0.2 V
DYNAMIC (Note 5)
Charge-Pump Delay Time tCP CP_ENA from 0 to 1 until switch on 1 ms
Analog-Switch Turn-On Time tON MAX14578E, I2C STOP to switch on,
RL = 50I 0.1 1 ms
Analog-Switch Turn-Off Time tOFF MAX14578E, I2C STOP to switch off,
RL = 50I 0.1 1 ms
Break-Before-Make
Delay Time tBBM RL = 50I, TA = +25NC > 0 Fs
Off-Capacitance COFF
TD-, TD+, applied voltage is 0.5VP-P,
DC bias = 0V, f = 240MHz; CD-, CD+
not connected to TD-, TD+
2 pF
On-Capacitance CON
TD-, TD+, applied voltage is 0.5VP-P,
DC bias = 0V, f = 240MHz; CD-, CD+
connected to TD-, TD+; RL = 50I
4.5 pF
-3dB Bandwidth BW VCD_ = 0.5VP-P 1000 MHz
Off-Isolation VISO RL = 50I, f = 20kHz, VCD_ = 0.5VP-P -60 dB
I2C TIMING SPECIFICATIONS
I2C Max Clock fI2CCLK 400 kHz
Bus Free Time Between STOP
and START Conditions tBUF 1.3 Fs
START Condition Setup Time 0.6 Fs
Repeat START Condition
Setup Time tSU:STA 90% to 90% 0.6 Fs
START Condition Hold Time tHD:STA 10% of SDA to 90% of SCL 0.6 Fs
STOP Condition Setup Time tSU:STO 90% of SCL to 10% of SDA 0.6 Fs
Clock Low Period tLOW 10% to 10% 1.3 Fs
Clock High Period tHIGH 90% to 90% 0.6 Fs
Data Valid to SCL Rise Time tSU:DAT Write setup time 100 ns
Data Hold Time to SCL Fall tHD:DAT Write hold time 0 ns
ESD PROTECTION
CD+, CD- Human Body Model ±15 kV
IEC 61000-4-2 Contact Discharge ±8
6 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Typical Operating Characteristics
(VBAT = +4.2V, VB = +5.0V, CBAT = 1FF, CVB = 1FF, unless otherwise noted.)
ANALOG-SWITCH EYE DIAGRAM
TIME (x 10-9s)
DIFFERENTIAL SIGNAL (V)
2.01.81.4 1.60.4 0.6 0.8 1.0 1.20.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0
MAX14578E toc09
LOUT LOAD REGULATION (MAX14578AE)
MAX14578E toc08
LOUT CURRENT (mA)
LOUT VOLTAGE (V)
8642
3.5
4.0
4.5
5.0
5.5
6.0
3.0
01
0
VB = 6V TA = +85°C
TA = +25°C TA = -40°C
LOUT VOLTAGE REGULATION (MAX14578AE)
MAX14578E toc07
VB SUPPLY VOLTAGE (V)
LOUT VOLTAGE (V)
6.56.05.55.04.5
3.5
4.0
4.5
5.0
5.5
6.0
3.0
4.0 7.0
ILOUT = 1mA TA = +85°C
TA = +25°C TA = -40°C
VB SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX14578AE)
MAX14578E toc06
VB SUPPLY VOLTAGE (V)
VB SUPPLY CURRENT (µA)
5.35.14.94.7
50
100
150
200
0
4.5 5.5
VBAT = +3.6V, EN = HIGH
TA = +85°C
TA = +25°C TA = -40°C
VB SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX14578E)
MAX14578E toc05
VB SUPPLY VOLTAGE (V)
VB SUPPLY CURRENT (µA)
5.35.14.94.7
50
100
150
200
0
4.5 5.5
VBAT = +3.6V, CP_ENA = 0, USBSWC = 0
TA = +85°C
TA = +25°C
TA = -40°C
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14578E toc04
BAT SUPPLY VOLTAGE (V)
BAT SUPPLY CURRENT (µA)
3.83.3
5
10
15
20
25
0
2.8 4.3
VB = 0V, CP_ENA = 0, USBSWC = 1
TA = +85°C
TA = +25°C TA = -40°C
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14578E toc03
BAT SUPPLY VOLTAGE (V)
BAT SUPPLY CURRENT (µA)
3.83.3
10
20
30
40
50
0
2.8 4.3
VB = 0V, CP_ENA = 1, USBSWC = 0
TA = +85°C
TA = +25°C TA = -40°C
BAT SUPPLY CURRENT INCREASE
vs. SUPPLY VOLTAGE
MAX14578E toc02
BAT SUPPLY VOLTAGE (V)
BAT SUPPLY CURRENT (µA)
3.83.3
2
4
6
8
10
0
2.8 4.3
TA = +85°C
TA = +25°C
VB = 0V, CP_ENA = 0, USBSWC = 0
VSDA = VSCL = 1.8V
TA = -40°C
BAT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14578E toc01
BAT SUPPLY VOLTAGE (V)
BAT SUPPLY CURRENT (µA)
3.83.3
0.5
1.0
1.5
2.0
0
2.8 4.3
VB = 0V, CP_ENA = 0, USBSWC = 0
VSDA = VSCL = 0V
TA = +85°C
TA = +25°C
TA = -40°C
7Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Typical Operating Characteristics (continued)
(VBAT = +4.2V, VB = +5.0V, CBAT = 1FF, CVB = 1FF, unless otherwise noted.)
CE_ vs. VBUS CONNECTION (MAX14578AE)
USB CHARGING DOWNSTREAM PORT
(VTD+ = 3V)
MAX14578E toc16
100ms/div
VB
5V/div
VCD+
2V/div
VCE2
5V/div
VCE1
5V/div
CE_ vs. VBUS CONNECTION (MAX14578E)
APPLE 1A CHARGER, USB COMPLIANT
(USB_CPL = 1, USBSWC = 0, VTD+ = 3V)
MAX14578E toc15
20ms/div
VB
5V/div
VCD+
2V/div
VCE2
5V/div
VCE1
5V/div
CE_ vs. VBUS CONNECTION (MAX14578E)
USB CHARGING DOWNSTREAM PORT, USB COMPLIANT
(USB_CPL = 1, USBSWC = 0, VTD+ = 3V)
MAX14578E toc14
40ms/div
VB
5V/div
VCD+
0.5V/div
VCE2
5V/div
VCE1
5V/div
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
MAX14578E toc13
BAT SUPPLY VOLTAGE (V)
LOGIC-INPUT THRESHOLD (V)
5.24.94.64.34.03.73.43.1
0.5
1.0
1.5
2.0
0
2.8 5.5
VIH
VIL
CD+/CD- LEAKAGE CURRENT
vs. TEMPERATURE
MAX14578E toc12
TEMPERATURE (°C)
CD+/CD- LEAKAGE CURRENT (nA)
603510-15
10
20
30
40
50
0
-40 85
OFF-LEAKAGE
ON-LEAKAGE
CD+/CD- FREQUENCY RESPONSE
MAX14578E toc11
FREQUENCY (MHz)
CD+/CD- FREQUENCY RESPONSE (dB)
1001
-60
-40
-20
0
-80
0.01 10,000
ON-LOSS
OFF-ISOLATION
CD+/CD- ON-RESISTANCE
vs. VCD_ VOLTAGE
MAX14578E toc10
VCD_ VOLTAGE (V)
CD+/CD- ON-RESISTANCE (Ω)
2.52.01.51.00.5
1
2
3
4
5
0
0 3.0
TA = +85°C
TA = +25°C
TA = -40°C
ICD_ = 10mA
8 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Bump Configuration
Bump Description
TOP VIEW
(BUMP SIDE DOWN)
A
B
C
() MAX14578AE ONLY.
() MAX14578AE ONLY.
*CONNECT EP TO GND.
WLP
2413
+
CD+ CD- VBINT
(LOUT)
GND SCL
(EN)
SDA
(CE0) CE1
TD+ TD- BAT CE2
MAX14578E/MAX14578AE
15
16
14
13
5
6
7
N.C.
CD+
8
TD+
N.C.
(LOUT_SNS)
INT
(LOUT)
CE2
13
SCL
(EN)
4
12 10 9
TD-
N.C.
VB
BAT
CD-
GND
EP*
N.C. CE1
2
11
SDA
(CEO)
TQFN
MAX14578E
MAX14578AE
TOP VIEW
+
PIN
NAME FUNCTION
MAX14578E MAX14578AE
TQFN-EP WLP TQFN-EP WLP
1 C1 1 C1 TD+ USB Transceiver D+ Connection
2, 3,
10, 16 —2, 3, 16 — N.C. No Connection. Not internally connected.
4 A1 4 A1 CD+ USB Connector D+ Connection
5 B1 5 B1 GND Ground
6 A2 6 A2 CD- USB Connector D- Connection
7 C3 7 C3 BAT Battery Connection Input. Connect a 1FF capacitor as close as possible
between BAT and GND.
8 A3 8 A3 VBUSB Connector VBUS Connection. Connect a 1FF capacitor as close
as possible between VB and GND for Q15kV ESD protection.
9 A4 — — INT Active-Low Interrupt Request, Open-Drain Output
— — 9 A4 LOUT +5.3V USB Transceiver VBUS Power Output. Connect a 1FF capacitor
as close as possible between LOUT and GND.
— — 10 — LOUT_SNS Connect Externally to LOUT (MAX14578AE, TQFN Only)
11 B4 11 B4 CE1 Charger-Enable Control 1, Open-Drain Output
12 C4 12 C4 CE2 Charger-Enable Control 2, Open-Drain Output
13 B3 — — SDA I2C Serial-Data Input/Output. Connect SDA to an external pullup
resistor.
— — 13 B3 CE0 Charger-Enable Control 0, Open-Drain Output
— — 14 B2 EN
Active-Low Enable Input. Drive EN low to enable the charger ID
detection and close the USB switches after charger detection is
complete.
9Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
MAX14578E Functional Diagram/Typical Application Circuit
MAX14578E
USB CHARGER DETECTION
CONTROL
LOGIC
USB
TRANSCEIVER
CD+TD+
CD-TD-
ID
D+
D-
VCC VB
1µF
PMIC/
CHARGER
MICRO-B
USB
CONNECTOR
D-
ID
GND
D+
VBUS
AUDIO CODEC/
AMPLIFIER
PROCESSOR
BAT
CE1
BATTERY
CE2
VIO
GND
1µF
INT
INT
SCLSCL
SDASDA
VIO
VIO
PIN
NAME FUNCTION
MAX14578E MAX14578AE
TQFN-EP WLP TQFN-EP WLP
14 B2 — — SCL I2C Serial-Clock Input. Connect SCL to an external pullup resistor.
15 C2 15 C2 TD- USB Transceiver D- Connection
— — — — EP
Exposed Pad (TQFN Only). EP is internally connected to GND.
Connect to a large ground plane to maximize thermal performance.
Not intended as an electrical connection point.
10 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
MAX14578AE Functional Diagram/Typical Application Circuit
MAX14578AE
MAX14544
MAX8903/MAX8934
MAX8677
USB CHARGER DETECTION
LDO
CONTROL
LOGIC
USB
TRANSCEIVER
CD+TD+
CD-TD-
ID
LOUT
D+
D-
VCC VB
1µF 1µF
SWITCH MODE CHARGER
MICRO-B
USB
CONNECTOR
D-
ID
GND
D+
VBUS
AUDIO CODEC/
AMPLIFIER
PROCESSOR
BAT
CE2
BATTERY
BATTERY
CE1 CE0
IUSB DCM USUS
CHG
VCC
GND
1µF
EN
EN
VIO
11Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Table 1. Register Map
Table 2. Detailed Register Map
ADDRESS NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x00 DEVICE ID VENDOR_ID CHIP_REV
0x01 CONTROL
1INTPOL INTEN USBSWC CP_ENA LOW_POW DCHK CHG_TYP_M USB_CHGDET
0x02 INTERRUPT CHG_TYP VBCOMP RFU DCD_T CHGRUN RFU
0x03 CONTROL
2RFU RFU DB_IDLE SUS_LOW CE_FRC CE
0x04 CONTROL
3RFU RFU RFU CDP_DET USB_CPL SFOUT_EN SFOUTASRT DCD_EXIT
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
DEVICE ID (I2C ADDRESS = 0x00)
VENDOR_ID Read Only [7:4] 0010 Vendor Identification
CHIP_REV Read Only [3:0] 0001 Chip Revision
CONTROL 1 (I2C ADDRESS = 0x01)
INTPOL Read/Write 7 0
Interrupt Polarity
0 = Active low
1 = Active high
INTEN Read/Write 6 0
Interrupt Enable. If interrupt is disabled, pending interrupts
are not cleared and the INT pin deasserts. INTEN is a
global setting to mask all interrupts.
0 = Interrupt disabled
1 = Interrupt enabled
USBSWC Read/Write 5 0
Opens/Closes USB Switch
0 = Switch open
1 = Switch closed
CP_ENA Read/Write 4 0
Charge-Pump Enable
0 = Charge pump disabled
1 = Charge pump enabled
LOW_POW Read/Write 3 1
Low-Power Mode
0 = Low-power mode disabled; oscillator/bandgap always on
1 = Low-power mode enabled; oscillator/bandgap turned
off under the following conditions: no VBUS, USBSWC = 0,
and CP_ENA = 0
DCHK Read/Write 2 0
Charger-Type Source-Detection Time
0 = DCHK, tDP_SRC_ON = 40ms
1 = DCHK, tDP_SRC_ON = 625ms
CHG_TYP_M Read/Write 1 0
Charger-Type Manual-Detection Enable. Set CHG_TYP_M
to 1 to force the internal logic to open the USB switches
and perform a charger-type detection. After the detection
state matching completes, this bit resets to 0.
0 = Charger detection disabled
1 = Force a manual charge detection
12 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Table 2. Detailed Register Map (continued)
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
USB_CHGDET Read/Write 0 1
Charger-Detection-Enable Start. Charger detection starts
with any change in VB.
0 = Charger detection disabled
1 = Charger detection enabled
INTERRUPT (I2C ADDRESS = 0x02)
CHG_TYP Read Only [7:5] 000
Output of USB Charger Detection
000 = Nothing attached
001 = USB cable attached
010 = Charging dowstream port: current depends on USB
operating speed
011 = Dedicated charger: current up to 1.8A
100 = Special charger: 500mA max
101 = Special charger: current up to 1A
110 = RFU
VBCOMP Read Only 4 0
Output of VB Comparator. Changes in VBCOMP triggers
interrupt.
0 = VB < VVBDET
1 = VB R VVBDET
RFU Read Only 3 0
DCD_T Read Only 2 0
Data-Contact Detection (DCD) Time Wait. DCD_T
generates an interrupt after a 0-to-1 transition.
0 = Data contact detection not running
1 = Data contact detection running for > 2s
CHGRUN Read Only 1 0
Charger-Detection State Machine Running. For information
only—no interrupt generated.
0 = Charger detection not running
1 = Charger detection running (DCD, dead battery, D+/D-
short)
RFU Read Only 0 0 Reserved
CONTROL 2 (I2C ADDRESS = 0x03)
DCD_EN Read/Write 7 1
DCD Enable. If DCD_EN = 1, D+/D- is tested for a short
after DCD passes. If DCD_EN = 0, DCD is skipped and
D+/D- short detection begins when VBUS is connected or
CHG_TYP_M = 1. If DCD is stuck (DCD_T) = 1, setting
DCD_EN = 0 bypasses DCD and D+/D- short detection
begins.
0 = Disabled
1 = Enabled
13Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Table 2. Detailed Register Map (continued)
Note: CP_ENA, DCHK, USB_CHGDET, DCD_EN, SUS_LOW, CE_FRC, CE, USB_CPL, SFOUT_EN, SFOUTASRT, and DCD_EXIT
can be configured to have different default values. Contact the factory for more information.
*Default value for MAX14578AE only.
FIELD NAME READ/WRITE BIT DEFAULT DESCRIPTION
RFU Read/Write 6 0
RFU Read/Write 5 0
SUS_LOW Read/Write 4 0 (1)*
Suspend Mode Selection
0 = When the charger is disabled, CE1 = CE2 = 1
1 = When the charger is disabled, CE1 = CE2 = 0
CE_FRC Read/Write 3 0
CE Outputs Force Enable
0 = CE outputs follow the charger-detection finite state
machine (FSM)
1 = CE outputs follow the CE[2:0] register regardless of the
result from the charger-detection FSM
CE Read/Write [2:0] 000
CE Outputs (CE2, CE1, CE0). If CE_FRC = 0, registers are
set by the result of charger FSM. If CE_FRC = 1, registers
are set by I2C command only.
CONTROL 3 (I2C ADDRESS = 0x04)
RFU Read/Write [7:5] 000 Reserved
CDP_DET Read/Write 4 0 0 = Normal detection
1 = Resistive detection
USB_CPL Read/Write 3 1 (0)*
USB Compliance
0 = Device is not USB compliant
1 = Device is USB compliant
SFOUT_EN Read/Write 2 0 (1)*
LOUT Enable
0 = LOUT off
1 = LOUT on as per SFOUTASRT
SFOUTASRT Read/Write 1 1
LOUT Assert Timing
0 = LOUT asserts when the charger-detection FSM
completes
1 = LOUT asserts after valid VBUS voltage detection
DCD_EXIT Read/Write 0 1
Exit Charger-Type-Detection Routine After DCD_T is Set to 1
0 = Disabled
1 = Enabled
14 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Detailed Description
The MAX14578E/MAX14578AE are USB charger detec-
tors compliant with USB Battery Charging Revision 1.1.
The USB charger-detection circuitry detects USB stan-
dard downstream ports (SDPs), USB charging down-
stream ports (CDPs), or dedicated charger ports (DCPs),
and controls an external lithium-ion (Li+) battery charger.
The MAX14578E features I2C communication, while the
MAX14578AE features an EN pin and an LDO output pin.
The internal USB switch is compliant to Hi-Speed USB,
full-speed USB, and low-speed USB signals. Both devic-
es feature low on-resistance, low on-resistance flatness,
and very low capacitance.
Input Sources and Routing
The typical Micro/Mini-USB connector has five signal
lines: USB power, two USB signal lines (D-, D+), ID line,
and ground. The USB power on the Micro/Mini-USB con-
nector connects to VB on the MAX14578E/MAX14578AE.
The two USB signal lines, D- and D+, connect to CD- and
CD+.
USB (CD-, CD+)
The MAX14578E/MAX14578AE support Hi-Speed
(480Mbps), full-speed (12Mbps), and low-speed USB
(1.5Mbps) signal levels. The USB channel is bidirectional
and has low 3.3I (typ) on-resistance and 4.5pF (typ)
on-capacitance. The low on-resistance is stable as the
analog input signals are swept from ground to VSWPOS
for low signal distortion.
LOUT LDO Output (MAX14578AE Only)
The LOUT LDO provides a 5.3V (typ) output, used to
power a USB transceiver. Most USB transceivers are
powered from a 3.3V or higher voltage that is difficult to
derive from a Li+ battery. One solution is to power the
transceivers from the USB VBUS power; however, VBUS
can rise as high as +28V in a fault condition. The LOUT
pin provides a voltage-limited supply that protects the
USB transceiver from these high voltages. When VBUS
rises above 9.0V (typ), the MAX14578AE detects an
overvoltage fault and LOUT goes to 0V. Additionally,
LOUT features a 100mA (typ) current limit to protect the
device in the event of a short circuit.
Interrupts
The MAX14578E generates an interrupt for any change in
VBCOMP, and when DBCHG or DCD_T transitions from
0 to 1. The INTEN bit in the CONTROL 1 register (0x01)
enables interrupt output. When INTEN is set to zero, all
interrupts are masked but not cleared. A read to the
INTERRUPT register (0x02) is required to clear interrupts.
Detection Debounce
To avoid multiple interrupts at the insertion of an acces-
sory and for added noise/disturbance protection, a
30ms (typ) debounce timer is present that requires an
inserted or removed state hold for the debounce time
before it sends an interrupt.
Low-Power Modes
The MAX14578E has two I2C bits in the CONTROL 1
register (0x01) dedicated to low-power operation:
LOW_POW and CP_ENA.
LOW_POW sets low-power mode. In low-power mode,
the internal oscillator is turned off under the following
conditions: no VBUS, USBSWC = 0, and CP_ENA = 0.
When enabled, all switches are high impedance (note
that no negative rail voltage can be applied).
CP_ENA controls the charge pump required for proper
operation of the analog switches. When set to disable,
no negative rail voltage can be applied. A factory default
sets CP_ENA = 0 automatically.
USB Charger Detection
The MAX14578E includes internal logic to detect if a valid
USB charger is connected. When a valid VBUS voltage is
applied to VB or when CHG_TYP_M in the CONTROL 1
register is set to 1, the MAX14578E/MAX14578AE begin
the charger-type-detection sequence (see Figure 1).
During the charger-type-detection sequence, the CD-
and CD+ switches are open, and once the sequence
completes, the switches return to their previous state.
Figure 2 shows a timing diagram for an example char-
ger-type-detection sequence.
15Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Figure 1. Charger-Type-Detection Sequence
Figure 2. Charger-Detection Timing
tMDEB
VB
DCD START
ENABLE
COMPARATORS
LOUT ENABLE (MAX14578AE)
(SFOUTASRT = 0)
CHGRUN
VVBDET DCD PASS D+/D- SHORT DEDICATED CHARGER
CHG_TYP = 011
ENABLE CHARGING DOWNSTREAM
PORT DETECTION
ENABLE STANDARD DOWNSTREAM
PORT DETECTION
tMDEB tMDEB tMDEB
tDP_SRC_ON
CHARGER CONFIGURATION
(USB SWITCH CLOSED)
CONFIGURE CE_
SPECIAL CHARGER
SONY CHARGER TEST
APPLE CHARGER TEST
DCP/CDP TEST
DCD
BEGIN DCD TEST
D+/D- SHORT TEST
DORMANT
CE_ = HI-Z
VB < VVBDET
VB < VVBDET
() MAX14578AE ONLY.
VB < VVBDET
MAX14578E: USB_CHGDET = 1
MAX14578AE: VEN = 0V
NOT DCD COMPLIANTDCD COMPLIANT
16 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Figure 3 shows D+/D- terminations for a standard USB
host/charging downstream port, an Apple charger, a
Sony charger, and a dedicated charger.
Charger-Enable Control Outputs
The MAX14578E/MAX14578AE feature digital open-drain
outputs—CE0 (MAX14578AE only), CE1, and CE2—to
control an external charger autonomously. See Table 3.
Figure 3. Standard USB Host/Charging Downstream Port, Apple Charger, Sony Charger, and Dedicated Charger
Table 3. Charger-Enable Control Outputs
Note: When CE_FRC = 1, CE[2:0] are set by an I2C command.
X = Don’t care.
VLOAD PU
3.6V
STANDARD USB
HOST CHARGING
DOWNSTREAM PORT
HLPU
300kΩ
HPD
14.25kΩ TO 24.8kΩ
D+
VLOAD PU
3.6V
HLPU
300kΩ
HPD
14.25kΩ TO 24.8kΩ
D-
VBUS
5.0V
APPLE CHARGER
ADPPU
75.0kΩ
ADPPD
49.9kΩ
D+
VBUS
5.0V
ADMPU
43.2kΩ (FOR 1A)
75.0kΩ (FOR 0.5A)
ADMPD
49.9kΩ
D-
VBUS
5.0V
SONY CHARGER
SDPPU
5.1kΩ
SDPPD
10kΩ
D+
VBUS
5.0V
SDPPU
5.1kΩ
SDPPD
10kΩ
D-
VBUS
5.0V
DEDICATED CHARGER
2MΩ
(MIN)
D+
2MΩ
(MIN)
D-
SUS_LOW EN CHG_TYP USB_CPL CE2 CE1 CE0
0 1 X X 1 1 1
1 1 X X 0 0 1
0 0 000 X 1 1 1
1 0 000 X 0 0 1
0 0 110 X 1 1 1
1 0 110 X 0 0 1
X 0 001 0 1 0 0
0 0 001 1 1 1 1
1 0 001 1 0 0 1
X 0 010 X 0 1 0
X 0 011 X 0 1 0
X 0 100 X 1 0 0
X 0 101 X 0 1 0
X 0 111 X 0 0 0
17Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
I2C Serial Interface (MAX14578E)
Serial Addressing
The MAX14578E operates as a slave device that sends
and receives data through an I2C-compatible 2-wire
interface. The interface uses a serial-data line (SDA) and
a serial-clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typi-
cally a microcontroller) initiates all data transfers to and
from the MAX14578E and generates the SCL clock that
synchronizes the data transfer. The SDA line operates as
both an input and an open-drain output. A pullup resis-
tor is required on SDA. The SCL line operates only as an
input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START condition (Figure
4) sent by a master, followed by the MAX14578E 7-bit
slave address plus a R/W bit, a register address byte,
one or more data bytes, and finally a STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high (see Figure 5). When the
master has finished communicating with the slave, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission.
Figure 4. I2C Interface Timing Details
Figure 5. START and STOP Conditions
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tSU:DAT tSU:STA
tSU:STO
tBUF
tHD:STA
tHD:DAT
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED
START CONDITION
tR
SDA
SCL
START
CONDITION
STOP
CONDITION
S P
18 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Figure 6. Bit Transfer
Figure 7. Acknowledge
Figure 8. Slave Address
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 6). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the
recipient uses to handshake receipt of each byte of
data (Figure 7). Thus, each byte transferred effectively
requires nine bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse. The SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX14578E, it generates
the acknowledge bit because the MAX14578E is the
recipient. When the MAX14578E is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX14578E has a 7-bit long slave address. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The slave address is 01011001 for read commands and
01011000 for write commands. See Figure 8.
Bus Reset
The MAX14578E resets the bus with the I2C START
condition for reads. When the R/W bit is set to 1, the
MAX14578E transmits data to the master, thus the mas-
ter is reading from the device.
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1 2 8 9
S
SDA 1ACK
SCL
MSB LSB
01 R/W
01 00
19Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Format for Writing
A write to the MAX14578E comprises the transmission
of the slave address with the R/W bit set to zero, fol-
lowed by at least one byte of information. The first byte
of information is the register address or command byte.
The register address determines which register of the
MAX14578E is to be written by the next byte, if received.
If a STOP (P) condition is detected after the register
address is received, the MAX14578E takes no further
action beyond storing the register address (Figure 9).
Any bytes received after the register address are data
bytes. The first data byte goes into the register selected
by the register address, and subsequent data bytes go
into subsequent registers (Figure 10). If multiple data
bytes are transmitted before a STOP condition, these
bytes are stored in subsequent registers because the
register addresses autoincrements.
Format for Reading
The MAX14578E is read using the internally stored reg-
ister address as an address pointer, the same way the
stored register address is used as an address pointer
for a write. The pointer autoincrements after each data
byte is read using the same rules as for a write. Thus, a
read is initiated by first configuring the register address
by performing a write (Figure 11). The master can now
read consecutive bytes from the MAX14578E, with the
first data byte being read from the register address
pointed by the previously written register address. Once
the master sends a NACK, the MAX14578E stops send-
ing valid data.
Figure 9. Format for I2C Write
Figure 10. Format for Writing to Multiple Registers
0101 001
ADDRESS = 0x58
REGISTER 0x01 WRITE DATA
S
d7 d6 d5 d4 d2 d1d3
0 = WRITE
0000 0010
REGISTER ADDRESS = 0x01
0A A
Pd0 A
S = START BIT
P = STOP BIT
A = ACK
N = NACK
d_ = DATA BIT
0101 001
ADDRESS = 0x58
REGISTER 0x01 WRITE DATA
S
0 = WRITE
0000 0010
REGISTER ADDRESS = 0x01
0A A
d7 d6 d5 d4 d2 d1 d0d3 A
REGISTER 0x02 WRITE DATA
d7 d6 d5 d4 d2 d1d3 d0 A/N P
20 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Figure 11. Format for Reads (Repeated START)
Applications Information
Charger Control
The MAX14578E charger-enable control outputs are
ideal for autonomous external charger control. Table 4
shows example connections for various Maxim chargers.
Hi-Speed USB
Hi-Speed USB requires careful PCB layout with 45I
single-ended/90I differential controlled-impedance
matched traces of equal lengths.
Power-Supply Bypassing
Bypass VB and BAT with 1FF ceramic capacitors to GND
as close as possible to the device.
Choosing I2C Pullup Resistors
I2C requires pullup resistors to provide a logic-high level
to data and clock lines. There are trade-offs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when device is not in operation. I2C specifies 300ns rise
times to go from low to high (30% to 70%) for fast-mode,
which is defined for a clock frequency up to 400kHz (see
the I2C Serial Interface (MAX14578E) section for details).
To meet the rise time requirement, choose pullup resis-
tors so that tR = 0.85 x RPULLUP x CBUS < 300ns. If the
transition time becomes too slow, the setup and hold
times may not be met and waveforms may not be rec-
ognized.
Extended ESD Protection
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges up to ±2kV
(Human Body Model) encountered during handling and
assembly. The CD- and CD+ pins are further protected
against ESD up to ±15kV (Human Body Model) and
Q8kV IEC 61000-4-2 Contact Discharge without damage.
Table 4. CE_ Outputs for Different Charger Control
() MAX14578AE only.
01010001
ADDRESS = 0x58
0000 0010
REGISTER 0x00 READ DATA
S P
01010011
ADDRESS = 0x59
S d7 d6 d5 d4 d2 d1 d0d3 P
REGISTER ADDRESS = 0x01
0 = WRITE
1 = READ
A
A
A/N
A/N
CE_
OUTPUTS OFF 100mA 500mA ISET MAX8606,
MAX8856
MAX8814,
MAX8845
SUS_LOW = 0
(CE0) 1 0 0 0 — EN
CE1 1 0 0 1 EN1 —
CE2 1 0 1 0 EN2 —
CE_
OUTPUTS OFF 100mA 500mA ISET MAX8934,
MAX8677 MAX8903
SUS_LOW = 1
(CE0) 1 0 0 0 USUS USUS
CE1 0 0 0 1 PEN1 DCM
CE2 0 0 1 0 PEN2 IUSB
21Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
The VB input withstands up to ±15kV (HBM) if bypassed
with a 1FF ceramic capacitor close to the pin. The ESD
structures withstand high ESD both in normal operation
and when the devices are powered down. After an ESD
event, the MAX14578E/MAX14578AE continue to func-
tion without latchup.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 12 shows the Human Body Model, and Figure 13
shows the current waveform it generates when dis-
charged into a low-impedance state. This model con-
sists of a 100pF capacitor charged to the ESD voltage of
interest that is then discharged into the device through
a 1.5kI resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and per-
formance of finished equipment. However, it does not spe-
cifically refer to integrated circuits. The MAX4895E assists
in designing equipment to meet IEC 61000-4-2 without
the need for additional ESD-protection components.
The major difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2, because series resistance is
lower in the IEC 61000-4-2 model. Hence, the ESD with-
stand voltage measured to IEC 61000-4-2 is generally
lower than that measured using the Human Body Model.
Figure 14 shows the IEC 61000-4-2 model, and Figure
15 shows the current waveform for IEC 61000-4-2 ESD
Contact Discharge test.
Figure 12. Human Body ESD Test Model Figure 14. IEC 61000-4-2 ESD Test Model
Figure 13. Human Body Current Waveform Figure 15. IEC 61000-4-2 ESD Generator Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
CS
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
100%
36.8%
tRL
TIME
tDL
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
00
IPEAK (AMPS)
90%
10%
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
CS
150pF
RC
50MΩ TO 100MΩ
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
tR = 0.7ns TO 1ns
30ns
60ns
t
100%
90%
10%
IPEAK (AMPS)
22 Maxim Integrated
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
12 WLP W121A1+1 21-0449
Refer to
Application
Note 1891
16 TQFN T1633+5 21-0136 90-0032
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 23
© 2014 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
USB Battery Charger Detectors
MAX14578E/MAX14578AE
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/11 Initial release —
1 2/12 Added TQFN package, corrected MAX14578E Functional Diagram/Typical
Operating Circuit, and corrected default values for MAX14578AE in Table 2
1, 2, 8, 9,
13, 22
2 9/12 Updated Package Thermal Characteristics section and VB supply current parameter
for the MAX14578A 2, 3
3 8/13 Removed USB dead-battery charging information 1, 11, 12, 13
4 5/14 Corrected typo in Ordering Information/Selector Guide that created double entry. 1
