ADVANCED INFORMATION MX29L.1610T/B 16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH EEPROM FEATURES Extended single-supply voltage range 2.7V to 3.6V for read and write JEDEC-standard EEPROM commands Endurance 100,000 cycles Fast access time: 90/120ns Optimized block architecture - One 16 Kbyte protected block(16K-block) - Two 8 Kbyte parameter blocks - One 32 Kbyte main block - Thirty-one 64 Kbyte main blocks Hardware and software data protection - Hardware Write Protection pin (WP) - Hardware Lockout bit for 16K-block - Software command data protection Software EEPROM emulation with parameter blocks Status register and RY/BY pin - For detection of program or erase cycle completion Auto Erase operation - Automatically erases any one of the sectors or the whole chip - Erase suspend capability - Fast erase time: 50ms typical for chip erase 1.0 GENERAL DESCRIPTION The MX29L1610T/B is a 16 Mbit, 3 V-only Flash memory organized as a either 1 Mbytesx16 or 512K word x32. For flexible erase and program capability, the 16 Mbits of data is divided into 35 sectors of one 16 Kbyte block, two 8 Kbyte parameter blocks, one 32 Kbyte main block, and thirty-one 64 Kbyte main blocks. To allow for simple in-system operation, the device can be operated with a single 2.7 V to 3.6 V supply voltage. Since many de- signs read from the flash memory a large percentage of the time, significant power saving is achieved with the 2.7 V VCC operation. Manufactured with MXICs ad- vanced nonvolatile memory technology, the device of- fers access times of 90 ns. The MX2911610T/B command set is compatible with the JEDEC single-power-supply flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. MXICs flash memory augments EPROM functionality with an internal state ma- chine which controls the erase and program circuitry. Auto Page Program operation - Automatically programs and verifies data at specified addresses - Internal address and data latches for 128 bytes per page Low power dissipation - 20mA active current - 20UA standby current - 1uA deep power-down current Hardware Reset pin (RP) - Reset internal state machine, and put the device into deep power-down mode Built-in 128 Bytes/64 words Page Buffer - Work as SRAM for temporary data storage - Fast access to temporary data Low Vcc write inhibit is equal to or less than 1.8V Industry standard surface mount packaging - 48-Lead TSOP Type | - 44-Lead SOP - 48-Ball CSP (0.8mm Ball Ptich) The device Status Register provides a convenient way to monitor when a program or erase cycle is complete, and the success or failure of that cycle. Programming the MX29L1610T/B is performed on a page basis; 128 bytes of data are loaded into the de- vice and then programmed simultaneously. The typi- cal Page Program time is 5ms.The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar to reading from an EPROM or other flash. Erase is accomplished by executing the Erase com- mand sequence. This will invoke the Auto Erase algo- rithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXICs advanced design technology, no preprogram is required (internally P/N:PM0S82 REV.0.2, NOV. 06, 1998=IG MX29L 16107T/B or externally). As a result, the whole chip can be typi- 1.1 PINOUTS catly erased and verified in as fast.as 200 ms. A combined feature of Write Protection pin (WP), Reset 48-TSOP (TPYE 1) 12 x 20mm pin (RP), 16K-block lockout bit, and software command sequences provides complete data protection. First, me 2 O ag software data protection protects the device from inad- az 4 45 | ors vertent program or erase. Two unlock write cycles ao |e ey oe must be presented to the device before the program or ois fy os erase command can be accepted by the device. For we 4 | on hardware data protection, the WP pin and RP pin pro- ane Mx29L1610718 a | vec vide protection against unwanted command writes due aw |i ss | 98 to invalid system bus condition that may occur during ae | 6 sf ae system reset and power-up/down sequence. Finally, a | sy ot with 16K-block lockout bit feature, the device provides ss] a} complete core security for the kernel code required for | 2 zy ae system initialization. as a4 4 The device has 128 Bytes built-in page buffer, which 44-SOP can serve as SRAM. This feature provides a conve- re fo 44 |. WE nient way to store temporary data for fast read and write. ag 3 ol a / Av 4 a1 | Ag MXICs Ftash technology reliably stores memory con- s : o a tents after 100,000 cycles. The MXICs cell is designed A 7 aa | at2 to optimize the erase and program mechanism. In addi- a3 3 a tion, the combination of advanced tunnel oxide process- 10 S 35 | ats ing and low internal electric fields for erase and pro- ao | 11 Bef ANG . : . Cet ]i12 = 33 |: BYTE gram operations produce reliable cycling. ves | 19 S&F 32] VSS oe | 4 S 31 | oatsas The highest degree of latch-up protection is achieved dao | is mo | bead with MXICs proprietary non-epi process. Latch-up pro- pat}! 17 28} DOs. tection is proved for stresses up to 100 milliamps on poe | ie bo address and data pin from -1V to VCC +1V." poio | 20 25 | pate paz |} 21 24 |. DO4 bait 22 28 VCC PIN CONFIGURATIONS SYMBOL PIN NAME 48-Ball CSP 8mm x 14mm (all Pitch=0.8mm) AO-A19 = Address Input A B C DB E F G H Q0-Q14 Data Input/Output 13 M 2 MN A CEC CC GND QI15/A-1 Q15(word mode)/LSB addr(Byte mode) 27 Al7 46 % @ @ oo a CE Chip Enable Input 3 RYBY NC AIS NO @ Qi an Ce OE Output Enable Input 4 We FP NC AIS CH OGI2 WC ow WE Write Enable 5 AQ AB AIO AIL GF O14 ON oe RP Reset/Deep Power-down 6 AI3 Al2 Al4 AI5 Al BYTE Q15/A-1 GND WP Write Protect BYTE Word/Byte Selection Input Voc Power Supply Pin (2.7V - 3.6V) GND Ground Pin RY/BY Ready/Busy pin PAN:PM0582 : : . REV. 0.2, NOV. 06, 1998 32-2Mic co MX29L1610T/B 1. 2-1 MX29L1610T/B SECTOR ARCHITECTURE (Byte Mode Addr. A-1 ~ A19) 000000-003F FF 16K bytes 000000-00FFFF 64K bytes 004000-005FFF 8K bytes 010000-01FFFF 64K bytes 006000-007FFF 8K bytes 020000-02FFFF 64K bytes 008000-00FFFF 64K bytes 030000-03FFFF 64K bytes 010000-01FFFF 64K bytes 040000-04FFFF 64K bytes 020000-02FFFF 64K bytes 050000-05F FFF 64K bytes 030000-03FFFF 64K bytes 060000-06FFFF 64K bytes 040000-04F FFF 64K bytes 070000-07FFFF 64K bytes 050000-05F FFF 64K bytes 080000-08FFFF 64K bytes 060000-06F FFF 64K bytes 090000-09FFFF 64K bytes 070000-07F FFF 64K bytes OA0000-OAFFFF 64K bytes 080000-08F FFF 64K bytes 0B0000-0BFFFF 64K bytes 090000-09F FFF 64K bytes 0COG00-OCFFFF 64K bytes 0A0000-OAFFFF 64K bytes 0D0000-0DFFFF 64K bytes 0B0000-OBFFFF 64K bytes 0E0000-OEFFFF 64K bytes 0C0000-OCFFFF 64K bytes QFO000-OF FFFF 64K bytes 0D0000-ODFFFF 64K bytes 100000-10FFFF 64K bytes QE0000-OEFFFF 64K bytes 110000-11 FFFF 64K bytes OF0000-OF FFFF 64K bytes 120000-12FFFF 64K bytes 100000-10FFFF 64K bytes 130000-13FFFF 64K bytes 110000-11 FFFF 64K bytes 140000-14FFFF 64K bytes 120000-12FFFF 64K bytes 150000-15FFFF 64K bytes 130000-13FFFF 64K bytes 160000-16FFFF 64K bytes 140000-1 4FFFF 64K bytes 170000-17FFFF 64K bytes 150000-1 S5FFFF 64K bytes 180000-18FFFF 64K bytes 160000-16FFFF 64K bytes 190000-19FFFF 64K bytes 170000-17FFFF 64K bytes 1A0000-1 AFFFF 64K bytes 180000-1 8FFFF 64K bytes 1B0000-1BFFFF 64K bytes 190000-19F FFF 64K bytes 1C0000-1CFFFF 64K bytes 1A0000-1 AFFFF 64K bytes 1D0000-1 DFFFF 64K bytes 1B0000-1 BFFFF 64K bytes 1E0000-1 EF FFF 64K bytes 1C0000-1CFFFF 64K bytes 1F0000-1F7FFF 32K bytes 1D0000-1 DFFFF 64K bytes 1F8000-1FSFFF 8K bytes 1E0000-1EFFFF 64K bytes 1FAQ00-1FBFFF 8K bytes 1F0000-1 FFFFF 64K bytes 1FC000-1FFFFF 16K bytes MX29L1610B Memory Map MX29L.1610T Memory Map P/N-PM0582 = " . REV.0.2, NOV. 06, 1998. 32-3M=ic MX29L1610T/B 1. 2-2 MX29L1610T/B SECTOR ARCHITECTURE (Word Mode Addr. AO ~ A19) 00000-01 FFF 8 K words 00000-07FFF 32 K words 02000-02FFF 4K words 08000-OFFFF 32 K words 03000-03FFF 4K words 10000-17FFF 32 K words 04000-07F FF 16 K words 18000-1FFFF 32 K words 08000-OFFFF 32 K words 20000-27FFF 32 K words 10000-17FFF 32 K words 28000-2FFFF 32 K words 18000-1 FFFF 32 K words 30000-37FFF 32 K words 20000-27F FF 32 K words 38000-3FFFF 32 K words 28000-2FFFF 32 K words 40000-47FFF 32 K words 30000-37FFF 32 K words 48000-4F FFF 32 K words 38000-3FFFF 32 K words 50000-57FFF 32 K words 40000-47FFF 32 K words 58000-5FFFF 32 K words 48000-4FFFF 32 K words 60000-67FFF 32 K words 50000-57FFF 32 K words 68000-6F FFF 32 K words 58000-5FFFF 32 K words 70000-77FFF 32 K words 60000-67FFF 32 K words 78000-7FFFF 32 K words 68000-6FFFF 32 K words 80000-87FFF 32 K words 70000-77F FF 32 K words 88000-8F FFF 32 K words 78000-7FFFF 32 K words 90000-97FFF 32 K words 80000-87FFF 32 K words 98000-9FFFF 32 K words 88000-8FFFF 32 K words A0000-A7FFF 32 K words 90000-97FFF 32 K words A8000-AFFFF 32 K words 98000-9FFFF 32 K words BO000-B7FFF 32 K words AQ000-A7FFF 32 K words B8000-BFFFF 32 K words A8000-AFFFF 32 K words C0000-C7FFF 32 K words BO0000-B7FFF 32 K words C8000-CFFFF 32 K words B8000-BFFFF 32 K words D0000-D7FFF 32 K words C0000-C7FFF 32 K words D8000-DFFFF 32 K words C8000-CFFFF 32 K words E0000-E7FFF 32 K words D0000-D7FFF 32 K words E8000-EFFFF 32 K words D8000-DFFFF 32 K words FO000-F7FFF 32 K words E0000-E7FFF 32 K words F8000-FBFFF 16 K words E8000-EFFFF 32 K words FCO00-ECFFF 4K words FO000-FFFFF 32 K words FDO00-FDFFF 4K words F8000-FFFFF 32 K words FEQO0-FFFFF 8 K words MX29L.1610B Memory Map MX29L.1610T Memory Map P/N:PMO582 REV. 0.2, NOV. 06, 1998 32-4M=Iic MX29L1610T/B BLOCK DIAGRAM RP, WP 1 ap WRITE | te CONTROL PROGRAM/ERASE 1 a STATE | OE => INPUT HIGH VOLTAGE WE Logic _| MACHINE BYTE (WSM) <---- COMMAND INTERFACE 5 REGISTER i 0 MX29L1610T/B (CIR) ADDRESS Q FLASH 8 . QI5/A-1 LATCH a ARRAY ARRAY A0-A19 SOURCE AND z HV COMMAND DATA BUFFER 8 QO . g | PASS GATE DECODER SENSE rom DATA AMPLIFIER | | Hy COMMAND J (i DATA LATCH PAGE PROGRAM DATA LATCH Q15/A-1 Q0-014 VO BUFFER P/N:PM0582 " REV. 0.2, NOV. 06, 1998 32-5=I MxX29L1610T/B Table 1 .PIN DESCRIPTIONS SYMBOL TYPE NAME AND FUNCTION AQ-A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. Q0 -Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array, status, identifier data, and page buffer in the appropriate read mode. Float to tri-state when the chip is deselected or the outputs are disabled. Q8-O14 INPUT/OUTPUT HIGH-BYTE DATA BUS:Input data during x16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled. Q15/A-1 INPUT/OUTPUT Selectes between high-byte data INPUT/OUTPUT (BYTE=HIGH) and LSB ADDRESS (BYTE=LOW) BYTE INPUT BYTE ENABLE:BYTE Low places device in x8 mode. All data is then input or output on Q0~7 and Q8~14 float. Address Q15/A-1 selectes between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address AO, then becomes the lowest order address. CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, de- coders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device. OE INPUT OUTPUT ENABLES: Gates the devices data through the output buffers during aread cycle. OE is active low. WE INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. RP INPUT RESET/DEEP POWER-DOWN: When RP is low, the device is in reset/deep power-down mode. When RP is high, the device is in standard operation. WP INPUT WRITE PROTECTION: Provides a method for locking the 16K-block, using three voltage levels (VIL, VIH, and VHH). When WP is low, the 16K-block is locked. When WP is high the 16K-block is unlocked, if the 16K-block lockout bit is disabled. When WP is at VHH, the 16K-block is unlocked. This overrides the status of the lockout bit. See Section3 for details of data-protection VCC DEVICE POWER SUPPLY (2.7V - 3.6V) GND GROUND P/N:PM0582 REV. 0.2, NOV.06, 1998 32-6M=_Iic MX29L.161 oT/B 1.3 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or. from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized below: Table2-1 MX291.1610T/B Bus Operations for Byte-Wide Mode (BYTE=VIL) Mode Notes CE OF WE RP AO Ai AS Q0-Q7 Q8-Q14 Q15/A-1 Read VIL Vil VIH VIH X X xX DOUT HighZ VIL/VIH Output Disable VIL VWIH VIH VIH X X xX High Z HighZ Xx Standby VIH_ X X VIH X X xX High Z HighZ Deep power down Xx X X VIL xX X Xx HighZ HighZ Xx Manufacturer ID VIL VIL) OVIH-_~VIH_-_=~VIL- SEOVIL_- ~VHH -COH HighZ VIL Device ID VIL VIL) VIH- VIH_ VIH_~ VIL VHH 61H(TopBoot) HighZ VIL 62H(Bottom Boot) Write VIL VIH VIL VIH X X xX DIN HighZ VIL/VIH NOTES :1. X can be VIH or VIL for address or control pins. 2. VHH = 11.5V- 12.5V. 3. QI5/A-1=VIL, Q0~Q7=D0~D7 out, Q15/A-1=VIH, Q0~Q7=D8~D15 out. Table2-2 MX291L.1610T/B Bus Operations for Word-Wide Mode (BYTE=VIH) Mode Notes CE OF WE RP AO Al AS 0-07 08-14 QI15/A-1 Read VIL VIL VIH VIH X X xX DOUT DOUT DOUT Output Disable VIL VIH VIH VIH X X xX High Z HighZ HighZ Standby VIH X x VIH X X xX High Z HighZ HighZ Deep power down xX xX x VIL xX X x HighZ HighZ HighZ Manufacturer ID VIL VIL VIH) VIH- VIL) VIL) VHH C2H GOH 0H Device ID VIL VIL) VIH VIH) VIH) VIL VHH 61H(Top Boot) 00H OH 62H(Bottom Boot) Write VIL VIH VIL VIH X X xX DIN DIN DIN NOTES :1..X can be VIH or VIL for address or control pins. 2. VHH = 11.5V- 12.5V. PM PAN:PM0582 32-7 REV. 0.2, NOV. 06, 1998M=Ic 1.4 WRITE OPERATIONS The Command Interface Register (CIR) is the interface between the microprocessor and the internal chip control- ler. Device operations are selected by writing specific address and data sequence into the CIR, using standard microprocessor write timings. Writing incorrect data value or writing them in improper sequence will reset the de- vice to the read mode.(read array or read buffer) Table 3 defines the valid command sequences. Note that the Erase Suspend (BOH) and Erase Resume (30H) are valid only while an erase operation is in progress and will be TABLE 3. COMMAND DEFINITIONS MxX291L1610T/B ignored in other circumstance. There are four read modes: Read Array, Read Silicon ID, Read Status Reg- ister, and Read Page Buffer. For Program and Erase inform the internal state machine that a program or erase sequence has been requested. During the execution of program or erase operation, the state machine will con- trol the program /erase sequence. After the state ma- chine has completed its task, it will set bit 7 of the Sta- tus Register (SR. 7) to a "1", which indicates that the CIR can respond to the full command set. Command Read/ | Silicon Page/Byte | Chip Block |Erase Erase Sleep Se quence Reset | IDRead | Program | Erase | Erase |Suspend | Resume | Mode Bus Write 1 4 4 6 6 3 3 3 Cycles Required First Bus Addr | XXXXH| 5555H 5555H 5555H | 5555H |5555H 5555H =| S555H Write Cycle Data | FOH AAH AAH AAH | AAH |AAH AAH AAH Second Bus Addr | RA 2AAAH | 2AAAH 2AAAH | 2AAAH/2AAAH | 2AAAH | 2AAAH Write Cycle Data | RD 55H 55H 55H 55H =| 55H 55H 55H Third Bus Addr 5555H 5555H 5555H | 5555H /5555H 5555H | 5555H Write Cycle Data 90H ~=-| AOH 80H 80H BOH DOH COH Fourth Bus Addr OOH/01H | PA 5555H | 5555H Read/Write Cycie | Data C2H/61H | PD AAH_ | AAH C2H/62H Fifth Bus Addr 2AAAH | 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H | SA Write Cycle Data 10H 30H P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-8M=Ii MxX291L.1610T/B COMMAND DEFINITIONS(continue Table 3.) Command Block Block Lock Status Read Clear Sequence Lock Unlock Read Status Register | Status Register Bus Write 6 6 4 3 3 Cycles Required First Bus Addr 5855H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H 55H Third Bus Adar 5555H 5555H 5555H 5555H 5555H Write Cycle _| Data 60H 60H 90H 70H 50H Fourth Bus Addr 5555H 5555H Read/Write Cycle | Data AAH AAH C2H/00H Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr SA SA Write Cycle Data 20H 40H Notes: 1.Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AO to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. __ PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the block to be erased. The combination of A12 -- A19 will uniquely select any block. 4. RD = Data read from location RA during a read operation. __ PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 5. Erase can be suspended during sector erase with Addr = dont care, Data = BOH 6. Erase can be resumed after suspend with Addr = don't care, Data = 30H. 7. Clear Buffer set all buffer data to 1. 8. Only Q0O~Q7 command data is taken, Q8~Q15=Don't care P/N:PMO0582 REV. 0.2, NOV. 06, 1998 32-9M=ic 2.0 DEVICE OPERATION 2.1 SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. This mode is intended for use by programming equipment for the purpose of automati- cally matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VHH (11.5V~12.5V) on address pin AQ. Two iden- tifier bytes may then be sequenced from the device out- puts by toggling address AO from VIL to VIH. All ad- dresses are dont cares except AO and A1. MX29L1610T/B The manufacturer and device codes may also be read via the command register, for instances when the MX29L1610T/B is erased or programmed in a system without access to high voltage on the A9 pin. The com- mand sequence is illustrated in Table 3. Following the command write, a read cycle with AO = VIL retrieves the manufacturer code of C2H. A read cycle with AQ = VIH returns the device code . MX29L1610T Device Code =61H, MX29L1610B Device Code = 62H To terminate the operation, it is necessary to write the Read/Reset command sequence into the CIR. Table 4. MX291L.1610T/B Silion ID Codes and Verify Sector Protect Code Type A,-A, A, A, Code(HEX) DQ, DQ, DQ, DQ, DQ, DQ, DQ, Da, Manufacturer Code xX VIL VIL C2H 1 1 0 0 0 0 1 0 MX29L1610T DeviceCode X VIL VIH 61H 1 0 0 0 0 1 0 1 MX29L1610B Device Code X VIL VIH 62H 1 0 0 0 Oo 61 0 0 Verify 16K-Block Protect* SA VIH_ VIL C2H* 1 1 0 0 0 0 1 0 * Outputs C2H if 16K byte-block is protected (lockout bit is enabled), OOH otherwise. ** Only the 16K byte-Block has protect-bit verify feature. MX29L1610T Manufacter Code=C2H, Device Code=61H when BYTE=VIL. MX29L1610B Manufacter Code=C2H, Device Code=62H when BYTE=VIL. MX29L1610T Manufacter Code=00C2H, Device Code=0061H when BYTE=VIH. MX29L1610B Manufacter Code=00C2H, Device Code=0062H when BYTE=VIH. 2.2 READ/RESET COMMAND The read or reset operation is initiated by writing the Read/Reset command sequence into the command reg- ister. Microprocessor read cycles retrieve array data from the memory. The device remains ready for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/re- set state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value en- sures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29L1610T/Bis accessed like an EPROM. When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the Read/Reset command is not valid when program or erase is in progress. P/N:PMO582 32-10 REV. 0.2, NOV. 06; 19982.3 PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program command AQH. Any attempt to write to the device with- out the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be writ- ten to the device. After three-cycle command sequence is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page. 2.3.1 BYTE-WIDE LOAD/WORD-WIDE LOAD Byte(word) loads are used to enter the 128 bytes (64 words) of a page to be programmed or the software codes for data protection. A byte load (word load) is performed by applying a low pulse on the WE or CE input with CE or WE low respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determinded (BYTE=VIL or VIH is latched) on the falling edge of the WE (or CE) during the 3rd command write cycle. 2.3.2 PROGRAM Any page to be programmed should have the page in the erased state first, ie. performing sector erase is sug- gested before page programming can be performed. The device is programmed on a page basis. If a byte of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simulta- neously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same MX29L1610T/B manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) of the preceding byte. A6 to A18 specify the page address, i.e., the de- vice is page-aligned on 128 bytes boundary. The page address must be valid during each high to low transition of WE or CE. A-1 to A5 specify the byte address within the page The byte may be loaded in any order; se- quential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the inter- nal programming period will start. The load period will also end if the same address is consecutively loaded twice. The first data and address will be treated as normal data to be progammed. The second data needs to be "00" to terminate the load cycle. Other numbers besides "00" are reserved for future use. The status of program can be determined by checking the Status Register. While the program operation is in progress, bit 7 of the Status Register (SR. 7) is "0". When the Status Register indicates that program is complete (when SR. 7 = 1), the Program Status bit should bechecked to verify that the program operation was suc- cessful. If the program operation was unsuccessful, SR. 4 of the Status. Register will be set to "1" to indicate a program failure. The Status Register should be cleared before attempting the next operation. 2.4 CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the Chip Erase command 10H. Chip erase does not require the user to program the device prior to erase. The 16K-Block will not be erased if it is protected (16K-Block Lockout bit enabled). The Auto Chip Erase begins on the rising edge of the last WE pulse in the command sequence and termi- nates when the status on SR.7 is "1". While the erase sequence is in progress, SR.7 of the Status Register is "0". When erase is complete, the Erase Status bit should be checked. If the erase operation was unsuccessful, SR.5 of the Status Register is set to a "1" to indicate an erase failure. Clear the Status Register before attempt- ing the next operation. P/N:PM0582 32-11 REV. 0.2, NOV. 06, 1998M=Ic 2.5 BLOCK ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command- 30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the ris- ing edge of WE. Only one sector can be erased at a time. Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The AutomaticBlock Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on SR.7 is "1". When erasing a block, the remaining unselected blocks are unaffected. During the execution of the Block Erase command, only the Erase Suspend and Erase Resume commands are allowed. The Erase Suspend/Resume command may be issued as many time as required. Similar to the Chip Erase mode, the Status Register should be checked when erase is complete. Table5. Status Register Bit Definition MX29L1610T/B 2.6 ERASE SUSPEND AND RESUME The Erase Suspend command is provided to allow the user to interrupt an erase sequence and then read data from a block other than that which is being erased. This command is applicable only during the erase operation. During the erase operation, writing the Erase Suspend command to the CIR will cause the internal state ma- chine to pause the erase sequence at a predetermined point. The Status Register will indicate when the erase operation has been suspended. Once in erase suspend, a Read Array command can be written to the CIR in order to read data from blocks not being erase suspended. The only other valid com- mands during erase suspend are Erase Resume and Read Status Register commands. Read Page Buffer command, however, is not applicable during erase sus- pend. To resume the erase operation, the Erase Resume command 30H should be written to the CIR. Another Erase Suspend command can be written after the chip has resumed erasing. WSMS ESS ES PS SLP SLK 7 6 5 4 2 1 SR.7 =WRITE STATE MACHINE STATUS(WSMS) NOTE: 1 = Ready State machine bit must first be checked to determine Pro- 0 = Busy gram or Erase completion, before the Program or Erase SR.6 =ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 =ERASE STATUS 1 = Error in Erase 0 = Successful Erasure SR.4 =PROGRAM STATUS 1 = Error in Page/Byte Program 0 = Successful Page/Byte Program SR.2 =SLEEP STATUS 1 = Device in sleep mode 0 = Device not in sleep mode SR.3 = 0 SR.1 = Boot sector lock status 1: lock, 0: unlock Others = Reserved for future enhancements Status bits are checked for success. When Erase Suspend is issued, state machine halts ex- ecution and sets both WSMS and ESS bits to "1," ESS bit remains set to "1" until an Erase Resume command is issued. When this bit set to "1," state machine has applied the maximum number of erase pulses to the device and is still unable to successfully verify erasure. When this bit is set to "1," state machine has attempted but failed to program page data. When this bit is set to "1", the device is in sleep mode (deep power-down). Writing the Read Array command will wake up the device, and the device will return to standby. P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-122.7 STATUS REGISTER The device contains a Status Register which may be read to determine when a Program or Erase operation is complete, and whether that operation completed suc- cessfully. The Status Register may be read at any time by writing the Read Status command to the command interface. After writing this command, all subsequent Read operations output data from the Status Register until another command is written to the command interface. A Read Array command must be written to the command interface to return to the read array mode. The Status Register bits are output on DQ[0:7]. In the word-wide(x16) mode the upper byte, DQ(8:15) is set to OOH during a Read status command, in the byte- wide mode, DQ(8:14) are tri-stated and DQ15/A-1 re- tains the low order address function. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the Status Register change while reading the Status Register. CE or OE must be toggled with each subsequent status read, or the com- pletion of a Program or Erase operation will not be evi- dent from the Status Register. When the state machine is active, this register will indi- cate the status of the state machine, and will also hold the bits indicating whether or not the state machine was successful in performing the desired operation. MX29L1610T/B 2.7.1 CLEARING THE STATUS REGISTER The state machine sets status bits 4 through 7 to "1", and clears bits 6 and 7 to "0", but cannot clear status bits 4 and 5 to "0". Bits 4 and 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The Status Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Once an error occurred, the command Interface only responds to clear Status Register, Read Status Register and Read Array. To clear the Status Register, the Clear Status Register command is written to the command interface. Then, any other command may be issued to the command interface. Note, again, that before read cycle can be initiated, a Read Array command must be written to the command interface to specify whether the read data is to come from the Memory Array, Status Register, Page Buffer, or silicon ID. 2.8 SLEEP MODE The MX29L1610T/B features a sofware controlled low power modes: Sleep modes. Sleep mode is allowed during any current operations except that once Suspend command is issued, Sleep command is ignored. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to Table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consumed is diffusion leakage, tran- sistor subthreshold conduction, input leakage, and out- put leakage. The Steep command aliows the device to complete its current operations before going into Sleep mode. Dur- ing Sleep mode, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit SR.2 will indi- cate that the device in the sleep mode. The device is in read SR. mode during sleep mode. Writing the Read Array command wakes up the device out of sleep mode. SR.2 is reset to "0" and device re- turns to standby current level. PAN:PMOS82 32-13 REV.0.2, NOV.06, 1998M=Ic 3.0 DATA PROTECTION The MX29L1610T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device auto- matically resets the internal state machine in the Read Array made. Also, with its control register architecture, alteration of the memory contents only occurs after suc- cessful completion of specific multi-bus cycle command sequences. The device also incorporates several features to pre- vent inadvertent write cycles resulting from VCC power- up and power-down transitions or system noise. 3.1 16K-BLOCK LOCKING The MX29L.1610T/B features hardware 16K-Block protec- tion. This feature will disable both program and erase operations in the 16K-Block. The block protection fea- ture is enabled using system software by the user (Re- fer to Table 3). The device is shipped with 16K-Block unprotected. Alternatively, MXIC may protect 16K-Biock in the factory prior to shipping the device. 3.1.1 LOCK BLOCK To active this mode, a six-bus cycle operation is required. There are two "unlock" write cycles. These are followed by writting the "set-up" command. Two more unlock write cycles are then followed the Lock Sector command 20H. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is "1" at which time the device stays at the read mode. 3.1.2 LOCK STATUS READ To verify the Protect status of the 16K-Block, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from addressSA02H(See Table3) retrieves the Manufacturer code of (C2H in byte mode, 00C2H in word mode) if the 16K-Block is protected. If the 16K- Block is unprotected, (OOH in byte mode, O000H in word mode) will be read instead. To terminate the operation, it is necessary to write the Read/Reset command se- quence into the CIR. MxX29L.161 OoT/B The lock status information can also be retrieved by read- ing SR.. The SR.1 ="1" if 16K-Block is locked. The SR.1 ="0" if 16K-Block is unlocked. A few retries are required if Protect status can not be verified successfully after each operation. Execute lock bit protection operation three additional times after protect bit is verified successfully to guaran- tee lock bit status under all conditions. 3.2 HARDWARE PROTECTION Protection for parameter blocks and main blocks can be achieved using combinations of RP and WP pins. 3.2.1 RP = VIL FOR COMPLETE PROTECTION For complete data protection of all blocks, the RP can be held low. 3.2.2 WP = VIL FOR 16K-BLOCK LOCKING When WP = VIL, the 16K-block is locked, while all other blocks remain unlocked in this condition and can be programmed or erased normally. 3.2.3 WP = VHH FOR 16K-BLOCK UNLOCKING lf WP = VHH, the 16K-Block is unlocked and can be programmed or erased. Note that this feature will over- ride the 16K-Block Lock bit protection. 3.2.4 WP = VIH FOR REGULAR BLOCK UNLOCKING lf WP = VIH and RP = VIH, all the regular blocks (pa- rameter blocks and main blocks) are unlocked and can be programmed or erased. In this condition, whether the 16K-Block is locked is dependent on the 16K-Block Lock bit. If the 16K-Block Lock bit is enabled, then the 16K-Block is still protected; otherwise, it is unlocked. The following truth table clearly defines the write protec- tion methods. P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-14=I MX291 1610T/B Table 5. WRITE PROTECTION TRUTH TABLE Figure 1. AUTO. PAGE PROGRAM FLOW CHART FOR MX29L.16107/B RP wpe 16K-Block Write Protection Provided Lockout bit 16K-Block Regular Block VIH == VHH xX unlocked unlocked VIL x locked locked Write Program Cmd Sequence x ViH VIL x locked unlocked ' VIH VIH 1 locked unlocked Write Program 0. VIH VIH 0 unlocked unlocked 3.3 LOW VCC WRITE INHIBIT Loading End? To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO( typically 1.8V). if VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. YES (rmea >) 3.4 WRITE PULSE "GLITCH" PROTECTION e Noise pulses of less than 5ns (typical) on CE or WE will (Page Program Completed) not initiate a write cycle. 3.5 LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. P/N:PM0582 REV.0.2, NOV.06, 1998 32-15M=Ic MX29L.1610T/B Figure 2, AUTO ERASE FLOW CHART START ! Write Erase Cmd Sequence Y Read Status Register Erase Suspend Flow (Figure 3.) YES YES NO ' P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-16M=IGC oS MxX291L1610T/8 Figure 3. ERASE SUSPEND/ERASE RESUME Figure 4. 16K-BLOCK PROTECTION FLOW FLOW CHART CHART : Write 16K-Biock Protect Cmd Sequence Read Status Register YES Sector Protect Completed Read Status Register NO ( Erase Completed ) Erase Suspended Figure 5. VERIFY 16K-BLOCK PROTECT ! FLOW CHART Write FOH Y START Read Array Write Varify-Protection and Sequence Read Protect Status Y Note: Write 30H 1. Protect Status: Data Outputs (C2H in byte mode, 0OC2H in word mode) if block is protected(lockout bit is enabled). Data Outputs (00H in byte mode, O0GOH in word mode) otherwise 2. Silicon ID can be read via this Fiow Chart. Erase Resumed Refer to Table 4, 3. SR1 also contains the lock bit information Refer to Table 5. Done Reading YES P/N:PM0582 REV. 0.2, NOV. 06, 1993 32-175.0 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Temperature -40 Cto85 C Storage Temperature -65 Cto 125 C Applied Input Voltage -0.5V to VCC + 0.5 Applied Output Voltage -0.5V ta VCC + 0.6 VCC to Ground Potential -0.5V to 4V AS, WP -0.5V to 12.5V CAPACITANCE TA = 25C, f = 1.0 MHz MxX29L.1610T/B OPERATING RANGES VALUE RATING Ambient Temperature -40 Cto85 C Vcc Supply Voltage 2.7V to 3.6V NOTICE: 1.Thig document contains information on product in the dsign phase of development. Revised information will be published when the product is available. 2.Specifications contained within the following tables are subject to change. WARNING: Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended period may affect reliability. SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS eh. DEVICE : 2.7KW UNDER [TT <I 0 trv TEST | | bog Ok DIODES = IN3064 | = 6.2KW OR EQUIVALENT CL = 35 pF SWITCHING TEST WAVEFORMS - 2.4V : oy 2.0V TEST POINTS > 1BV _f \ 0.8V 0.45V INPUT , OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are 5ns. P/N:PMO0S82 REV. 0.2, NOV. 06, 1998 32-18M=Iic. | MX29L.1610T/B 5.1 DC CHARACTERISTICS Vcc = 2.7V to 3.6V SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load 1 . 1... uA VCC = VCC Max Current : VIN = VCC or GND ILO Output Leakage 1 10 uA VGC = VCC Max Current VIN = VCC. or GND ISB1 VCC Standby 1 20 50 uA VCC = VCC Max Current(CMOS) CE=VCC 0.2V ISB2 VCC. Standby 1 2 mA VCC = VCC Max Current(TTL) CE =VIH ICC VCC Read 1 20 35 mA VCC = VEC Max Current f = 10MHz, IOUT = 0 mA Icc2 VCC Erase 1,2 5 mA CE = VIH Suspend Current Block Erase Suisperided | ICC3 VCC Program 1 15 30 mA Program in Progress Current Icc4 VCC Erase Current 1 15 30 mA Erase in Progress IPPD VCC Deep Power-down 1 8 uA VCC = VCC Max Current .. AP = VIL. - VIL Input Low Voltage 3 -0.3 0.6 Vv VIH _ Input High Voltage 4 0.7xVCC VCC+0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA, Vee = Vcc Min VOH Output High Voltage 2.4 Vv IOH = -100uA, Voc = Vcc Min NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.0V, T= 25 C. These currents are valid for all product versions (package and speeds). 2. ICC2 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC2 and ICC1. 3. VIL min. = -1.0V for pulse width is equal to or less than 50ns. VIL min. = -2.0V for pulse width is equal to or less than 20ns. 4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. if VIH is over the specified maximum value, read operation cannot be guaranteed. P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-19Mic MxX29L1610T/Bs8 5.2 AC CHARACTERISTICS READ OPERATIONS 29L1610T/B-90 29L1610T/B-12 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 90 120 ns CE=OE=VIL tCE CE to Output Delay 90 120 ns OEeVIL tOE SE to Output Delay 60 60 ns CE=VIL tDF(1) OE High to Output Delay 0 55 0 55 ns CE=VIL tOH Address to Output hold 0 90 0 ns CEZOE=VIL tBACC _BYTE to Output Delay 50 120 ns CE=OE=VIL tBHZ BYTE Low to Output in HighZ 55 ns CE=VIL . TEST CONDITIONS: NOTE: 1. tDF is defined as the time at which the output achieves the * Input pulse levels: 0.45V/2.4V open circuit condition and data is no longer driven. + Input rise and fall times: 5ns * Output load: 1TTL gate+35pF Including scope and jig) + Reference levels for measuring timing: 1.5V Figure 6.1 READ TIMING WAVEFORMS Standby Device and Outputs Enabled Standby address selection Data valid VIH ADDRESSES eee ADDRESSES STABLE vit GE VIL MN fe = vit OE aq OF VIH / WE VIL a 0E ~ 1CE ~ = tOH ~ VOH HIGH Z HIGH Z DATA OUT & e{ Data out valid mye VOL ~ tACC - P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-20M=Ic . MX29L16107T/B Figure 6.2 BYTE TIMING WAVEFORMS VIH 4 . ADDRESSES ADDRESSES STABLE oer ed VIL 14 VIH CE VIL / | \ viL ; Of ' 1DF ~~ - we tBACC ~ VIH ~ ~ : t0E 1 BYTE VIL : (CE ~ we! 10H Lg VOH HIGH Z Te Lll ' 5 5 \ HIGH Z DATA(DQ0-DQ7) Data Output ' Data O ( VOL TWA xX ata Output / tACG tBHZ VOH ~ ~ HIGH Z DATA(DQ8-DQ15) HIGH Z CELE ata opt p= VOL P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-21TY | ee MX29L16107T/B 5.3 AC CHARACTERISTICS -- WRITE/ERASE/PROGRAM OPERATIONS 29L1610T/B-9029L1610T/B-12 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. UNIT two Write Cycle Time 90 120 ns tAS Address Setup Time 0 0 ns tAH Address Hold Time 60 60 ns tDS Data Setup Time 50 50 ns {DH Data Hold Time 10 10 ns s0ES Output Enable Setup Time 0 0 ns tCES CE Setup Time 0 0 ns tGHWL Read Recover Time Before Write 0 0 ns tCS CE Setup Time 0 0 ns tCH CE Hold Time 0 ) ns tWwP Write Pulse Width 60 60 ns tWPH Write Pulse Width High 40 40 ns tBALC Byte Address Load Cycle 0.2 30 0.2 30 us tBAL Byte Address Load Time 100 100 us tSRA Status Register Access Time 120 150 ns tCESR CE Setup before S.R. Read 100 100 ns tPHWL RP High Recovery to WE GoingLow 1 1 us VCS VCC Setup Time 2 2 us Figure 7. COMMAND WRITE TIMING WAVEFORMS CE 1cH ~ OE ~ - ADDRESSES voc ~ wes =o NOTE:BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. P/N:PM0S82 REV.0.2, NOV. 06, 1998 32-22MEIGS wixzerisi0T/e Figure 8. AUTOMATIC PAGE PROGRAM/WRITE PAGE BUFFER TIMING WAVEFORMS Byte offset A0~AS 55H AAH 55H address AB~A14 ; 55H 2AM 55H x Page Address 2"* tAS tAH Page Address 2** A15~A19 iwc tBALC IBAL nO Oe WP tWPH <_< ay A tCES <> OE (DS IOH * _ ~ SRA Write DATA AAH 55H AOH/EO (taste SAD tPHWL -~aP> RP ~ NOTE: 1.Please refer to SECTION 2.3 for detail page program operation. **2.Page address is not required for Write Page Butter P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-23M=ic MxX291L.1610T/B Figure 9. AUTOMATIC BLOCK/CHIP ERASE TIMING WAVEFORMS AO~AT4 x 5555H x 2AAAH x 5555H \ 5555H x 2AAAH x "15555 Veg tAS tAH A12~A19 WP IWPH __ -._ > <P NI NS VS VS VS VN ae tCES Pd OE _/ \ fo StH : - a {SRA <_ > DATA { aH yon 55H X 80H yan AAH WH 55H Gonit0%)("_ sp) tPHWL a - RP _ NOTES: *1."X" means "don't care in this diagram **2."SA" means Block Address"(required for Block Erase only) P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-24M=ic MX29L1610T/B 5.4 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS (Alternate CE Controlled) 29L1610T/B-90 29L1610T/B-12 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. UNIT twc Write Cycle Time 120 150 ns tAS Address Setup Time 0 0 ns tAH Address Hold Time 60 60 ns tDS Data Setup Time 50 50 ns tDH Data Hold Time 40 10 ns tOES Output Enable Setup Time 0 0 ns tCES CE Setup Time 0 0 ns tGHWL Read Recover TimeBefore Write 0 0 ns tWS WE Setup Time 0 0 ns tWH WE Hold Time 0 0 ns tCP CE Pulse Width 60 60 ns tCPH CE Pulse Width High 40 40 ns tvCS VCC Setup Time 2 2 uA P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-25=I. . a MX29L.16107/B8 Figure 10. COMMAND WRITE TIMING WAVEFORMS (Alternate CE Controlled) NE , , : (WH WE . 7 , ~ ~ tOES . * tws OE ~t ~ two ~t ~ CE : tGHWL ~ ICPH _ _ tcp _ ~ ADDRESSES tDS tDH DATA HIGH Z oN (D/Q) = vec _/ ves -_ > NOTE: 1. BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. 2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world applicaton, BYTE oin should be either static high(word mode) or static low(byte mode). P/N:PMO0562 a 32-26 : - " REV.0.2, NOV.-06, 1998M=Ic So oS! Mx29L.1610T/B Figure 11. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled) ' Word offset AQ~AS = 55H AAH 55H ross - Byte Select ((Byte Mode Only) AB~A14 A15~A19 Page Address two : ~ - tBALC A ad * NV NIV SIV SNV SS tcp ICPH BAL - a > ae ~a. TN IND NV INSP SNS VS tCES <a OE _f \ ff StH ~~ tSRA <_< ~ DATA AAH 55H ADH Write (wa oR /N:PMO582 REV.0.2, NOV. 06; 1898 , 32-27M=Ic MX29L1610T/B 5.5 ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNITS Chip/Sector Erase Time 200 ms Page Programming Time 5 ms Chip Programming Time 80 sec Byte Program Time(average) 40 us Erase/Program Cycles 100,000 Cycles 5.6 LATCHUP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on ail pins except I/O pins -1.0V 6.6V Input Voltage with respect to GND on all I/O pins -1.0V Vec + 1.0V Current -100mA +100mA Includes ail pins except Vcc. Test conditions: Vcc = 3.3V, one pin at a time. P/N:PM0582 32:28 REV. 0.2, NOV. 06, 1998M=Ii MX291L1610T/B REVISION HISTORY REVISION DESCRIPTION PAGE DATE 0.2 Pin Configuration table is added to RY/BY item P2 NOV/06/1998 Pin out Diagram: CE# > CE, OE#--> OE, BYTE# > BYTE P/N:PM0582 REV. 0.2, NOV. 06, 1998 32-29