LT3959
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For more information www.linear.com/LT3959
Typical applicaTion
FeaTures DescripTion
Wide Input Voltage Range
Boost/SEPIC/Inverting Converter
with 6A, 40V Switch
2.5V to 24V Input, 12V Output SEPIC Converter
Excellent for Automotive 12V Post Regulator
applicaTions
n Wide VIN Range: 1.6V (2.5V Start-Up) to 40V
n Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n PGOOD Output Voltage Status Report
n Internal 6A/40V Power Switch
n Programmable Soft-Start
n Programmable Operating Frequency (100kHz to 1MHz)
with One External Resistor
n Synchronizable to an External Clock
n Low Shutdown Current < 1µA
n INTVCC Regulator Supplied from VIN or DRIVE
n Programmable Input Undervoltage Lockout with
Hysteresis
n Thermally Enhanced QFN (5mm × 6mm) and TSSOP
Packages
n Automotive
n Telecom
n Industrial
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7825665.
The LT
®
3959 is a wide input range, current mode, DC/DC
controller which is capable of regulating either positive or
negative output voltages from a single feedback pin. It can
be configured as a boost, SEPIC or inverting converter.
It features an internal low side N-channel MOSFET rated
for 6A at 40V and driven from an internal regulated sup-
ply provided from VIN or DRIVE. The fixed frequency,
current-mode architecture results in stable operation over
a wide range of supply and output voltages. The operating
frequency of LT3959 can be set over a 100kHz to 1MHz
range with an external resistor, or can be synchronized
to an external clock using the SYNC pin.
The LT3959 features soft-start and frequency foldback
functions to limit inductor current during start-up and
output short-circuit. A window comparator on the FBX
pin reports via the PGOOD pin, providing output voltage
status indication.
Efficiency vs Output Current
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
90
95
100
600 1000
3959 TA01b
85
200 400 800
80
75
70
65
60
VIN = 12V
LT3959
VIN
VIN
2.5V TO
24V CIN
22µF
50V
×2
27.4k
300kHz
4.7µF
50V
GND
DRIVE
FBX
SGND INTVCC
EN_UVLO
PGOOD
SYNC
TIE TO SGND
IF NOT USED
RT
SS
VC
L1A
L1B
GNDK
SW
124k
121k
0.1µF 7.5k
22nF
105K
150k
4.7µF
VOUT
12V
500mA AT VIN = 2.5V
1.5A AT VIN > 8V
3959 TA01a
15.8K
COUT
47µF
16V
×2
LT3959
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For more information www.linear.com/LT3959
pin conFiguraTion
absoluTe MaxiMuM raTings
VIN ............................................................................40V
EN/UVLO (Note 2) .....................................................40V
DRIVE .......................................................................40V
PGOOD ...................................................................... 40V
SW ............................................................................40V
INTVCC ........................................................................8V
SYNC ..........................................................................8V
(Note 1)
VC, SS .........................................................................3V
RT ............................................................................1.5V
GND, GNDK to SGND .............................................±0.3V
FBX ................................................................. –3V to 3V
Operating Junction Temperature Range (Note 3)
LT3959E/LT3959I .............................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
12 13 14
TOP VIEW
UHEMA PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1NC
NC
NC
SGND
NC
SW
SW
NC
DRIVE
VIN
EN/UVLO
SGND
NC
SW
SW
INTVCC
PGOOD
SYNC
RT
SS
FBX
VC
GNDK
GND
GND
GND
GND
GND
20
9
10
37
SGND
38
SW
TJMAX =125°C, θJA = 42°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
NC
NC
NC
VC
FBX
SS
RT
SYNC
PGOOD
SGND
NC
SW
NC
NC
SW
NC
GNDK
GND
GND
NC
NC
NC
NC
EN/UVLO
VIN
DRIVE
INTVCC
NC
SGND
NC
SW
NC
NC
SW
NC
GND
GND
GND
39
SGND
40
SW
TJMAX =125°C, θJA = 42°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 40) IS SW, MUST BE SOLDERED TO SW PLANE
LT3959
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elecTrical characTerisTics
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage l1.6 40 V
VIN Start-Up Voltage RT = 27.4kΩ, FBX = 0 l2.5 2.65 V
VIN Shutdown IQEN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1 1
6
µA
µA
VIN Operating IQ350 450 µA
DRIVE Shutdown Quiescent Current EN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1
0.1
1
2
µA
µA
DRIVE Quiescent Current (Not Switching) RT = 27.4kΩ, DRIVE = 6V 2.0 2.5 mA
SW Pin Current Limit l6.0 7.0 8.0 A
SW Pin On Voltage ISW = 3A 100 mV
SW Pin Leakage Current SW = 40V 5 µA
Error Amplifier
FBX Regulation Voltage (VFBX(REG)) FBX > 0V
FBX < 0V
l
l
1.580
–0.815
1.6
–0.80
1.620
–0.785
V
V
FBX Pin Input Current FBX = 1.6V
FBX = –0.8V
–10
80 130
10
nA
nA
Transconductance gm (∆IVC/∆VFBX) FBX = VFBX(REG) 240 µs
VC Output Impedance 5 MΩ
FBX Line Regulation [∆VFBX(REG)/(∆VIN • VFBX(REG))] 1.6V < VIN < 40V, FBX >0
1.6V < VIN < 40V, FBX <0
0.02
0.02
0.05
0.05
%/V
%/V
VC Source Current FBX = 0V, VC = 1.3V –13 µA
VC Sink Current FBX = 1.7V, VC = 1.3V
FBX = –0.85V, VC = 1.3V
13
10
µA
µA
Oscillator
Switching Frequency RT = 27.4k to SGND, VFBX = 1.6V
RT = 86.6k to SGND, VFBX = 1.6V
RT = 6.81k to SGND, VFBX = 1.6V
l250 300
100
1000
340 kHz
kHz
kHz
RT Voltage FBX = 1.6V, –0.8V 1.13 V
SW Minimum Off-Time 150 200 ns
SW Minimum On-Time 150 200 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3959EUHE#PBF LT3959EUHE#TRPBF 3959 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT3959IUHE#PBF LT3959IUHE#TRPBF 3959 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT3959EFE#PBF LT3959EFE#TRPBF LT3959FE 38-Lead Plastic TSSOP –40°C to 125°C
LT3959IFE#PBF LT3959IFE#TRPBF LT3959FE 38-Lead Plastic TSSOP –40°C to 125°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LT C Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LT3959
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For more information www.linear.com/LT3959
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC Input Low l0.4 V
SYNC Input High l1.5 V
SS Pull-Up Current SS = 0V, Current Out of Pin l–14 –10.5 –7 µA
Low Dropout Regulators (DRIVE LDO and VIN LDO)
DRIVE LDO Regulation Voltage DRIVE = 6V, Not Switching l4.6 4.75 4.9 V
VIN LDO Regulation Voltage DRIVE = 0V, Not Switching l3.6 3.75 3.9 V
DRIVE LDO Current Limit INTVCC = 4V 60 mA
VIN LDO Current Limit DRIVE = 0V, INTVCC = 3V 60 mA
DRIVE LDO Load Regulation (∆VINTVCC/VINTVCC) 0 < IINTVCC < 20mA, DRIVE = 6V –1 –0.6 %
VIN LDO Load Regulation (∆VINTVCC/VINTVCC) DRIVE = 0V, 0 < IINTVCC < 20mA –1 –0.6 %
DRIVE LDO Line Regulation [∆VINTVCC/(VINTVCC • ∆VIN)] 1.6V < VIN < 40V, DRIVE = 6V 0.03 0.07 %/V
VIN LDO Line Regulation [∆VINTVCC/(VINTVCC • ∆VIN)] DRIVE = 0V, 5V < VIN < 40V 0.03 0.07 %/V
DRIVE LDO Dropout Voltage (VDRIVE – VINTVCC) DRIVE = 4V, IINTVCC = 20mA l190 400 mV
VIN LDO Dropout Voltage (VIN – VINTVCC) VIN = 3V, DRIVE = 0V,
IINTVCC = 20mA
l190 400 mV
INTVCC Undervoltage Lockout Threshold Falling l1.85 2.0 2.15 V
INTVCC Undervoltage Lockout Threshold Rising l2.15 2.3 2.45 V
INTVCC Current in Shutdown EN/UVLO = 0V 25 µA
Logic
EN/UVLO Threshold Voltage Falling l1.17 1.22 1.27 V
EN/UVLO Threshold Voltage Rising Hysteresis 20 mV
EN/UVLO Input Low Voltage IVIN < 1μA 0.4 V
EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.8 2.2 2.6 µA
EN/UVLO Pin Bias Current High EN/UVLO = 1.30V 10 100 nA
FBX Power Good Threshold Voltage FBX > 0V, PGOOD Falling
FBX < 0V, PGOOD Falling
VFBX(REG) – 0.08
VFBX(REG) + 0.04
V
V
FBX Overvoltage Threshold FBX > 0V, PGOOD Rising
FBX < 0V, PGOOD Rising
VFBX(REG) + 0.12
VFBX(REG) – 0.06
V
V
PGOOD Output Low (VOL) IPGOOD = 250µA 210 300 mV
PGOOD Leakage Current PGOOD = 40V 1 µA
INTVCC Minimum Voltage to Enable PGOOD Function l2.5 2.7 2.9 V
INTVCC Minimum Voltage to Enable SYNC Function l2.5 2.7 2.9 V
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: For VIN below 4V, the EN/UVLO pin must not exceed VIN for proper
operation.
Note 3: The LT3959E is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3959I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 4: The LT3959 is tested in a feedback loop which servos VFBX to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
LT3959
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Typical perForMance characTerisTics
Dynamic Quiescent Current
vs Switching Frequency RT vs Switching Frequency
Normalized Switching Frequency
vs FBX Voltage
Switching Frequency
vs Temperature SW Current Limit vs Temperature SW Current Limit vs Duty Cycle
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
Quiescent Current
vs Temperature
SWITCHING FREQUENCY (kHz)
0
IQ (mA)
15
20
25
600 1000
3959 G04
10
200 400 800
5
0
IQ (VIN)
IQ (DRIVE)
DRIVE = 6V
SWITCHING FREQUENCY (kHz)
0
RT (k)
60
50
80
70
100
90
600 1000
3959 G05
40
30
200100 400 800
700
300 500 900
20
10
0
FBX VOLTAGE (V)
–0.8
NORMALIZED FREQUENCY (%)
80
60
120
100
1.6
3959 G06
40
–0.4 0.8
0 0.4 1.2
20
0
TEMPERATURE (°C)
–50
FBX REGULATION VOLTAGE (V)
1.61
1.62
0 125
3959 G01
1.60
–25 25 50 75 100
1.59
1.58
TEMPERATURE (°C)
–50
FBX REGULATION VOLTAGE (V)
–0.79
–0.78
0 125
3959 G02
–0.80
–25 25 50 75 100
–0.81
–0.82
TEMPERATURE (°C)
–50
IQ (mA)
2.4
2.0
1.6
1.2
0.4
0.8
0.0
0 125
3959 G03
–25 25 50 75 100
IQ (VIN)
VIN = 12V
DRIVE = 6V
IQ (DRIVE)
TEMPERATURE (°C)
–50
SW CURRENT LIMIT (A)
7.6
7.4
7.2
7.0
6.8
6.6
6.4 0 125
3959 G08
–25 25 50 75 100
DUTY CYCLE (%)
0
SW CURRENT LIMIT (A)
6.5
5.5
7.0
8.0
7.5
100
3959 G09
6.0
20 60
40 80
5.0
TEMPERATURE (°C)
–50
SWITCHING FREQUENCY (kHz)
350
325
300
275
250
0 125
3959 G07
–25 25 50 75 100
TA = 25°C, unless otherwise noted.
LT3959
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Typical perForMance characTerisTics
INTVCC vs Temperature INTVCC Load Regulation INTVCC Line Regulation
INTVCC Dropout Voltage
vs Current, Temperature
Internal Switch On-Resistance
vs Temperature
Internal Switch On-Resistance
vs INTVCC
EN/UVLO Threshold
vs Temperature
SW Minimum On- and Off-Times
vs Temperature
EN/UVLO Hysteresis Current
vs Temperature
TEMPERATURE (°C)
–50
ON-RESISTANCE (mΩ)
60
40
50
30
1251007550
3959 G17
0
–25 25
20
INTCCC (V)
2
ON-RESISTANCE (mΩ)
50
45
40
35
54 4.5
3959 G18
3
2.5 3.5
30
TEMPERATURE (°C)
–50
EN/UVLO VOLTAGE (V)
1.27
1.25
1.23
1.21
1.19
1.17
0 125
3959 G10
–25 25 50 75 100
EN/UVLO RISING
EN/UVLO FALLING
TEMPERATURE (°C)
–50
EN/UVLO (µA)
2.4
2.2
2.0
1.8
1.6
0 125
3959 G12
–25 25 50 75 100
INTVCC LOAD (mA)
0
INTVCC VOLTAGE (V)
4
5
4.5
25
3959 G14
3.5
515
10 20
3
DRIVE LDO
VIN LDO (DRIVE = 0V)
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
200
400
300
25
3959 G16
100
515
10 20
0
VIN = 12V
DRIVE = 4V
125°C
25°C
–40°C
TEMPERATURE (°C)
–50
INTVCC (V)
5.0
4.8
4.6
4.4
4.0
3.8
4.2
3.6
0 125
3959 G13
–25 25 50 75 100
DRIVE LDO
VIN LDO
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
MINIMUM ON/OFF TIME (ns)
200
190
180
170
160
150
140
130
0 125
3959 G11
–25 25 50 75 100
MINIMUM
OFF TIME
MINIMUM
ON TIME
VIN (V)
0
INTVCC VOLTAGE (V)
5.0
4.5
4.0
4535 40
3959 G15
3.5
515
10 20 3025
3.0
DRIVE LDO
DRIVE = 6V
DRIVE = 0V
VIN LDO
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pin FuncTions
DRIVE: DRIVE LDO Supply Pin. This pin can be connected
to either VIN or a quasi-regulated voltage supply such as a
DC converter output. This pin must be bypassed to GND
with a minimum of 1µF capacitor placed close to the pin.
Tie this pin to VIN if not used.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.22V (nominal) falling threshold with externally
programmable hysteresis detects when power is okay to
enable switching. Rising hysteresis is generated by the
external resistor divider and an accurate internal 2.2μA
pull-down current. An undervoltage condition resets soft-
start. Tie to 0.4V, or less, to disable the device and reduce
VIN quiescent current below 1μA.
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
between the output and SGND. FBX is the input of two error
amplifiers—one configured to regulate a positive output;
the other, a negative output. Depending upon topology
selected, switching causes the output to ramp positive or
negative. The appropriate amplifier takes control while the
other becomes inactive. Additionally FBX is input for two
window comparators that indicate through the PGOOD
pin when the output is within 5% of the regulation volt-
ages. FBX also modulates the switching frequency during
start-up and fault conditions when FBX is close to SGND.
GND: Source Terminal of Switch and the GND Input to the
Switch Current Comparator.
GNDK: Kelvin Connection Pin between GND and SGND.
Kelvin connect this pin to the SGND plane close to the IC.
See the Board Layout section.
INTVCC: Regulated Supply for Internal Loads and Gate
Driver. Regulated to 4.75V if powered from DRIVE or
regulated to 3.75V if powered from VIN. The INTVCC pin
must be bypassed to SGND with a minimum of 4.7µF
capacitor placed close to the pin.
NC: No Internal Connection. Leave these pins open or
connect them to the adjacent pins.
PGOOD: Output Ready Status Pin. An open-collector pull
down on PGOOD asserts when INTVCC is greater than
2.7V and the FBX voltage is within 5% (80mV if VFBX =
1.6V or 40mV if VFBX = –0.8V) of the regulation voltage.
RT : Switching Frequency Adjustment Pin. Set the frequency
using a resistor to SGND. Do not leave the RT pin open.
SGND: Signal Ground. Must be soldered directly to the
signal ground plane. Connect to ground terminal of: ex-
ternal resistor dividers for FBX and EN/UVLO; capacitors
for INTVCC, SS, and VC; and resistor RT.
SS: Soft-Start Pin. This pin modulates compensation pin
voltage (VC) clamp. The soft-start interval is set with an
external capacitor. The pin has a 10µA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to SGND by an EN/UVLO undervoltage condition,
an INTVCC undervoltage condition or an internal thermal
lockout.
SW: Drain of Internal Power N-Channel MOSFET.
SYNC: Frequency Synchronization Pin. Used to synchronize
the internal oscillator to an outside clock. If this feature is
used, an RT resistor should be chosen to program a switch-
ing frequency 20% slower than SYNC pulse frequency.
Tie the SYNC pin to SGND if this feature is not used. This
signal is ignored during FB frequency foldback or when
INTVCC is less than 2.7V.
VIN: Supply Pin for Internal Leads and the VIN LDO Regu-
lator of INTVCC. Must be locally bypassed to GND with a
minimum of 1µF capacitor placed close to this pin.
VC: Error Amplifier Compensation Pin. Used to stabilize
the voltage loop with an external RC network. Place com-
pensation components between the VC pin and SGND.
LT3959
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block DiagraM
Figure 1. LT3959 Block Diagram Working as a SEPIC Converter (Shown for QFN Package)
1.22V
1.2V
2.5V
CIN
CVCC
INTVCC
DRIVEVIN
RSENSE
VISENSE
IS1
2.2µA
28
36
8, 9, 20, 21
30
25
EN/UVLO
BANDGAP
REFERENCE
TSD
~165˚C
A10
Q3
VC
SGND
VC
BG_LOW
UVLO
OTP
IS2
10µA
IS3
CC1
RPG
VIN
CC2
RC
DRIVER
SLOPE
GND
13, 14
15, 16
17
SW
M1
45mV
SR1
+
–
RAMP
GENERATOR
+
–
R Q
S
2.5V
SS
CSS
SYNC
FREQ
FOLDBACK
1.25V
FBX
PGOOD
FBX
Q4
1.6V
–0.8V
+
–
+
–
31
35
32 34
+
–
+
–
RAMP
PWM
COMPARATOR
FREQUENCY
FOLDBACK
100kHz ~ 1MHz
OSCILLATOR
R1
R2
L2
FBX
D1
CDC
VOUT
COUT
•
3759 F01
A1
A2
1.72V
–0.86V
+
–
+
–
A11
A12
+
–
A3
1.25V
FREQ
PROG
–
+
+Q1
RT
RT
A4
A5
A6
G5
G6
A7
Q2
G4
R3R4
VIN
27
INTERNAL BIAS
GENERATOR
DRIVE LDO
CURRENT
LIMIT
INTERNAL BIAS
CURRENT
LIMIT
VIN LDO
A8
+
–
G8
1.52V
–0.76V
+
–
+
–
A13
A14
G7
2.7V
A15
+
–
G2
G1
•
L1
BG
SGND GNDK4, 24
33 12
SGND
SGND
SGND
(QFN Package)
LT3959
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applicaTions inForMaTion
Main Control Loop
The LT3959 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
and turns on the internal power MOSFET switch M1 through
driver G2. The switch current flows through the internal
current sensing resistor RSENSE and generates a voltage
proportional to the switch current. This current sense
voltage VISENSE (amplified by A5) is added to a stabilizing
slope compensation ramp and the resulting sum (SLOPE)
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
The LT3959 has a switch current limit function. The cur-
rent sense voltage is input to the current limit comparator
A6. If the SENSE voltage is higher than the sense current
limit threshold VSENSE(MAX) (45mV, typical), A6 will reset
SR1 and turn off M1 immediately.
The LT3959 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost or SEPIC converter to generate
positive output voltage, or as an inverting converter to
generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
age divider (R1 and R2) connected from VOUT to SGND.
Comparator A2 becomes inactive and comparator A1
performs the inverting amplification from FBX to VC. When
the LT3959 is in an inverting configuration, the FBX pin
is pulled down to –0.8V by a voltage divider connected
from VOUT to SGND. Comparator A1 becomes inactive and
comparator A2 performs the noninverting amplification
from FBX to VC.
The LT3959 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 40mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 7.5% and turns off
M1. Similarly, an overvoltage comparator A12 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
negative regulated voltage (–0.8V) by 7.5% and turns
off M1. Both reset pulses are sent to the main RS latch
(SR1) through G6 and G5. The internal power MOSFET
switch M1 is actively held off for the duration of an output
overvoltage condition.
Programming Turn-On and Turn-Off Thresholds with
EN/UVLO Pin
The EN/UVLO pin controls whether the LT3959 is enabled
or is in shutdown state. A micropower 1.22V reference, a
comparator A10 and controllable current source IS1 allow
the user to accurately program the supply voltage at which
the IC turns on and off. The falling value can be accurately
set by the resistor dividers R3 and R4. When EN/UVLO
is above 0.7V, and below the 1.22V threshold, the small
pull-down current source IS1 (typical 2.2µA) is active.
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the comparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
VVIN(FALLING) =1.22 •
(R3+R4)
R4
VVIN(RISING) =2.2µA •R3+VIN(FALLING)
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
to the input voltage VIN for always-on operation.
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INTVCC Low Dropout Voltage Regulators
The LT3959 features two internal low dropout (LDO) volt-
age regulators (VIN LDO and DRIVE LDO) powered from
different supplies (VIN and DRIVE respectively). Both LDO’s
regulate the internal INTVCC supply which powers the gate
driver and the internal loads, as shown in Figure 1. Both
regulators are designed so that current does not flow from
INTVCC to the LDO input under a reverse bias condition.
DRIVE LDO regulates the INTVCC to 4.75V, while VIN LDO
regulates the INTVCC to 3.75V. VIN LDO is turned off when
the INTVCC voltage is greater than 3.75V (typical). Both
LDO’s can be turned off if the INTVCC pin is driven by a
supply of 4.75V or higher but less than 8V (the INTVCC
maximum voltage rating is 8V). A table of the LDO sup-
ply and output voltage combination is shown in Table 1.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
SUPPLY VOLTAGES LDO OUTPUT LDO STATUS
(Note 7)
VIN DRIVE INTVCC
VIN ≤ 3.9V VDRIVE < VIN VIN – 0.15V #1 Is ON
VDRIVE = VIN VIN – 0.15V #1 #2 are ON
VIN < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON
4.9V ≤ VDRIVE ≤ 40V 4.75V #2 Is ON
3.9V < VIN ≤ 40V VDRIVE < 3.9V 3.75V #1 Is ON
VDRIVE = 3.9V 3.75V #1 #2 are ON
3.9V < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON
4.9V ≤ VDRIVE ≤ 40V 4.75V #2 Is ON
Note 7: #1 is VIN LDO and #2 is DRIVE LDO
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used,
the DRIVE pin should be tied to VIN.
The INTVCC pin must be bypassed to SGND immediately
adjacent to the INTVCC pin with a minimum of 4.7µF ceramic
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate driver.
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency op-
eration improves efficiency by reducing gate drive current
and internal MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loop compensation. The LT3959 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT
pin to SGND, as shown in Figure 1. The RT pin must have
an external resistor to SGND for proper operation of the
LT3959. A table for selecting the value of RT for a given
operating frequency is shown in Table 2.
Table 2. Timing Resistor (RT) Value
OSCILLATOR FREQUENCY (kHz) RT (kΩ)
100 86.6
200 41.2
300 27.4
400 21.0
500 16.5
600 13.7
700 11.5
800 9.76
900 8.45
1000 6.81
The switching frequency of the LT3959 can be synchro-
nized to the positive edge of an external clock source.
By providing a digital clock signal into the SYNC pin,
the LT3959 will operate at the SYNC clock frequency. If
this feature is used, an RT resistor should be chosen to
program a switching frequency 20% slower than SYNC
pulse frequency. The SYNC pulse should have a minimum
pulse width of 200ns. Tie the SYNC pin to SGND if this
feature is not used.
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Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation. As such, its limits must be considered. Minimum
on-time is the smallest time duration that the LT3959 is
capable of turning on the internal power MOSFET. This time
is generally about 150ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3959 keeps the power switch off for at least
150ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage (VOUT) is set by a resistor divider, as
shown in Figure 1. The positive VOUT and negative VOUT
are set by the following equations:
VOUT(POSITIVE) =1.6V •1+
R2
R1
VOUT(NEGATIVE) =–0.8V •1+R2
R1
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FBX pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 at about 121k).
Soft-Start
The LT3959 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
LT3959 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the internal power
MOSFET current by pulling down the VC pin through Q2.
In this way the SS allows the output capacitor to charge
gradually toward its final value while limiting the start-up
peak currents.
Besides start-up, soft-start can also be triggered by
INTVCC undervoltage lockout and/or thermal lockout, which
causes the LT3959 to stop switching immediately. The SS
pin will be discharged by Q3. When all faults are cleared
and the SS pin has been discharged below 0.2V, a 10µA
current source IS2 starts charging the SS pin, initiating a
soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS =CSS •
1.25V
10µA
FBX Frequency Foldback
When VOUT is very low during start-up or a short-circuit
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decay rate is very low during switch off time. The minimum
on-time limitation may prevent the switcher from attaining
a sufficiently low duty cycle at the programmed switching
frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3959 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
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Some frequency foldback waveforms are shown in the
Typical Applications section. The frequency foldback func-
tion prevents IL from exceeding the programmed limits
because of the minimum on-time.
During frequency foldback, external clock synchronization
is disabled to allow the frequency reducing operation to
function properly.
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3959 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3959, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral-
lel with the RC compensation network to attenuate the
VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
The Internal Power Switch Current
For control and protection, the LT3959 measures the
internal power MOSFET current by using a sense resistor
(RSENSE) between GND and the MOSFET source. Figure 2
shows a typical wave-form of the internal switch current
(ISW).
Due to the current limit (minimum 6A) of the internal power
switch, the LT3959 should be used in the applications
that the switch peak current ISW(PEAK) during steady state
normal operation is lower than 6A by a sufficient margin
(10% or higher is recommended).
It is recommended to measure the IC temperature in steady
state to verify that the junction temperature limit (125°C) is
not exceeded. A low switching frequency may be required
to ensure TJ(MAX) does not exceed 125°C.
If LT3959 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
APPLICATION CIRCUITS
The LT3959 can be configured as different topologies.
The design procedure for component selection differs
somewhat between these topologies. The first topology
to be analyzed will be the boost converter, followed by
SEPIC and inverting converters.
Figure 2. The SW Current During a Switching Cycle
applicaTions inForMaTion
3959 F02
ISW(PEAK)
∆ISW
ISW
t
DTS
TS
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Boost Converter: Switch Duty Cycle and Frequency
The LT3959 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
The conversion ratio as a function of duty cycle is:
V
OUT
V
IN
=
1
1−D
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =
V
OUT
−V
IN(MIN)
VOUT
The alternative to CCM, discontinuous conduction mode
(DCM) is not limited by duty cycle to provide high con-
version ratios at a given frequency. The price one pays
is reduced efficiency and substantially higher switching
current.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
For the boost topology, the maximum average inductor
current is:
IL(MAX) =IO(MAX) •
1
1−D
MAX
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Due to the current limit of its internal power switch, the
LT3959 should be used in a boost converter whose maxi-
mum output current (IO(MAX)) is less than the maximum
output current capability by a sufficient margin (10% or
higher is recommended):
IO(MAX) <
IN(MIN)
VOUT
•(6A – 0.5 •∆ISW )
The inductor ripple current ∆ISW has a direct effect on the
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of
∆ISW increases output current capability, but requires
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
values of ∆ISW provides fast transient response and
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value of the boost converter can be determined
using the following equation:
L=
V
IN(MIN)
∆ISW •fOSC
•DMAX
The peak inductor current is the switch current limit (7A
typical), and the RMS inductor current is approximately
equal to IL(MAX). The user should choose the inductors
having sufficient saturation and RMS current ratings.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
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It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually sufficient).
The power dissipated by the diode is:
P
D
=I
O(MAX)
•V
D
Where VD is diode’s forward voltage drop, and the diode
junction temperature is:
T
J
=T
A
+P
D
•Rθ
JA
The RθJA to be used in this equation normally includes the
RθJC for the device plus the thermal resistance from the
board to the ambient temperature in the enclosure. TJ must
not exceed the diode maximum junction temperature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 3.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ∆VESR and charging/discharging
∆VCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ∆VESR and ∆VCOUT. This percentage ripple will
change, depending on the requirements of the application,
applicaTions inForMaTion
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
ESRCOUT ≤
0.01•V
OUT
ID(PEAK)
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥
I
O(MAX)
0.01•VOUT •ƒOSC
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 3. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:
I
RMS(COUT) ≥IO(MAX) •DMAX
1−DMAX
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
the required RMS current rating. Additional ceramic capaci-
tors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a boost
converter is:
IRMS(CIN) = 0.3 • ∆IL
VOUT
(AC)
tON
∆VESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆VCOUT
3959 F03
tOFF
Figure 3. The Output Ripple Waveform of a Boost Converter
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SEPIC CONVERTER APPLICATIONS
The LT3959 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
V
OUT
+V
D
V
IN
=
D
1−D
In continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and diode forward
voltage (VD).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
V
OUT
+V
D
VIN(MIN) +VOUT +V
D
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX) =IIN(MAX) =IO(MAX)•
D
MAX
1– DMAX
IL2(MAX) =IO(MAX)
Due to the current limit of it’s internal power switch,
the LT3959 should be used in a SEPIC converter whose
maximum output current (IO(MAX)) is less than the output
current capability by a sufficient margin (10% or higher
is recommended):
IO(MAX) < (1–DMAX) • (6A – 0.5 • ∆ISW)
The inductor ripple currents ∆IL1 and ∆IL2 are identical:
∆IL1 = ∆IL2 = 0.5 • ∆ISW
The inductor ripple current ∆ISW has a direct effect on the
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of ∆ISW
requires large inductances and reduces the current loop
gain (the converter will approach voltage mode). Accepting
larger values of ∆ISW allows the use of low inductances,
but results in higher input current ripple and greater core
losses and reduces output current capability.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value (L1 and L2 are independent) of the SEPIC
converter can be determined using the following equation:
L1 = L2 =
V
IN(MIN)
0.5 •∆ISW •ƒOSC
•DMAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L=
V
IN(MIN)
∆ISW •ƒOSC
•DMAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
IL1(PEAK) = IL1(MAX) + 0.5 • ∆IL1
IL2(PEAK) = IL2(MAX) + 0.5 • ∆IL2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
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Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS cur-
rent ratings.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
The power dissipated by the diode is:
PD = IO(MAX) • VD
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
TJ = TA + PD • RθJA
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 1) should be larger than the maximum
input voltage:
VCDC > VIN(MAX)
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •VOUT +VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT3959 can be configured as a dual-inductor inverting
topology, as shown in Figure 4. The VOUT to VIN ratio is:
V
OUT
– V
D
V
IN
=–
D
1−D
In continuous conduction mode (CCM).
applicaTions inForMaTion
CDC
VIN
CIN
L1
D1 COUT VOUT
3959 F04
+
GND
SW
LT3959
L2
+
–
+–
+
Figure 4. A Simplified Inverting Converter
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
V
OUT
– V
D
VOUT – VD– VIN(MIN)
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Inverting Converter: Output Diode and Input Capacitor
Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost and SEPIC converters
for similar output ripple. This is due to the fact that, in the
inverting converter, the inductor L2 is in series with the
output, and the ripple current flowing through the output
capacitors are continuous. The output ripple voltage is
produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
∆VOUT(P−P) = ∆IL2 •ESRCOUT +1
8•fOSC •COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 • ∆IL2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 4) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •DMAX
1– DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high power and high speed operation of the LT3959
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3959 at high input voltages,
high switching frequencies, and high internal power switch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher
di/dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive ringing:
• In boost configuration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
• In SEPIC configuration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
internal power MOSFET, Schottky diode and the coupling
capacitor.
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Check the stress on the internal power MOSFET by mea-
suring the SW-to-GND voltage directly across the IC ter-
minals. Make sure the inductive ringing does not exceed
the maximum rating of the internal power MOSFET (40V).
The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3959 in order to keep the high impedance
FBX node short.
Figure 5 shows the suggested layout of the 2.5V to 8V
input, 12V output boost converter in the Typical Applica-
tion section.
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applicaTions inForMaTion
Figure 5. Suggested Layout of the 2.5V to 8V Input. 12V Output Boost Converter
in the Typical Application Section (Shown for QFN Package)
3959 F05
LT3959
37
38
10
VIA TO VOUT
R1
R2
CSS
CVCC
RT
R5 RCCC
R3
R4
D1
SW
SGND
L1
COUT
COUT
CIN
GND VOUT
VIN
VIA TO VOUT
VIA TO VOUT
VIA TO VIN
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
36 35 34 33 32 31 30
21
23
24
25
27
28
20
12 13 14 15 16 17
8
6
4
3
2
1
9
LT3959
20
3959fa
For more information www.linear.com/LT3959
Typical applicaTions
2.5V to 5V Input, –5V Output Inverting Converter
Efficiency vs Output Current
GND
LT3959
VIN
VIN
2.5V TO 5V
CIN
47µF
10V
X5R
CDC
4.7µF, 25V
X7R
1µF
16V
X5R
DRIVE
FBX
INTVCC
SSRT
EN/UVLO
SYNC
PGOOD
SGND
VC
L1B
L1A
GNDK
SW
22k
9.09k
10nF
0.1µF
27.4k
300kHz
124k
121k
CVCC
4.7µF
10V
X5R
VOUT
–5V
1A
3959 TA02
D2 D1
84.5k
15.8k
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
D2: PHILIPS PMEG2005EJ
COUT
47µF
10V
X5R
×2
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
100
600
3759 TA02a
200 400 1000800
70
60
80
90
50
VIN = 5V
LT3959
21
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For more information www.linear.com/LT3959
Typical applicaTions
2.5V to 24V Input, 12V Output SEPIC Converter
DRIVE
LT3959
L1A
L1B
VIN
VC
SW
D1
L1A, L1B: COILTRONICS DRQ127-150
D1: VISHAY 6CWQ06FN
GND
FBX
RT
SS
INTVCC
EN/UVLO
SYNC
TIE TO SGND IF
NOT USED
PGOOD
SGND
3959 TA03
124k
121k150k
7.5k 4.7µF
27.4k
300kHz
22nF0.1µF
105k
15.8k
GNDK
4.7µF
50V VOUT
12V
500mA AT VIN = 2.5V
1.5A AT VIN > 8v
VIN
2.5V TO 24V CIN
22µF
50V
×2
COUT1
47µF
16V
X5R
×2
•
•
Efficiency vs Output Current
Load Step Response at VIN = 12V Frequency Foldback Waveforms
When Output Short-Circuits
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
90
100
800
3759 TA03b
80
400200 600 1000
65
70
75
85
95
60
VIN = 12V
500µs/DIV
VOUT
500mV/DIV
(AC)
IOUT
500mA/DIV 0.2A
0.8A
3959 TA03c 500µs/DIV
VOUT
10V/DIV
VSW
20V/DIV
IL1A+L1B
2.5A/DIV
3959 TA03d
LT3959
22
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For more information www.linear.com/LT3959
Typical applicaTions
2.5V to 8V Input, 12V LED Driver
Efficiency vs VIN
3959 TA04
DRIVE
LT3959
L1
8.2µH
VIN SW
L1: TOKO 962BS-BR2M
D1: VISHAY SILICONIX 20BQ030
DZ1: CENTRAL SEMICONDUCTOR CMHZ5252B
GND
FBX
RT SS INTVCC
EN/UVLO
PGOOD
SYNC
SGND
R2
121k
VC
D1
DZ1
24V
GNDK
R1
124k
RT
27.4k
300kHz CVCC
4.7µF
10V
X5R
CSS
0.1µF
RC
4.99k
CC
22nF
R4
3.48k
R5
0.5Ω
COUT
22µF
16V
X5R
×2
12V LEDs
500mA
VOUT
VIN
2.5V TO 8V CIN
22µF
16V
X5R
R3
7.68k
VIN (V)
2
EFFICIENCY (%)
90
94
7
3959 TA04b
86
543 6 8
84
88
92
82
LT3959
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For more information www.linear.com/LT3959
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
5.00 ± 0.10
6.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
363530 31 32 33 34
28
20
21
23
24
25
27 2
3
4
6
8
9
10
121314151617
BOTTOM VIEW—EXPOSED PAD
2.00 REF
1.50 REF
0.75 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
PIN 1 NOTCH
R = 0.30 OR
0.35 × 45°
CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UHE36(28)MA) QFN 0112 REV D
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.10 ± 0.05
5.50 ± 0.05
PACKAGE OUTLINE
1.88 ± 0.10
1.53 ± 0.10
2.00 REF
1.50 REF
5.10 ± 0.05
6.50 ± 0.05
UHE Package
Variation: UHE36(28)MA
36(28)-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev D)
3.00 ± 0.10
3.00 ± 0.10
0.12
± 0.10
1.88
± 0.05
1.53
± 0.05
3.00 ± 0.05 3.00 ± 0.05
0.48 ± 0.05
0.12
± 0.05
0.48 ± 0.10
0.25 ±0.05
0.50 BSC
101 2 3 4 6 8 9
17
20212324252728
30
31
32
33
34
35
36
12
13
14
15
16
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
LT3959
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For more information www.linear.com/LT3959
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.75
(.187) REF
FE38 (AC) TSSOP REV Ø 0311
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.70 1.60
0.45
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1779 Rev Ø)
Split Exposed Pad Variation AC
0.45
(.018)
REF
2.70
(.106)
REF
1.60
(.063)
2.38
(.094) 2.74
(.108)
REF
LT3959
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3959fa
For more information www.linear.com/LT3959
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 06/13 Added TSSOP-28 package 1, 2, 7, 24
LT3959
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3959fa
For more information www.linear.com/LT3959
LINEAR TECHNOLOGY CORPORATION 2012
LT 0613 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3959
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT3957 Boost, Flyback, SEPIC and Inverting Converter
with 5A, 40V Switch
3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
5mm × 6mm QFN Package
LT3958 Boost, Flyback, SEPIC and Inverting Converter
with 3.3A, 84V Switch
5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operation Frequency,
5mm × 6mm QFN Package
LT3759 Boost, Flyback, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, 100kHz to 1MHz Programmable Operation Frequency,
MSOP-12E Package
LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operation Frequency,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3748 100V Isolated Flyback Controller 5V ≤ VIN ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage Spacing
LT3798 Off-Line Isolated No Opto-Coupler Flyback
Controller with Active PFC
VIN and VOUT Limited Only by External Components
2.5V to 8V Input, 12V Output Boost Converter
DRIVE
LT3959
L1
10µH
VIN SW
L1: COILTRONICS DR125-100
D1: VISHAY SILICONIX 20BQ030
GND
FBX
RT SS INTVCC
EN/UVLO
PGOOD
SYNC
SGND
R4
121k
VC
3959 TA05
D1
GNDK
R3
124k
R5
47k
RT
27.4k
300kHz
CVCC
4.7µF
10V
X5R
CSS
0.22µF
RC
3.4k
CC
22nF
R2
105k
R1
15.8k
COUT
47µF
16V
X5R
×2
VOUT
12V
500mA, 2.5V ≤ VIN < 5V
1A, 5V ≤ VIN ≤ 8V
VIN
2.5V TO 8V CIN
22µF
16V
X5R
Efficiency vs Output Current Load Step Response at VIN = 8V
OUTPUT CURRENT (mA)
0
EFFICIENCY (%)
85
95
100
600 800
3759 TA05b
75
200 400 1000
80
90
70
VIN = 5V
500µs/DIV
VOUT
500mV/DIV
(AC)
IOUT
500mA/DIV 0.2A
0.8A
3959 TA05c