B66387G1500X187 - EPCOS - Product.Network

DDR2 SDRAM

MT47H256M4 – 32 Meg x 4 x 8 banks

MT47H128M8 – 16 Meg x 8 x 8 banks

MT47H64M16 – 8 Meg x 16 x 8 banks

Features

•V

DD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V

• JEDEC-standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

• Duplicate output strobe (RDQS) option for x8

• DLL to align DQ and DQS transitions with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Selectable burst lengths (BL): 4 or 8

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• On-die termination (ODT)

• Industrial temperature (IT) option

• Automotive temperature (AT) option

• RoHS-compliant

• Supports JEDEC clock jitter specification

Options1Marking

• Configuration

– 256 Meg x 4 (32 Meg x 4 x 8 banks) 256M4

– 128 Meg x 8 (16 Meg x 8 x 8 banks) 128M8

– 64 Meg x 16 (8 Meg x 16 x 8 banks) 64M16

• FBGA package (Pb-free) – x16

– 84-ball FBGA (8mm x 12.5mm)

Rev. G, H

• FBGA package (Pb-free) – x4, x8

– 60-ball FBGA (8mm x 11.5mm)

Rev. G

• FBGA package (Pb-free) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. H CF

• FBGA package (lead solder) – x16

– 84-ball FBGA (8mm x 12.5mm)

Rev. G, H

• FBGA package (lead solder) – x4, x8

– 60-ball FBGA (8mm x 11.5mm)

Rev. G

• FBGA package (lead solder) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. H JN

• Timing – cycle time

– 1.875ns @ CL = 7 (DDR2-1066) -187E

– 2.5ns @ CL = 5 (DDR2-800) -25E

– 2.5ns @ CL = 6 (DDR2-800) -25

– 3.0ns @ CL = 4 (DDR2-667) -3E

– 3.0ns @ CL = 5 (DDR2-667) -3

– 3.75ns @ CL = 4 (DDR2-533) -37E

• Self refresh

– Standard None

– Low-power L

• Operating temperature

– Commercial (0°C ื TC ื +85°C) None

– Industrial (–40°C ื TC ื +95°C;

–40°C ื TA ื +85°C)

– Automotive (–40°C ื TC , TA ื

+105ºC)

• Revision :G/:H

Note: 1. Not all options listed can be combined to

define an offered product. Use the Part

Catalog Search on www.micron.com for

product offerings and availability.

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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1GbDDR2.pdf – Rev. W 7/11 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)

tRC (ns)CL = 3 CL = 4 CL = 5 CL = 6 CL = 7

-187E 400 533 800 800 1066 54

-25E 400 533 800 800 n/a 55

-25 400 533 667 800 n/a 55

-3E 400 667 667 n/a n/a 54

-3 400 533 667 n/a n/a 55

-37E 400 533 n/a n/a n/a 55

Table 2: Addressing

Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16

Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks

Refresh count 8K 8K 8K

Row address A[13:0] (16K) A[13:0] (16K) A[12:0] (8K)

Bank address BA[2:0] (8) BA[2:0] (8) BA[2:0] (8)

Column address A[11, 9:0] (2K) A[9:0] (1K) A[9:0] (1K)

Figure 1: 1Gb DDR2 Part Numbers

Package

Pb-free

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 11.5mm FBGA

60-ball 8mm x 10.0mm FBGA

Lead solder

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 10mm FBGA

60-ball 8mm x 11.5mm FBGA

Example Part Number: MT47H128M8CF-25

Configuration

256 Meg x 4

128 Meg x 8

64 Meg x 16

256M4

128M8

64M16

Speed Grade

tCK = 1.875ns, CL = 7

tCK = 2.5ns, CL = 5

tCK = 2.5ns, CL = 6

tCK = 3ns, CL = 4

tCK = 3ns, CL = 5

tCK = 3.75ns, CL = 4

-187E

-25E

-25

-3E

-3

-37E

Configuration

MT47H Package Speed

Revision

:G/:H

Low power

Industrial temperature

Automotive temperature

Note: 1. Not all speeds and configurations are available in all packages.

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

1Gb: x4, x8, x16 DDR2 SDRAM

Features

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Contents

State Diagram .................................................................................................................................................. 9

Functional Description ................................................................................................................................... 10

Industrial Temperature ............................................................................................................................... 10

Automotive Temperature ............................................................................................................................ 11

General Notes ............................................................................................................................................ 11

Functional Block Diagrams ............................................................................................................................. 12

Ball Assignments and Descriptions ................................................................................................................. 15

Packaging ...................................................................................................................................................... 19

Package Dimensions ................................................................................................................................... 19

FBGA Package Capacitance ......................................................................................................................... 22

Electrical Specifications – Absolute Ratings ..................................................................................................... 23

Temperature and Thermal Impedance ........................................................................................................ 23

Electrical Specifications – IDD Parameters ........................................................................................................ 26

IDD Specifications and Conditions ............................................................................................................... 26

IDD7 Conditions .......................................................................................................................................... 27

AC Timing Operating Specifications ................................................................................................................ 34

AC and DC Operating Conditions .................................................................................................................... 46

ODT DC Electrical Characteristics ................................................................................................................... 47

Input Electrical Characteristics and Operating Conditions ............................................................................... 48

Output Electrical Characteristics and Operating Conditions ............................................................................. 51

Output Driver Characteristics ......................................................................................................................... 53

Power and Ground Clamp Characteristics ....................................................................................................... 57

AC Overshoot/Undershoot Specification ......................................................................................................... 58

Input Slew Rate Derating ................................................................................................................................ 60

Commands .................................................................................................................................................... 73

Truth Tables ............................................................................................................................................... 73

DESELECT ................................................................................................................................................. 77

NO OPERATION (NOP) ............................................................................................................................... 78

LOAD MODE (LM) ...................................................................................................................................... 78

ACTIVATE .................................................................................................................................................. 78

READ ......................................................................................................................................................... 78

WRITE ....................................................................................................................................................... 78

PRECHARGE .............................................................................................................................................. 79

REFRESH ................................................................................................................................................... 79

SELF REFRESH ........................................................................................................................................... 79

Mode Register (MR) ........................................................................................................................................ 79

Burst Length .............................................................................................................................................. 80

Burst Type .................................................................................................................................................. 81

Operating Mode ......................................................................................................................................... 81

DLL RESET ................................................................................................................................................. 81

Write Recovery ........................................................................................................................................... 82

Power-Down Mode ..................................................................................................................................... 82

CAS Latency (CL) ........................................................................................................................................ 83

Extended Mode Register (EMR) ....................................................................................................................... 84

DLL Enable/Disable ................................................................................................................................... 85

Output Drive Strength ................................................................................................................................ 85

DQS# Enable/Disable ................................................................................................................................. 85

RDQS Enable/Disable ................................................................................................................................. 85

Output Enable/Disable ............................................................................................................................... 85

On-Die Termination (ODT) ......................................................................................................................... 86

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 86

Posted CAS Additive Latency (AL) ................................................................................................................ 86

Extended Mode Register 2 (EMR2) ................................................................................................................... 88

Extended Mode Register 3 (EMR3) ................................................................................................................... 89

Initialization .................................................................................................................................................. 90

ACTIVATE ...................................................................................................................................................... 93

READ ............................................................................................................................................................. 95

READ with Precharge .................................................................................................................................. 99

READ with Auto Precharge ......................................................................................................................... 101

WRITE .......................................................................................................................................................... 106

PRECHARGE ................................................................................................................................................. 116

REFRESH ...................................................................................................................................................... 117

SELF REFRESH .............................................................................................................................................. 118

Power-Down Mode ........................................................................................................................................ 120

Precharge Power-Down Clock Frequency Change ........................................................................................... 127

Reset ............................................................................................................................................................. 128

CKE Low Anytime ...................................................................................................................................... 128

ODT Timing .................................................................................................................................................. 130

MRS Command to ODT Update Delay ........................................................................................................ 132

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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List of Figures

Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 9

Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12

Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13

Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 14

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 16

Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 19

Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ................................................................................ 20

Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 21

Figure 11: Example Temperature Test Point Location ...................................................................................... 24

Figure 12: Single-Ended Input Signal Levels ................................................................................................... 48

Figure 13: Differential Input Signal Levels ...................................................................................................... 49

Figure 14: Differential Output Signal Levels .................................................................................................... 51

Figure 15: Output Slew Rate Load .................................................................................................................. 52

Figure 16: Full Strength Pull-Down Characteristics ......................................................................................... 53

Figure 17: Full Strength Pull-Up Characteristics .............................................................................................. 54

Figure 18: Reduced Strength Pull-Down Characteristics .................................................................................. 55

Figure 19: Reduced Strength Pull-Up Characteristics ...................................................................................... 56

Figure 20: Input Clamp Characteristics .......................................................................................................... 57

Figure 21: Overshoot ..................................................................................................................................... 58

Figure 22: Undershoot ................................................................................................................................... 58

Figure 23: Nominal Slew Rate for tIS ............................................................................................................... 63

Figure 24: Tangent Line for tIS ........................................................................................................................ 63

Figure 25: Nominal Slew Rate for tIH .............................................................................................................. 64

Figure 26: Tangent Line for tIH ....................................................................................................................... 64

Figure 27: Nominal Slew Rate for tDS ............................................................................................................. 69

Figure 28: Tangent Line for tDS ...................................................................................................................... 69

Figure 29: Nominal Slew Rate for tDH ............................................................................................................. 70

Figure 30: Tangent Line for tDH ..................................................................................................................... 70

Figure 31: AC Input Test Signal Waveform Command/Address Balls ................................................................ 71

Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 71

Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 72

Figure 34: AC Input Test Signal Waveform (Differential) .................................................................................. 72

Figure 35: MR Definition ............................................................................................................................... 80

Figure 36: CL ................................................................................................................................................. 83

Figure 37: EMR Definition ............................................................................................................................. 84

Figure 38: READ Latency ............................................................................................................................... 87

Figure 39: WRITE Latency .............................................................................................................................. 87

Figure 40: EMR2 Definition ........................................................................................................................... 88

Figure 41: EMR3 Definition ........................................................................................................................... 89

Figure 42: DDR2 Power-Up and Initialization ................................................................................................. 90

Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 93

Figure 44: Multibank Activate Restriction ....................................................................................................... 94

Figure 45: READ Latency ............................................................................................................................... 96

Figure 46: Consecutive READ Bursts .............................................................................................................. 97

Figure 47: Nonconsecutive READ Bursts ........................................................................................................ 98

Figure 48: READ Interrupted by READ ............................................................................................................ 99

Figure 49: READ-to-WRITE ............................................................................................................................ 99

Figure 50: READ-to-PRECHARGE – BL = 4 ..................................................................................................... 100

1Gb: x4, x8, x16 DDR2 SDRAM

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Figure 51: READ-to-PRECHARGE – BL = 8 ..................................................................................................... 100

Figure 52: Bank Read – Without Auto Precharge ............................................................................................. 102

Figure 53: Bank Read – with Auto Precharge .................................................................................................. 103

Figure 54: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window .................................................. 104

Figure 55: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 105

Figure 56: Data Output Timing – tAC and tDQSCK ......................................................................................... 106

Figure 57: Write Burst ................................................................................................................................... 108

Figure 58: Consecutive WRITE-to-WRITE ...................................................................................................... 109

Figure 59: Nonconsecutive WRITE-to-WRITE ................................................................................................ 109

Figure 60: WRITE Interrupted by WRITE ....................................................................................................... 110

Figure 61: WRITE-to-READ ........................................................................................................................... 111

Figure 62: WRITE-to-PRECHARGE ................................................................................................................ 112

Figure 63: Bank Write – Without Auto Precharge ............................................................................................ 113

Figure 64: Bank Write – with Auto Precharge .................................................................................................. 114

Figure 65: WRITE – DM Operation ................................................................................................................ 115

Figure 66: Data Input Timing ........................................................................................................................ 116

Figure 67: Refresh Mode ............................................................................................................................... 117

Figure 68: Self Refresh .................................................................................................................................. 119

Figure 69: Power-Down ................................................................................................................................ 121

Figure 70: READ-to-Power-Down or Self Refresh Entry .................................................................................. 123

Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 123

Figure 72: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 124

Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 124

Figure 74: REFRESH Command-to-Power-Down Entry .................................................................................. 125

Figure 75: ACTIVATE Command-to-Power-Down Entry ................................................................................. 125

Figure 76: PRECHARGE Command-to-Power-Down Entry ............................................................................. 126

Figure 77: LOAD MODE Command-to-Power-Down Entry ............................................................................. 126

Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 127

Figure 79: RESET Function ........................................................................................................................... 129

Figure 80: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 131

Figure 81: Timing for MRS Command to ODT Update Delay .......................................................................... 132

Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 132

Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 133

Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 133

Figure 85: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 134

Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 135

Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 136

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 2

Table 2: Addressing ......................................................................................................................................... 2

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17

Table 4: Input Capacitance ............................................................................................................................ 22

Table 5: Absolute Maximum DC Ratings ......................................................................................................... 23

Table 6: Temperature Limits .......................................................................................................................... 24

Table 7: Thermal Impedance ......................................................................................................................... 25

Table 8: General IDD Parameters ..................................................................................................................... 26

Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 27

Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E and G) ...................................................... 28

Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) ................................................................ 31

Table 12: AC Operating Specifications and Conditions .................................................................................... 34

Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 46

Table 14: ODT DC Electrical Characteristics ................................................................................................... 47

Table 15: Input DC Logic Levels ..................................................................................................................... 48

Table 16: Input AC Logic Levels ...................................................................................................................... 48

Table 17: Differential Input Logic Levels ......................................................................................................... 49

Table 18: Differential AC Output Parameters ................................................................................................... 51

Table 19: Output DC Current Drive ................................................................................................................ 51

Table 20: Output Characteristics .................................................................................................................... 52

Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 53

Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 54

Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 55

Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 56

Table 25: Input Clamp Characteristics ............................................................................................................ 57

Table 26: Address and Control Balls ................................................................................................................ 58

Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 58

Table 28: AC Input Test Conditions ................................................................................................................ 59

Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) .................................................... 61

Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) ........................................... 62

Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ...................................................... 65

Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................. 66

Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb ................................................... 67

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ...................................... 67

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ...................................... 68

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ...................................... 68

Table 37: Truth Table – DDR2 Commands ...................................................................................................... 73

Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 74

Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 76

Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 77

Table 41: Burst Definition .............................................................................................................................. 81

Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 101

Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 107

Table 44: Truth Table – CKE .......................................................................................................................... 122

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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State Diagram

Figure 2: Simplified State Diagram

Automatic Sequence

Command Sequence

PRE

Initialization

sequence

Self

refreshing

CKE_L

Refreshing

Precharge

power-

down

Setting

MRS

EMRS

CKE_H

REFRESH

Idle

all banks

precharged

CKE_L

(E)MRS

OCD

default

Activating

ACT

Bank

active

Reading

READ

Writing

WRITE

Active

power-

down

CKE_L

CKE_H

CKE_L

Writing

with

auto

precharge

Reading

with

auto

precharge

READ A

WRITE A

PRE, PRE_A

WRITE A

READ A

PRE , PRE_A

READ A

READ

WRITE

Precharging

CKE_H

WRITE READ

PRE, PRE_A

ACT = ACTIVATE

CKE_H = CKE HIGH, exit power-down or self refresh

CKE_L = CKE LOW, enter power-down

(E)MRS = (Extended) mode register set

PRE = PRECHARGE

PRE_A = PRECHARGE ALL

READ = READ

READ A = READ with auto precharge

REFRESH = REFRESH

SR = SELF REFRESH

WRITE = WRITE

WRITE A = WRITE with auto precharge

Note: 1. This diagram provides the basic command flow. It is not comprehensive and does not

identify all timing requirements or possible command restrictions such as multibank in-

teraction, power down, entry/exit, etc.

1Gb: x4, x8, x16 DDR2 SDRAM

State Diagram

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Functional Description

The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture, with an

interface designed to transfer two data words per clock cycle at the I/O balls. A single

read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide,

one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-

wide, one-half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

during READs and by the memory controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for WRITEs. The x16 offering has two data

strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,

UDQS#).

The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE command are used to select

the bank and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write burst lengths of four or

eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another

read or a burst write of eight with another write. An auto precharge function may be en-

abled to provide a self-timed row precharge that is initiated at the end of the burst ac-

cess.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM

enables concurrent operation, thereby providing high, effective bandwidth by hiding

row precharge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength

outputs are SSTL_18-compatible.

Industrial Temperature

The industrial temperature (IT) option, if offered, has two simultaneous requirements:

ambient temperature surrounding the device cannot be less than –40°C or greater than

85°C, and the case temperature cannot be less than –40°C or greater than 95°C. JEDEC

specifications require the refresh rate to double when TC exceeds 85°C; this also requires

use of the high-temperature self refresh option. Additionally, ODT resistance, input/

output impedance and IDD values must be derated when TC is < 0°C or > 85°C.

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

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Automotive Temperature

The automotive temperature (AT) option, if offered, has two simultaneous require-

ments: ambient temperature surrounding the device cannot be less than –40°C or great-

er than 105°C, and the case temperature cannot be less than –40°C or greater than

105°C. JEDEC specifications require the refresh rate to double when TC exceeds 85°C;

this also requires use of the high-temperature self refresh option. Additionally, ODT re-

sistance the input/output impedance and IDD values must be derated when TC is < 0°C

or > 85°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.

For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the up-

per byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1k˖* resistor

– Connect UDQS# to VDD via 1k˖* resistor

– Connect UDM to VDD via 1k˖* resistor

– Connect DQ[15:8] individually to either VSS or VDD via 1k˖* resistors, or float

DQ[15:8].

*If ODT is used, 1k˖ resistor should be changed to 4x that of the selected ODT.

• Complete functionality is described throughout the document, and any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

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Functional Block Diagrams

The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-

nally configured as a multibank DRAM.

Figure 3: 256 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A13,

BA0–BA2

Address

512

(x16)

8,192

Column

decoder

Bank 0

Memory array

(16,384 x 512 x 16)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

RCVRS

CK out

DATA

DQS, DQS#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

DQ0–DQ3

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logic DQS, DQS#

sw1 sw2

Vss Q

sw1 sw2

ODT control

sw3

sw1 sw2

sw3

sw1 sw2

sw3

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

PDF: 09005aef821ae8bf

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Figure 4: 128 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A13,

BA0–BA2

Address

256

(x32)

8,192

Column

decoder

Bank 0

Memory array

(16,384 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

CK out

Data

UDQS, UDQS#

LDQS, LDQS#

CK,CK#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

DQ0–DQ7

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logic DQS, DQS#

RDQS#

RDQS

sw1 sw2

Vss Q

sw1 sw2

ODT control

sw3

sw1 sw2

sw3

sw1 sw2

sw3

RCVRS

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

PDF: 09005aef821ae8bf

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Figure 5: 64 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A12,

BA0–BA2

Address

(x64)

16,384

Column

decoder

Bank 0

Memory array

(8,192 x 256 x 64)

Bank 0

row-

address

latch

and

decoder

8,192

Sense amplifier

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

16 16

RCVRS

CK out

DATA

UDQS, UDQS#

LDQS, LDQS#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

UDQS, UDQS#

LDQS, LDQS#

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

UDM, LDM

DQ0–DQ15

sw1 sw2

Vss Q

sw1 sw2

ODT control

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logic

sw3

sw1 sw2

sw3

sw1 sw2

sw3

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

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Ball Assignments and Descriptions

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View)

465

DDQ

NF, DQ7

DDQ

NF, DQ5

ODT

NF, DQ6

DDQ

NF, DQ4

DDL

BA2

NC, RDQS#/NU

SSQ

DQ1

SSQ

REF

CKE

BA0

A10

A12

SSQ

DQS

DDQ

DQ2

SSDL

RAS#

CAS#

A11

RFU

DQS#/NU

SSQ

DQ0

SSQ

CK#

CS#

A13

DM, DM/RDQS

DDQ

DQ3

WE#

BA1

RFU

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef821ae8bf

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Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

VDD

VSS

UDQS#/NU

VSSQ

DQ8

VSSQ

LDQS#/NU

VSSQ

DQ0

VSSQ

CK#

CS#

RFU

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A11

RFU

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE#

BA1

RFU

VSSQ

DQ9

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VDD

DQ14

VDDQ

DQ12

VDD

DQ6

VDDQ

DQ4

VDDL

BA2

VSS

VDD

1234 67 895

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions

Symbol Type Description

A[12:0] (x16)

,A[13:0] (x4, x8)

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command.

BA[2:0] Input Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. BA[2:0] define which mode register, including MR,

EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK#. Output

data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates

clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides

precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-

er-down (row active in any bank). CKE is synchronous for power-down entry, power-

down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down.

Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input

but will detect a LVCMOS LOW level after VDD is applied during first power-up. After VREF

has become stable during the power-on and initialization sequence, it must be main-

tained for proper operation of the CKE receiver. For proper SELF REFRESH operation, VREF

must be maintained.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered high. CS# provides for exter-

nal bank selection on systems with multiple ranks. CS# is considered part of the com-

mand code.

LDM, UDM, DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on

both edges of DQS. Although DM balls are input-only, the DM loading is designed to

match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for

upper byte DQ[15:8].

ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to

the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:

DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,

RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input

will be ignored if disabled via the LOAD MODE command.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered.

DQ[15:0] (x16)

DQ[3:0] (x4)

DQ[7:0] (x8)

I/O Data input/output: Bidirectional data bus for 64 Meg x 16.

Bidirectional data bus for 256 Meg x 4.

Bidirectional data bus for 128 Meg x 8.

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

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Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)

Symbol Type Description

DQS, DQS# I/O Data strobe: Output with read data, input with write data for source synchronous oper-

ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used

when differential data strobe mode is enabled via the LOAD MODE command.

LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

RDQS, RDQS# Output Redundant data strobe: For x8 only. RDQS is enabled/disabled via the LOAD MODE

command to the extended mode register (EMR). When RDQS is enabled, RDQS is output

with read data only and is ignored during write data. When RDQS is disabled, ball B3 be-

comes data mask (see DM ball). RDQS# is only used when RDQS is enabled and differen-

tial data strobe mode is enabled.

VDD Supply Power supply: 1.8V ±0.1V.

VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.

VDDL Supply DLL power supply: 1.8V ±0.1V.

VREF Supply SSTL_18 reference voltage (VDDQ/2).

VSS Supply Ground.

VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

NC – No connect: These balls should be left unconnected.

NF – No function: x8: these balls are used as DQ[7:4]; x4: they are no function.

NU – Not used: For x16 only. If EMR(E10) = 0, A8 and E8 are UDQS# and LDQS#. If EMR(E10) =

1, then A8 and E8 are not used.

NU – Not used: For x8 only. If EMR(E10) = 0, A2 and E8 are RDQS# and DQS#. If EMR(E10) = 1,

then A2 and E8 are not used.

RFU – Reserved for future use: Row address bits A13 (x16 only), A14, and A15.

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

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Packaging

Package Dimensions

Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

123789

Ball A1 ID Ball A1 ID

0.25 MIN

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

11.2 CTR

12.5 ±0.1

84X Ø0.45

Dimensions apply

to solder balls

post-reflow on

Ø0.35 SMD ball pads.

0.8 TYP

Exposed gold plated pad

1.0 MAX X 0.7 nominal.

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn,

36%Pb, 2% Ag).

1Gb: x4, x8, x16 DDR2 SDRAM

Packaging

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1GbDDR2.pdf – Rev. W 7/11 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8

Ball A1 ID

0.8 TYP

8 ±0.1

987 321

Seating

plane

8 CTR

6.4 CTR

0.12 A

60X Ø0.45

Dimensions apply to

solder balls post-

reflow on Ø0.35

SMD ball pads.

11.5 ±0.1

Ball A1 ID

0.8 TYP

Exposed

gold-plated pad

1.0 MAX X 0.7

nonconductive

floating pad

0.8 ±0.1

1.2 MAX

0.25 MIN

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn,

36%Pb, 2% Ag).

1Gb: x4, x8, x16 DDR2 SDRAM

Packaging

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Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

123789

Ball A1 ID Ball A1 ID

0.25 MIN

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

8 CTR

10 ±0.1

60X Ø0.45

Dimensions

apply to solder

balls post-reflow

on Ø0.35 SMD

ball pads.

0.8 TYP

Exposed gold plated pad

1.0 MAX X 0.7 nominal.

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn,

36%Pb, 2% Ag).

1Gb: x4, x8, x16 DDR2 SDRAM

Packaging

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FBGA Package Capacitance

Table 4: Input Capacitance

Parameter Symbol Min Max Units Notes

Input capacitance: CK, CK# CCK 1.0 2.0 pF 1

Delta input capacitance: CK, CK# CDCK – 0.25 pF 2, 3

Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT CI1.0 2.0 pF 1, 4

Delta input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE,

ODT

CDI – 0.25 pF 2, 3

Input/output capacitance: DQ, DQS, DM, NF CIO 2.5 4.0 pF 1, 5

Delta input/output capacitance: DQ, DQS, DM, NF CDIO – 0.5 pF 2, 3

Notes: 1. This parameter is sampled. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V, VREF = VSS, f = 100 MHz,

TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O

balls, reflecting the fact that they are matched in loading.

2. The capacitance per ball group will not differ by more than this maximum amount for

any given device.

3. ˂C are not pass/fail parameters; they are targets.

4. Reduce MAX limit by 0.25pF for -25, -25E, and -187E speed devices.

5. Reduce MAX limit by 0.5pF for -3, -3E, -25, -25E, and -187E speed devices.

1Gb: x4, x8, x16 DDR2 SDRAM

Packaging

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Electrical Specifications – Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions outside those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 5: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD –1.0 2.3 V 1

VDDQ supply voltage relative to VSSQ VDDQ –0.5 2.3 V 1, 2

VDDL supply voltage relative to VSSL VDDL –0.5 2.3 V 1

Voltage on any ball relative to VSS VIN, VOUT –0.5 2.3 V 3

Input leakage current; any input 0V ื VIN ื VDD; all other

balls not under test = 0V

II–5 5 μA

Output leakage current; 0V ื VOUT ื VDDQ; DQ and ODT dis-

abled

IOZ –5 5 μA

VREF leakage current; VREF = Valid VREF level IVREF –2 2 μA

Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times; this is not re-

quired when power is ramping down.

2. VREF ื 0.6 × VDDQ; however, VREF may be ุ VDDQ provided that VREF ื 300mV.

3. Voltage on any I/O may not exceed voltage on VDDQ.

Temperature and Thermal Impedance

It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in

Table 6 (page 24), be maintained in order to ensure the junction temperature is in the

proper operating range to meet data sheet specifications. An important step in main-

taining the proper junction temperature is using the device’s thermal impedances cor-

rectly. The thermal impedances are listed in Table 7 (page 25) for the applicable and

available die revision and packages.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-

ces listed in Table 7. For designs that are expected to last several years and require the

flexibility to use several DRAM die shrinks, consider using final target theta values (rath-

er than existing values) to account for increased thermal impedances from the die size

reduction.

The DDR2 SDRAM device’s safe junction temperature range can be maintained when

the TC specification is not exceeded. In applications where the device’s ambient tem-

perature is too high, use of forced air and/or heat sinks may be required in order to sat-

isfy the case temperature specifications.

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – Absolute Ratings

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Table 6: Temperature Limits

Parameter Symbol Min Max Units Notes

Storage temperature TSTG –55 150 °C 1

Operating temperature: commercial TC0 85 °C 2, 3

Operating temperature: industrial TC–40 95 °C 2, 3, 4

TA–40 85 °C 4, 5

Operating temperature: automotive TC–40 105 °C 2, 3, 4

TA–40 105 °C 4, 5

Notes: 1. MAX storage case temperature TSTG is measured in the center of the package, as shown

in Figure 11. This case temperature limit is allowed to be exceeded briefly during pack-

age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa-

rameters.”

2. MAX operating case temperature TC is measured in the center of the package, as shown

in Figure 11.

3. Device functionality is not guaranteed if the device exceeds maximum TC during opera-

tion.

4. Both temperature specifications must be satisfied.

5. Operating ambient temperature surrounding the package.

Figure 11: Example Temperature Test Point Location

Width (W)

0.5 (W)

Length (L)

0.5 (L)

Test point

Lmm x Wmm FBGA

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – Absolute Ratings

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Table 7: Thermal Impedance

Die Revision Package

Substrate

(pcb)

JA (°C/W)

Airflow = 0m/s

JA (°C/W)

Airflow = 1m/s

JA (°C/W)

Airflow = 2m/s

JB (°C/W)

JC (°C/W)

G160-ball 2-layer 66.5 49.6 43.1 30.3 5.9

4-layer 49.2 40.4 36.4 30

84-ball 2-layer 60.2 44.5 39.3 26.1 5.6

4-layer 44 35.7 32.8 26.1

H160-ball 2-layer 72.5 55.5 49.5 35.6 5.7

4-layer 54.5 45.7 42.3 35.2

84-ball 2-layer 68.8 52.0 46.5 32.5 5.6

4-layer 51.3 42.7 39.6 32.3

Note: 1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – Absolute Ratings

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Electrical Specifications – IDD Parameters

IDD Specifications and Conditions

Table 8: General IDD Parameters

IDD Parameters -187E -25E -25 -3E -3 -37E -5E Units

CL (IDD) 7564543

tCK

tRCD (IDD) 13.125 12.5 15 12 15 15 15 ns

tRC (IDD) 58.125 57.5 60 57 60 60 55 ns

tRRD (IDD) - x4/x8 (1KB) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns

tRRD (IDD) - x16 (2KB) 10 10 10 10 10 10 10 ns

tCK (IDD) 1.875 2.5 2.5 3 3 3.75 5 ns

tRAS MIN (IDD) 45454545454540ns

tRAS MAX (IDD) 70,000 70,000 70,000 70,000 70,000 70,000 70,000 ns

tRP (IDD) 13.125 12.5 15 12 15 15 15 ns

tRFC (IDD - 256Mb) 75 75 75 75 75 75 75 ns

tRFC (IDD - 512Mb) 105 105 105 105 105 105 105 ns

tRFC (IDD - 1Gb) 127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns

tRFC (IDD - 2Gb) 197.5 197.5 197.5 197.5 197.5 197.5 197.5 ns

tFAW (IDD) - x4/x8 (1KB) Defined by pattern in Table 9 (page 27) ns

tFAW (IDD) - x16 (2KB) Defined by pattern in Table 9 (page 27) ns

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

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IDD7 Conditions

The detailed timings are shown below for IDD7. Where general IDD parameters in

Table 8 (page 26) conflict with pattern requirements of Table 9, then Table 9 require-

ments take precedence.

Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation)

Speed

Grade IDD7 Timing Patterns

Timing patterns for 8-bank x4/x8 devices

-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7

-37E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-3 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

-3E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

-25 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-25E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-187E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

Timing patterns for 8-bank x16 devices

-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-3 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

-3E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

-25 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

-25E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

-187E A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D

D D D A7 RA7 D D D D

Notes: 1. A = active; RA = read auto precharge; D = deselect.

2. All banks are being interleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.

3. Control and address bus inputs are stable during deselects.

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E and G)

Notes: 1–7 apply to the entire table

Parameter/Condition Symbol Configuration -187E

-25E/

-25

-3E/

-3 -37E -5E Units

Operating one bank active-

precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN

(IDD); CKE is HIGH, CS# is HIGH be-

tween valid commands; Address

bus inputs are switching; Data bus

inputs are switching

IDD0 x4, x8 115 90 85 70 70 mA

x16 180 150 135 110 110

Operating one bank active-read-

precharge current: IOUT = 0mA; BL

= 4, CL = CL (IDD), AL = 0; tCK = tCK

(IDD), tRC = tRC (IDD), tRAS = tRAS

MIN (IDD), tRCD = tRCD (IDD); CKE is

HIGH, CS# is HIGH between valid

commands; Address bus inputs are

switching; Data pattern is same as

IDD4W

IDD1 x4, x8 130 110 100 95 90 mA

x16 210 175 130 120 115

Precharge power-down current:

All banks idle; tCK = tCK (IDD); CKE

is LOW; Other control and address

bus inputs are stable; Data bus in-

puts are floating

IDD2P x4, x8, x16 7 7 7 7 7 mA

Precharge quiet standby

current: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is

HIGH; Other control and address

bus inputs are stable; Data bus in-

puts are floating

IDD2Q x4, x8 60 50 40 40 35 mA

x16 90 75 65 45 40

Precharge standby current: All

banks idle; tCK = tCK (IDD); CKE is

HIGH, CS# is HIGH; Other control

and address bus inputs are switch-

ing; Data bus inputs are switching

IDD2N x4, x8 60 50 40 40 35 mA

x16 95 80 70 50 40

Active power-down current: All

banks open; tCK = tCK (IDD); CKE is

LOW; Other control and address

bus inputs are stable; Data bus in-

puts are floating

IDD3Pf Fast exit

MR12 = 0

50 40 30 30 30 mA

IDD3Ps Slow exit

MR12 = 1

10 10 10 10 10

Active standby current: All banks

open; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is

HIGH, CS# is HIGH between valid

commands; Other control and ad-

dress bus inputs are switching; Data

bus inputs are switching

IDD3N x4, x8 70 60 55 45 40 mA

x16 95 85 75 60 55

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E and G) (Continued)

Notes: 1–7 apply to the entire table

Parameter/Condition Symbol Configuration -187E

-25E/

-25

-3E/

-3 -37E -5E Units

Operating burst write current:

All banks open, continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH,

CS# is HIGH between valid com-

mands; Address bus inputs are

switching; Data bus inputs are

switching

IDD4W x4 190 145 120 110 90 mA

x8 210 160 135 125 105

x16 405 315 200 180 160

Operating burst read current:

All banks open, continuous burst

reads, IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRAS =

tRAS MAX (IDD), tRP = tRP (IDD); CKE

is HIGH, CS# is HIGH between valid

commands; Address bus inputs are

switching; Data bus inputs are

switching

IDD4R x4 190 145 120 110 90 mA

x8 210 160 135 125 105

x16 420 320 220 180 160

Burst refresh current: tCK = tCK

(IDD); REFRESH command at every

tRFC (IDD) interval; CKE is HIGH, CS#

is HIGH between valid commands;

Other control and address bus in-

puts are switching; Data bus inputs

are switching

IDD5 x4, x8 265 235 215 210 205 mA

x16 300 280 270 250 240

Self refresh current: CK and CK#

at 0V; CKE ื 0.2V; Other control

and address bus inputs are floating;

Data bus inputs are floating

IDD6 x4, x8, x16 7 7 7 7 7 mA

IDD6L 555 5 5

Operating bank interleave read

current: All bank interleaving

reads, IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = tRCD (IDD) - 1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD

= tRRD (IDD), tRCD = tRCD (IDD); CKE

is HIGH, CS# is HIGH between valid

commands; Address bus inputs are

stable during deselects; Data bus

inputs are switching; See on page

for details

IDD7 x4, x8 425 335 280 270 260 mA

x16 520 440 350 330 300

Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ื TC ื +85°C.

2. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V, VDDL = 1.8V ±0.1V, VREF = VDDQ/2.

3. IDD parameters are specified with ODT disabled.

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and

UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.

5. Definitions for IDD conditions:

LOW VIN ื VIL(AC)max

HIGH VIN ุ VIH(AC)min

Stable Inputs stable at a HIGH or LOW level

Floating Inputs at VREF = VDDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.

7. The following IDD values must be derated (IDD limits increase) on IT-option and AT-option

devices when operated outside of the range 0°C ื TC ื 85°C:

When

TC ื

ื

0°C

IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derat-

ed by 2%; and IDD6 and IDD7 must be derated by 7%

When

ุ

85°C

IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derat-

ed by 2%; IDD2P must be derated by 20%; IDD3P(SLOW) must be derated by

30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if

TC < 85°C and the 2X refresh option is still enabled)

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 11: DDR2 IDD Specifications and Conditions (Die Revision H)

Notes: 1–7 apply to the entire table

Parameter/Condition Symbol Configuration -187E

-25E/

-25

-3E/

-3 Units

Operating one bank active-

precharge current: tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is

HIGH between valid commands; Address bus in-

puts are switching; Data bus inputs are switch-

ing

IDD0 x4, x8 85 65 60 mA

x16 100 80 75

Operating one bank active-read-precharge

current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL =

0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS

MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is

HIGH between valid commands; Address bus in-

puts are switching; Data pattern is same as

IDD4W

IDD1 x4, x8 100 75 70 mA

x16 115 95 90

Precharge power-down current: All banks

idle; tCK = tCK (IDD); CKE is LOW; Other control

and address bus inputs are stable; Data bus in-

puts are floating

IDD2P x4, x8, x16 7 7 7 mA

Precharge quiet standby

current: All banks idle; tCK = tCK (IDD); CKE is

HIGH, CS# is HIGH; Other control and address

bus inputs are stable; Data bus inputs are float-

ing

IDD2Q x4, x8 35 24 24 mA

x16 40 26 26

Precharge standby current: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are switching;

Data bus inputs are switching

IDD2N x4, x8 40 28 24 mA

x16 45 30 26

Active power-down current: All banks open;

tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs

are floating

IDD3Pf Fast exit

MR12 = 0

30 20 15 mA

IDD3Ps Slow exit

MR12 = 1

10 10 10

Active standby current: All banks open;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, CS# is HIGH be-

tween valid commands; Other control and ad-

dress bus inputs are switching; Data bus inputs

are switching

IDD3N x4, x8 40 33 30 mA

x16 45 35 32

Operating burst write current: All banks

open, continuous burst writes; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs

are switching; Data bus inputs are switching

IDD4W x4 ,x8 155 125 115 mA

x16 200 160 135

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) (Continued)

Notes: 1–7 apply to the entire table

Parameter/Condition Symbol Configuration -187E

-25E/

-25

-3E/

-3 Units

Operating burst read current: All banks

open, continuous burst reads, IOUT = 0mA; BL =

4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS =

tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS#

is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switch-

ing

IDD4R x4, x8 150 120 110 mA

x16 190 150 125

Burst refresh current: tCK = tCK (IDD); RE-

FRESH command at every tRFC (IDD) interval;

CKE is HIGH, CS# is HIGH between valid com-

mands; Other control and address bus inputs

are switching; Data bus inputs are switching

IDD5 x4, x8 180 145 140 mA

x16 210 150 145

Self refresh current: CK and CK# at 0V; CKE ื

0.2V; Other control and address bus inputs are

floating; Data bus inputs are floating

IDD6 x4, x8, x16 7 7 7 mA

IDD6L 555

Operating bank interleave read

current: All bank interleaving reads, IOUT =

0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 ×

tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD =

tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is

HIGH between valid commands; Address bus in-

puts are stable during deselects; Data bus inputs

are switching; See on page for details

IDD7 x4, x8 250 210 185 mA

x16 300 260 230

Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ื TC ื +85°C.

2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and

UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.

5. Definitions for IDD conditions:

LOW VIN ื VIL(AC)max

HIGH VIN ุ VIH(AC)min

Stable Inputs stable at a HIGH or LOW level

Floating Inputs at VREF = VDDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.

7. The following IDD values must be derated (IDD limits increase) on IT-option and AT-option

devices when operated outside of the range 0°C ื TC ื 85°C:

When

TC ื

ื

0°C

IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derat-

ed by 2%; and IDD6 and IDD7 must be derated by 7%

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice.

When

TC ุ

ุ

85°C

IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derat-

ed by 2%; IDD2P must be derated by 20%; IDD3P(SLOW) must be derated by

30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if

TC < 85°C and the 2X refresh option is still enabled)

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice.

AC Timing Operating Specifications

Table 12: AC Operating Specifications and Conditions

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Clock

cycle time

CL = 7 tCK (avg) 1.875 8.0 – – – – – – – – – – – – ns 6, 7, 8,

CL = 6 tCK (avg) 2.5 8.0 2.5 8.0 2.5 8.0 – – – – – – – –

CL = 5 tCK (avg) 2.5 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 – – – –

CL = 4 tCK (avg) 3.75 8.0 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0

CL = 3 tCK (avg) 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0

CK high-level

width

tCH (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK 10

CK low-level width tCL (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK

Half clock period tHP MIN = lesser of tCH and tCL

MAX = n/a

ps 11

Absolute tCK tCK (abs) MIN = tCK (AVG) MIN + tJITper (MIN)

MAX = tCK (AVG) MAX + tJITper (MAX)

Absolute CK

high-level width

tCH (abs) MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN)

MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)

Absolute CK

low-level width

tCL (abs) MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)

MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Clock Jitter

Period jitter tJITper –90 90 –100 100 –100 100 –125 125 –125 125 –125 125 –125 125 ps 12

Half period tJITdty –75 75 –100 100 –100 100 –125 125 –125 125 –125 125 –150 150 ps 13

Cycle to cycle tJITcc 180 200 200 250 250 250 250 ps 14

Cumulative error,

2 cycles

tERR2per –132 132 –150 150 –150 150 –175 175 –175 175 –175 175 –175 175 ps 15

Cumulative error,

3 cycles

tERR3per –157 157 –175 175 –175 175 –225 225 –225 225 –225 225 –225 225 ps 15

Cumulative error,

4 cycles

tERR4per –175 175 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15

Cumulative error,

5 cycles

tERR5per –188 188 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15, 16

Cumulative error,

6–10 cycles

tERR6–

10per

–250 250 –300 300 –300 300 –350 350 –350 350 –350 350 –350 350 ps 15, 16

Cumulative error,

11–50 cycles

tERR11–

50per

–425 425 –450 450 –450 450 –450 450 –450 450 –450 450 –450 450 ps 15

Data Strobe-Out

DQS output access

time from CK/CK#

tDQSCK –300 300 –350 350 –350 350 –400 400 –400 400 –450 450 –500 500 ps 19

DQS read pream-

ble

tRPRE MIN = 0.9 × tCK

MAX = 1.1 × tCK

tCK 17, 18,

DQS read

postamble

tRPST MIN = 0.4 × tCK

MAX = 0.6 × tCK

tCK 17, 18,

19, 20

CK/CK# to DQS

Low-Z

tLZ1MIN = tAC (MIN)

MAX = tAC (MAX)

ps 19, 21,

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Data Strobe-In

DQS rising edge to

CK rising edge

tDQSS MIN = –0.25 × tCK

MAX = 0.25 × tCK

tCK 18

DQS input-high

pulse width

tDQSH MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS input-low

pulse width

tDQSL MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS falling to CK

rising: setup time

tDSS MIN = 0.2 × tCK

MAX = n/a

tCK 18

DQS falling from

CK rising:

hold time

tDSH MIN = 0.2 × tCK

MAX = n/a

tCK 18

Write preamble

setup time

tWPRES MIN = 0

MAX = n/a

ps 23, 24

DQS write

preamble

tWPRE MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS write

postamble

tWPST MIN = 0.4 × tCK

MAX = 0.6 × tCK

tCK 18, 25

WRITE command

to first DQS

transition

– MIN = WL - tDQSS

MAX = WL + tDQSS

tCK

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Data-Out

DQ output access

time from CK/CK#

tAC –350 350 –400 400 –400 400 –450 450 –450 450 –500 500 –600 600 ps 19

DQS–DQ skew,

DQS to last DQ

valid, per group,

per access

tDQSQ – 175 – 200 – 200 – 240 – 240 – 300 – 350 ps 26, 27

DQ hold from next

DQS strobe

tQHS – 250 – 300 – 300 – 340 – 340 – 400 – 450 ps 28

DQ–DQS hold, DQS

to first DQ not val-

tQH MIN = tHP - tQHS

MAX = n/a

ps 26, 27,

CK/CK# to DQ, DQS

High-Z

tHZ MIN = n/a

MAX = tAC (MAX)

ps 19, 21,

CK/CK# to DQ

Low-Z

tLZ2MIN = 2 × tAC (MIN)

MAX = tAC (MAX)

ps 19, 21,

Data valid output

window

DVW MIN = tQH - tDQSQ

MAX = n/a

ns 26, 27

Data-In

DQ and DM input

setup time to DQS

tDSb 0 – 50 – 50 – 100 – 100 – 100 – 150 – ps 26, 30,

DQ and DM input

hold time to DQS

tDHb 75 – 125 – 125 – 175 – 175 – 225 – 275 – ps 26, 30,

DQ and DM input

setup time to DQS

tDSa 200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26, 30,

DQ and DM input

hold time to DQS

tDHa 200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26, 30,

DQ and DM input

pulse width

tDIPW MIN = 0.35 × tCK

MAX = n/a

tCK 18, 32

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Command and Address

Input setup time tISb 125 – 175 – 175 – 200 – 200 – 250 – 350 – ps 31, 33

Input hold time tIHb 200 – 250 – 250 – 275 – 275 – 375 – 475 – ps 31, 33

Input setup time tISa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33

Input hold time tIHa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33

Input pulse width tIPW 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – tCK 18, 32

ACTIVATE-to-

ACTIVATE delay,

same bank

tRC 54 – 55 – 55 – 54 – 55 – 55 – 55 – ns 18, 34,

ACTIVATE-to-READ

or WRITE delay

tRCD 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18

ACTIVATE-to-

PRECHARGE delay

tRAS 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K ns 18, 34,

PRECHARGE period tRP 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36

PRE-

CHARGE

ALL period

<1Gb tRPA 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36

ุ1Gb tRPA 15 – 15 – 17.5 15 18 18.75 20 ns 18, 36

ACTIVATE

-to-

ACTIVATE

delay

different

bank

x4, x8 tRRD 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18, 37

x16 tRRD 10 – 10 – 10 – 10 – 10 – 10 – 10 – ns 18, 37

4-bank

activate

period

(ุ1Gb)

x4, x8 tFAW 35 – 35 – 35 – 37.5 – 37.5 – 37.5 – 37.5 – ns 18, 38

x16 tFAW 45 – 45 – 45 – 50 – 50 – 50 – 50 – ns 18, 38

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Command and Address

Internal READ-to-

PRECHARGE delay

tRTP 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18, 37,

CAS#-to-CAS#

delay

tCCD2 – 2–2–2–2–2–2–

tCK 18

Write recovery

time

tWR 15 – 15 – 15 – 15 – 15 – 15 – 15 – ns 18, 37

Write AP recovery

+ precharge time

tDAL tWR +

tRP

–tWR +

tRP

–tWR +

tRP

–tWR +

tRP

–tWR +

tRP

–tWR +

tRP

–tWR +

tRP

–ns 40

Internal WRITE-to-

READ delay

tWTR 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 10 – ns 18, 37

LOAD MODE cycle

time

tMRD2 – 2–2–2–2–2–2–

tCK 18

Refresh

REFRESH-

to-

ACTIVATE

or to

-REFRESH

interval

256Mb tRFC 75 – 75 – 75 – 75 – 75 – 75 – 75 – ns 18, 41

512Mb 105 – 105 – 105 – 105 – 105 – 105 – 105 –

1Gb 127.5 – 127.5 – 127.5 – 127.5 – 127.5 – 127.5 – 127.5 –

2Gb 195 – 195 – 195 – 195 – 195 – 195 – 195 –

Average periodic

refresh

(commercial)

tREFI – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 μs 18, 41

Average periodic

refresh

(industrial)

tREFIIT – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 μs 18, 41

Average periodic

refresh

(automotive)

tREFIAT – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 μs 18, 41

CKE LOW to CK,

CK# uncertainty

tDELAY MIN limit = tIS + tCK + tIH

MAX limit = n/a

ns 42

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Self Refresh

Exit SELF REFRESH

to nonREAD

command

tXSNR MIN limit = tRFC (MIN) + 10

MAX limit = n/a

Exit SELF REFRESH

to READ command

tXSRD MIN limit = 200

MAX limit = n/a

tCK 18

Exit SELF REFRESH

timing reference

tISXR MIN limit = tIS

MAX limit = n/a

ps 33, 43

Power-Down

Exit active

power-

down to

READ

command

MR12

= 0

tXARD 3 – 2 – 2 – 2 – 2 – 2 – 2 – tCK 18

MR12

= 1

10 -

– 8 - AL – 8 - AL – 7 - AL – 7 - AL – 6 - AL – 6 - AL – tCK 18

Exit precharge

power-down and

active power-down

to any

nonREAD

command

tXP 3 – 2–2–2–2–2–2–

tCK 18

CKE MIN

HIGH/LOW time

tCKE MIN = 3

MAX = n/a

tCK 18, 44

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

ODT

ODT to power-

down entry latency

tANPD 4 – 3 – 3 – 3 – 3 – 3 – 3 – tCK 18

ODT power-down

exit latency

tAXPD 11 – 10 – 10 – 8 – 8 – 8 – 8 – tCK 18

ODT turn-on delay tAOND 2 tCK 18

ODT turn-off delay tAOFD 2.5 tCK 18, 45

ODT turn-on tAON tAC

(MIN)

tAC

(MAX)

2575

MIN = tAC (MIN)

MAX = tAC (MAX) + 600

MIN = tAC (MIN)

MAX = tAC (MAX) + 700

MIN = tAC (MIN)

MAX = tAC (MAX) + 1000

ps 19, 46

ODT turn-off tAOF MIN = tAC (MIN)

MAX = tAC (MAX) + 600

ps 47, 48

ODT turn-on

(power-down

mode)

tAONPD tAC

(MIN)

+ 2000

2 ×

tCK +

tAC

(MAX)

1000

MIN = tAC (MIN) + 2000

MAX = 2 × tCK + tAC (MAX) + 1000

ps 49

ODT turn-off

(power-down

mode)

tAOFPD MIN = tAC (MIN) + 2000

MAX = 2.5 × tCK + tAC (MAX) + 1000

ODT enable from

MRS command

tMOD MIN = 12

MAX = n/a

ns 18, 50

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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Notes: 1. All voltages are referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply

voltage levels, but the related specifications and the operation of the device are warranted for the full voltage

range specified. ODT is disabled for all measurements that are not ODT-specific.

3. Outputs measured with equivalent load (see Figure 15 (page 52)).

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment, and parameter specifica-

tions are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input

signals used to test the device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates other than

1.0 V/ns may require the timing parameters to be derated as specified.

5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will effective-

ly switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal

does not ring back above [below] the DC input LOW [HIGH] level).

6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).

7. Operating frequency is only allowed to change during self refresh mode (see Figure 78 (page 127)), precharge

power-down mode, or system reset condition (see Reset (page 128)). SSC allows for small deviations in operating

frequency, provided the SSC guidelines are satisfied.

8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock

rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed provided it does not

exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.

9. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate

spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent tCK (AVG); however, the

spread spectrum may not use a clock rate below tCK (AVG) MIN or above tCK (AVG) MAX.

10. MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the

device. The clock’s half period must also be of a Gaussian distribution; tCH (AVG) and tCL (AVG) must be met with

or without clock jitter and with or without duty cycle jitter. tCH (AVG) and tCL (AVG) are the average of any 200

consecutive CK falling edges. tCH limits may be exceeded if the duty cycle jitter is small enough that the absolute

half period limits (tCH [ABS], tCL [ABS]) are not violated.

11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK# inputs; thus, tHP (MIN) ุ the lesser

of tCL (ABS) MIN and tCH (ABS) MIN.

12. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock allowed

in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During

DLL lock time, the jitter values should be 20 percent less those than noted in the table (DLL locked).

13. The half-period jitter (tJITdty) applies to either the high pulse of clock or the low pulse of clock; however, the two

cumulatively can not exceed tJITper.

14. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next. JEDEC speci-

fies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent

less than those noted in the table (DLL locked).

15. The cumulative jitter error (tERRnper), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time allowed to

consecutively accumulate away from the average clock over any number of clock cycles.

16. JEDEC specifies using tERR6–10per when derating clock-related output timing (see notes 19 and 48). Micron requires

less derating by allowing tERR5per to be used.

17. This parameter is not referenced to a specific voltage level but is specified when the device output is no longer

driving (tRPST) or beginning to drive (tRPRE).

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-

er, the input timing (in ns) references to the tCK (AVG) when determining the required number of clocks. The fol-

lowing input parameters are determined by taking the specified percentage times the tCK (AVG) rather than tCK:

tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.

19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by

the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The

following parameters are required to be derated by subtracting tERR5per (MAX): tAC (MIN), tDQSCK (MIN), tLZDQS

(MIN), tLZDQ (MIN), tAON (MIN); while the following parameters are required to be derated by subtracting

tERR5per (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter

tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX), is derated by subtracting tJITper (MIN).

The parameter tRPST (MIN) is derated by subtracting tJITdty (MAX), while tRPST (MAX), is derated by subtracting

tJITdty (MIN). Output timings that require tERR5per derating can be observed to have offsets relative to the clock;

however, the total window will not degrade.

20. When DQS is used single-ended, the minimum limit is reduced by 100ps.

21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not

referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driv-

ing (tLZ).

22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.

23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-

ded due to bus turnaround.

24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-

ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous

WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.

25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either

be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input

requirements. That is, if DQS transitions HIGH (above VIH[DC]min), then it must not transition LOW (below VIH[DC])

prior to tDQSH (MIN).

26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and

UDQS with DQ[15:8].

27. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS).

The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can

be derived.

28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or tCH (ABS) MAX times tCK (ABS) MIN

- tQHS. Minimizing the amount of tCH (AVG) offset and value of tJITdty will provide a larger tQH, which in turn

will provide a larger valid data out window.

29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST

(MAX) condition.

30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns

for each signal). There are two sets of values listed: tDSa, tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference

only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The

baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb is referenced

from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tDHb is referenced from VIL(DC) for a rising sig-

nal and VIH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values

must be derated by adding the values from Table 31 (page 65) and Table 32 (page 66). If the DQS differential

strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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Table 33 (page 67). Single-ended DQS data timing is referenced at DQS crossing VREF. The correct timing values

for a single-ended DQS strobe are listed in Table 34 (page 67)–Table 36 (page 68) on Table 34 (page 67),

Table 35 (page 68), and Table 36 (page 68); listed values are already derated for slew rate variations and con-

verted from baseline values to VREF values.

31. VIL/VIH DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification (page 58).

32. For each input signal—not the group collectively.

33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values (for reference

only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1 V/ns. The baseline values,

tISb, tIHb, are the JEDEC-defined values, referenced from the logic trip points. tISb is referenced from VIH(AC) for a

rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a

falling signal. If the command/address slew rate is not equal to 1 V/ns, then the baseline values must be derated

by adding the values from Table 29 (page 61) and Table 30 (page 62).

34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to tWR during auto pre-

charge.

35. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied because tRAS lock-

out feature is supported in DDR2 SDRAM.

36. When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing applies when the PRE-

CHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices (ุ1Gb), tRPA (MIN)

= tRP (MIN) + tCK (AVG) (Table 12 (page 34) lists tRP [MIN] + tCK [AVG] MIN).

37. This parameter has a two clock minimum requirement at any tCK.

38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE commands may

be issued in a given tFAW (MIN) period. tRRD (MIN) restriction still applies.

39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch begins to

when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the

READ so that data will output CL later. This parameter is only applicable when tRTP/(2 × tCK) > 1, such as frequen-

cies faster than 533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK) ื 1, then equation AL + BL/2 applies. tRAS (MIN) has

to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS

(MIN) has been satisfied.

40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next integer.

tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR9–MR11. For exam-

ple, -37E at tCK = 3.75ns with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks =

4 + (4) clocks = 8 clocks.

41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average refresh

rate of 7.8125μs (commercial) or 3.9607μs (industrial and automotive). To ensure all rows of all banks are properly

refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial and automotive).

The JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.

42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being re-

moved in a system RESET condition (see Reset (page 128)).

43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in Figure 68 (page 119).

44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must re-

main at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any

CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 × tCK + tIH.

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the

amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 -

0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or 2.53, for tAOF (MAX).

46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-

on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.

47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX)

is when the bus is in High-Z. Both are measured from tAOFD.

48. Half-clock output parameters must be derated by the actual tERR5per and tJITdty when input clock jitter is present;

this will result in each parameter becoming larger. The parameter tAOF (MIN) is required to be derated by sub-

tracting both tERR5per (MAX) and tJITdty (MAX). The parameter tAOF (MAX) is required to be derated by subtract-

ing both tERR5per (MIN) and tJITdty (MIN).

49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1000 but it will likely be 3 x tCK + tAC (MAX) + 1000 in the

future.

50. Should use 8 tCK for backward compatibility.

51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-

dress may result in reduction of the product lifetime.

1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

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AC and DC Operating Conditions

Table 13: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to VSS

Parameter Symbol Min Nom Max Units Notes

Supply voltage VDD 1.7 1.8 1.9 V 1, 2

VDDL supply voltage VDDL 1.7 1.8 1.9 V 2, 3

I/O supply voltage VDDQ 1.7 1.8 1.9 V 2, 3

I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V4

I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC) VREF(DC) + 40 mV 5

Notes: 1. VDD and VDDQ must track each other. VDDQ must be ื VDD.

2. VSSQ = VSSL = VSS.

3. VDDQ tracks with VDD; VDDL tracks with VDD.

4. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the

DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed

±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent

of VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.

5. VTT is not applied directly to the device. VTT is a system supply for signal termination re-

sistors, is expected to be set equal to VREF, and must track variations in the DC level of

VREF.

1Gb: x4, x8, x16 DDR2 SDRAM

AC and DC Operating Conditions

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ODT DC Electrical Characteristics

Table 14: ODT DC Electrical Characteristics

All voltages are referenced to VSS

Parameter Symbol Min Nom Max Units Notes

RTT effective impedance value for 75˖ setting

EMR (A6, A2) = 0, 1

RTT1(EFF) 60 75 90 ˖1, 2

RTT effective impedance value for 150˖ setting

EMR (A6, A2) = 1, 0

RTT2(EFF) 120 150 180 ˖1, 2

RTT effective impedance value for 50˖ setting

EMR (A6, A2) = 1, 1

RTT3(EFF) 40 50 60 ˖1, 2

Deviation of VM with respect to VDDQ/2 ˂VM –6 – 6 % 3

Notes: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(DC) to the ball

being tested, and then measuring current, I(VIH[AC]), and I(VIL[AC]), respectively.

2. Minimum IT and AT device values are derated by six percent less when the devices oper-

ate between –40°C and 0°C (TC ).

3. Measure voltage (VM) at tested ball with no load.

1Gb: x4, x8, x16 DDR2 SDRAM

ODT DC Electrical Characteristics

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Input Electrical Characteristics and Operating Conditions

Table 15: Input DC Logic Levels

All voltages are referenced to VSS

Parameter Symbol Min Max Units

Input high (logic 1) voltage VIH(DC) VREF(DC) + 125 VDDQ1mV

Input low (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV

Note: 1. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Table 16: Input AC Logic Levels

All voltages are referenced to VSS

Parameter Symbol Min Max Units

Input high (logic 1) voltage (-37E/-5E) VIH(AC) VREF(DC) + 250 VDDQ1mV

Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3) VIH(AC) VREF(DC) + 200 VDDQ1mV

Input low (logic 0) voltage (-37E/-5E) VIL(AC) –300 VREF(DC) - 250 mV

Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3) VIL(AC) –300 VREF(DC) - 200 mV

Note: 1. Refer to AC Overshoot/Undershoot Specification (page 58).

Figure 12: Single-Ended Input Signal Levels

650mV

775mV

864mV

882mV

900mV

918mV

936mV

1,025mV

1,150mV

VIL(AC)

VIL(DC)

VREF - AC noise

VREF - DC error

VREF + DC error

VREF + AC noise

VIH(DC)

VIH(AC)

Note: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

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Table 17: Differential Input Logic Levels

All voltages referenced to VSS

Parameter Symbol Min Max Units Notes

DC input signal voltage VIN(DC) –300 VDDQ mV 1, 6

DC differential input voltage VID(DC) 250 VDDQ mV 2, 6

AC differential input voltage VID(AC) 500 VDDQ mV 3, 6

AC differential cross-point voltage VIX(AC) 0.50 × VDDQ - 175 0.50 × VDDQ + 175 mV 4

Input midpoint voltage VMP(DC) 850 950 mV 5

Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,

CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where

VTR is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary

input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to VIH(DC) -

VIL(DC). Differential input signal levels are shown in Figure 13.

3. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where

VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the comple-

mentary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is

equal to VIH(AC) - VIL(AC), as shown in Table 16 (page 48).

4. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device

and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which

differential input signals must cross, as shown in Figure 13.

5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is

the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC)

is expected to be approximately 0.5 × VDDQ.

6. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Figure 13: Differential Input Signal Levels

TR2

CP2

2.1V

VDDQ = 1.8V

VIN(DC)max1

VIN(DC)min1

–0.30V

0.9V

1.075V

0.725V

VID(AC)6

VID(DC)5

VMP(DC)3VIX(AC)4

Notes: 1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.

2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,

RDQS#, LDQS#, and UDQS# signals.

3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be

VDDQ/2.

4. TR and CP must cross in this region.

5. TR and CP must meet at least VID(DC)min when static and is centered around VMP(DC).

6. TR and CP must have a minimum 500mV peak-to-peak swing.

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

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7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

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Output Electrical Characteristics and Operating Conditions

Table 18: Differential AC Output Parameters

Parameter Symbol Min Max Units Notes

AC differential cross-point voltage VOX(AC) 0.50 × VDDQ - 125 0.50 × VDDQ + 125 mV 1

AC differential voltage swing Vswing 1.0 – mV

Note: 1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting de-

vice and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at

which differential output signals must cross.

Figure 14: Differential Output Signal Levels

Crossing point

VOX

VSSQ

Vswing

VDDQ

VTR

VCP

Table 19: Output DC Current Drive

Parameter Symbol Value Units Notes

Output MIN source DC current IOH –13.4 mA 1, 2, 4

Output MIN sink DC current IOL 13.4 mA 2, 3, 4

Notes: 1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21˖ for val-

ues of VOUT between VDDQ and VDDQ - 280mV.

2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21˖ for values of VOUT

between 0V and 280mV.

3. The DC value of VREF applied to the receiving device is set to VTT.

4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They

are used to test device drive current capability to ensure VIH,min plus a noise margin and

VIL,max minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-

ues are derived by shifting the desired driver operating point (see output IV curves)

along a 21˖ load line to define a convenient driver current for measurement.

1Gb: x4, x8, x16 DDR2 SDRAM

Output Electrical Characteristics and Operating Conditions

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Table 20: Output Characteristics

Parameter Min Nom Max Units Notes

Output impedance See Output Driver Characteristics (page 53) ˖1, 2

Pull-up and pull-down mismatch 0 – 4 ˖1, 2, 3

Output slew rate 1.5 – 5 V/ns 1, 4, 5, 6

Notes: 1. Absolute specifications: 0°C ื TC ื +85°C; VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V.

2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V;

VOUT = 1420mV; (VOUT - VDDQ)/IOH must be less than 23.4˖ for values of VOUT between

VDDQ and VDDQ - 280mV. The impedance measurement condition for output sink DC cur-

rent: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4˖ for values of VOUT

between 0V and 280mV.

3. Mismatch is an absolute value between pull-up and pull-down; both are measured at

the same temperature and voltage.

4. Output slew rate for falling and rising edges is measured between VTT - 250mV and

VTT + 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew

rate is measured between DQS - DQS# = –500mV and DQS# - DQS = 500mV. Output slew

rate is guaranteed by design but is not necessarily tested on each device.

5. The absolute value of the slew rate as measured from VIL(DC)max to VIH(DC)min is equal to

or greater than the slew rate as measured from VIL(AC)max to VIH(AC)min. This is guaran-

teed by design and characterization.

6. IT and AT devices require an additional 0.4 V/ns in the MAX limit when TC is between –

40°C and 0°C.

Figure 15: Output Slew Rate Load

Output

(VOUT)

Reference

point

25ȍ

VTT = VDDQ/2

1Gb: x4, x8, x16 DDR2 SDRAM

Output Electrical Characteristics and Operating Conditions

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Output Driver Characteristics

Figure 16: Full Strength Pull-Down Characteristics

VOUT (V)

0.0 0.5 1.0 1.5

120

100

IOUT (mA)

Table 21: Full Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 4.30 5.63 7.95

0.2 8.60 11.30 15.90

0.3 12.90 16.52 23.85

0.4 16.90 22.19 31.80

0.5 20.40 27.59 39.75

0.6 23.28 32.39 47.70

0.7 25.44 36.45 55.55

0.8 26.79 40.38 62.95

0.9 27.67 44.01 69.55

1.0 28.38 47.01 75.35

1.1 28.96 49.63 80.35

1.2 29.46 51.71 84.55

1.3 29.90 53.32 87.95

1.4 30.29 54.9 90.70

1.5 30.65 56.03 93.00

1.6 30.98 57.07 95.05

1.7 31.31 58.16 97.05

1.8 31.64 59.27 99.05

1.9 31.96 60.35 101.05

1Gb: x4, x8, x16 DDR2 SDRAM

Output Driver Characteristics

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Figure 17: Full Strength Pull-Up Characteristics

VDDQ - VOUT (V)

–20

–40

–60

–80

–100

–120

0 0.5 1.0 1.5

IOUT (mA)

Table 22: Full Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 –4.30 –5.63 –7.95

0.2 –8.60 –11.30 –15.90

0.3 –12.90 –16.52 –23.85

0.4 –16.90 –22.19 –31.80

0.5 –20.40 –27.59 –39.75

0.6 –23.28 –32.39 –47.70

0.7 –25.44 –36.45 –55.55

0.8 –26.79 –40.38 –62.95

0.9 –27.67 –44.01 –69.55

1.0 –28.38 –47.01 –75.35

1.1 –28.96 –49.63 –80.35

1.2 –29.46 –51.71 –84.55

1.3 –29.90 –53.32 –87.95

1.4 –30.29 –54.90 –90.70

1.5 –30.65 –56.03 –93.00

1.6 –30.98 –57.07 –95.05

1.7 –31.31 –58.16 –97.05

1.8 –31.64 –59.27 –99.05

1.9 –31.96 –60.35 –101.05

1Gb: x4, x8, x16 DDR2 SDRAM

Output Driver Characteristics

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Figure 18: Reduced Strength Pull-Down Characteristics

0.0 0.5 1.0 1.5

VOUT (V)

IOUT (mV)

Table 23: Reduced Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 1.72 2.98 4.77

0.2 3.44 5.99 9.54

0.3 5.16 8.75 14.31

0.4 6.76 11.76 19.08

0.5 8.16 14.62 23.85

0.6 9.31 17.17 28.62

0.7 10.18 19.32 33.33

0.8 10.72 21.40 37.77

0.9 11.07 23.32 41.73

1.0 11.35 24.92 45.21

1.1 11.58 26.30 48.21

1.2 11.78 27.41 50.73

1.3 11.96 28.26 52.77

1.4 12.12 29.10 54.42

1.5 12.26 29.70 55.80

1.6 12.39 30.25 57.03

1.7 12.52 30.82 58.23

1.8 12.66 31.41 59.43

1.9 12.78 31.98 60.63

1Gb: x4, x8, x16 DDR2 SDRAM

Output Driver Characteristics

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Figure 19: Reduced Strength Pull-Up Characteristics

–10

–20

–30

–40

–50

–60

–70

0.0 0.5 1.0 1.5

VDDQ - VOUT (V)

IOUT (mV)

Table 24: Reduced Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 –1.72 –2.98 –4.77

0.2 –3.44 –5.99 –9.54

0.3 –5.16 –8.75 –14.31

0.4 –6.76 –11.76 –19.08

0.5 –8.16 –14.62 –23.85

0.6 –9.31 –17.17 –28.62

0.7 –10.18 –19.32 –33.33

0.8 –10.72 –21.40 –37.77

0.9 –11.07 –23.32 –41.73

1.0 –11.35 –24.92 –45.21

1.1 –11.58 –26.30 –48.21

1.2 –11.78 –27.41 –50.73

1.3 –11.96 –28.26 –52.77

1.4 –12.12 –29.10 –54.42

1.5 –12.26 –29.69 –55.8

1.6 –12.39 –30.25 –57.03

1.7 –12.52 –30.82 –58.23

1.8 –12.66 –31.42 –59.43

1.9 –12.78 –31.98 –60.63

1Gb: x4, x8, x16 DDR2 SDRAM

Output Driver Characteristics

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Power and Ground Clamp Characteristics

Power and ground clamps are provided on the following input-only balls: Address balls,

bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.

Table 25: Input Clamp Characteristics

Voltage Across Clamp (V)

Minimum Power Clamp Current

(mA)

Minimum Ground Clamp Current

(mA)

0.0 0.0 0.0

0.1 0.0 0.0

0.2 0.0 0.0

0.3 0.0 0.0

0.4 0.0 0.0

0.5 0.0 0.0

0.6 0.0 0.0

0.7 0.0 0.0

0.8 0.1 0.1

0.9 1.0 1.0

1.0 2.5 2.5

1.1 4.7 4.7

1.2 6.8 6.8

1.3 9.1 9.1

1.4 11.0 11.0

1.5 13.5 13.5

1.6 16.0 16.0

1.7 18.2 18.2

1.8 21.0 21.0

Figure 20: Input Clamp Characteristics

Voltage Across Clamp (V)

Minimum Clamp Current (mA)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

1Gb: x4, x8, x16 DDR2 SDRAM

Power and Ground Clamp Characteristics

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AC Overshoot/Undershoot Specification

Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V

maximum average amplitude shown in Table 26 and Table 27.

Table 26: Address and Control Balls

Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, and ODT

Parameter

Specification

-187E -25/-25E -3/-3E -37E -5E

Maximum peak amplitude allowed for overshoot area

(see Figure 21) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 22) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum overshoot area above VDD (see Figure 21) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns

Maximum undershoot area below VSS (see Figure 22) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns

Table 27: Clock, Data, Strobe, and Mask Balls

Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, and LDM

Parameter

Specification

-187E -25/-25E -3/-3E -37E -5E

Maximum peak amplitude allowed for overshoot area

(see Figure 21)

0.50V 0.50V 0.50V 0.50V 0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 22)

0.50V 0.50V 0.50V 0.50V 0.50V

Maximum overshoot area above VDDQ (see Figure 21) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns

Maximum undershoot area below VSSQ (see Figure 22) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns

Figure 21: Overshoot

Maximum amplitude

Overshoot area

VDD/VDDQ

VSS/VSSQ

Volts (V)

Time (ns)

Figure 22: Undershoot

VSS/VSSQ

Maximum amplitude

Undershoot area

Time (ns)

Volts (V)

1Gb: x4, x8, x16 DDR2 SDRAM

AC Overshoot/Undershoot Specification

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Table 28: AC Input Test Conditions

Parameter Symbol Min Max Units Notes

Input setup timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,

DM, UDM, LDM, and CKE

VRS See Note 2 1, 2, 3, 4

Input hold timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,

DM, UDM, LDM, and CKE

VRH See Note 5 1, 3, 4, 5

Input timing measurement reference level (single-ended)

DQS for x4, x8; UDQS, LDQS for x16

VREF(DC) VDDQ × 0.49 VDDQ × 0.51 V 1, 3, 4, 6

Input timing measurement reference level (differential)

CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,

RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16

VRD VIX(AC) V 1, 3, 7, 8, 9

Notes: 1. All voltages referenced to VSS.

2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the

VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under

test, as shown in Figure 31 (page 71).

3. See Input Slew Rate Derating (page 60).

4. The slew rate for single-ended inputs is measured from DC level to AC level, VIL(DC) to

VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced

to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in

Figure 24 (page 63), Figure 26 (page 64), Figure 28 (page 69), and Figure 30

(page 70).

5. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the

VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under

test, as shown in Figure 31 (page 71).

6. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is

referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to

the device under test, as shown in Figure 33 (page 72).

7. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe

is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/

LDQS#, as shown in Figure 32 (page 71).

8. Input waveform timing is referenced to the crossing point level (VIX) of two input signals

(VTR and VCP) applied to the device under test, where VTR is the true input signal and VCP

is the complementary input signal, as shown in Figure 34 (page 72).

9. The slew rate for differentially ended inputs is measured from twice the DC level to

twice the AC level: 2 × VIL(DC) to 2 × VIH(AC) on the rising edge and 2 × VIL(AC) to 2 ×

VIH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK

rising edge and would be 250mV to –500mV for CK falling edge.

1Gb: x4, x8, x16 DDR2 SDRAM

AC Overshoot/Undershoot Specification

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Input Slew Rate Derating

For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated

by adding the data sheet tIS (base) and tIH (base) value to the ˂tIS and ˂tIH derating

value, respectively. Example: tIS (total setup time) = tIS (base) + ˂tIS.

tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup nominal slew rate (tIS) for

a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the

first crossing of VIL(AC)max.

If the actual signal is always earlier than the nominal slew rate line between shaded

“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 23

(page 63)).

If the actual signal is later than the nominal slew rate line anywhere between the shaded

“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC

level to DC level is used for the derating value (see Figure 24 (page 63)).

tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of VIL(DC)max and the first crossing of VREF(DC). tIH, nominal slew rate for a fall-

ing signal, is defined as the slew rate between the last crossing of VIH(DC)min and the first

crossing of VREF(DC).

If the actual signal is always later than the nominal slew rate line between shaded “DC

to VREF(DC) region,” use the nominal slew rate for the derating value (Figure 25

(page 64)).

If the actual signal is earlier than the nominal slew rate line anywhere between shaded

“DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC

level to VREF(DC) level is used for the derating value (Figure 26 (page 64)).

Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

For slew rates in between the values listed in Table 29 (page 61) and Table 30

(page 62), the derating values may obtained by linear interpolation.

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)

Command/Address Slew Rate (V/ns)

CK, CK# Differential Slew Rate

Units

2.0 V/ns 1.5 V/ns 1.0 V/ns

tIS

tIH

tIS

tIH

tIS

tIH

4.0 187 94 217 124 247 154 ps

3.5 179 89 209 119 239 149 ps

3.0 167 83 197 113 227 143 ps

2.5 150 75 180 105 210 135 ps

2.0 125 45 155 75 185 105 ps

1.5 83 21 113 51 143 81 ps

1.0 0 0 30 30 60 60 ps

0.9 –11 –14 19 16 49 46 ps

0.8 –25 –31 5 –1 35 29 ps

0.7 –43 –54 –13 –24 17 6 ps

0.6 –67 –83 –37 –53 –7 –23 ps

0.5 –110 –125 –80 –95 –50 –65 ps

0.4 –175 –188 –145 –158 –115 –128 ps

0.3 –285 –292 –255 –262 –225 –232 ps

0.25 –350 –375 –320 –345 –290 –315 ps

0.2 –525 –500 –495 –470 –465 –440 ps

0.15 –800 –708 –770 –678 –740 –648 ps

0.1 –1450 –1125 –1420 –1095 –1390 –1065 ps

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH)

Command/

Address Slew

Rate (V/ns)

CK, CK# Differential Slew Rate

Units

2.0 V/ns 1.5 V/ns 1.0 V/ns

tIS

tIH

tIS

tIH

tIS

tIH

4.0 150 94 180 124 210 154 ps

3.5 143 89 173 119 203 149 ps

3.0 133 83 163 113 193 143 ps

2.5 120 75 150 105 180 135 ps

2.0 100 45 160 75 160 105 ps

1.5 67 21 97 51 127 81 ps

1.0 0 0 30 30 60 60 ps

0.9 –5 –14 25 16 55 46 ps

0.8 –13 –31 17 –1 47 29 ps

0.7 –22 –54 8 –24 38 6 ps

0.6 –34 –83 –4 –53 36 –23 ps

0.5 –60 –125 –30 –95 0 –65 ps

0.4 –100 –188 –70 –158 –40 –128 ps

0.3 –168 –292 –138 –262 –108 –232 ps

0.25 –200 –375 –170 –345 –140 –315 ps

0.2 –325 –500 –295 –470 –265 –440 ps

0.15 –517 –708 –487 –678 –457 –648 ps

0.1 –1000 –1125 –970 –1095 –940 –1065 ps

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Figure 23: Nominal Slew Rate for tIS

VSS

CK#

tIH

tIS tIH

Setup slew rate

rising signal

Setup slew rate

falling signal

ǻTF ǻTR

VIH(AC)min -

REF

(DC)

VDDQ

tIS

Nominal

slew rate

REF

to AC

region

VREF to AC

region

REF

(DC)

- VIL(AC)max

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

Nominal

slew rate

Figure 24: Tangent Line for tIS

Setup slew rate

rising signal

Tangent line (VIH[AC]min

- VREF[DC])

ǻTR

Tangent

line

Tangent

line

REF to AC

region

Nominal

line

tIH

tIS tIH tIS

VSS

CK#

VDDQ

VIH(AC)min

VIH(DC)min

VREF(DC)

VIL(DC)max

VIL(AC)max

REF to AC

region

Nominal

line

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Figure 25: Nominal Slew Rate for tIH

ǻTR ǻTF

Nominal

slew rate DC to V

REF

region

tIH

tIS tIS

VSS

CK#

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

DC to V

REF

region

Nominal

slew rate

tIH

Figure 26: Tangent Line for tIH

Tangent

line DC to V

REF

region

tIH

tIS tIS

VSS

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

DC to V

REF

region Tangent

line

tIH

CK#

Hold slew rate

falling signal

ǻTFǻTR

Tangent line (V

IH[DC]min

- V

REF[DC]

)

Nominal

line

Hold slew rate

rising signal

Tangent line (V

REF[DC]

- V

IL[DC]max

)

Nominal

line

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe

All units are shown in picoseconds

Slew

Rate

(V/ns)

DQS, DQS# Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

2.0 125 45 125 45 125 45 – – – – – – – – – – – –

1.5 83 21 83 21 83 21 95 33 – – – – – – – – – –

1.0 0 0 0 0 0 0 12 12 24 24 – – – – – – – –

0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –

0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –

0.7 – – – – – – –31 –42 –19 –30 –7 –18 5 –6 17 6 – –

0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11

0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53

0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116

Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data

sheet value to the derating value listed in Table 31.

2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-

ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-

tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating

value (see Figure 27 (page 69)). If the actual signal is later than the nominal slew rate

line anywhere between the shaded “VREF(DC) to AC region,” the slew rate of a tangent

line to the actual signal from the AC level to DC level is used for the derating value (see

Figure 28 (page 69)).

3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of VIH(DC)min and the first

crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line

between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-

rating value (see Figure 29 (page 70)). If the actual signal is earlier than the nominal

slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tan-

gent line to the actual signal from the DC level to VREF(DC) level is used for the derating

value (see Figure 30 (page 70)).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

5. For slew rates between the values listed in this table, the derating values may be ob-

tained by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special derating. The values in Table 33 (page 67) are the

DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at

the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced

to the AC/DC trip points to DQ referenced to VREF is listed in Table 35 (page 68) and

Table 36 (page 68). Table 35 provides the VREF-based fully derated values for the DQ

(tDSa and tDHa) for DDR2-533. Table 36 provides the VREF-based fully derated values for

the DQ (tDSa and tDHa) for DDR2-400.

1Gb: x4, x8, x16 DDR2 SDRAM

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Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe

All units are shown in picoseconds

Slew

Rate

(V/ns)

DQS, DQS# Differential Slew Rate

2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135

1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114

1.0000000121224243636484860607272

0.9 –5 –14 –5 –14 –5 –14 7 –2 19 10 31 22 43 34 55 46 67 58

0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41

0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18

0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11

0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53

0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116

Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data

sheet value to the derating value listed in Table 32.

2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-

ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-

tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating

value (see Figure 27 (page 69)). If the actual signal is later than the nominal slew rate

line anywhere between shaded “VREF(DC) to AC region,” the slew rate of a tangent line

to the actual signal from the AC level to DC level is used for the derating value (see Fig-

ure 28 (page 69)).

3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of VIH(DC)min and the first

crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line

between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-

rating value (see Figure 29 (page 70)). If the actual signal is earlier than the nominal

slew rate line anywhere between the shaded “DC to VREF(DC) region,” the slew rate of a

tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat-

ing value (see Figure 30 (page 70)).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

5. For slew rates between the values listed in this table, the derating values may be ob-

tained by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special derating. The values in Table 33 (page 67) are the

DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at

the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced

to the AC/DC trip points to DQ referenced to VREF is listed in Table 34 (page 67). Ta-

ble 34 provides the VREF-based fully derated values for the DQ (tDSa and tDHa) for

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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DDR2-667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-

ended DQS; however, Table 33 would be used with the base values.

Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb

Reference points indicated in bold; Derating values are to be used with base tDSb- and tDHb--specified values

DQ (V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38

1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17

1.0 30 –10 30 –10 30 –10 30 –10 30 –10 45 –15 55 –18 65 –22 75 –25

0.9 25 –24 25 –24 25 –24 25 –24 25 –24 40 –29 50 –32 60 –36 70 –39

0.8 17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56

0.7 5 –64 5 –64 5 –64 5 –64 5 –64 20 –69 30 –72 40 –75 50 –79

0.6 –7 –93 –7 –93 –7 –93 –7 –93 –7 –93 8 –98 18 –102 28 –105 38 –108

0.5 –28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143 7 –147 17 –150

0.4 –78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667

Reference points indicated in bold

DQ (V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276

1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275

1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275

0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275

0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275

0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275

0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275

0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275

0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533

Reference points indicated in bold

DQ (V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326

1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325

1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325

0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325

0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325

0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325

0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325

0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325

0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400

Reference points indicated in bold

DQ (V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376

1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375

1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375

0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375

0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375

0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375

0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375

0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375

0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Figure 27: Nominal Slew Rate for tDS

REF

to AC

region

REF

to AC

region

Setup slew rate

rising signal

Setup slew rate

falling signal

VREF(DC)

- V

IL(AC)max

ǻTF

IH(AC)min

VREF(DC)

ǻTR

Nominal

slew rate

VSS

DQS#1

DQS1

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

tDH

tDS

Nominal

slew rate

tDH

tDS

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

Figure 28: Tangent Line for tDS

Setup slew rate

rising signal

Setup slew rate

falling signal

Tangent line (VREF[DC] - VIL[AC]max

)

ǻTF

Tangent line (V

IH[AC]min

- VREF[DC])

ǻTR

tDH

tDS

tDH

tDS

VSS

DQS#1

DQS1

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

Nominal line

Tangent line

Nominal

line

Tangent line

REF

to AC

region

REF

to AC

region

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

1Gb: x4, x8, x16 DDR2 SDRAM

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Figure 29: Nominal Slew Rate for tDH

Hold slew rate

falling signal

Hold slew rate

rising signal

VREF(DC) -

IL(DC)max

IH(DC)min

VREF(DC)

ǻTR ǻTF

Nominal

slew rate DC to V

REF

region

tIH

tIS tIS

VSS

DQS#1

DQS1

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

DC to V

REF

region

Nominal

slew rate

tIH

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

Figure 30: Tangent Line for tDH

Tangent

line DC to V

REF

region

tIH

tIS tIS

VSS

VDDQ

VIH(DC)min

VREF(DC)

VIL(AC)max

VIL(DC)max

VIH(AC)min

DC to V

REF

region Tangent

line

tIH

DQS1

DQS#1

Hold slew rate

falling signal

ǻTF

ǻTR

Tangent line (V

IH[DC]min

- V

REF[DC]

)

ǻTF

Nominal

line

Hold slew rate

rising signal

Tangent line (V

REF[DC]

- V

IL[DC]max

)

ǻTR

Nominal

line

Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Figure 31: AC Input Test Signal Waveform Command/Address Balls

tISa

Logic levels

VREF levels

tIHatISatIHa

tISbtIHbtISbtIHb

CK#

VDDQ

VIH(AC)min

VIH(DC)min

VREF(DC)

VIL(DC)min

VIL(AC)min

VSSQ

Vswing (MAX)

Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)

DQS#

DQS

tDSatDHatDSatDHa

tDSbtDHbtDSbtDHb

Logic levels

VREF levels

VREF(DC)

VIL(DC)max

VIL(AC)max

VSSQ

VIH(DC)min

VIH(AC)min

VDDQ

Vswing (MAX)

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended)

DQS

VREF

REF(DC)

IL(DC)max

IL(AC)max

SSQ

IH(DC)min

IH(AC)min

DDQ

Vswing (MAX)

Logic levels

VREF levels

tDSatDHatDSatDHa

tDSbtDHbtDSbtDHb

Figure 34: AC Input Test Signal Waveform (Differential)

VTR

Vswing

VCP

VDDQ

VSSQ

VIX

Crossing point

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

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Commands

Truth Tables

The following tables provide a quick reference of available DDR2 SDRAM commands,

including CKE power-down modes and bank-to-bank commands.

Table 37: Truth Table – DDR2 Commands

Notes: 1–3 apply to the entire table

Function

CKE

CS# RAS# CAS# WE#

BA2–

BA0 An–A11 A10 A9–A0 Notes

Cycle

Current

Cycle

LOAD MODE H H L L L L BA OP code 4, 6

REFRESH H H L L L H X X X X

SELF REFRESH entry H L L L L H X X X X

SELF REFRESH exit L H H X X X X X X X 4, 7

LHHH

Single bank

PRECHARGE

HHLLHLBAXLX6

All banks PRECHARGE H H L L H L X X H X

Bank ACTIVATE H H L L H H BA Row address 4

WRITE H H L H L L BA Column

address

L Column

address

4, 5, 6,

WRITE with auto

precharge

H H L H L L BA Column

address

H Column

address

4, 5, 6,

READ H H L H L H BA Column

address

L Column

address

4, 5, 6,

READ with auto

precharge

H H L H L H BA Column

address

H Column

address

4, 5, 6,

NO OPERATION H X L H H H X X X X

Device DESELECT H X H X X X X X X X

Power-down entry H L H X X X X X X X 9

LHHH

Power-down exit L H H X X X X X X X 9

LHHH

Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at

the rising edge of the clock.

2. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh. See ODT Timing (page 130) for details.

3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.

4. BA2 is only applicable for densities ุ1Gb.

5. An n is the most significant address bit for a given density and configuration. Some larg-

er address bits may be “Don’t Care” during column addressing, depending on density

and configuration.

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD

MODE command selects which mode register is programmed.

7. SELF REFRESH exit is asynchronous.

8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 48

(page 99) and Figure 60 (page 110) for other restrictions and details.

9. The power-down mode does not perform any REFRESH operations. The duration of

power-down is limited by the refresh requirements outlined in the AC parametric sec-

tion.

Table 38: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6 apply to the entire table

Current

State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle L L H H ACTIVATE (select and activate row)

L L L H REFRESH 7

L L L L LOAD MODE 7

Row active L H L H READ (select column and start READ burst) 8

L H L L WRITE (select column and start WRITE burst) 8

L L H L PRECHARGE (deactivate row in bank or banks) 9

Read (auto

precharge

disabled)

L H L H READ (select column and start new READ burst) 8

L H L L WRITE (select column and start WRITE burst) 8, 10

L L H L PRECHARGE (start PRECHARGE) 9

Write

(auto pre-

charge disa-

bled)

L H L H READ (select column and start READ burst) 8

L H L L WRITE (select column and start new WRITE burst) 8

L L H L PRECHARGE (start PRECHARGE) 9

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (the current state is for a specific bank

and the commands shown are those allowed to be issued to that bank when in that

state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, tRP has been met, and any READ burst is com-

plete.

Row

active:

A row in the bank has been activated, and tRCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled and has not yet

terminated.

Write: A WRITE burst has been initiated with auto precharge disabled and has not yet

terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Issue DESELECT or NOP commands, or allowable commands to the other bank, on any

clock edge occurring during these states. Allowable commands to the other bank are

determined by its current state and this table, and according to Table 39 (page 76).

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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Precharge: Starts with registration of a PRECHARGE command and ends when

tRP is met. After tRP is met, the bank will be in the idle state.

Read with auto

precharge

enabled:

Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Row activate: Starts with registration of an ACTIVATE command and ends when

tRCD is met. After tRCD is met, the bank will be in the row active

state.

Write with auto

precharge

enabled:

Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

5. The following states must not be interrupted by any executable command (DESELECT or

NOP commands must be applied on each positive clock edge during these states):

Refresh: Starts with registration of a REFRESH command and ends when tRFC is

met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle

state.

Accessing

mode

Starts with registration of the LOAD MODE command and ends when

tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in the

all banks idle state.

Precharge

all:

Starts with registration of a PRECHARGE ALL command and ends when

tRP is met. After tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and bursts are not in progress.

8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

9. May or may not be bank-specific; if multiple banks are to be precharged, each must be

in a valid state for precharging.

10. A WRITE command may be applied after the completion of the READ burst.

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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Table 39: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6 apply to the entire table

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle X X X X Any command otherwise allowed to bank m

Row

active, active,

or precharge

L L H H ACTIVATE (select and activate row)

L H L H READ (select column and start READ burst) 7

L H L L WRITE (select column and start WRITE burst) 7

L L H L PRECHARGE

Read (auto

precharge

disabled)

L L H H ACTIVATE (select and activate row)

L H L H READ (select column and start new READ burst) 7

L H L L WRITE (select column and start WRITE burst) 7, 8

L L H L PRECHARGE

Write (auto

precharge

disabled)

L L H H ACTIVATE (select and activate row)

L H L H READ (select column and start READ burst) 7, 9, 10

L H L L WRITE (select column and start new WRITE burst) 7

L L H L PRECHARGE

Read (with

auto

precharge)

L L H H ACTIVATE (select and activate row)

L H L H READ (select column and start new READ burst) 7

L H L L WRITE (select column and start WRITE burst) 7, 8

L L H L PRECHARGE

Write (with

auto

precharge)

L L H H ACTIVATE (select and activate row)

L H L H READ (select column and start READ burst) 7, 10

L H L L WRITE (select column and start new WRITE burst) 7

L L H L PRECHARGE

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been

met (if the previous state was self refresh).

2. This table describes an alternate bank operation, except where noted (the current state

is for bank n and the commands shown are those allowed to be issued to bank m, as-

suming that bank m is in such a state that the given command is allowable). Exceptions

are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, tRP has been met, and any READ

burst is complete.

Row active: A row in the bank has been activated and tRCD has been met.

No data bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated with auto precharge disabled

and has not yet terminated.

Write: A WRITE burst has been initiated with auto precharge disabled

and has not yet terminated.

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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READ with auto

precharge enabled/

WRITE with auto

precharge enabled:

The READ with auto precharge enabled or WRITE with auto pre-

charge enabled states can each be broken into two parts: the ac-

cess period and the precharge period. For READ with auto pre-

charge, the precharge period is defined as if the same burst was

executed with auto precharge disabled and then followed with

the earliest possible PRECHARGE command that still accesses all

of the data in the burst. For WRITE with auto precharge, the pre-

charge period begins when tWR ends, with tWR measured as if

auto precharge was disabled. The access period starts with regis-

tration of the command and ends where the precharge period

(or tRP) begins. This device supports concurrent auto precharge

such that when a READ with auto precharge is enabled or a

WRITE with auto precharge is enabled, any command to other

banks is allowed, as long as that command does not interrupt

the read or write data transfer already in process. In either case,

all other related limitations apply (contention between read da-

ta and write data must be avoided).

The minimum delay from a READ or WRITE command with auto precharge enabled to

a command to a different bank is summarized in Table 40 (page 77).

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.

5. Not used.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. A WRITE command may be applied after the completion of the READ burst.

9. Requires appropriate DM.

10. The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever

is greater.

Table 40: Minimum Delay with Auto Precharge Enabled

From Command (Bank n) To Command (Bank m)

Minimum Delay

(with Concurrent Auto Precharge) Units

WRITE with auto precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

READ with auto precharge READ or READ with auto precharge (BL/2) tCK

WRITE or WRITE with auto precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by

the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in

progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to

perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted

commands from being registered during idle or wait states. Operations already in pro-

gress are not affected.

LOAD MODE (LM)

The mode registers are loaded via bank address and address inputs. The bank address

balls determine which mode register will be programmed. See Mode Register (MR)

(page 79). The LM command can only be issued when all banks are idle, and a subse-

quent executable command cannot be issued until tMRD is met.

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the bank address inputs determines the bank, and the

address inputs select the row. This row remains active (or open) for accesses until a pre-

charge command is issued to that bank. A precharge command must be issued before

opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value

on the bank address inputs determine the bank, and the address provided on address

inputs A0–Ai (where Ai is the most significant column address bit for a given configura-

tion) selects the starting column location. The value on input A10 determines whether

or not auto precharge is used. If auto precharge is selected, the row being accessed will

be precharged at the end of the read burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command

to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the bank select inputs selects the bank, and the address provided on inputs A0–Ai

(where Ai is the most significant column address bit for a given configuration) selects

the starting column location. The value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row being accessed will be pre-

charged at the end of the WRITE burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command

to be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

Input data appearing on the DQ is written to the memory array subject to the DM input

logic level appearing coincident with the data. If a given DM signal is registered LOW,

the corresponding data will be written to memory; if the DM signal is registered HIGH,

the corresponding data inputs will be ignored, and a WRITE will not be executed to that

byte/column location (see Figure 65 (page 115)).

1Gb: x4, x8, x16 DDR2 SDRAM

Commands

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PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row activation

a specified time (tRP) after the PRECHARGE command is issued, except in the case of

concurrent auto precharge, where a READ or WRITE command to a different bank is al-

lowed as long as it does not interrupt the data transfer in the current bank and does not

violate any other timing parameters. After a bank has been precharged, it is in the idle

state and must be activated prior to any READ or WRITE commands being issued to

that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle

state) or if the previously open row is already in the process of precharging. However,

the precharge period will be determined by the last PRECHARGE command issued to

the bank.

REFRESH

REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to

CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing

a REFRESH command. This command is nonpersistent, so it must be issued each time

a refresh is required. The addressing is generated by the internal refresh controller. This

makes the address bits a “Don’t Care” during a REFRESH command.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if

the rest of the system is powered down. When in the self refresh mode, the DDR2

SDRAM retains data without external clocking. All power supply inputs (including Vref)

must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-

tion.

The SELF REFRESH command is initiated like a REFRESH command except CKE is

LOW. The DLL is automatically disabled upon entering self refresh and is automatically

enabled upon exiting self refresh.

Mode Register (MR)

The mode register is used to define the specific mode of operation of the DDR2 SDRAM.

This definition includes the selection of a burst length, burst type, CAS latency, operat-

ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 35

(page 80). Contents of the mode register can be altered by re-executing the LOAD

MODE (LM) command. If the user chooses to modify only a subset of the MR variables,

all variables must be programmed when the command is issued.

The MR is programmed via the LM command and will retain the stored information un-

til it is programmed again or until the device loses power (except for bit M8, which is

self-clearing). Reprogramming the mode register will not alter the contents of the mem-

ory array, provided it is performed correctly.

The LM command can only be issued (or reissued) when all banks are in the precharged

state (idle state) and no bursts are in progress. The controller must wait the specified

time tMRD before initiating any subsequent operations such as an ACTIVATE com-

mand. Violating either of these requirements will result in an unspecified operation.

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

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Burst Length

Burst length is defined by bits M0–M2, as shown in Figure 35. Read and write accesses

to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to

either four or eight. The burst length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most

significant column address bit for a given configuration). The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting location within the block. The pro-

grammed burst length applies to both read and write bursts.

Figure 35: MR Definition

Burst Length

CAS#

BTPD

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9 765438210

A10A12 A11BA0

BA1

101112n

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency (CL)

Reserved

Mode

Normal

Test

DLL TM

DLL Reset

Yes

Write Recovery

Reserved

M10

M11

An2

M14

Mode Register Definition

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

M15

M12

PD Mode

Fast exit

(normal)

Slow exit

(low power)

Latency

BA21

Notes: 1. M16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be

programmed to “0.”

2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are re-

served for future use and must be programmed to “0.”

3. Not all listed WR and CL options are supported in any individual speed grade.

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

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Burst Type

Accesses within a given burst may be programmed to be either sequential or inter-

leaved. The burst type is selected via bit M3, as shown in Figure 35. The ordering of ac-

cesses within a burst is determined by the burst length, the burst type, and the starting

column address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-

bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-

ted; however, sequential address ordering is nibble-based.

Table 41: Burst Definition

Burst Length Starting Column Address

(A2, A1, A0)

Order of Accesses Within a Burst

Burst Type = Sequential Burst Type = Interleaved

4 0 0 0, 1, 2, 3 0, 1, 2, 3

0 1 1, 2, 3, 0 1, 0, 3, 2

1 0 2, 3, 0, 1 2, 3, 0, 1

1 1 3, 0, 1, 2 3, 2, 1, 0

8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,”

and all other bits set to the desired values, as shown in Figure 35 (page 80). When bit M7

is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”

places the DDR2 SDRAM into a test mode that is only used by the manufacturer and

should not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 35. Programming bit M8 to “1” will

activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a

value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ

command can be issued to allow time for the internal clock to be synchronized with the

external clock. Failing to wait for synchronization to occur may result in a violation of

the tAC or tDQSCK parameters.

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

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Write Recovery

Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 35 (page 80).

The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-

tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-

nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last

data burst. An example of WRITE with auto precharge is shown in Figure 64 (page 114).

WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The

user is required to program the value of WR, which is calculated by dividing tWR (in

nanoseconds) by tCK (in nanoseconds) and rounding up a noninteger value to the next

integer; WR (cycles) = tWR (ns)/tCK (ns). Reserved states should not be used as an un-

known operation or incompatibility with future versions may result.

Power-Down Mode

Active power-down (PD) mode is defined by bit M12, as shown in Figure 35. PD mode

enables the user to determine the active power-down mode, which determines per-

formance versus power savings. PD mode bit M12 does not apply to precharge PD

mode.

When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.

The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to

be enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-

abled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can

be enabled but “frozen” during active PD mode because the exit-to-READ command

timing is relaxed. The power difference expected between IDD3P normal and IDD3P low-

power mode is defined in the DDR2 IDD Specifications and Conditions table.

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

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CAS Latency (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 35 (page 80). CL is

the delay, in clock cycles, between the registration of a READ command and the availa-

bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending

on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be

used as an unknown operation otherwise incompatibility with future versions may re-

sult.

DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-

ture allows the READ command to be issued prior to tRCD (MIN) by delaying the inter-

nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further

detail in Posted CAS Additive Latency (AL) (page 86).

Examples of CL = 3 and CL = 4 are shown in Figure 36; both assume AL = 0. If a READ

command is registered at clock edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n + m (this assumes AL = 0).

Figure 36: CL

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

CL = 3 (AL = 0)

READ

T0 T1 T2

Don’t careTransitioning data

NOP NOP NOP

T3 T4 T5

NOP NOP

NOP

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

T3 T4 T5

NOP NOP

NOP

Notes: 1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

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Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode

die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#

enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-

tions are controlled via the bits shown in Figure 37. The EMR is programmed via the LM

command and will retain the stored information until it is programmed again or the de-

vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-

ray, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 37: EMR Definition

DLLPosted CAS# R

Out

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10A12BA0BA1

101112n

Output Drive Strength

Full

Reduced

Posted CAS# Additive Latency (AL) 3

Reserved

DLL Enable

Enable (normal)

Disable (test/debug)

E11

RDQS Enable

Yes

OCD Program

An2

ODS

DQS#

E10

DQS# Enable

Enable

Disable

RDQS

(Nominal)

disabled

75

150

50

Outputs

Enabled

Disabled

E12

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

E14

MRS

BA21

OCD Operation 4

OCD exit

Reserved

Enable OCD defaults

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to “0.”

3. Not all listed AL options are supported in any individual speed grade.

4. As detailed in the Initialization (page 90) section notes, during initialization of the

OCD operation, all three bits must be set to “1” for the OCD default state, then set to

“0” before initialization is finished.

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register (EMR)

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DLL Enable/Disable

The DLL may be enabled or disabled by programming bit E0 during the LM command,

as shown in Figure 37 (page 84). These specifications are applicable when the DLL is en-

abled for normal operation. DLL enable is required during power-up initialization and

upon returning to normal operation after having disabled the DLL for the purpose of

debugging or evaluation. Enabling the DLL should always be followed by resetting the

DLL using the LM command.

The DLL is automatically disabled when entering SELF REFRESH operation and is auto-

matically re-enabled and reset upon exit of SELF REFRESH operation.

Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-

fore a READ command can be issued to allow time for the internal clock to synchronize

with the external clock. Failing to wait for synchronization to occur may result in a vio-

lation of the tAC or tDQSCK parameters.

Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-

FRESH command should be followed by a PRECHARGE ALL command.

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure 37. The normal drive

strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-

mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-

tion (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18

drive strength. This option is intended for the support of lighter load and/or point-to-

point environments.

DQS# Enable/Disable

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the dif-

ferential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-

ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-

ing; however, it may be tied to ground via a 20˖ to 10k˖ resistor. This function is also

used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =

0), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS ball is enabled by bit E11, as shown in Figure 37. This feature is only applica-

ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and

timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored

by the DDR2 SDRAM.

Output Enable/Disable

The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 37. When ena-

bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. When

disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-

moving output buffer current. The output disable feature is intended to be used during

IDD characterization of read current.

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register (EMR)

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On-Die Termination (ODT)

ODT effective resistance, RTT(EFF), is defined by bits E2 and E6 of the EMR, as shown in

Figure 37 (page 84). The ODT feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM controller to independently turn on/off

ODT for any or all devices. RTT effective resistance values of 50˖˖, and 150˖ are se-

lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/

LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is en-

abled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is se-

lected by enabling switch “sw1,” which enables all R1 values that are 150˖ each, ena-

bling an effective resistance of 75˖(RTT2 [EFF] = R2/2). Similarly, if “sw2” is enabled, all

R2 values that are 300˖ each, enable an effective ODT resistance of 150˖

(RTT2[EFF] = R2/2). Switch “sw3” enables R1 values of 100˖, enabling effective resistance

of 50˖. Reserved states should not be used, as an unknown operation or incompatibility

with future versions may result.

The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming

ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input

ball are only used during active, active power-down (both fast-exit and slow-exit

modes), and precharge power-down modes of operation.

ODT must be turned off prior to entering self refresh mode. During power-up and initi-

alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-

sued. This will enable the ODT feature, at which point the ODT ball will determine the

RTT(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven

HIGH until eight clocks after the EMR has been enabled (see Figure 80 (page 131) for

ODT timing diagrams).

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by

Micron and thereby must be set to the default state. Enabling OCD beyond the default

settings will alter the I/O drive characteristics and the timing and output I/O specifica-

tions will no longer be valid (see Initialization (page 90) for proper setting of OCD de-

faults).

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus effi-

cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as

shown in Figure 37. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL

of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-

tion or incompatibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued

prior to tRCD (MIN) with the requirement that AL ื tRCD (MIN). A typical application

using this feature would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE command

is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.

RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to

RL minus one clock; WL = AL + CL - 1 × tCK. An example of RL is shown in Figure 38

(page 87). An example of a WL is shown in Figure 39 (page 87).

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register (EMR)

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Figure 38: READ Latency

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

AL = 2

ACTIVE n

T0 T1 T2

Don’t CareTransitioning Data

READ n NOP NOP

T3 T4 T5

NOP

T7 T8

NOP NOP

CL = 3

RL = 5

tRCD (MIN)

NOP

Notes: 1. BL = 4.

2. Shown with nominal tAC, tDQSCK, and tDQSQ.

3. RL = AL + CL = 5.

Figure 39: WRITE Latency

CK#

Command

DQS, DQS#

ACTIVE n

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

NOP

n + 3

n + 2

n + 1

WL = AL + CL - 1 = 4

NOP

tRCD (MIN)

NOP

AL = 2 CL - 1 = 2

WRITE n

Notes: 1. BL = 4.

2. CL = 3.

3. WL = AL + CL - 1 = 4.

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register (EMR)

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Extended Mode Register 2 (EMR2)

The extended mode register 2 (EMR2) controls functions beyond those controlled by

the mode register. Currently all bits in EMR2 are reserved, except for E7, which is used

in commercial or high-temperature operations, as shown in Figure 40. The EMR2 is pro-

grammed via the LM command and will retain the stored information until it is pro-

grammed again or until the device loses power. Reprogramming the EMR will not alter

the contents of the memory array, provided it is performed correctly.

Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT de-

vices if TC exceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 40: EMR2 Definition

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10A12 A11BA0BA1

101112n

1415

An2

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

MRS 000

SRT 0 00000 0

BA21

SRT Enable

1X refresh rate (0°C to 85°C)

2X refresh rate (>85°C)

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to “0.”

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register 2 (EMR2)

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Extended Mode Register 3 (EMR3)

The extended mode register 3 (EMR3) controls functions beyond those controlled by

the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 41. The

EMR3 is programmed via the LM command and will retain the stored information until

it is programmed again or until the device loses power. Reprogramming the EMR will

not alter the contents of the memory array, provided it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 41: EMR3 Definition

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10A12 A11

BA0BA1

101112n

1415

An2

MRS 0 0 0 0 0 0 0 0 0 0 00 0

BA21

Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, is reserved for future use, and must be

programmed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to “0.”

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register 3 (EMR3)

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Initialization

Figure 42: DDR2 Power-Up and Initialization

DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in unde-

fined operation. Figure 42 illustrates, and the notes outline, the sequence required for power-up and initialization.

tVTD1

CKE

Power-up:

and stable

clock (CK, CK#)

T = 200μs (MIN)3

High-Z

DM15

DQS15 High-Z

Address16

CK#

tCL

REF

DDQ

Command

NOP3

PRE

T0 Ta0

Don’t care

tCL

tCK

ODT

DQ15 High-Z

Tb0

200 cycles of CK are required before a READ command can be issued

MR with

DLL RESET

tRFC

LM8PRE9

LM7REF10 REF10 LM11

Tg0 Th0 Ti0 Tj0

MR without

DLL RESET

EMR with

OCD default

Tk0 Tl0 Tm0

Te0 Tf0

EMR(2) EMR(3)

tMRD

LM6

LM5

A10 = 1

tRPA

Tc0 Td0

SSTL_18

low level2

Valid14

Valid

Indicates a Break in

Time Scale

LM12

EMR with

OCD exit

LM13

Normal

operation

6HHQR WH

Code Code

A10 = 1

Code Code

Code Code Code

tMRD tMRD tMRD tMRD

tRPA tRFC

DDL

tMRD tMRD

EMR

T = 400ns (MIN)4

LVCMOS

low level2

1Gb: x4, x8, x16 DDR2 SDRAM

Initialization

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Notes: 1. Applying power; if CKE is maintained below 0.2 × VDDQ, outputs remain disabled. To

guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied

to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than

VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not ap-

plied directly to the device; however, tVTD should be ุ0 to avoid device latch-up. At

least one of the following two sets of conditions (A or B) must be met to obtain a stable

supply state (stable supply defined as VDD, VDDL, VDDQ, VREF, and VTT are between their

minimum and maximum values as stated in Table 13 (page 46)):

A. Single power source: The VDD voltage ramp from 300mV to VDD,min must take no lon-

ger than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ื 0.3V. Once supply voltage

ramping is complete (when VDDQ crosses VDD,min), Table 13 specifications apply.

•V

DD, VDDL, and VDDQ are driven from a single power converter output

•V

TT is limited to 0.95V MAX

•V

REF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply

ramp time; does not need to be satisfied when ramping power down

•V

DDQ ุ VREF at all times

B. Multiple power sources: VDD ุ VDDL ุ VDDQ must be maintained during supply voltage

ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ

crosses VDD,min). Once supply voltage ramping is complete, Table 13 specifications apply.

• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp time

must be ื 200ms from when VDD ramps from 300mV to VDD,min

• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from when

VDD,min is achieved to when VDDQ,min is achieved must be ื 500ms; while VDD is ramp-

ing, current can be supplied from VDD through the device to VDDQ

•V

REF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during sup-

ply ramp time; VDDQ ุ VREF must be met at all times; does not need to be satisfied

when ramping power down

• Apply VTT; the VTT voltage ramp time from when VDDQ,min is achieved to when VTT,min

is achieved must be no greater than 500ms

2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de-

vice power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18

input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of

the initialization sequence.

3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT

commands, then take CKE HIGH.

4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide

LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropri-

ate self refresh rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2

(EMR2) (page 88) for all EMR(2) requirements).

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide

HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3

(EMR3) for all EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE com-

mand, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set

to “0” or “1;” Micron recommends setting them to “0;” remaining EMR bits must be

“0.” Extended Mode Register (EMR) (page 84) for all EMR requirements.

8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is re-

quired to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to

BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits

must be “0.” Mode Register (MR) (page 79) for all MR requirements.

9. Issue PRECHARGE ALL command.

1Gb: x4, x8, x16 DDR2 SDRAM

Initialization

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10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation

(that is, to program operating parameters without resetting the DLL). To access the MR,

set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register

(MR) (page 79) for all MR requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,

and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0

HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 84) for all EMR require-

ments.

13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and

E9 to “0,” and then setting all other desired parameters. To access the extended mode

registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-

ter the DLL RESET at Tf0.

15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-

tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the ap-

propriate configuration (x4, x8, x16); DQ represents DQ[3:0] for x4, DQ[7:0] for x8 and

DQ[15:0] for x16.

16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are

required to be decoded).

1Gb: x4, x8, x16 DDR2 SDRAM

Initialization

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ACTIVATE

Before any READ or WRITE commands can be issued to a bank within the DDR2

SDRAM, a row in that bank must be opened (activated), even when additive latency is

used. This is accomplished via the ACTIVATE command, which selects both the bank

and the row to be activated.

After a row is opened with an ACTIVATE command, a READ or WRITE command may

be issued to that row subject to the tRCD specification. tRCD (MIN) should be divided

by the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVATE command on which a READ or WRITE command can be

entered. The same procedure is used to convert other specification limits from time

units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz

clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 43,

which covers any case where 5 < tRCD (MIN)/tCK ื 6. Figure 43 also shows the case for

tRRD where 2 < tRRD (MIN)/tCK ื 3.

Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN)

Command

Don’t Care

T1T0 T2 T3 T4 T5 T6 T7

tRRD tRRD

Row Row Col

Bank x Bank y

Row

Bank z Bank y

NOPACT NOP NOPACT NOP NOP RD/WR

tRCD

CK#

Address

Bank address

T8 T9

NOP NOP

A subsequent ACTIVATE command to a different row in the same bank can only be is-

sued after the previous active row has been closed (precharged). The minimum time in-

terval between successive ACTIVATE commands to the same bank is defined by tRC.

A subsequent ACTIVATE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The mini-

mum time interval between successive ACTIVATE commands to different banks is de-

fined by tRRD.

DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. This

requires no more than four ACTIVATE commands may be issued in any given tFAW

(MIN) period, as shown in Figure 44 (page 94).

1Gb: x4, x8, x16 DDR2 SDRAM

ACTIVATE

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Figure 44: Multibank Activate Restriction

Command

Don’t Care

T1T0 T2 T3 T4 T5 T6 T7

tRRD (MIN)

Row Row

READACT ACT NOP

tFAW (MIN)

Bank address

CK#

Address

T8 T9

Col

Bank a

ACTREAD READ READACT NOP

Row

Col Row

Col Col

Bank cBank b Bank dBank c Bank e

ACT

Row

T10

Bank dBank bBank a

Note: 1. DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns,

tFAW (MIN) = 37.5ns.

1Gb: x4, x8, x16 DDR2 SDRAM

ACTIVATE

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READ

READ bursts are initiated with a READ command. The starting column and bank ad-

dresses are provided with the READ command, and auto precharge is either enabled or

disabled for that burst access. If auto precharge is enabled, the row being accessed is

automatically precharged at the completion of the burst. If auto precharge is disabled,

the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address will

be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL:

RL = AL + CL. The value for AL and CL are programmable via the MR and EMR com-

mands, respectively. Each subsequent data-out element will be valid nominally at the

next positive or negative clock edge (at the next crossing of CK and CK#). Figure 45

(page 96) shows examples of RL based on different AL and CL settings.

DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state

on DQS and the HIGH state on DQS# are known as the read preamble (tRPRE). The

LOW state on DQS and the HIGH state on DQS# coincident with the last data-out ele-

ment are known as the read postamble (tRPST).

Upon completion of a burst, assuming no other commands have been initiated, the DQ

will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out

window hold), and the valid data window are depicted in Figure 54 (page 104) and Fig-

ure 55 (page 105). A detailed explanation of tDQSCK (DQS transition skew to CK) and

tAC (data-out transition skew to CK) is shown in Figure 56 (page 106).

Data from any READ burst may be concatenated with data from a subsequent READ

command to provide a continuous flow of data. The first data element from the new

burst follows the last element of a completed burst. The new READ command should be

issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 46

(page 97)).

Nonconsecutive read data is illustrated in Figure 47 (page 98). Full-speed random read

accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of

concurrent auto precharge timing (see Table 42 (page 101)).

DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4

operations. Once the BL = 4 READ command is registered, it must be allowed to com-

plete the entire READ burst. However, a READ (with auto precharge disabled) using BL =

8 operation may be interrupted and truncated only by another READ burst as long as

the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of

DDR2 SDRAM. As shown in Figure 48 (page 99), READ burst BL = 8 operations may

not be interrupted or truncated with any other command except another READ com-

mand.

Data from any READ burst must be completed before a subsequent WRITE burst is al-

lowed. An example of a READ burst followed by a WRITE burst is shown in Figure 49

(page 99). The tDQSS (NOM) case is shown (tDQSS [MIN] and tDQSS [MAX] are de-

fined in Figure 57 (page 108)).

1Gb: x4, x8, x16 DDR2 SDRAM

READ

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Figure 45: READ Latency

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CK#

Command

Address

DQS, DQS#

T0 T1 T2 T3 T4n T5nT4 T5

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,

Col n

RL = 3 (AL = 0, CL = 3)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,

Col n

RL = 4 (AL = 0, CL = 4)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

AL = 1 CL = 3

RL = 4 (AL = 1 + CL = 3)

Don’t Care

Transitioning Data

Notes: 1. DO n = data-out from column n.

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

1Gb: x4, x8, x16 DDR2 SDRAM

READ

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Figure 46: Consecutive READ Bursts

CK#

Command READ NOP READ NOP NOP NOP NOP

Address Bank,

Col n Bank,

Col b

Command READ NOP READ NOP NOP NOP

Address Bank,

Col n Bank,

Col b

RL = 3

CK#

DQS, DQS#

RL = 4

DQS, DQS#

nDO

T0 T1 T2 T3 T3n T4nT4 T5 T6

T5n T6n

T0 T1 T2 T3T2n

NOP

T3n T4nT4 T5 T6

T5n T6n

Don’t CareTransitioning Data

tCCD

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Three subsequent elements of data-out appear in the programmed order following

DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

1Gb: x4, x8, x16 DDR2 SDRAM

READ

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Figure 47: Nonconsecutive READ Bursts

Command READ NOP NOP NOP NOP NOP NOP NOPREAD

T0 T1 T2 T3 T3n T4 T5 T7 T8T6T4n T6n T7n

CK#

T5 T7 T8T5n T6T4n T7n

Command NOP NOP NOP NOPREAD NOP NOP NOPREAD

T0 T1 T2 T3 T4

DQ DO

nDO

Don’t CareTransitioning Data

Address Bank,

Col n Bank,

Col b

Address Bank,

Col n Bank,

Col b

CK#

CL = 4

CL = 3

DQ DO

nDO

DQS, DQS#

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Three subsequent elements of data-out appear in the programmed order following

DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecu-

tive READs.

1Gb: x4, x8, x16 DDR2 SDRAM

READ

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Figure 48: READ Interrupted by READ

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6

Command READ

NOP

Valid Valid Valid

READ

Valid Valid Valid

T7 T8 T9

CK#

CL = 3 (AL = 0)

tCCD

Address Valid

Valid

CL = 3 (AL = 0)

DQ DO DO DO DO DO DO DO DO DO DO DO DO

A10 Valid

DQS, DQS#

Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).

2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-

sued to banks used for READs at T0 and T2.

3. Interrupting READ command must be issued exactly 2 × tCK from previous READ.

4. READ command can be issued to any valid bank and row address (READ command at T0

and T2 can be either same bank or different bank).

5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-

terrupting READ command.

6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and

tDQSQ.

Figure 49: READ-to-WRITE

CK# T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6 T7 T8 T9 T10 T11

AL = 2 CL = 3

RL = 5

WL = RL - 1 = 4

tRCD = 3

Command

ACT n NOP NOP NOP NOP NOP NOP

READ n NOP NOP NOPWRITE

DQS, DQS#

DQ DO

nDO

n + 1 DO

n + 2 DO

n + 3 DI

nDI

n + 1 DI

n + 2 DI

n + 3

Notes: 1. BL = 4; CL = 3; AL = 2.

2. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ with Precharge

A READ burst may be followed by a PRECHARGE command to the same bank, provided

auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-

ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and

tRTP. tRTP is the minimum time from the rising clock edge that initiates the last 4-bit

prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time

from the actual READ (AL after the READ command) to PRECHARGE command. For

BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command. Fol-

1Gb: x4, x8, x16 DDR2 SDRAM

READ

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lowing the PRECHARGE command, a subsequent command to the same bank cannot

be issued until tRP is met. However, part of the row precharge time is hidden during the

access of the last data elements.

Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 50 and in Figure 51

for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/2 -

2CK + MAX (tRTP/tCK or 2 × CK) where MAX means the larger of the two.

Figure 50: READ-to-PRECHARGE – BL = 4

CK#

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6 T7

Address Bank a Bank a Bank a

tRAS (MIN)

tRTP (MIN)

tRP (MIN)

AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)

Command READ NOP

PRE

ACTNOP NOP NOP NOP

4-bit

prefetch

DQ DO DO DO DO

A10 Valid Valid

CL = 3AL = 1

DQS, DQS#

tRC (MIN)

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.

2. tRTP ุ 2 clocks.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

Figure 51: READ-to-PRECHARGE – BL = 8

CK# T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6 T7 T8

CL = 3

AL = 1

DQS, DQS#

First 4-bit

prefetch

Second 4-bit

prefetch

tRTP (MIN) tRP (MIN)

Address

Bank a Bank a Bank a

tRC (MIN)

tRAS (MIN)

A10

Valid Valid

AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)

DO DO DO DO DO DO DO DO

Command

READ NOP NOP NOPNOP NOPNOP ACTPRE

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.

2. tRTP ุ 2 clocks.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

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READ with Auto Precharge

If A10 is high when a READ command is issued, the READ with auto precharge function

is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock

edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-

ded tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at this rising clock

edge, the start point of the auto precharge operation will be delayed until tRAS (MIN) is

satisfied. If tRTP (MIN) is not satisfied at this rising clock edge, the start point of the au-

to precharge operation will be delayed until tRTP (MIN) is satisfied. When the internal

precharge is pushed out by tRTP, tRP starts at the point where the internal precharge

happens (not at the next rising clock edge after this event).

When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE

command is AL + (tRTP + tRP)/tCK. When BL = 8, the minimum time from READ with

auto precharge to the next ACTIVATE command is AL + 2 clocks + (tRTP + tRP)/tCK. The

term (tRTP + tRP)/tCK is always rounded up to the next integer. A general purpose equa-

tion can also be used: AL + BL/2 - 2CK + (tRTP + tRP)/tCK. In any event, the internal pre-

charge does not start earlier than two clocks after the last 4-bit prefetch.

READ with auto precharge command may be applied to one bank while another bank is

operational. This is referred to as concurrent auto precharge operation, as noted in Ta-

ble 42. Examples of READ with precharge and READ with auto precharge with applica-

ble timing requirements are shown in Figure 52 (page 102) and Figure 53 (page 103),

respectively.

Table 42: READ Using Concurrent Auto Precharge

From Command (Bank n) To Command (Bank m)

Minimum Delay

(with Concurrent Auto Precharge) Units

READ with auto precharge READ or READ with auto precharge BL/2 tCK

WRITE or WRITE with auto precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

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Figure 52: Bank Read – Without Auto Precharge

CK#

CKE

A10

Bank address

tCK tCH tCL

tRCD

tRAS3

tRC

tRP

CL = 3

T0 T1 T2 T3 T4 T5 T7n T8nT6 T7 T8

DQ8

DQS, DQS#

Case 1: tAC (MIN)

and tDQSCK (MIN)

Case 2: tAC (MAX)

and tDQSCK (MAX)

DQ8

DQS, DQS#

RPRE

tRPRE

tRPST

DQSCK (MIN)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MIN)

NOP1

Command ACT

RA Col n

PRE

Bank x

Bank xBank x6

ACT

Bank x

NOP1NOP1NOP1NOP1

HZ (MIN)

One bank

All banks

Don’t CareTransitioning Data

Address

tRTP4

tRPST

DQSCK (MAX)

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4 and AL = 0 in the case shown.

3. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.

4. READ-to-PRECHARGE = AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK).

5. Disable auto precharge.

6. “Don’t Care” if A10 is HIGH at T5.

7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

8. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

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Figure 53: Bank Read – with Auto Precharge

4-bit

prefetch

CK#

CKE

A10

Bank address

tCK tCH tCL

tRCD

tRAS

tRC

tRP

CL = 3

T0 T1 T2 T3 T4 T5 T7n T8nT6 T7 T8

DQ6

DQS, DQS#

Case 1: tAC (MIN)

and tDQSCK (MIN)

Case 2: tAC (MAX)

and tDQSCK (MAX)

DQ6

DQS, DQS#

RPRE

tRPRE

tRPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MAX)

NOP1

Command1

ACT

RA Col n

Bank x

ACT

Bank x

NOP1NOP1NOP1NOP1NOP1

HZ (MIN)

Don’t CareTransitioning Data

Address

AL = 1

tRTP

Internal

precharge

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.

3. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)

have been satisfied.

4. Enable auto precharge.

5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

6. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

1Gb: x4, x8, x16 DDR2 SDRAM

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Figure 54: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

DQ (last data valid)

DQ4

DQS#

DQS3

DQ (last data valid)

DQ (first data no longer valid)

All DQs and DQS collectively6

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T1 T2 T3 T4T2n T3n

tQH5

tHP1tHP1t

HP1

tQH5

tQHS

tQH5

tHP1tHP1tHP1

tQH5

tDQSQ2t

DQSQ2t

DQSQ2

Data

valid

window

Data

valid

window

Data

valid

window

Data

valid

window

tQHS

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

3. DQ transitioning after the DQS transition defines the tDQSQ window. DQS transitions at

T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”

4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.

5. tQH is derived from tHP: tQH = tHP - tQHS.

6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.

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Figure 55: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

DQ (last data valid)4

DQ4

LDSQ#

LDQS3

DQ (last data valid)4

DQ (first data no longer valid)4

DQ0–DQ7 and LDQS collectively6T2

T2n

T3n

CK# T1 T2 T3 T4T2n T3n

tQH

tDQSQ

Data valid

window

Data valid

window

DQ (last data valid)7

DQ7

UDQS#

UDQS3

DQ (last data valid)7

DQ (first data no longer valid)7

DQ8–DQ15 and UDQS collectively6T2

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data valid

window

Data valid

window

Data valid

window

Data valid

window

Data valid

window

Upper Byte

Lower Byte

Data valid

window

tQHS

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

3. DQ transitioning after the DQS transitions define the tDQSQ window. LDQS defines the

lower byte, and UDQS defines the upper byte.

4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

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5. tQH is derived from tHP: tQH = tHP - tQHS.

6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

Figure 56: Data Output Timing – tAC and tDQSCK

CK#

DQS#/DQS or

LDQS#/LDQS/UDQ#/UDQS3

T01T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7

tRPST

tDQSCK2 (MIN) tDQSCK2 (MAX)

DQ (last data valid)

DQ (first data valid)

All DQs collectively4

tAC5 (MIN) tAC5 (MAX)

tLZ (MIN) tHZ (MAX)

T3n T4n T5n T6n

T3n

T4n

T5n

T6n

T3 T4 T5 T6

tHZ (MAX)

tLZ (MIN) tRPRE

Notes: 1. READ command with CL = 3, AL = 0 issued at T0.

2. tDQSCK is the DQS output window relative to CK and is the long-term component of

DQS skew.

3. DQ transitioning after DQS transitions define tDQSQ window.

4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

5. tAC is the DQ output window relative to CK and is the “long term” component of DQ

skew.

6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.

7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.

8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

WRITE

WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL

minus one clock cycle (WL = RL - 1CK) (see READ (page 78)). The starting column and

bank addresses are provided with the WRITE command, and auto precharge is either

enabled or disabled for that access. If auto precharge is enabled, the row being accessed

is precharged at the completion of the burst.

Note:

For the WRITE commands used in the following illustrations, auto precharge is disa-

bled.

During WRITE bursts, the first valid data-in element will be registered on the first rising

edge of DQS following the WRITE command, and subsequent data elements will be reg-

istered on successive edges of DQS. The LOW state on DQS between the WRITE com-

mand and the first rising edge is known as the write preamble; the LOW state on DQS

following the last data-in element is known as the write postamble.

The time between the WRITE command and the first rising DQS edge is WL ±tDQSS.

Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as

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±tDQSS. tDQSS is specified with a relatively wide range (25% of one clock cycle). All of

the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS

[MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 57

(page 108) shows the nominal case and the extremes of tDQSS for BL = 4. Upon com-

pletion of a burst, assuming no other commands have been initiated, the DQ will re-

main High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to

provide continuous flow of input data. The first data element from the new burst is ap-

plied after the last element of a completed burst. The new WRITE command should be

issued x cycles after the first WRITE command, where x equals BL/2.

Figure 58 (page 109) shows concatenated bursts of BL = 4 and how full-speed random

write accesses within a page or pages can be performed. An example of nonconsecutive

WRITEs is shown in Figure 59 (page 109). DDR2 SDRAM supports concurrent auto pre-

charge options, as shown in Table 43.

DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4

operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-

plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-

charge disabled) might be interrupted and truncated only by another WRITE burst as

long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture

of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated

with any command except another WRITE command, as shown in Figure 60

(page 110).

Data for any WRITE burst may be followed by a subsequent READ command. To follow

a WRITE, tWTR should be met, as shown in Figure 61 (page 111). The number of clock

cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any

WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be

met, as shown in Figure 62 (page 112). tWR starts at the end of the data burst, regardless

of the data mask condition.

Table 43: WRITE Using Concurrent Auto Precharge

From Command

(Bank n)

To Command

(Bank m)

Minimum Delay

(with Concurrent Auto Precharge) Units

WRITE with auto precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

1Gb: x4, x8, x16 DDR2 SDRAM

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Figure 57: Write Burst

DQS, DQS#

tDQSS (MAX)

tDQSS (NOM)

tDQSS (MIN)

CK#

Command

WRITE NOP NOP

Address

Bank a,

Col b

NOP NOP

T0 T1 T2 T3T2n T4T3n

DQS, DQS#

Don’t CareTransitioning Data

tDQSS5

WL ± tDQSS

WL - tDQSS tDQSS5

WL + tDQSS

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

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Figure 58: Consecutive WRITE-to-WRITE

CK#

Command

WRITE NOP WRITE NOP NOP NOP

Address

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n

DQS, DQS#

Don’t CareTransitioning Data

WL ± tDQSS

tDQSS (NOM)

WL = 2

tCCD

WL = 2

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b, etc. = data-in for column b, etc.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Three subsequent elements of data-in are applied in the programmed order following

DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any bank.

Figure 59: Nonconsecutive WRITE-to-WRITE

CK#

Command

WRITE NOP NOP NOP NOP NOP

Address

Bank,

Col b

WRITE

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4nT3n T5n T6 T6n

DQS, DQS#

tDQSS (NOM) WL ± tDQSS

Don’t CareTransitioning Data

WL = 2 WL = 2

111

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b (or n), etc. = data-in for column b (or column n).

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Three subsequent elements of data-in are applied in the programmed order following

DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any bank.

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Figure 60: WRITE Interrupted by WRITE

CK#

Command

DQS, DQS#

WL = 3

WRITE1 a

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6

WRITE3 b

T7 T8 T9

WL = 32-clock requirement

Address

A10

Valid6

Valid5Valid5

Valid4Valid4

Valid

NOP2

7 7777

a + 1 DI

a + 3

a + 2 DI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

Notes: 1. BL = 8 required and auto precharge must be disabled (A10 = LOW).

2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot

be issued to banks used for WRITEs at T0 and T2.

3. The interrupting WRITE command must be issued exactly 2 × tCK from previous WRITE.

4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR

starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).

5. The WRITE command can be issued to any valid bank and row address (WRITE command

at T0 and T2 can be either same bank or different bank).

6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-

terrupting WRITE command.

7. Subsequent rising DQS signals must align to the clock within tDQSS.

8. Example shown uses AL = 0; CL = 4, BL = 8.

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Figure 61: WRITE-to-READ

tDQSS (NOM)

CK#

Command

WRITE NOP NOP NOP NOP NOP NOP NOP

Address

Bank a,

Col b Bank a,

Col n

READ

T0 T1 T2 T3T2n T4 T5 T9nT3n T6 T7 T8 T9

tWTR1

CL = 3

DQS, DQS#

tDQSS (MIN)

DQS, DQS#

tDQSS (MAX)

DQS, DQS#

Don’t CareTransitioning Data

WL ± tDQSS

WL - tDQSS

WL + tDQSS

NOP

Notes: 1. tWTR is required for any READ following a WRITE to the same device, but it is not re-

quired between module ranks.

2. Subsequent rising DQS signals must align to the clock within tDQSS.

3. DI b = data-in for column b; DO n = data-out from column n.

4. BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. One subsequent element of data-in is applied in the programmed order following DI b.

6. tWTR is referenced from the first positive CK edge after the last data-in pair.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

8. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is

greater.

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Figure 62: WRITE-to-PRECHARGE

tDQSS (NOM)

CK#

Command

WRITE NOP NOP NOP NOPNOP

Address

Bank a,

Col b Bank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5T3n T6 T7

tWR tRP

DQS#

DQS

tDQSS (MIN)

DQS#

DQS

tDQSS (MAX)

DQS#

DQS

Don’t CareTransitioning Data

WL + tDQSS

WL - tDQSS

WL + tDQSS

PRE

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. BL = 4, CL = 3, AL = 0; thus, WL = 2.

5. tWR is referenced from the first positive CK edge after the last data-in pair.

6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE

and WRITE commands may be to different banks, in which case tWR is not required and

the PRECHARGE command could be applied earlier.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

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Figure 63: Bank Write – Without Auto Precharge

CK#

CKE

A10

tCK tCH tCL

tRCD

tRAS tRP

tWR

T0 T1 T2 T3 T5 T6 T6n T7 T8 T9T5n

NOP1

Command

ACT

RA Col n

WRITE2NOP1

One bank

All banks

Bank x

PRE

Bank x

NOP1NOP1NOP1

tDQSL tDQSH tWPST

Bank x4

DQ6

Don’t CareTransitioning Data

WL ±tDQSS (NOM)

tWPRE

DQS, DQS#

Address

NOP1

WL = 2

Bank select

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T9.

5. Subsequent rising DQS signals must align to the clock within tDQSS.

6. DI n = data-in for column n; subsequent elements are applied in the programmed order.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

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Figure 64: Bank Write – with Auto Precharge

CK#

CKE

A10

Bank select

tCK tCH t

tRCD

tRAS tRP

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T6n

NOP1

Command

ACT

RA Col n

WRITE2NOP1

Bank x

NOP1

Bank x

NOP1NOP1NOP1

tDQSL tDQSH tWPST

DQ6

WL ±tDQSS (NOM)

Don’t Care

Transitioning Data

tWPRE

DQS, DQS#

Address

NOP1

WL = 2

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4 and AL = 0 in the case shown.

3. Enable auto precharge.

4. WR is programmed via MR9–MR11 and is calculated by dividing tWR (in ns) by tCK and

rounding up to the next integer value.

5. Subsequent rising DQS signals must align to the clock within tDQSS.

6. DI n = data-in from column n; subsequent elements are applied in the programmed or-

der.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

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Figure 65: WRITE – DM Operation

CK#

CKE

A10

Bank select

RCD

RAS tRPA

tWR5

T0 T1 T2 T3 T4 T5 T7nT6 T7 T8T6n

NOP1

Command

ACT

RA Col n

WRITE2

NOP1

One bank

All banks

Bank xBank x

NOP1NOP1NOP1NOP1NOP1NOP1

tDQSL tDQSH

tWPST

Bank x4

DQ7

Don’t CareTransitioning Data

WL ±

DQSS (NOM)

tWPRE

PRE

DQS, DQS#

Address

T9 T10 T11

AL = 1 WL = 2

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

2. BL = 4, AL = 1, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T11.

5. tWR starts at the end of the data burst regardless of the data mask condition.

6. Subsequent rising DQS signals must align to the clock within tDQSS.

7. DI n = data-in for column n; subsequent elements are applied in the programmed order.

8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.

9. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.

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Figure 66: Data Input Timing

DQS

DQS#

tDQSH tWPST

tDQSL

tDSS 2tDSH 1

tDSH 1tDSS 2

CK#

T1T0 T1n T2 T2n T3 T4T3n

Don’t CareTransitioning Data

WPRE

WL - tDQSS (NOM)

Notes: 1. tDSH (MIN) generally occurs during tDQSS (MIN).

2. tDSS (MIN) generally occurs during tDQSS (MAX).

3. Subsequent rising DQS signals must align to the clock within tDQSS.

4. WRITE command issued at T0.

5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.

PRECHARGE

Precharge can be initiated by either a manual PRECHARGE command or by an autopre-

charge in conjunction with either a READ or WRITE command. Precharge will deacti-

vate the open row in a particular bank or the open row in all banks. The PRECHARGE

operation is shown in the previous READ and WRITE operation sections.

During a manual PRECHARGE command, the A10 input determines whether one or all

banks are to be precharged. In the case where only one bank is to be precharged, bank

address inputs determine the bank to be precharged. When all banks are to be pre-

charged, the bank address inputs are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and must be activated prior to

any READ or WRITE commands being issued to that bank. When a single-bank PRE-

CHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL) com-

mand is issued, tRPA timing applies, regardless of the number of banks opened.

1Gb: x4, x8, x16 DDR2 SDRAM

PRECHARGE

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REFRESH

The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-

terval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every

64ms. The refresh period begins when the REFRESH command is registered and ends

tRFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when TC exceeds

85°C.

Figure 67: Refresh Mode

CK#

Command

NOP1

NOP1NOP1

PRE

CKE

Address

A10

Bank

Bank(s)

REF NOP1REF2NOP1ACT

NOP1

One bank

All banks

tCK tCH tCL

DQ4

DM4

DQS, DQS#4

tRFC2

tRP tRFC (MIN)

T0 T1 T2 T3 T4 Ta0 Tb0

Ta1 Tb1 Tb2

Don’t Care

Indicates a break in

time scale

Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possi-

ble at these times. CKE must be active during clock positive transitions.

2. The second REFRESH is not required and is only shown as an example of two back-to-

back REFRESH commands.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is

active (must precharge all active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

1Gb: x4, x8, x16 DDR2 SDRAM

REFRESH

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SELF REFRESH

The SELF REFRESH command is initiated when CKE is LOW. The differential clock

should remain stable and meet tCKE specifications at least 1 × tCK after entering self re-

fresh mode. The procedure for exiting self refresh requires a sequence of commands.

First, the differential clock must be stable and meet tCK specifications at least 1 × tCK

prior to CKE going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied

with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-

mands issued for tXSNR. A simple algorithm for meeting both refresh and DLL require-

ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-

ing any other command.

1Gb: x4, x8, x16 DDR2 SDRAM

SELF REFRESH

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Figure 68: Self Refresh

CK1

CK#

Command

NOP REF

Address

CKE1

Valid

DQS#, DQS

NOP4

tRP

tCH tCL tCK

tCK

tXSNR

2, 5, 10

tISXR

Enter self refresh

mode (synchronous)

Exit self refresh

mode (asynchronous)

T0 T1 Ta2Ta1

Don’t Care

Ta0 Tc0Tb0

tXSRD2,

Valid5

NOP4

tCKE (MIN)

ODT6

tAOFD/tAOFPD

Td0

Valid7

Valid5

Indicates a break in

time scale

W,+

tCKE3

Notes: 1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self

refresh mode and at least 1 × tCK prior to exiting self refresh mode.

2. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first ris-

ing clock edge where CKE HIGH satisfies tISXR.

3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE

may go back LOW after tXSNR is satisfied.

4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,

which allows any nonREAD command.

5. tXSNR is required before any nonREAD command can be applied.

6. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to en-

tering self refresh at state T1.

7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state

Td0.

8. Device must be in the all banks idle state prior to entering self refresh mode.

9. After self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self re-

fresh.

10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.

1Gb: x4, x8, x16 DDR2 SDRAM

SELF REFRESH

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Power-Down Mode

DDR2 SDRAM supports multiple power-down modes that allow significant power sav-

ings over normal operating modes. CKE is used to enter and exit different power-down

modes. Power-down entry and exit timings are shown in Figure 69 (page 121). Detailed

power-down entry conditions are shown in Figure 70 (page 123)–Figure 77 (page 126).

Table 44 (page 122) is the CKE Truth Table.

DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is

in progress—from the issuing of a READ or WRITE command until completion of the

burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined

when the read postamble is satisfied; for WRITEs, a burst completion is defined when

the write postamble and tWR (WRITE-to-PRECHARGE command) or tWTR (WRITE-to-

READ command) are satisfied, as shown in Figure 72 (page 124) and Figure 73

(page 124) on Figure 73 (page 124). The number of clock cycles required to meet tWTR

is either two or tWTR/tCK, whichever is greater.

Power-down mode (see Figure 69 (page 121)) is entered when CKE is registered low co-

incident with an NOP or DESELECT command. CKE is not allowed to go LOW during a

mode register or extended mode register command time, or while a READ or WRITE op-

eration is in progress. If power-down occurs when all banks are idle, this mode is refer-

red to as precharge power-down. If power-down occurs when there is a row active in

any bank, this mode is referred to as active power-down. Entering power-down deacti-

vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum

power savings, the DLL is frozen during precharge power-down. Exiting active power-

down requires the device to be at the same voltage and frequency as when it entered

power-down. Exiting precharge power-down requires the device to be at the same volt-

age as when it entered power-down; however, the clock frequency is allowed to change

(see Precharge Power-Down Clock Frequency Change (page 127)).

The maximum duration for either active or precharge power-down is limited by the re-

fresh requirements of the device tRFC (MAX). The minimum duration for power-down

entry and exit is limited by the tCKE (MIN) parameter. The following must be main-

tained while in power-down mode: CKE LOW, a stable clock signal, and stable power

supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t

Care” except ODT. Detailed ODT timing diagrams for different power-down modes are

shown in Figure 82 (page 132)–Figure 87 (page 136).

The power-down state is synchronously exited when CKE is registered HIGH (in con-

junction with a NOP or DESELECT command), as shown in Figure 69 (page 121).

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Figure 69: Power-Down

CK#

Command

NOP NOP NOP

Address

CKE

DQS, DQS#

Valid

tCH tCL

Enter

power-down

mode6

Exit

power-down

mode Don’t Care

tCKE (MIN)2

tCKE (MIN)

Valid

Valid1

Valid

tXP3, tXARD4

tXARDS5

Valid Valid

tIS

tIH

T1 T2 T3 T4 T5 T6 T7 T8

tCK

Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVATE

(or if at least one row is already active), then the power-down mode shown is active

power-down.

2. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive

clock edges. CKE must remain at the valid input level the entire time it takes to achieve

the three clocks of registration. Thus, after any CKE transition, CKE may not transition

from its valid level during the time period of tIS + 2 × tCK + tIH. CKE must not transition

during its tIS and tIH window.

3. tXP timing is used for exit precharge power-down and active power-down to any non-

READ command.

4. tXARD timing is used for exit active power-down to READ command if fast exit is selec-

ted via MR (bit 12 = 0).

5. tXARDS timing is used for exit active power-down to READ command if slow exit is se-

lected via MR (bit 12 = 1).

6. No column accesses are allowed to be in progress at the time power-down is entered. If

the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exit-

ing power-down mode for proper READ operation.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Table 44: Truth Table – CKE

Notes 1–4 apply to the entire table

Current State

CKE Command (n)

CS#, RAS#, CAS#,

WE# Action (n) Notes

Previous Cycle

(n - 1)

Current

Cycle (n)

Power-down L L X Maintain power-down 5, 6

L H DESELECT or NOP Power-down exit 7, 8

Self refresh L L X Maintain self refresh 6

L H DESELECT or NOP Self refresh exit 7, 9, 10

Bank(s) active H L DESELECT or NOP Active power-down en-

try

7, 8, 11, 12

All banks idle H L DESELECT or NOP Precharge power-down

entry

7, 8, 11

H L Refresh Self refresh entry 10, 12, 13

H H Shown in Table 37 (page 73) 14

Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the

previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.

3. Command (n) is the command registered at clock edge n, and action (n) is a result of

command (n).

4. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh (see ODT Timing (page 130) for more details and spe-

cific restrictions).

5. Power-down modes do not perform any REFRESH operations. The duration of power-

down mode is therefore limited by the refresh requirements.

6. “X” means “Don’t Care” (including floating around VREF) in self refresh and power-

down. However, ODT must be driven high or low in power-down if the ODT function is

enabled via EMR.

7. All states and sequences not shown are illegal or reserved unless explicitly described

elsewhere in this document.

8. Valid commands for power-down entry and exit are NOP and DESELECT only.

9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-

curring during the tXSNR period. READ commands may be issued only after tXSRD (200

clocks) is satisfied.

10. Valid commands for self refresh exit are NOP and DESELECT only.

11. Power-down and self refresh can not be entered while READ or WRITE operations,

LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH

(page 118) and SELF REFRESH (page 79) for a list of detailed restrictions.

12. Minimum CKE high time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK.

This requires a minimum of 3 clock cycles of registration.

13. Self refresh mode can only be entered from the all banks idle state.

14. Must be a legal command, as defined in Table 37 (page 73).

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Figure 70: READ-to-Power-Down or Self Refresh Entry

CK#

Command

DQS, DQS#

RL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid

T6 T7

tCKE (MIN)

Address

A10

NOP

CKE

READ

Valid

Power-down

self refresh entry

NOP1

Valid

DODO DO

Notes: 1. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

2. Power-down or self refresh entry may occur after the READ burst completes.

Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry

CK#

Command

DQS, DQS#

RL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid Valid

T6 T7

tCKE (MIN)

Address

A10

NOP

CKE

READ

Valid

Power-down or

self refresh

entry

NOP1

DO DODO DO

Notes: 1. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

2. Power-down or self refresh entry may occur after the READ burst completes.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Figure 72: WRITE-to-Power-Down or Self Refresh Entry

CK#

Command

DQS, DQS#

WL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid Valid

Valid

T7 T8

tCKE (MIN)

Address

A10

NOPWRITE

Valid

Power-down or

self refresh entry1

tWTR

NOP

DO DO DO

CKE

Note: 1. Power-down or self refresh entry may occur after the WRITE burst completes.

Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry

CK#

Command

DQS, DQS#

WL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid Valid

Ta0

Valid1NOP

Ta1 Ta2

tCKE (MIN)

Address

A10

NOP

CKE

WRITE

Valid

Power-down or

self refresh entry

WR2

DO DO DO

Indicates a break in

time scale

Notes: 1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-

cur 1 x tCK later at Ta1, prior to tRP being satisfied.

2. WR is programmed through MR9–MR11 and represents (tWR [MIN] ns/tCK) rounded up

to next integer tCK.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Figure 74: REFRESH Command-to-Power-Down Entry

CK#

Command

Don’t Care

T0 T1

Valid

REFRESH

T2 T3

tCKE (MIN)

CKE

Power-down1

entry

1 x tCK

NOP

Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the

REFRESH command. Precharge power-down entry occurs prior to tRFC (MIN) being satis-

fied.

Figure 75: ACTIVATE Command-to-Power-Down Entry

CK#

Command

Don’t Care

T0 T1

Valid ACT

NOP

tCKE (MIN)

CKE

Power-down1

entry

1 tCK

Address

VALID

Note: 1. The earliest active power-down entry may occur is at T2, which is 1 × tCK after the ACTI-

VATE command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Figure 76: PRECHARGE Command-to-Power-Down Entry

CK#

Command

Don’t Care

T0 T1

Valid

PRE

NOP

tCKE (MIN)

CKE

Power-down1

entry

1 x tCK

Address

A10

Valid

All banks

Single bank

Note: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the

PRECHARGE command. Precharge power-down entry occurs prior to tRP (MIN) being sat-

isfied.

Figure 77: LOAD MODE Command-to-Power-Down Entry

CK#

Command

Don’t Care

T0 T1

Valid LM

NOP

T3 T4

tCKE (MIN)

CKE

Power-down

entry

tMRD

Address

Valid1

tRP

NOP

Notes: 1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

2. All banks must be in the precharged state and tRP met prior to issuing LM command.

3. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

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Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off

and CKE must be at a logic LOW level. A minimum of two differential clock cycles must

pass after CKE goes LOW before clock frequency may change. The device input clock

frequency is allowed to change only within minimum and maximum operating fre-

quencies specified for the particular speed grade. During input clock frequency change,

ODT and CKE must be held at stable LOW levels. When the input clock frequency is

changed, new stable clocks must be provided to the device before precharge power-

down may be exited, and DLL must be reset via MR after precharge power-down exit.

Depending on the new clock frequency, additional LM commands might be required to

adjust the CL, WR, AL, and so forth. Depending on the new clock frequency, an addi-

tional LM command might be required to appropriately set the WR MR9, MR10, MR11.

During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock

time, the DRAM is ready to operate with a new clock frequency.

Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode

CK#

Command

Valid4NOP

Address

CKE

DQS, DQS#

NOP

tCK

Enter precharge

power-down mode Exit precharge

power-down mode

T0 T1 T3 Ta0T2

Don’t Care

Valid

tCKE (MIN)

tXP

DLL RESET

Valid

NOP

tCH tCL

Ta1 Ta2 Tb0Ta3

2 x tCK (MIN)

1 x tCK (MIN)

tCH tCL

tCK

ODT

200 x tCK

NOP

Ta4

Previous clock frequency New clock frequency

Frequency

change

Indicates a break in

time scale

High-Z

tCKE (MIN)

Notes: 1. A minimum of 2 × tCK is required after entering precharge power-down prior to chang-

ing clock frequencies.

2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is re-

quired prior to exiting precharge power-down.

1Gb: x4, x8, x16 DDR2 SDRAM

Precharge Power-Down Clock Frequency Change

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3. Minimum CKE high time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK.

This requires a minimum of three clock cycles of registration.

4. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down, which is required prior to the clock

frequency change.

Reset

CKE Low Anytime

DDR2 SDRAM applications may go into a reset state anytime during normal operation.

If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-

vice resumes normal operation after reinitializing. All data will be lost during a reset

condition; however, the DDR2 SDRAM device will continue to operate properly if the

following conditions outlined in this section are satisfied.

The reset condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and

VREF) are stable and meet all DC specifications prior to, during, and after the RESET op-

eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during RE-

SET with the exception of CKE.

If CKE asynchronously drops LOW during any valid operation (including a READ or

WRITE burst), the memory controller must satisfy the timing parameter tDELAY before

turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-

fore CKE is raised HIGH, at which time the normal initialization sequence must occur

(see Initialization). The DDR2 SDRAM device is now ready for normal operation after

the initialization sequence. Figure 79 (page 129) shows the proper sequence for a RE-

SET operation.

1Gb: x4, x8, x16 DDR2 SDRAM

Reset

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Figure 79: RESET Function

CKE

RTT

Bank address

High-Z

DM3

DQS3

High-Z

Address

A10

CK#

tCL

Command

NOP2PRE

All banks

Ta0

Don’t CareTransitioning Data

tRPA

tCL

tCK

ODT

DQ3

High-Z

T = 400ns (MIN)

Tb0

READ NOP2

T0 T1 T2

Col n

Bank a

tDELAY

DODO

READ NOP2

Col n

Bank b

High-Z

Unknown RTT On

System

RESET

T3 T4 T5

Start of normal

initialization

sequence

NOP2

Indicates a break in

time scale



tCKE (MIN)

Notes: 1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.

2. Either NOP or DESELECT command may be applied.

3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS

represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-

ate configuration (x4, x8, x16).

4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the

completion of the burst.

5. Initialization timing is shown in Figure 42 (page 90).

1Gb: x4, x8, x16 DDR2 SDRAM

Reset

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ODT Timing

Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been ena-

bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-

gories. ODT will operate either in synchronous mode or asynchronous mode, depend-

ing on the state of CKE. ODT can switch anytime except during self refresh mode and a

few clocks after being enabled via EMR, as shown in Figure 80 (page 131).

There are two timing categories for ODT—turn-on and turn-off. During active mode

(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,

MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in

Figure 82 (page 132).

During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)

and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),

tAONPD and tAOFPD timing parameters are applied, as shown in Figure 83 (page 133).

ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-

rameter tANPD (MIN), as shown in Figure 84 (page 133). At state T2, the ODT HIGH sig-

nal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD

(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 84 (page 133) also

shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not oc-

cur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.

ODT turn-on timing prior to entering any power-down mode is determined by the pa-

rameter tANPD, as shown in Figure 85 (page 134). At state T2, the ODT HIGH signal sat-

isfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is

satisfied, tAOND and tAON timing parameters apply. Figure 85 (page 134) also shows

the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur un-

til state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.

ODT turn-off timing after exiting any power-down mode is determined by the parame-

ter tAXPD (MIN), as shown in Figure 86 (page 135). At state Ta1, the ODT LOW signal

satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is

satisfied, tAOFD and tAOF timing parameters apply. Figure 86 (page 135) also shows the

example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.

When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply.

ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-

er-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 87

(page 136). At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting pow-

er-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing pa-

rameters apply. Figure 87 (page 136) also shows the example where tAXPD (MIN) is not

satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied,

tAONPD timing parameters apply.

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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Figure 80: ODT Timing for Entering and Exiting Power-Down Mode

tANPD (3 tCKs)

First CKE latched LOW

tAXPD (8 tCKs)

First CKE latched HIGH

Synchronous

Applicable modes

Applicable timing parameters

SynchronousSynchronous or

Asynchronous

Any mode except

self refresh mode

Any mode except

self refresh mode

Active power-down fast (synchronous)

Active power-down slow (asynchronous)

Precharge power-down (asynchronous)

tAOND/tAOFD (synchronous)

tAONPD/tAOFPD (asynchronous)

tAOND/tAOFD tAOND/tAOFD

CKE

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be

changed with an EMRS set command. tMOD (MAX) updates the RTT setting.

Figure 81: Timing for MRS Command to ODT Update Delay

CK#

ODT2

Internal

RTT setting

EMRS1NOP NOPNOP NOP NOP

Command

tMOD

Old setting Undefined New setting

0ns

tIS

tAOFD

Indicates a break in

time scale

T0 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5

Notes: 1. The LM command is directed to the mode register, which updates the information in

EMR (A6, A2), that is, RTT (nominal).

2. To prevent any impedance glitch on the channel, the following conditions must be met:

tAOFD must be met before issuing the LM command; ODT must remain LOW for the en-

tire duration of the tMOD window until tMOD is met.

Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode

T1T0 T2 T3 T4 T5 T6

Valid

Valid Valid Valid

CK#

ODT

RTT

tAOF (MAX)

tAON (MIN)

tAOND

Address

tAOFD

tAON (MAX) tAOF (MIN)

Valid

Valid Valid Valid

Command

tCH tCL

Don’t CareRTT Unknown RTT On

tCK

CKE

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes

Don’t Care

T1T0 T2 T3 T4 T5 T6

ValidValid Valid ValidValid Valid Valid

CK#

CKE

ODT

Address

ValidValid Valid ValidValid Valid Valid

Command

tCL

tAONPD (MIN)

tAONPD (MAX)

tAOFPD (MIN)

tAOFPD (MAX)

Transitioning R

Valid

Unknown R

tCK

Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode

T1T0 T2 T3 T4 T5 T6

NOPNOP NOP NOPNOP NOP NOP

CK#

Command

CKE

ODT

RTT

tAOF (MIN)

tAOF (MAX)

tAOFD

ODT

RTT

tAOFPD (MIN)

Don’t Care

Transitioning RTT RTT Unknown RTT ON

tANPD (MIN)

tAOFPD (MAX)

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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Figure 85: ODT Turn-On Timing When Entering Power-Down Mode

T1T0 T2 T3 T4 T5 T6

NOP

NOP NOP NOP

CK#

RTT

tAON (MIN)

tAON (MAX)

ODT

RTT

tAONPD (MIN)

tAONPD (MAX)

Don’t CareTransitioning RTT RTT Unknown RTT On

ODT

Command

tAOND

CKE

tANPD (MIN)

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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1GbDDR2.pdf – Rev. W 7/11 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode

Transitioning RTT

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tAXPD (MIN)

ODT

tAOF (MAX)

ODT

tAOFPD (MIN)

tAOFPD (MAX)

Command

Ta2 Ta3 Ta4 Ta5

NOP

NOP NOP NOP

Don’t Care

TT Unknown

tAOF (MIN)

Indicates a break in

time scale

TT On

tCKE (MIN)

tAOFD

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

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Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode

T1T0 T2 T3 T4 Ta0 Ta1

NOP

NOP NOP NOP

CK#

CKE

tAXPD (MIN)

Command

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP NOP

tAON (MIN)

tAON (MAX)

RTT

tAONPD (MIN)

tAONPD (MAX)

Don’t Care

RTT

Unknown

RTT

Indicates a break in

time scale

Transitioning RTT

tAOND

tCKE (MIN)

RTT

ODT

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www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

PDF: 09005aef821ae8bf

1GbDDR2.pdf – Rev. W 7/11 EN 136 Micron Technology, Inc. reserves the right to change products or specifications without notice.