1
®
FN8172.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9268
Dual Supply/Low Power/256-Tap/2-Wire Bus
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/Pot–0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
•Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current <5µA Max
•V
CC: ±2.7V to ±5.5V Operation
•50kΩ, 100kΩ Versions of End to End Pot
Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 24 Ld SOIC
• Low Power CMOS
• Power Supply VCC = ±2.7V to ±5.5V
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9268 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
R
H0
R
L0
R
W0
V
CC
V
SS
2-Wire
Bus
50k
Ω
or 100k
Ω
versions
R
H1
R
L1
R
W1
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0–DR3)
Interface
Bus
Interface
and Control
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Control
V+
V-
Data Sheet August 29, 2006
2FN8172.4
August 29, 2006
Ordering Information
PART NUMBER PART
MARKING VCC LIMITS
(V) POTENTIOMETER
ORGANIZATION (kΩ)TEMP. RANGE
(°C) PACKAGE PKG.
DWG. #
X9268TS24 X9268TS 5 ±10% 100 0 to +70 24 Ld SOIC (300mil) M24.3
X9268TS24Z (Note) X9268TS Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268TS24I X9268TS I -40 to +85 24 Ld SOIC (300mil) M24.3
X9268TS24IZ (Note) X9268TS ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268US24 X9268US 50 0 to +70 24 Ld SOIC (300mil) M24.3
X9268US24Z (Note) X9268US Z 0 to +70 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268US24I X9268US I -40 to +85 24 Ld SOIC (300mil) M24.3
X9268US24IZ (Note) X9268US ZI -40 to +85 24 Ld SOIC (300mil) (Pb-free) M24.3
X9268TS24I-2.7 X9268TS G 2.7 to 5.5 100 -40 to +85 24 Ld SOIC (300mil) M24.3
X9268TS24IZ-2.7 (Note) X9268TS ZG -40 to +85 24 Ld SOIC (300mil) (Pb-Free) M24.3
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9268
3FN8172.4
August 29, 2006
DETAILED FUNCTIONAL DIAGRAM
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage ampli-
fier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF wire-
less systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
INTERFACE
AND
CONTROL
CIRCUITRY
A0
SCL
SDA
A1
A2
WP
A3
V
CC
V
SS
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Data
8
Pot 0
Power-on
Recall
Power-on
Recall
R
H0
R
L0
R
W0
R
H1
R
L1
R
W1
256-taps
50k
Ω
and 100k
Ω
V+
V-
X9268
4FN8172.4
August 29, 2006
PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(SOIC) Symbol Function
1 NC No Connect
2 A0 Device Address for 2-Wire bus.
3 NC No Connect
4 NC No Connect
5 NC No Connect
6 V+ Analog Suppy Pin (Positive)
7V
CC System Supply Voltage
8R
L0 Low Terminal for Potentiometer 0.
9R
H0 High Terminal for Potentiometer 0.
10 RW0 Wiper Terminal for Potentiometer 0.
11 A2 Device Address for 2-Wire bus.
12 WP Hardware Write Protect
13 SDA Serial Data Input/Output for 2-Wire bus.
14 A1 Device Address for 2-Wire bus.
15 RL1 Low Terminal for Potentiometer 1.
16 RH1 High Terminal for Potentiometer 1.
17 RW1 Wiper Terminal for Potentiometer 1.
18 VSS System Ground
19 V- Analog Supply Pin (Negative)
20 NC No Connect
21 NC No Connect
22 NC No Connect
23 SCL Serial Clock for 2-Wire bus.
24 A3 Device Address for 2-Wire bus.
NC
A0
NC
V+
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
SCL
NC
NC
NC
V-
VSS
RW1
RH1
RL1
24 LD SOIC
X9268
NC
14
13
11
12
NC
RH0
RW0
A2 A1
SDA
WP
X9268
5FN8172.4
August 29, 2006
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9268.
DEVICE ADDRESS (A3 - A0)
The address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9268. A maximum of 8 devices may occupy the
2-Wire serial bus.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of RH and
RL such that RH0 and RL0 are the terminals of POT 0
and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of RW such that RW0
is the terminal of POT 0 and so on.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Analog Supply Voltages (V+ and V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
X9268
6FN8172.4
August 29, 2006
PRINCIPLES OF OPERATION
The X9268 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description.
Array Description
The X9268 is comprised of a resistor array (See
Figure 1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power-up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, VCC, V+, and V- must reach their
final values within 1msecs of each other. The VCC
ramp rate spec is always in effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCL
UP/DN
RH
RL
RW
8 8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
WIPER
(WCR)
One of Two Potentiometers
(DR0) (DR1)
(DR2) (DR3)
X9268
7FN8172.4
August 29, 2006
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9268 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9268 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9268 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9268 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9268 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9268 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
DATA
OUTPUT
FROM
TRANSMITTER
189
DATA
OUTPUT
FROM
RECEIVER
START ACKNOWLEDGE
X9268
8FN8172.4
August 29, 2006
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9268
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9268 is still busy with the write operation no ACK
will be returned. If the X9268 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
INSTRUCTION AND REGISTER DESCRIPTION
Instructions
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9268 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9268; this is fixed
as 0101[B] (refer to Table 1).
The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9268
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9268 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
INSTRUCTION BYTE (I)
The next byte sent to the X9268 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.
Register Selection
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
No
Yes
Yes
Proceed
Issue STOP
No
Proceed
Register Selected RB RA
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
X9268
9FN8172.4
August 29, 2006
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3 I2 I1 I0 RB RA 0 P0
Read Wiper Counter
Register
100100 01/0Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter Register 101000 01/0Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register 10111/01/001/0Read the contents of the Data Register
pointed to by P0 and RB - RA
Write Data Register 11001/01/001/0Write new value to the Data Register
pointed to by P0 and RB - RA
XFR Data Register to Wiper
Counter Register
11011/01/001/0Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter Register
to Data Register
11101/01/001/0Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers
00011/01/00 0Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
10001/01/00 0Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Increment/Decrement Wiper
Counter Register
001000 01/0Enable Increment/decrement of the Control
Latch pointed to by P0
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier Slave Address
I3 I2 I1 I0 RB RA 0 P0
(MSB) (LSB)
Instruction Register Pot Selection
Opcode Selection (WCR Selection)
Data
X9268
10 FN8172.4
August 29, 2006
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9268 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9268 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR (See
Design Considerations Section).
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
X9268
11 FN8172.4
August 29, 2006
DEVICE DESCRIPTION
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
–Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
–Read Data Register – read the contents of the
selected Data Register;
–Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register
Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9268; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
–XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
–Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.
–Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9268 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
See Instruction format for more details.
X9268
12 FN8172.4
August 29, 2006
Figure 3. Two-Byte Instruction Sequence
Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
S
T
A
R
T
0101
A2 A0 A
C
K
I2 I1 I0 RB RA 0 A
C
K
SCL
SDA
S
T
O
P
ID3 ID2 ID1 ID0 P0
Device ID Internal Instruction
Opcode
Address Register
Address
Pot/WCR
Address
A1
A3 I3
I3 I2 I1 I0 RB RA
ID3 ID2
ID1
ID0
Device ID Internal Instruction
Opcode
Address Register
Address
Pot/WCR
Address
WCR[7:0]
or
Data Register D[7:0]
S
T
A
R
T
0101
A2 A1 A0 A
C
K
0P0A
C
K
SCL
SDA
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A3
0
I3 I2 I1 I0
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address
Register
Address Pot/WCR
Address
S
T
A
R
T
0101
A2 A1 A0 A
C
K
RA 0 P0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
RB
A3
0
SCL
SDA
RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
X9268
13 FN8172.4
August 29, 2006
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by X9268 on SDA) M
A
C
K
S
T
O
P
0101A3A2A1A0 100100 0 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
0101A3A2A1A0 101000 0 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by X9268 on SDA) M
A
C
K
S
T
O
P
0101A3A2A1A0 1011RBRA 0 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A3A2A1A0 1100RBRA0 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0 0 0 0 1 RB RA 0 0
X9268
14 FN8172.4
August 29, 2006
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counter Register (WCR)
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1A3A2A1A0 1000RBRA00
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1A3A2A1A0 1110RBRA 0 P0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0 1 1 0 1 RB RA 0 P0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/WCR
Addresses S
A
C
K
Increment/Decrement
(Sent by Master on SDA) S
T
O
P
0101A3A2A1A0 001000 0 P0 I/DI/D. . . .I/DI/D
X9268
15 FN8172.4
August 29, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address input
with respect to VSS ................................. -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) ..............................................................12V
Any VH/RH..............................................................V+
Any VL/RL.................................................................V-
Lead temperature (soldering, 10s) .................. +300°C
IW (10s) ..............................................................±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH - RL) / 255, single pot
(4) During power-up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC)(4) Limits
X9268 5V ±10%
X9268-2.7 2.7V to 5.5V
V+ 2.7V to 5.5V
V- -2.7V to -5.5V
Symbol Parameter Test Conditions Min. Typ. Max. Unit
RTOTAL End to End Resistance T version 100 kΩ
RTOTAL End to EndResistance U version 50 kΩ
End to end resistance tolerance ±20 %
Power rating +25°C, each pot 50 mW
IW Wiper current ±3 mA
RWWiper resistance IW = ± 1mA, V+ = 3V; V- = -3V 250 Ω
RWWiper resistance IW = ± 1mA, V+ = 5V; V- = -5V 150 Ω
V+ Voltage on V+ Pin X9268 +4.5 +5.5 V
X9268-2.7 +2.7 +5.5
V- Voltage on V- Pin X9268 -5.5 -4.5 V
X9268 -2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL pin V- V+ V
Noise Ref: 1kHz -120 dBV
Resolution (4) 0.4 %
Absolute linearity (1) Vw(n)(actual) - Vw(n)(expected) ±1 MI(3)
Relative linearity (2) Vw(n + 1) - [Vw(n) + MI]±0.6MI
(3)
Temperature coefficient of resistance ±300 ppm/°C
Ratiometric Temperature Coefficient ±20 ppm/°C
CH/CL/CWPotentiometer Capacitance See Circuit #3 10/10/25 pF
X9268
16 FN8172.4
August 29, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
Symbol Parameter Test Conditions Min. Typ. Max. Units
ICC1 VCC supply current
(active)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
3mA
ICC2 VCC supply current
(nonvolatile write)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
5mA
ISB VCC current (standby) VCC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby State only)
5µA
ILI Input leakage current VIN = VSS to VCC 10 µA
ILO Output leakage current VOUT = VSS to VCC 10 µA
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage -1 VCC x 0.3 V
VOL Output LOW voltage IOL = 3mA 0.4 V
VOH Output HIGH voltage
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
CIN/OUT(6) Input / Output capacitance (SDA) 8 pF VOUT = 0V
CIN(6) Input capacitance (SCL, WP, A3, A2, A1 and A0)6 pF V
IN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up rate 0.2 50 V/ms
tPUR(7) Power-up to initiation of read operation 1 ms
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9268
17 FN8172.4
August 29, 2006
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Symbol Parameter Min. Max. Units
fSCL Clock Frequency 400 kHz
tCYC Clock Cycle Time 2500 ns
tHIGH Clock High Time 600 ns
tLOW Clock Low Time 1300 ns
tSU:STA Start Setup Time 600 ns
tHD:STA Start Hold Time 600 ns
tSU:STO Stop Setup Time 600 ns
tSU:DAT SDA Data Input Setup Time 100 ns
tHD:DAT SDA Data Input Hold Time 30 ns
tRSCL and SDA Rise Time 300 ns
tF SCL and SDA Fall Time 300 ns
tAA SCL Low to SDA Data Output Valid Time 0.9 µs
tDH SDA Data Output Hold Time 0 ns
TINoise Suppression Time Constant at SCL and SDA inputs 50 ns
tBUF Bus Free Time (Prior to Any Transmission) 1200 ns
tSU:WPA A0, A1 Setup Time 0 ns
tHD:WPA A0, A1 Hold Time 0 ns
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs
5V
1533
Ω
100pF
SDA pin
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macromodel
3V
867
Ω
100pF
SDA pin
X9268
18 FN8172.4
August 29, 2006
TIMING DIAGRAMS
Start and Stop Timing
Input Timing
Output Timing
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9268
19 FN8172.4
August 29, 2006
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
SCL
SDA
VWx
(STOP)
LSB
tWRL
SDA
SCL ...
...
...
WP
A0, A1
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9268
20 FN8172.4
August 29, 2006
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9268
21 FN8172.4
August 29, 2006
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9268
22
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8172.4
August 29, 2006
X9268
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0° 8° 0° 8° -
Rev. 1 4/06
