ee FAIRCHILD ee SEMICONDUCTOR m www .fairchildsemi.com TMC1175A/TMC1275 Video A/D Converter 8 bit, 50 Msps Features * 8-Bit resolution 50 Msps conversion rate Low power: 100mW at 20 Msps * Integral track/hold * Integral and differential linearity error 0.5 LSB Single or dual +5 Volt supplies * Differential phase 0.5 degree Differential gain 1.5% * Three-state TTL/CMOS-compatible outputs Low cost Applications Video digitizing * VGA and CCD digitizing LCD projection panels * Image scanners * Personal computer video boards * Multimedia systems * Low cost, high speed data conversion Block Diagram VIN VR+ Rt VR- CONV Description The TMC1175A/1275 analog-to-digital (A/D) converter employs a two-step flash architecture to convert analog signals into 8-bit digital words at sample rates of up to 50 Msps (Megasamples per second). An integral Track/Hold circuit delivers excellent performance on signals with full- scale frequency components up to 12 MHz. Innovative archi- tecture and submicron CMOS technology limit typical power dissipation to 100 mW. Power may be derived from either single or dual +5V supplies. Internal voltage reference resistors allow self-bias operation. Input capacitance is very low, simplifying or eliminating input driving amplifiers. All digital three-state outputs are TTL- and CMOS-compatible. The TMC1175A and TMC1275 share their core architec- tures; the TMC1275 adds two overrange outputs that indicate when the analog input signal is beyond the conversion range. The TMC1175A/1275 is available in 24-pin plastic DIP, 24-lead plastic SOIC, and 28-lead J-lead PLCC packages. Performance specifications are guaranteed from -20C to 75C, Digital ORP Error- Dz.9 Corrector ORN* OE TMG1275 Only 2AASSA Rev. 1.2.0TMC1175A/TMC1275 PRODUCT SPECIFICATION Functional Description The TMC1175A/1275 8-bit A/D converter uses a two-step architecture to perform analog-to-digital conversion at rates up to 50 Msps. The input signal is held in an integral track/ hold stage during the conversion process. Operation is pipe- lined, with one input sample taken and one output word pro- vided for each CONVert cycle. The first step in the conversion process is a coarse 4-bit quantization. This determines the range of the subsequent fine 4-bit quantization step. To eliminate spurious codes, the fine 4-bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse result to form a complete 8-bit result. Analog Input and Voltage References The TMC1175A/1275 converts analog signals in the range RB to RT into digital data. Input signals outside that range produce saturated 00h or FFh output codes. The device will not be damaged by signals within the range AGND to VDDA. The A/D converter input range is very flexible and extends from the +5 Volt power supply to ground. The nominal input range is 2 Volts, from 0.6V to 2.6V. The circuit is character- ized and performance is specified over that range. However, the part will work well with a full-scale range from 1.0V to 5.0V. A reduced input range may simplify analog signal con- ditioning circuitry, at the expense of additional noise sensitivity and some reduced differential linearity perfor- mance. Similarly, increasing the range can improve differen- tial linearity, but puts a greater burden on the input signal conditioning circuitry. In many applications, external voltage reference sources are connected to the Rr and Rp pins. Rp can be grounded. Gain and offset errors are directly related to the accuracy and stability of the applied reference voltages. Two reference pull-up and pull-down resistors connected to VR+ and VR- are provided internally for operation without external voltage reference circuitry (Figure 1). The reference voltages applied to RT and Rp may be generated by connect- ing VR+ to Rp and VR- to Rp. The power supply voltage is divided by the on-chip resistors to bias the Rr and Rg points. This sets-up the converter for operation in its nominal range from 0.6V to 2.6V. VDDA t R+ 3240 RREF 2700 R- 812 | 27010A Figure 1. Reference Resistors With VpDa at 5.0V, connecting VR+ to RT and grounding Rp will provide an input range from 0.0V to 2.27V, while connecting RT to Vp pa and Rp to VR- produces a full scale range of 3.85V referenced to Vppa. External resistors may also be employed to provide arbitrary reference voltages, but they will not match the temperature coefficient of the on- chip resistors as well as R+ and R-, and will cause the con- verter transfer function to vary with temperature. With this implementation, errors in the power supply voltage end up on the conversion data output. Because a two-step conversion process is employed, it is important that the references remain stable during the ENTIRE conversion process (two clock cycles). The refer- ence voltage can then be changed, but any conversion in progress during a reference change is invalid.PRODUCT SPECIFICATION TMC1175A/TMC1275 Table 1. Output Coding Input Voltage ORP* ORN* Output RT+1 LSB 1 0 FF RT 0 0 FF RT-1LSB 0 0 FE Rea +128 LSB 0 0 80 Re+127 LSB 0 0 7F RB+1LSB 0 0 o1 RB 0 0 00 RB-1LSB 0 1 00 Notes: 1. LSB = (RTRep) /255 2. TMC1275 Only Digital Inputs and Outputs Sampling of the applied input signal takes place on the fall- ing edge of the CONY signal (Figure 2). The output word is delayed by ? 1/2 CONV cycles. It is then available after the rising edge of CONV. The previous data on the output remain valid for to (Output Hold Time), satisfying any hold time requirement of the receiving circuit. The new data become valid too (Output Delay Time) after this rising edge of CONV. Sample N tuo * Sample N+1 Whenever the analog input signal is sampled and found to be at a level beyond the A/D conversion range, an Overrange output of the TMC1275 will go HIGH. If the input is more positive (by at least one LSB) than the positive end of the range, ORP will go HIGH and D7-9 will be FFh. If the input is more negative (by at least one LSB) than the negative end of the range, ORN will go HIGH and D7-9 will be OOh. The outputs of the TMC1175A/1275 are CMOS- and TTL-compatible, and are capable of driving four low-power Schottky TTL (54/74LS) loads. An Output Enable control, OE, places the outputs in a high-impedance state when HIGH. The outputs are enabled when OF is LOW. Power and Ground To minimize noise injection into the analog section, VDDA may be connected to a separate regulated +5 volt supply. VDDD may be connected to a digital supply. Power up sequence is immaterial. Latch-up will not occur. AGND and DGND pins should be connected to a common ground plane. For optimum performance treat analog and digital PWE traces as transmission lines. Route analog con- nections cleanly to the TMC1175A4/1275. Segregate digital connections and if necessary terminate clocks to eliminate ringing. Prevent digital returm currents from flowing across analog input sections of the TMC1175A/1275. Sample N+3 Data N-3 S| * D7.9 ORP ORN Data N-2 Hi-Z Data N1 Data N tENA 24455A Figure 2. Conversion TimingTMC1175A/TMC1275 Analog input External Clock Upper comparators block Upper data Lower reference voltage Lower comparators A block Lower data A Lower comparators B block Lower data B Digital output Pin Assignments V2) (3) PRODUCT SPECIFICATION v(4) _I | | Isa] ci) s@ | c@] s@] c@] sa) cw XM (0) MD) KX MDE) K MDX XR) x AVG) K RV) XK ORV) 1Say) H(t) | ccty] $03) H (3) | 643)| xX LD (4) xX LD (1) x Ho) | C(O) | $2] H@) | C(2)] S(4)) H(4) Ly-2) OK LD(0) XK LD2) x Out-2) XK Out) KX ouwoy Kutt) K Figure 3. Internal Timing SE id 11 24 Denp Do 3 [] 22 R- D, 4 Q 1] 21 Agenp VR- 26 Do 50 1] 20 Agno Rp 27 DB, 6 ri 19 Vin Denp 28 Dy 7 OC 1118 Vppa NC 4 Ds 8 17 Ry OE 2 Dg 9 (116 VR+ Deno 3 D> io O 115 ORNAppae Do 4 Vopp 114 ri 14 ORPMippae CONV 12 0 11 13 Vppp N2 Package M7? Package 1] 25 AGND 1) 24 AGND i 23 Vi_ i 22 NG 21 VDDA 119 VR+ Fe lean ealeneoal a a a Di 6q D2 6f b3 7] we 8 D4 af R3 Package Ds 10] D6 111 18 V7 16 15 14 13 12 65-7568 ORN/V1 pDA2 ORP/MiDDA2 Vppp N/G CONV Vppp Dz 1TMC1275 2TMC1175A 2445448,PRODUCT SPECIFICATION TMC1175A/TMC1275 Pin Descriptions Pin Number Pin Name | N2, M7 | R3 = =|Pin Type} Pin Function Description Inputs VIN 19 23 RT- RB} Analog Input. The input voltage conversion range lies between the voltages applied to the RT and RB pins. RT 17 20 2.6V | Reference Voltage Top Input. RT is the top input to the reference resistor ladder. A DC voltage applied to RT defines the positive end of the VIN conversion range. RB 23 27 0.6V | Reference Voltage Bottom Input. Rp is the bottom input to the reference resistor ladder. A DC voltage applied to Rp defines the negative end of the VIN conversion range. VR+ 16 19 Reference Voltage Top Source. VR+ is the internal pull-up reference resistor for self-bias operations. VR- 22 26 Reference Voltage Bottom Source. VR- is the internal pull-down reference resistor for self-bias operations. OE 1 2 CMOS | Output Enable. (CMOS-compatible} When LOW, D7-0 are enabled. When HIGH, D7-0 are in a high-impedance state. CONV 12 14 CMOS | Convert (Clock) Input. (CMOS-compatible) Vin is sampled on the falling edge of CONV. Outputs D7-0 10-3 12-9, | CMOS/ | Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible 7-4 TTL | digital outputs. Data is output following the rising edge of CONV, ORP" 14! 17 | CMOS/ | OverRange Positive Output. When HIGH, ORP indicates that the TTL analog input voltage is at least one LSB higher than the voltage that produces output code FFh. OFP is synchronous with D7-0. ORN' 15! 18' | CMOS/ | OverRange Negative Output. When HIGH, ORN indicates that the TTL | analog input voltage is at least one LSB lower than the voltage that produces output code 00h. ORN is synchronous with D7-0. Power VDDA 14 15, |17,18, | +5V Analog Supply Voltage. Independent +5 volt power connection to 18 21 analog comparator circuits. VDDD 11,13 13,16 +5V Digital Supply Voltage. Independent +5 volt power connection to digital error correction and output drivers. AGND 20, 21 24,25 0.0V | Analog Ground. Connect to the system analog ground plane. DGND 2, 24 3, 28 0.0V | Digital Ground. Connect to the system analog ground plane. No Connect N/G 1,8,15,| open Not Connected. 22 Notes: 1. TMC1275 Only. 2. TMC1175A Only.TMC1175A/TMC1275 PRODUCT SPECIFICATION Bandwidth Specification Notes The specification for bandwidth of an A/D converter is some- what different from the normal frequency-response specifi- cation used in amplifiers and filters. An understanding of the differences will help in selecting converters properly for par- ticular applications. A/D conversion comprises two distinct processes: sampling and quantizing. Sampling is grabbing a snapshot of the input signal and holding it steady for quantizing. The guan- tizing process is approximating the analog input, which may be any value within the conversion range, with its nearest numerical value. While sampling is a high-frequency pro- cess, quantizing operates on a dc signal, held steady by the track/hold circuit. Therefore, the sampling process is what relates to the dynamic characteristics of the converter. Sampling involves an aperture time, the time during which the track/hold is trying to capture the input signal and settle ona de value to hold. It is analogous to the shutter speed of a camera: the shorter the aperture (or faster the shutter) the less the signal will be blurred, and the less uncertainty there will be in the quantized value. For example, a 10 MHz sinewave with a 1V peak amplitude (2Vp-p) has a maximum slew rate of 27fA at zero crossing, or 62.8V/us. With an 8-bit A/D converter, q (the quantization step size) = 2V/255 = 7.8mV. The input signal will slew one LSB in 124ps. To limit the error (and noise) contribution due to aperture effects to 1/2LSB, the aperture must be shorter than 62ps. This is the primary reason that the signal to noise ratio drops off as full scale frequency increases. Note, also, that the slew rate is directly proportional to signal amplitude, A. A/Ds will handle lower-amplitude signals of higher bandwidth. All this is of particular interest in applications such as digi- tizing analog VGA RGB signals, or the output of a CCD imaging chip. These data are effectively pre-sampled: there is a period of rapid slewing from one pixel value to another, followed by a relatively stable dc level before the signal slews to the next pixel value. The goal is, of course, to sam- ple on these pixel values, not on the slewing between pixels. During the aperture time, the A/D sees essentially a dc sig- nal, and classic bandwidth considerations are not important. As long as the input circuit can slew and settle to the new value in the prescribed period, an accurate conversion will be made. The TMC1175A/1275 is capable of slewing a full 2V and settling between samples taken as little as 25ns apart, mak- ing it ideal for digitizing analog VGA and CCD outputs. Equivalent Circuits and Threshold Level Q Yop A ep Data or t, Gontrel + Input I Ae 4 = GND 270148 Figure 4. Equivalent Digital Input Circuit OQ pp al +) Output t "A it _L 27011B GND Figure 5. Equivalent Digital Output CircuitPRODUCT SPECIFICATION TMC1175A/TMC1275 VDDA VIN AenD = eee iD iD i io iD 27052A, Figure 6. Equivalent Analog Input Circuit Absolute Maximum Ratings (beyond which the device may be damaged) OE Three-State Outputs Fe a A 0.5V ~t High Impedance | (\ 0.5V _____ fH 2.0V 40.8 65-1175A-07 Figure 7. Threshold Levels for Three-State Measurements Parameter | Conditions Min | Typ | Max Unit Power Supply Voltages VDDA Measured to AGND -0.5 7.0 Vv VDDD Measured to DGND -0.5 7.0 VDDA Measured to VoDD -05 0.5 Vv AGND Measured to DGND -0.5 05 Digital Inputs Applied Voltage* Measured to DGND 05 Vbbb + 0.5 Vv Forced Current* -10.0 10.0 mA Analog Inputs Applied Voltage Measured to AGND -05 VDDA+O05/ V Forced Current* -10.0 10.0 mA Outputs Applied Voltage* Measured to DGND -0.5 Vpbpb + 0.5 V Forced Current* -6.0 6.0 mA Short Circuit Duration Single output in HIGH state te ground 1 sec Temperature Operating, Ambient -20 110 C Junction 150 C Storage -65 150 C Lead Soldering 10 seconds 300 C Vapor Phase Soldering 1 minute 220 C Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. 2. Applied voltage must be current limited to specified range. Forcing voltage must be limited to specified range. wo 4. Current is specified as conventional current flowing into the deviceTMC1175A/TMC1275 PRODUCT SPECIFICATION Operating Conditions Parameter Min Nom Max Units VDDD Digital Power Supply Voltage 4.75 5.0 5.25 V VDDA Analog Power Supply Voltage 4.75 5.0 5.25 Vv AGND Analog Ground (Measured to -0.1 0 0.1 V DGND)} fs Conversion Rate TMG1175A/1275-20 20 Msps TMG1175A/1 275-30 30 Msps TMG1175A/1275-40 40 Msps TMG1175A/1275-50 50 Msps tPWH CONV Pulsewidth, HIGH TMG1175A/1275-20 15 ns TMG1175A/1275-30 13 ns TMG1175A/1275-40 12 ns TMG1175A/1275-50 g ns tPWL CONV Pulsewidth, LOW TMG1175A/1275-20 15 ns TMG1175A/1 275-30 12 ns TMG1175A/1275-40 12 ns TMG1175A/1275-50 g ns VAT Reference Voltage, Top 2.0 2.6 VDDA Vv VRB Reference Voltage, Bottom 0 06 3.0 V VaAT-VRB | Reference Voltage Differential 1.0 5.0 V VIN Analog Input Range VAB VAT V VIH Input Voltage, Logic HIGH 07x VDDD V VDDD VIL Input Voltage, Logic LOW GND 0.3x Vv VDDD IOH Output Current, Logic HIGH -4.0 mA OL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air -20 75 C Electrical Characteristics Parameter Conditions Min Typ | Max | Units IDD Power Supply Current VppD = VDDA = Max, CLOAD = 35pF fs = 20Msps 20 30 mA fs = 30Msps 25 35 mA fs = 40Msps 30 40 mA fs = 50Msps 35 48 mA IDDQ | Power Supply Current, VDDD = VDDA = Max Quiescent CONV = LOW 7 | 18 | mA CONV = HIGH 10 20 mAPRODUCT SPECIFICATION TMC1175A/TMC1275 Electrical Characteristics (continued) Parameter Conditions Min Typ | Max | Units Pp Total Power Dissipation VDDD = VDDA = Max, CLOAD = 35pF fs = 20Msps 100 160 | mW fg = 30Msps 125 185 mW fs = 40Msps 150 210 | mW f = 50Msps 185 | 250 | mW Cal Input Capacitance, Analog CONV = LOW 4 pF CONV = HIGH 12 pF RIN Input Resistance 500 1000 kQ IoB Input Current, Analog +1 pA RREF | Reference Resistance 200 270 | 340 Q lH Input Current, HIGH VbDbDbD = Max, VIN = VDDD +5 pA IIL Input Current, LOW VDDD = Max, VIN = 0V +5 LA lozH | Hi-Z Output Leakage Vppp = Max, VIN = VDDD +5 LA lozL | Hi-Z Output Leakage VDDD = Max, VIN =0V +8 LA los Short-Circuit Current -30 mA VOH Output Voltage, HIGH IOH = -100pA Vppp-0.3 Vv IOH =-2.5mA 3.5 V IOH = Max 24 Vv VoL | Output Voltage, LOW loL = Max 04 Vv Cpl Digital Input Gapacitance 4 10 pF Cpe _ | Digital Output Capacitance 10 pF Note: 1. Typical values with VDDD = VODA = Nomand Ta = Nom, Minimum/Maximum values with VDDD = VDDA = Max and Ta = Min. Switching Characteristics Parameter Conditions Min Typ Max Units tsTto | Sampling Time Offset 2 5 8 ns tHO Output Hold Time CLOAD = 15pF 5 ns tbo Output Delay Time CLOAD = 15pF 20 ns tENA | Output Enable Time 27 ns {DIS Output Disable Time 42 nsTMC1175A/TMC1275 PRODUCT SPECIFICATION System Performance Characteristics Parameter Conditions Min | Typ | Max | Units ELI Integral Linearity Error, VRT =2.6V +0.5 | +1 LSB Independent VRB =0.6V ELD Differential Linearity Error | VRT =2.6V +0.3 | +1 | LSB VAB =0.6V BW Bandwidth TMG1178A/1275-20 10 | MHz TMC1175A/1275-30 12 | MHz TMC1175A/1275-40 12 | MHz TMG1175A/1275-50 12 | MHz EAP Aperture Error 30 ps EOT Offset Voltage, Top RT VIN for most positive code transition -8 -25 | -42 | mV Eos Offset Voltage, Bottom RB VIN for most negative code transition 30 40 60 mV dg Differential Gain fg = 14.3Msps 15 | 27 % NTSG 40 IRE Mod Ramp VDDA = +6.0V, TA=25C VAT =2.6V, VRB =0.6V dp Differential Phase fg = 14.3Msps 0.5 1.0 | deg NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25C VAT = 2.6V, VRB =0.6V SNR | Signal-to-Noise Ratio f = 20Msps, VAT = 2.6V, VRB = 0.6V fIN = 1.24MHz 44 48 dB fIN = 2.48MHz 43 47 dB fIN = 6.98MHz 41 45 dB fIN = 10.0MHz 37 42 dB fg = 30Msps, VAT = 2.6V, VRB = 0.6V fIN = 1.24MHz 42 47 dB fIN = 2.48MHz 40 45 dB fIN = 6.98MHz 38 43 dB fil = 10.0MHz 33 39 dB fIN = 12.0MHz 30 37 dB fs = 40Msps, VAT = 2.6V, VRB = 0.6V fIN = 1.24MHz 40 45 dB fIN = 2.48MHz 38 43 dB fIN = 6.98MHz 36 Al dB fiN = 10.0MHz 34 38 dB fIN = 12.0MHz 32 36 dB fg = 50Msps, VAT = 2.6V, VRB = 0.6V fIN = 10.0MHz 30 dB 10PRODUCT SPECIFICATION TMC1175A/TMC1275 System Performance Characteristics (continued) Parameter Conditions Min Typ! Max | Units SFDR4 Spurious-Free Dynamic fg = 20Msps, VAT = 2.6V, VRB = 0.6V Range flN = 1.24MHz 46 | 52 dB fIN = 2.48MHz 44 51 dB fIN = 6.98MHz 41 45 dB fIN = 10.0MHz 38 43 dB fg = 30Msps, VAT =2.6V, VRB = 0.6V fIN = 1.24MHz 42 49 dB fIN = 2.48MHz 40 45 dB fiN = 6.98MHz 37 41 dB fIN = 10.0MHz 35 40 dB fiN = 12.0MHz 34 39 dB fs = 40Msps, VAT = 2.6V, VRB = 0.6V fIN = 1.24MHz 40 44 dB fIN = 2.48MHz 39 43 dB fIN = 6.98MHz 38 41 dB fIN = 10.0MHz 36 40 dB fIN = 12.0MHz 36 39 dB fs = 50Msps, VRT = 2.6V, VRB = 0.6V fIN = 10.0MHz 33 dB Notes: 1. Values shown in Typ column are typical for VDDD = VDDA = +5V and TA = 25C. 2. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 11TMC1175A/TMC1275 PRODUCT SPECIFICATION Typical Performance Characteristics 0 190 20 30 40 Figure 8. Typical Ipp vs fs 30 5 io z a 20 4 ts = 20 Msps se--ts = 30 Msps 404 itg = 40 Msps 0 T T T T T 1 a 2 4 6 3 10 12 Figure 10. Typical SNR vs fin and fs Applications Discussion The circuit in Figure 12 employs a band-gap reference to generate a variable RT reference voltages for the TMC1175A/1275 as well as a bias voltage to offset the wideband input amplifier to mid-range. An "offset adjust is also shown for varying the mid-range voltage level. The operational amplifier in the reference circuitry is a standard 741-type. The voltage reference at Rr can be adjusted from 0.0 to 2.4 volts while Rp is grounded. Diodes are used to restrict the wideband amplifier output to between -0.7V and Vpp +0.7V. Diode protection is good practice to limit the analog input voltage at VIN to the safe operating range. 605 304 rm a 20 4 tg = 20 Msps ----1t5 = 30 Msps itg = 40 Msps 105 Qa 1 t 1 1 1 1 0 2 4 6 3 10 12 Figure 9. Typical SFDR vs fin and fs 507 40 4 30 4 or = a 20 ts = 20 Msps ----1fs = 33 Msps 105 0 T T T T T T T t 0 0.5 1.0 1.5 2.0 25 3.0 3.5 40 Figure 11. Typical SNR vs Full Scale Input Range The circuit in Figure 13 shows self-bias of RT and Rg by connection to VR+ and VR-. This sets up a 0.6 to 2.6 Volt input range for VIN. The input range is susceptible to power supply variation since the voltages on Rr and Rp are directly derived from Vppa. The video input is AC-coupled and biased at a adjustable midpoint of the A/D input range. This circuit offers the advantage of minimum support circuitry for the most cost-sensitive applications. In Figure 14, an external band-gap reference sets RT to +1.2 Volts while Rp is grounded. The internal pull-up resistor, R4+, provides the bias current for the band-gap reference. The A/D converter input is biased to the mid-point of the input range. 12PRODUCT SPECIFICATION TMC1175A/TMC1275 Regulated +5V +5V O.1pF 0.1,F YppA DDD Otfsei Adjust VR+ ORP* -/}> tT RT ORN* -}> = = 2ko 0.1pF TMC1175A > TMC1275 tt. > O.THF 10kQ 5 O70 Wideband tpn 47ur Lop. amp __ Video c VIN OE }+ Input a CONV }# *TMC1275 Only oe Agnd _DGNnD v Vv 27056A Figure 12. Typical Interface Circuit - High Performance Grounding The TMC1175A/1275 has separate analog and digital circuits. To keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDbDD and Vppa) originate from separate sources with VbDDa regulated, and that ground connections (DGND and AGND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1175A/1275 should be referred to the system digital ground plane. Printed Circuit Board Layout Designing with high performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option, even for breadboarding. Overall system per- formance is strongly influenced by the board layout. Capac- itive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VIN, RT, Rp, VR+, VR-) as short as possible and as far as possible from all digital signals. The TMC1175A/1275 should be located near the board edge, close to the analog input connectors. 2. The power plane for the TMC1175A/1275 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the Vpp pins. If the power supply for the TMC1175A/ 1275 is the same as that of the system's digital cir- cuitry, power to the TMC1175A4/1275 should be decou- pled with ferrite beads and 0.1pF capacitors to reduce noise. v v Offset DDA VDDD Adjust 45V VR oRP* - RT ORN' [* TMC1175A TMC1275 RB bo vR- OE }+ VIN CONV }# 10nF A D oy *TMC1275 Only PAASBA Figure 13. Typical Interface Circuit -Low Cost VDDA VDDD VR+ ORP* [|-} . Ry ORN* | LM385 =oipe | TMe175A ae TMC1275 1ka = AB do > sf 10uF _ OE + Mout VIN CONV fa AcnD DenD *TMC12750nly v u 2AASTA Figure 14. Typical Interface Circuit Stabilized Reference 13TMC1175A/TMC1275 PRODUCT SPECIFICATION The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. Decoupling capacitors should be applied liberally to Vpp pins. Remember that not all power supply pins are created equal. They supply different circuits on the inte- grated circuit, each of which generate varying amounts and types of noise. For best results, use O.1uF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1175A/ 1275, the voltage reference, or the analog inputs. Capac- itive coupling of digital power supply noise from this layer to the TMC1175A/1275 and its related analog cit- cuitry can have an adverse effect on performance. 6. CONV should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line at the CONV input, if required, to eliminate overshoot and ringing. Evaluation Board An evaluation board is available that implements good inter- face practices and provide a convenient testbed for develop- ing system applications and circuit variations. An on-board D/A converter is provided to reconstruct the digitized signal and to evaluate converter performance. Contact your sales representative for information. 14PRODUCT SPECIFICATION TMC1175A/TMC1275 Notes: 15TMC1175A/TMC1275 PRODUCT SPECIFICATION Notes: 16PRODUCT SPECIFICATION TMC1175A/TMC1275 Mechanical Dimensions 24 Lead SOIC (5.4 mm) Package Inches Millimeters Symbol Notes Min. Max. Min. Max. A .O67 075 1.70 1.90 Al 004 O12 0.10 0.31 B 014 020 0.36 0.51 Cc .006 012 0.15 0.30 B -587 .610 14.90 15.50 E .205 220 5.20 5.60 E1 .295 319 7.50 8.10 @ .050 BSC 1.27 BSG h .010 .020 0.25 0.50 L .016 .O50 0.41 1.27 N 24 24 ae o 8 0 8 ccc - 604 - 0.10 24 HE HHHHEE HEY 13 12 fog E See 1 SEATING PLANE LEAD COPLANARITY 17TMC1175A/TMC1275 PRODUCT SPECIFICATION Mechanical Dimensions (continued) 24 Lead Plastic DIP .300" Package Inches Millimeters Symbol Notes Min. Max. Min. Max. A _ 210 5.33 Ad 15 38 A2 115 195 2.53 4.95 B 14 022 36 56 Bi 045 .070 1.14 1.78 c .008 O15 20 38 4 D 1.125 1.275 28.58 32,39 2 D1 .005 43 E .300 25 *.62 8.26 Ei P40 .280 6.10 7.4 2 e .100 BSC 2.54 BSC eB _ 430 _ 10.9? L 115 160 2.9? 4.06 N a4 24 5 Aw AA A BAB | ' Lviv irr rery yy, t . pe ____ nee Notes: 1. 2. Dimensioning and tolerancing per ANSI 14.5M-1982. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall nol exceed .010 inch (0.25mm). Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is ihe maximum number of terminals.PRODUCT SPECIFICATION TMC1175A/TMC1275 Mechanical Dimensions (continued) 28 Lead PLCC Package Inches Millimeters Notes: Symbol Notes 1. All dimensions and tolerances conform to ANSI 14.5M-1982 Min. Max. Min. Max. 2. Gorner and edge chamfer (J) = 45 A 165 180 A419 A457 3. Dimension D1 and E1 do not include mald protrusion. Allowable Al 090 120 2.29 3.05 protrusion is .101" (25mm) Ae 020 31 _ B 013 021 33 53 Bi 026 032 .66 81 D/E A85 A495 12.32 12.57 DI/E1 450 456 11.43 41.58 3 D3/E3 300 BSC 7.62 BSG e .050 BSC 1.27 BSC J 042 | 048 | 107 | 4.22 2 ND/NE 7 7 N 28 28 cee | .o04 | ato |}__F }~# 1 J D D1 moomoo o | | [Da/E3] 19TMC1175A/TMC1275 PRODUCT SPECIFICATION Ordering Information Conversion Package Product Number Rate Temperature Range | Screening Package Marking TMG1175AM7C20 20Msps_ | TA =-20C to 75C Commercial 24-Lead SOIC | 1175AM7C20 TMG1175AM7C30 30Msps | TA =-20C to 75C Commercial 24-Lead SOIC | 1175AM7C30 TMG1175AM7C40 40Msps_ | TA =-20C to 75C Commercial 24-Lead SOIC | 1175AM7C40 TMG1175AM7C50 50Msps_ | TA =-20C to 75C Commercial 24-Lead SOIC | 1175AM7C50 TMC1175AN2C20 20Msps_ | Ta =-20C to 75C Commercial 24-Lead PDIP 1175AN2C20 TMG1175AN2C30 30Msps | TA =-20C to 75C Commercial 24-Lead PDIP 1175AN2C30 TMC1175AN2C40 40Msps_ | Ta =-20C to 75C Commercial 24-Lead PDIP 1175AN2C40 TMC1175AN2C50 50 Msps Ta =-20C to 75C Commercial 24-Lead PDIP 1175AN2C50 TMG1175AR3C20 20Msps_ | TA =-20C to 75C Commercial 28-Lead PLCC | 1175AR3C20 TMC1175AR8C30 30 Msps Ta =-20C to 75C Commercial 28-Lead PLCC 1175AR3C30 TMG1175AR3C40 40 Msps_ | TA =-20C to 75C Commercial 28-Lead PLCC | 1175AR3C40 TMC1175AR8C50 50 Msps Ta =-20C to 75C Commercial 28-Lead PLCC 1175AR3C50 TMG1275M7G20 20 Msps Ta = -20C to 75C Commercial 24-Lead SOIC 1275M7C20 TMC1275M7C30 30Msps | TA =-20C to 75C Commercial 24-Lead SOIC 1275M7C30 TMG1275M7C40 40 Msps Ta = -20C to 75C Commercial 24-Lead SOIC 1275M7C40 TMG1275M7GC50 50 Msps Ta =-20G to 75C Commercial 24-Lead SOIG 1275M7C50 TMC1275N2C20 20Msps_ | TA =-20C to 75C Commercial 24-Lead PDIP 1275N2C20 TMG1275N2C30 30 Msps Ta =-20G to 75C Commercial 24-Lead PDIP 1275N2C30 TMG 1275N2C40 40Msps | TA =-20C to 75C Commercial 24-Lead PDIP 1275N2C40 TMC1275N2C50 50 Msps Ta =-20C to 75C Commercial 24-Lead PDIP 1275N2C50 TMG1275R3C20 20 Msps | TA =-20C to 75C Commercial 28-Lead PLCC 1275R3C20 TMG1275R3C30 30Msps_ | TA =-20C to 75C Commercial | 28-Lead PLCC 1275R3C30 TMG1275R3C40 40Msps_ | TA =-20C to 75C Commercial 28-Lead PLCC 1275R3C40 TMG1275R3C50 50 Msps | Ta =-20C to 75C Commercial 28-Lead PLCC 1275R3C50 LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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