Low Cost, 80 MHz
FastFET Op Amps
AD8033/AD8034
Rev. D
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FEATURES
FET input amplifier
1 pA typical input bias current
Very low cost
High speed
80 MHz, −3 dB bandwidth (G = +1)
80 V/μs slew rate (G = +2)
Low noise
11 nV/√Hz (f = 100 kHz)
0.7 fA/√Hz (f = 100 kHz)
Wide supply voltage range: 5 V to 24 V
Low offset voltage: 1 mV typical
Single-supply and rail-to-rail output
High common-mode rejection ratio: −100 dB
Low power: 3.3 mA/amplifier typical supply current
No phase reversal
Small packaging: 8-lead SOIC, 8-lead SOT-23, and 5-lead SC70
APPLICATIONS
Instrumentation
Filters
Level shifting
Buffering
GENERAL DESCRIPTION
The AD8033/AD8034 FastFET™ amplifiers are voltage feedback
amplifiers with FET inputs, offering ease of use and excellent
performance. The AD8033 is a single amplifier and the AD8034
is a dual amplifier. The AD8033/AD8034 FastFET op amps in
Analog Devices, Inc., proprietary XFCB process offer significant
performance improvements over other low cost FET amps, such
as low noise (11 nV/√Hz and 0.7 fA/√Hz) and high speed (80 MHz
bandwidth and 80 V/µs slew rate).
With a wide supply voltage range from 5 V to 24 V and fully
operational on a single supply, the AD8033/AD8034 amplifiers
work in more applications than similarly priced FET input
amplifiers. In addition, the AD8033/AD8034 have rail-to-rail
outputs for added versatility.
Despite their low cost, the amplifiers provide excellent overall
performance. They offer a high common-mode rejection of
−100 dB, low input offset voltage of 2 mV maximum, and low
noise of 11 nV/√Hz.
CONNECTION DIAGRAMS
NC
1
–IN
2
+IN
3
–V
S4
NC
8
+V
S
7
V
OUT
6
NC
5
NC = NO CONNECT
02924-001
AD8033
V
OUT 1
+IN
3
–V
S2
+V
S
5
–IN
4
0
2924-002
AD8033
Figure 1. 8-Lead SOIC (R) Figure 2. 5-Lead SC70 (KS)
V
OUT1 1
–IN1
2
+IN1
3
–V
S4
+V
S
8
V
OUT2
7
–IN2
6
+IN2
5
02924-003
AD8034
Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ)
1000.1
1
FREQUENCY (MHz)
21
18
–9
15
12
9
6
3
0
–3
–6
24
GAIN (dB)
G = +5
1000
G = +1
V
OUT
= 200mV p-p
G = +10
G = +2
G = –1
02924-004
10
Figure 4. Small Signal Frequency Response
The AD8033/AD8034 amplifiers only draw 3.3 mA/amplifier of
quiescent current while having the capability of delivering up to
40 mA of load current.
The AD8033 is available in a small package 8-lead SOIC and a
small package 5-lead SC70. The AD8034 is also available in a
small package 8-lead SOIC and a small package 8-lead SOT-23.
They are rated to work over the industrial temperature range of
−40°C to +85°C without a premium over commercial grade
products.
AD8033/AD8034
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagrams ...................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Maximum Power Dissipation ..................................................... 6
Output Short Circuit .................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 14
Theory of Operation ...................................................................... 16
Output Stage Drive and Capacitive Load Drive ..................... 16
Input Overdrive .......................................................................... 16
Input Impedance ........................................................................ 16
Thermal Considerations ............................................................ 16
Layout, Grounding, and Bypassing Considerations .................. 18
Bypassing ..................................................................................... 18
Grounding ................................................................................... 18
Leakage Currents ........................................................................ 18
Input Capacitance ...................................................................... 18
Applications Information .............................................................. 19
High Speed Peak Detector ........................................................ 19
Active Filters ............................................................................... 20
Wideband Photodiode Preamp ................................................ 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/08—Rev. C to Rev. D
Deleted Usable Input Range Parameter, Table 1 ........................... 3
Deleted Usable Input Range Parameter, Table 2 ........................... 4
Deleted Usable Input Range Parameter, Table 3 ........................... 5
4/08—Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Features and General Description ............................. 1
Changes to Figure 13 Caption and Figure 14 Caption ................ 8
Changes to Figure 22 and Figure 23 ............................................... 9
Changes to Figure 25 and Figure 28 ............................................. 10
Changes to Input Capacitance Section ........................................ 18
Changes to Active Filters Section ................................................. 21
Changes to Outline Dimensions ................................................... 23
Changes to Ordering Guide .......................................................... 24
2/03—Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to Connection Diagrams ................................................. 1
Changes to Specifications ................................................................ 2
Changes to Absolute Maximum Ratings ....................................... 4
Replaced TPC 31............................................................................. 11
Changes to TPC 35 ......................................................................... 11
Changes to Test Circuit 3 ............................................................... 12
Updated Outline Dimensions ....................................................... 19
8/02—Rev. 0 to Rev. A
Added AD8033 ................................................................... Universal
VOUT = 2 V p-p Deleted from Default Conditions ......... Universal
Added SOIC-8 (R) and SC70 (KS) .................................................. 1
Edits to General Description Section ............................................. 1
Changes to Specifications ................................................................. 2
New Figure 2 ...................................................................................... 5
Edits to Maximum Power Dissipation Section .............................. 5
Changes to Ordering Guide ............................................................. 5
Change to TPC 3 ............................................................................... 6
Change to TPC 6 ............................................................................... 6
Change to TPC 9 ............................................................................... 7
New TPC 16 ....................................................................................... 8
New TPC 17 ....................................................................................... 8
New TPC 31 .................................................................................... 11
New TPC 35 .................................................................................... 11
New Test Circuit 9 .......................................................................... 13
SC70 (KS) Package Added ............................................................ 19
AD8033/AD8034
Rev. D | Page 3 of 24
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 65 80 MHz
G = +2, VOUT = 0.2 V p-p 30 MHz
G = +2, VOUT = 2 V p-p 21 MHz
Input Overdrive Recovery Time −6 V to +6 V input 135 ns
Output Overdrive Recovery Time −3 V to +3 V input, G = +2 135 ns
Slew Rate (25% to 75%) G = +2, VOUT = 4 V step 55 80 V/µs
Settling Time to 0.1% G = +2, VOUT = 2 V step 95 ns
G = +2, VOUT = 8 V step 225 ns
NOISE/HARMONIC PERFORMANCE
Distortion fC = 1 MHz, VOUT = 2 V p-p
Second Harmonic RL = 500 Ω −82 dBc
R
L = 1 kΩ −85 dBc
Third Harmonic RL = 500 Ω −70 dBc
R
L = 1 kΩ −81 dBc
Crosstalk, Output-to-Output f = 1 MHz, G = +2 −86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz
DC PERFORMANCE
Input Offset Voltage VCM = 0 V 1 2 mV
T
MIN − TMAX 3.5 mV
Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 27 V/°C
Input Bias Current 1.5 11 pA
T
MIN − TMAX 50 pA
Open-Loop Gain VOUT = ± 3 V 89 92 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range
FET Input Range −5.0 to +2.2 V
Common-Mode Rejection Ratio VCM = −3 V to +1.5 V −89 −100 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing ±4.75 ±4.95 V
Output Short-Circuit Current 40 mA
Capacitive Load Drive 30% overshoot, G = +1, VOUT = 400 mV p-p 35 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±2 V −90 −100 dB
AD8033/AD8034
Rev. D | Page 4 of 24
TA = 25°C, VS = 5 V, RL = 1 k, gain = +2, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 70 80 MHz
G = +2, VOUT = 0.2 V p-p 32 MHz
G = +2, VOUT = 2 V p-p 21 MHz
Input Overdrive Recovery Time −3 V to +3 V input 180 ns
Output Overdrive Recovery Time −1.5 V to +1.5 V input, G = +2 200 ns
Slew Rate (25% to 75%) G = +2, VOUT = 4 V step 55 70 V/s
Settling Time to 0.1% G = +2, VOUT = 2 V step 100 ns
NOISE/HARMONIC PERFORMANCE
Distortion fC = 1 MHz, VOUT = 2 V p-p
Second Harmonic RL = 500 Ω −80 dBc
R
L = 1 kΩ −84 dBc
Third Harmonic RL = 500 Ω −70 dBc
R
L = 1 kΩ −80 dBc
Crosstalk, Output to Output f = 1 MHz, G = +2 −86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz
DC PERFORMANCE
Input Offset Voltage VCM = 0 V 1 2 mV
T
MIN − TMAX 3.5 mV
Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 30 V/°C
Input Bias Current 1 10 pA
T
MIN − TMAX 50 pA
Open-Loop Gain VOUT = 0 V to 3 V 87 92 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range
FET Input Range 0 to 2.0 V
Common-Mode Rejection Ratio VCM = 1.0 V to 2.5 V −80 −100 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ 0.16 to 4.83 0.04 to 4.95 V
Output Short-Circuit Current 30 mA
Capacitive Load Drive 30% overshoot, G = +1, VOUT = 400 mV p-p 25 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±1 V −80 −100 dB
AD8033/AD8034
Rev. D | Page 5 of 24
TA = 25°C, VS = ±12 V, RL = 1 k, gain = +2, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VOUT = 0.2 V p-p 65 80 MHz
G = +2, VOUT = 0.2 V p-p 30 MHz
G = +2, VOUT = 2 V p-p 21 MHz
Input Overdrive Recovery Time −13 V to +13 V input 100 ns
Output Overdrive Recovery Time −6.5 V to +6.5 V input, G = +2 100 ns
Slew Rate (25% to 75%) G = +2, VOUT = 4 V step 55 80 V/s
Settling Time to 0.1% G = +2, VOUT = 2 V step 90 ns
G = +2, VOUT = 10 V step 225 ns
NOISE/HARMONIC PERFORMANCE
Distortion fC = 1 MHz, VOUT = 2 V p-p
Second Harmonic RL = 500 Ω −80 dBc
R
L = 1 kΩ −82 dBc
Third Harmonic RL = 500 Ω −70 dBc
R
L = 1 kΩ −82 dBc
Crosstalk, Output to Output f = 1 MHz, G = +2 −86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz
DC PERFORMANCE
Input Offset Voltage VCM = 0 V 1 2 mV
T
MIN − TMAX 3.5 mV
Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 24 V/°C
Input Bias Current 2 12 pA
T
MIN − TMAX 50 pA
Open-Loop Gain VOUT = ±8 V 88 96 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range
FET Input Range −12.0 to +9.0 V
Common-Mode Rejection Ratio VCM = ±5 V −92 −100 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing ±11.52 ±11.84 V
Output Short-Circuit Current 60 mA
Capacitive Load Drive 30% overshoot, G = +1 35 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±2 V −85 −100 dB
AD8033/AD8034
Rev. D | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 26.4 V
Power Dissipation See Figure 5
If the rms signal levels are indeterminate, consider the worst case,
when VOUT = VS/4 for RL to midsupply
PD = (VS × IS) + (VS/4)2/RL
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
Common-Mode Input Voltage 26.4 V
Differential Input Voltage 1.4 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
AMBIENT TEMPERATURE (°C)
–60 –20–40 10060 80
2.0
1.5
MAXIMUM POWER DISSIPATION (W)
1.0
0.5
0
SOIC-8
SOT-23-8
SC70-5
40020
02924-005
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic that encapsulates the die locally
reaches the junction temperature. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the AD8033/
AD8034. Exceeding a junction temperature of 175°C for an
extended period can result in changes in silicon devices, potentially
causing failure.
Figure 5. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as discussed
in the Layout, Grounding, and Bypassing Considerations section.
Figure 5 shows the maximum power dissipation in the package
vs. the ambient temperature for the 8-lead SOIC (125°C/W),
5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages
on a JEDEC standard 4-layer board. θJA values are approximations.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.
TJ = TA + (PD × θJA)
PD is the sum of the quiescent power dissipation and the power
dissipated in the package due to the load drive for all outputs.
The quiescent power is the voltage between the supply pins (VS)
times the quiescent current (IS). Assuming the load (RL) is
referenced to midsupply, the total drive power is VS/2 × IOUT,
some of which is dissipated in the package and some in the load
(VOUT × IOUT). The difference between the total drive power and
the load power is the drive power dissipated in the package
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
PD = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT2/RL]
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT.
AD8033/AD8034
Rev. D | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: VS = ±5 V, CL = 5 pF, RL = 1 k, TA = 25°C.
1000.1 1
FREQUENCY (MHz)
21
18
–9
15
12
9
6
3
0
–3
–6
24
GAIN (dB)
G = +5
1000
G = +1
V
OUT
= 200mV p-p
G = +10
G = +2
G = –1
10
02924-006
Figure 6. Small Signal Frequency Response for Various Gains
FREQUENCY (MHz)
–6
1
0
–1
–2
–3
–4
–5
V
S
= +5V
G = +1
V
OUT
= 200mV p-p
GAIN (dB)
V
S
= ±12V
V
S
=±5V
1000.1 1 10
02924-007
Figure 7. Small Signal Frequency Response for Various Supplies
(See Figure 44)
FREQUENCY (MHz)
2
1
–6
1000.1 1
GAIN (dB)
10
0
–1
–5
–2
–3
–4
G = +1
V
OUT
= 2V
p-p
V
S
= ±12V
V
S
=±5V
V
S
= +5V
02924-008
Figure 8. Large Signal Frequency Response for Various Supplies
(See Figure 44)
FREQUENCY (MHz)
1000.1 1 10
8
7
0
6
5
1
4
3
2
GAIN (dB)
V
OUT
= 1V p-p
V
OUT
= 4V p-p
VOUT
= 2V p-p
V
OUT
= 0.2V p-p
G = +2
02924-009
Figure 9. Frequency Response for Various Output Amplitudes (See Figure 45)
1000.1 1 10
FREQUENCY (MHz)
8
7
0
6
5
1
4
3
2
GAIN (dB)
V
S
= +5V
V
S
=
±12V
VS=±5V
G = +2
VOUT = 200mV p-p
02924-010
Figure 10. Small Signal Frequency Response for Various Supplies
(See Figure 45)
1000.1 1 10
FREQUENCY (MHz)
7
GAIN (dB)
6
5
1
4
3
2
0
G = +2
V
OUT
= 2V p-p
V
S
= ±12V
V
S
=±5V
V
S
= +5V
02924-011
Figure 11. Large Signal Frequency Response for Various Supplies
(See Figure 45)
AD8033/AD8034
Rev. D | Page 8 of 24
FREQUENCY (MHz)
1000.1
110
8
6
4
–4
2
0
–2
–6
GAIN (dB)
C
L
= 100pF
C
L
= 100pF
R
SNUB
= 25Ω
C
L
= 33pF
C
L
= 2pF
V
OUT
= 200mV p-p
G = +1
02924-012
Figure 12. Small Signal Frequency Response for Various CL (See Figure 44)
1000.1
110
9
8
0
7
6
2
5
4
3
1
GAIN (dB)
FREQUENCY (MHz)
CF= 0pF
CF= 1pF
CF= 1.5pF
CF= 2pF
VOUT = 200mV p-p
RF= 3kΩ
G = +2
02924-013
Figure 13. Small Signal Frequency Response for Various CF (See Figure 45)
FREQUENCY (Hz)
0.1
IMPEDANCE
(
Ω)
100
10
1
G = +2
G = +1
V
OUT
= 200mV p-p
0.01
100 1k 10k 100k 1M 10M 100M
0
2924-014
Figure 14. Output Impedance vs. Frequency (See Figure 47)
1000.1 110
FREQUENCY (MHz)
GAIN (dB)
10
9
0
8
7
6
5
4
3
2
1
C
L
= 100pF
C
L
= 51pF
C
L
= 33pF
C
L
= 2pF
V
OUT
= 200mV p-p
G = +2
02924-015
Figure 15. Small Signal Frequency Response for Various CL (See Figure 45)
FREQUENCY (MHz)
1000.1 1 10
8
7
0
GAIN (dB)
6
5
1
4
3
2
R
L
= 500Ω
R
L
= 1kΩ
V
OUT
= 200mV p-p
G = +2
02924-016
Figure 16. Small Signal Frequency Response for Various RL (See Figure 45)
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M 100M
100
80
–20
GAIN (dB)
40
20
0
60
180
150
0
PHASE (Degrees)
90
60
30
120
GAIN
PHASE
V
S
= ±12V
02924-017
Figure 17. Open-Loop Response
AD8033/AD8034
Rev. D | Page 9 of 24
FREQUENCY (MHz)
–
40
–50
–120
510.1
DISTORTION (dBc)
–60
–70
–110
–80
–90
–100
G = +2
HD2 R
L
= 500
Ω
HD2 R
L
= 1k
Ω
HD3 R
L
= 1k
Ω
HD3 R
L
= 500
Ω
02924-018
Figure 18. Harmonic Distortion vs. Frequency for Various Loads
(See Figure 45)
FREQUENCY (MHz)
–
40
–50
–120
50.1 1
DISTORTION (dBc)
–60
–70
–110
–80
–90
–100
G = +2
HD3 V
S
= 24V
HD2 V
S
= 24V
HD2 V
S
= 5V
HD3 V
S
= 5V
02924-019
Figure 19. Harmonic Distortion vs. Frequency for Various Supply Voltages
(See Figure 45)
FREQUENCY (Hz)
1000
10
M0110
100 1k 10k 100k 1M 10M 100M
NOISE (nV/
√
Hz)
100
02924-020
Figure 20. Voltage Noise vs. Frequency
FREQUENCY (MHz)
–
40
–50
–120
50.1 1
DISTORTION (dBc)
–60
–70
–110
–80
–90
–100
HD3 G = +2
HD2 G = +1
HD3 G = +1
HD2 G = +2
02924-021
Figure 21. Harmonic Distortion vs. Frequency for Various Gains
FREQUENCY (MHz)
–40
–50
–120
50.1 1
DISTORTION (dBc)
–60
–70
–110
–80
–90
–100
HD3 V
OUT
= 20V p-p
HD2 V
OUT
= 20V p-pHD3 V
OUT
= 10V p-p
HD2 V
OUT
= 10V p-p
HD3 V
OUT
= 2V p-p
HD2 V
OUT
= 2V p-p
–30
–
20
02924-022
G = +2
Figure 22. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 45), VS = 24 V
CAPACITIVE LOAD (pF)
80
0
PERCENT OVERSHOOT (%)
70
40
30
20
10
60
50
10 30 50 70 90 110
V
S
= +5V
POSITIVE SIDE
V
S
=±5V
POSITIVE SIDE
V
S
=±5V
NEGATIVE SIDE
V
S
= +5V
NEGATIVE SIDE
0
2924-023
G = +1
Figure 23. Percent Overshoot vs. Capacitive Load (See Figure 44)
AD8033/AD8034
Rev. D | Page 10 of 24
G = +1
25mV/DIV 20ns/DIV
02924-024
Figure 24. Small Signal Transient Response 5 V (See Figure 44)
3V/DIV 320ns/DIV
V
OUT
= 20V p-p
V
OUT
= 8V p-p
V
OUT
= 2V p-p
0
2924-025
G = +1
Figure 25. Large Signal Transient Response (See Figure 44)
G = –1
V
IN
V
OUT
1.5V/DIV 350ns/DIV
02924-026
Figure 26. Output Overdrive Recovery (See Figure 46)
G = +1
80mV/DIV 80ns/DIV
38pF 15pF
02924-027
Figure 27. Small Signal Transient Response ±5 V (See Figure 44)
3V/DIV 320ns/DIV
G = +2
V
OUT
= 2V p-p
V
OUT
= 8V p-p
V
OUT
= 20V p-p
02924-028
Figure 28. Large Signal Transient Response (See Figure 45)
G = +1
V
IN
V
OUT
1.5V/DIV 350ns/DIV
02924-029
Figure 29. Input Overdrive Recovery (See Figure 44)
AD8033/AD8034
Rev. D | Page 11 of 24
2mV/DIV 1.5µs/DIV
V
OUT
– 2V
IN
V
IN
= 1V
t
= 0
+0.1%
–0.1%
02924-030
Figure 30. Long-Term Settling Time
TEMPERATURE (°C)
8520
25 30 35 40 45 50 60 65 70 807555
0
–40
I
b
(pA)
–20
–25
–30
–35
–10
–15
–5
+I
b
–I
b
02924-031
Figure 31. Ib vs. Temperature
–I
b
+I
b
–I
b
+I
b
BJT INPUT RANGE
FET INPUT RANGE
COMMON-MODE VOLTAGE (V)
–4–6–8–10–12 –2
02468 1210
10
5
0
–5
–10
–15
–20
–25
–30
0
6
12
18
24
30
36
42
02924-032
I
b
(
µ
A)
I
b
(
p
A)
Figure 32. Ib vs. Common-Mode Voltage Range
2mV/DIV 20ns/DIV
V
IN
= 1V
t
= 0
+0.1%
–0.1%
V
OUT
– 2V
IN
02924-033
Figure 33. 0.1% Short-Term Settling Time
–40 –20
0 20406080
TEMPERATURE (°C)
7.0
6.4
5.9
QUIESCENT SUPPLY CURRENT (mA)
6.9
6.7
6.2
6.0
6.6
6.8
6.5
6.3
6.1
02924-034
V
S
= +5V
V
S
= ±5V
V
S
= ±12V
Figure 34. Quiescent Supply Current vs. Temperature for Various Supply
Voltages
4.0
0.5
–1.0
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14–14
NORMALIZED OFFSET (mV)
3.5
1.0
0
–0.5
2.5
1.5
3.0
2.0
COMMON-MODE VOLTAGE (V)
02924-035
V
S
= +5VV
S
= ±5V
V
S
= ±12V
Figure 35. Input Offset Voltage vs. Common-Mode Voltage
AD8033/AD8034
Rev. D | Page 12 of 24
FREQUENCY (MHz)
CMRR (dB)
0.1 1 10 100
0
2924-036
–
20
–30
–40
–50
–60
–70
–80
Figure 36. CMRR vs. Frequency (See Figure 50)
I
LOAD
(mA)
03005
OUTPUT SATURATION (V)
10 15 20 25
0.6
0.4
0.2
1.0
0.8
V
CC
–V
OH
V
OL
– V
EE
02924-037
Figure 37. Output Saturation Voltage vs. Load Current
FREQUENCY (MHz)
PSRR (dB)
0
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
100
0.0001 0.001 0.01 0.1 1 10
+PSRR
–PSRR
02924-038
Figure 38. PSRR vs. Frequency (See Figure 49 and Figure 51)
OUTPUT VOLTAGE (V)
12–10–8–6–4–2 2468100
105
100
60
OPEN-LOOP GAIN (dB)
80
75
70
65
90
85
95
–12
R
L
= 500Ω
R
L
= 1kΩ
R
L
= 2kΩ
0
2924-039
Figure 39. Open-Loop Gain vs. Output Voltage for Various RL
FREQUENCY (MHz)
–
40
–70
–100
0.1
CROSSTALK (dB)
50
–80
–90
–60
–50
101
SOIC A/B
SOIC B/A
SOT-23 B/A
SOT-23 A/B
0
2924-040
Figure 40. Crosstalk (See Figure 52)
V
OS
(mV)
–1.5 –1.0 –0.5 0 0.5 1.0 1.5
0
FREQUENCY
120
90
60
30
180
150
02924-041
Figure 41. Initial Offset
AD8033/AD8034
Rev. D | Page 13 of 24
1.2V/DIV
1µs/DIV
V
IN
V
OUT
0
2924-042
Figure 42. G = +1 Response, VS = ±5 V
1.2V/DIV V
IN
V
OUT
1µs/DIV
0
2924-043
Figure 43. G = +2 Response, VS = ±5 V
AD8033/AD8034
Rev. D | Page 14 of 24
TEST CIRCUITS
V
IN
49.9Ω
–V
S
+V
S
+
10nF
AD8033/AD8034
10nF
1µF
1µF
+
C
LOAD
R
SNUB
49.9Ω
976Ω
V
OUT
02924-044
Figure 44. G = +1
V
IN
49.9Ω
–VS
+VS
1µF
1µF
+
10nF
AD8033/AD8034
10nF
+
CLOAD
RSNUB
49.9Ω
976Ω
VOUT
CF
1kΩ
RF
1kΩ
499Ω
02924-045
Figure 45. G = +2
49.9
Ω
1kΩ1kΩ
1µF
1µF
976Ω
499Ω
+V
S
–V
S
V
IN
+
10nF
AD8033/AD8034
10nF
+
V
OUT
02924-046
Figure 46. G = −1
1
µF
1µF
+V
S
–V
S
+
10nF
AD8033/AD8034
10nF
V
SINE
0.2V p-p
+
+
–
02924-047
Figure 47. Output Impedance, G = +1
1k
Ω1kΩ
1µF
1µF
+V
S
–V
S
+
10nF
AD8033/AD8034
10nF
+
V
SINE
0.2V p-p
+
–
02924-048
Figure 48. Output Impedance, G = +2
AD8033/AD8034
Rev. D | Page 15 of 24
+V
S
49.9Ω
1µF
+
10nF
AD8033/AD8034
V
OUT
+
–
–V
S
–V
S
AC
1V p-p
02924-051
Figure 49. Negative PSRR
49.9
Ω
+V
S
V
IN
–V
S
1µF
1µF
+
10nF
AD8033/AD8034
10nF
+
976Ω
V
OUT
1kΩ
1kΩ
49.9Ω
1kΩ1kΩ
02924-050
Figure 50. CMRR
+V
S
+–
+V
S
AC
1V p-
49.9Ω
V
OUT
–V
S
AD8033/AD8034
10nF
1µF
+
02924-049
Figure 51. Positive PSRR
–V
S
+V
S
–V
S
+V
S
A
+
–
499Ω
1kΩ1kΩ
1kΩ
TO PORT 2
B
+
–
1kΩ
1kΩ1kΩ
499Ω
TO PORT 1
50Ω
+
–
V
IN
02924-052
Figure 52. Crosstalk
AD8033/AD8034
Rev. D | Page 16 of 24
THEORY OF OPERATION
The incorporation of JFET devices into the Analog Devices
high voltage XFCB process has enabled the ability to design the
AD8033/AD8034. The AD8033/AD8034 are voltage feedback
rail-to-rail output amplifiers with FET inputs and a bipolar-
enhanced common-mode input range. The use of JFET devices in
high speed amplifiers extends the application space into both the
low input bias current and low distortion, high bandwidth areas.
Using N-channel JFETs and a folded cascade input topology,
the common-mode input level operates from 0.2 V below the
negative rail to within 3.0 V of the positive rail. Cascading of
the input stage ensures low input bias current over the entire
common-mode range as well as CMRR and PSRR specifications
that are above 90 dB. Additionally, long-term settling issues that
normally occur with high supply voltages are minimized as a
result of the cascading.
OUTPUT STAGE DRIVE AND CAPACITIVE LOAD
DRIVE
The common emitter output stage adds rail-to-rail output
performance and is compensated to drive 35 pF (30% overshoot
at G = +1). Additional capacitance can be driven if a small snub
resistor is put in series with the capacitive load, effectively
decoupling the load from the output stage, as shown in Figure 12.
The output stage can source and sink 20 mA of current within
500 mV of the supply rails and 1 mA within 100 mV of the
supply rails.
INPUT OVERDRIVE
An additional feature of the AD8033/AD8034 is a bipolar input
pair that adds rail-to-rail common-mode input performance
specifically for applications that cannot tolerate phase inversion
problems.
Under normal common-mode operation, the bipolar input
pair is kept reversed, maintaining Ib at less than 1 pA. When
the input common-mode operation comes within 3.0 V of the
positive supply rail, I1 turns off and I4 turns on, supplying tail
current to the bipolar pair Q25 and Q27. With this configuration,
the inputs can be driven beyond the positive supply rail without
any phase inversion (see Figure 53).
As a result of entering the bipolar mode of operation, an offset
and input bias current shift occurs (see Figure 32 and Figure 35).
After re-entering the JFET common-mode range, the amplifier
recovers in approximately 100 ns (refer to Figure 29 for input
overload behavior). Above and below the supply rails, ESD
protection diodes activate, resulting in an exponentially
increasing input bias current. If the inputs are driven well
beyond the rails, series input resistance should be included
to limit the input bias current to <10 mA.
INPUT IMPEDANCE
The input capacitance of the AD8033/AD8034 forms a pole
with the feedback network, resulting in peaking and ringing
in the overall response. The equivalent impedance of the
feedback network should be kept small enough to ensure that
the parasitic pole falls well beyond the −3 dB bandwidth of the
gain configuration being used. If larger impedance values are
desired, the amplifier can be compensated by placing a small
capacitor in parallel with the feedback resistor. Figure 13 shows
the improvement in frequency response by including a small
feedback capacitor with high feedback resistance values.
THERMAL CONSIDERATIONS
Because the AD8034 operates at up to ±12 V supplies in the
small 8-lead SOT-23 package (160°C/W), power dissipation can
easily exceed package limitations, resulting in permanent shifts
in device characteristics and even failure. Likewise, high supply
voltages can cause an increase in junction temperature even
with light loads, resulting in an input bias current and offset
drift penalty. The input bias current doubles for every 10°C
shown in Figure 31. Refer to the Maximum Power Dissipation
section for an estimation of die temperature based on load and
supply voltage.
AD8033/AD8034
Rev. D | Page 17 of 24
V
TH
+
V
S
R2
Q6
–IN
J1 D4 Q25
Q7
I2
Q27
R3
R14
Q9
–V
S
J2
+IN
R7
Q29
Q4
Q13
V
CC
Q11
I3
Q28
R8
Q1
Q14
V2 V4
++
–
–
V
OUT
D5
I1 I4
02924-053
Figure 53. Simplified AD8033/AD8034 Input Stage
AD8033/AD8034
Rev. D | Page 18 of 24
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
BYPASSING
Power supply pins are actually inputs, and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering a
majority of the noise. Decoupling schemes are designed to
minimize the bypassing impedance at all frequencies with a
parallel combination of capacitors. The chip capacitors, 0.01 µF
or 0.001 µF (X7R or NPO), are critical and should be placed as
close as possible to the amplifier package. Larger chip capacitors,
such as the 0.1 µF capacitor, can be shared among a few closely
spaced active components in the same signal path. The 10 µF
tantalum capacitor is less critical for high frequency bypassing, and
in most cases, only one per board is needed at the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PCBs to
spread the current, thereby minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional
to the magnitude of the parasitic inductances and, thus, the
high frequency impedance of the path. High speed currents
in an inductive ground return create unwanted voltage noise.
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location.
Because load currents flow from the supplies as well, the ground
for the load impedance should be at the same physical location
as the bypass capacitor grounds. For the larger value capacitors
that are intended to be effective at lower frequencies, the current
return path distance is less critical.
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator material
can create leakage currents that are much larger than the input
bias currents of the AD8033/AD8034. Any voltage differential
between the inputs and nearby runs set up leakage currents
through the PCB insulator, for example, 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem). To significantly reduce
leakages, put a guard ring (shield) around the inputs and input
leads that is driven to the same voltage potential as the inputs.
This way there is no voltage potential between the inputs and
surrounding area to set up any leakage currents. For the guard
ring to be completely effective, it must be driven by a relatively
low impedance source and should completely surround the input
leads on all sides, above, and below using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials
such as Teflon® or ceramic may be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance reduces the input impedance at
high frequencies, in turn it increases the gain of the amplifier
and can cause peaking of the overall frequency response or even
oscillations if severe enough. It is recommended that the external
passive components that are connected to the input pins be placed
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.
AD8033/AD8034
Rev. D | Page 19 of 24
APPLICATIONS INFORMATION
HIGH SPEED PEAK DETECTOR
The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to ~1.4 V p-p maximum in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as shown in Figure 54.
AD8033/
AD8034
V
IN
~1.4V p-p MAX
V
OUT
02924-054
Figure 54. High Speed Peak Detector with Limited Input Range
Using the AD8033/AD8034, a unity gain peak detector can
be constructed that captures a 300 ns pulse while still taking
advantage of the low input bias current and wide common-
mode input range of the AD8033/AD8034, as shown in Figure 55.
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
at Node 3 equal to Node 1. D1 is off and the voltage drop across
R2 is zero. Capacitor C3 speeds up the loop by providing the
charge required by the input capacitance of the first amplifier,
helping to maintain a minimal voltage drop across R2 in the
sampling mode. A negative going edge results in D2 and D3
turning off and D1 turning on, closing the loop around the
first amplifier and forcing VOUT − VIN across R2. R4 makes
the voltage across D2 zero, minimizing leakage current and
kickback from D3 from affecting the voltage across C2.
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of VIN
before the output of the second amplifier can provide negative
feedback at the summing junction of the first amplifier. This
is accomplished with the combination of R1 and C1, which
allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns.
The selection of C2 and R3 is made by considering droop
rate, settling time, and kickback. R3 prevents overshoot from
occurring at Node 3. The time constants of R1, C1 and R3, C2
are roughly equal to achieve the best performance. Slower time
constants can be selected by increasing C2 to minimize droop
rate and kickback at the cost of increased settling time. R1 and
C1 should also be increased to match, reducing the incoming
pulse’s effect on kickback.
AD8034
1/2
C3
10pF
R2
1kΩ
R1
1kΩ
AD8034
1/2
–V
S
+V
S
C1 39pF/
120pF
LS4148
V
IN
R5
49.9Ω
D1
4.7pF
C4 R4
6kΩ
D3
LS4148 –V
S
+V
S
LS4148
R3
200Ω
C2 180pF/
560pF
V
OUT
D2
0
2924-056
Figure 55. High Speed, Unity Gain Peak Detector Using AD8034
AD8033/AD8034
Rev. D | Page 20 of 24
1V/DIV 100ns/DIV
02924-055
OUTPUT
INPUT
2
Figure 56. Peak Detector Response 4 V, 300 ns Pulse
Figure 56 shows the peak detector in Figure 55 capturing a
300 ns, 4 V pulse with 10 mV of kickback and a droop rate of
5 V/s. For larger peak-to-peak pulses, increase the time constants
of R1, C1 and R3, C3 to reduce overshoot. The best droop rate
occurs by isolating parasitic resistances from Node 3, which can
be accomplished using a guard band connected to the output of the
second amplifier that surrounds its summing junction (Node 3).
Increasing both time constants by a factor of 3 permits a larger
peak pulse to be captured and increases the output accuracy.
1V/DIV 200ns/DIV
02924-057
OUTPUT
INPUT
2
Figure 57. Peak Detector Response 5 V, 1 μs Pulse
Figure 57 shows a 5 V peak pulse being captured in 1 µs with
less than 1 mV of kickback. With this selection of time constants,
up to a 20 V peak pulse can be captured with no overshoot.
ACTIVE FILTERS
The response of an active filter varies greatly depending on the
performance of the active device. Open-loop bandwidth and
gain, along with the order of the filter, determines the stop-band
attenuation as well as the maximum cutoff frequency, while
input capacitance can set a limit on which passive components
are used. Topologies for active filters are varied, and some are
more dependent on the performance of the active device than
others are.
The Sallen-Key topology is the least dependent on the active
device, requiring that the bandwidth be flat to beyond the stop-
band frequency because it is used simply as a gain block. In the
case of high Q filter stages, the peaking must not exceed the open-
loop bandwidth and the linear input range of the amplifier.
Using an AD8033/AD8034, a 4-pole cascaded Sallen-Key filter
can be constructed with fC = 1 MHz and over 80 dB of stop-band
attenuation, as shown in Figure 58.
–V
S
+V
S
C2
10pF
–V
S
+V
S
V
IN
R1
4.22kΩ
AD8034
1/2
AD8034
1/2
R2
6.49kΩ
R5
49.9ΩC1
27pF
C3
33pF
R4
4.99kΩR3
4.99kΩ
C4
82pF
V
OUT
02924-058
Figure 58. 4-Pole Cascade Sallen-Key Filter
Component values are selected using a normalized cascaded,
2-stage Butterworth filter table and Sallen-Key 2-pole active
filter equations. The overall frequency response is shown in
Figure 59.
10M1M10k
FREQUENCY (Hz)
–100
REF LEVEL (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
100k
0
2924-059
Figure 59. 4-Pole Cascade Sallen-Key Filter Response
AD8033/AD8034
Rev. D | Page 21 of 24
When selecting components, the common-mode input capacitance
must be taken into consideration.
Filter cutoff frequencies can be increased beyond 1 MHz using the
AD8033/AD8034 but limited open-loop gain and input impedance
begin to interfere with the higher Q stages. This can cause early
roll-off of the overall response.
Additionally, the stop-band attenuation decreases with decreasing
open-loop gain.
Keeping these limitations in mind, a 2-pole Sallen-Key Butterworth
filter with fC = 4 MHz can be constructed that has a relatively
low Q of 0.707 while still maintaining 15 dB of attenuation an
octave above fC and 35 dB of stop-band attenuation. The filter
and response are shown in Figure 60 and Figure 61, respectively.
–V
S
+V
S
V
IN
R1
2.49kΩ
C3
22pF
V
OUT
AD8033
R2
2.49kΩ
R5
49.9Ω
C1
10pF
02924-060
Figure 60. 2-Pole Butterworth Active Filter
100M100k 1M
FREQUENCY (Hz)
–45
GAIN (dB)
–40
–35
–30
–25
–20
–15
–10
–5
0
5
0
2924-061
10M
Figure 61. 2-Pole Butterworth Active Filter Response
WIDEBAND PHOTODIODE PREAMP
Figure 62 shows an I/V converter with an electrical model of a
photodiode.
The basic transfer function is
FF
F
PHOTO
OUT RsC
R
I
V+
×
=1
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth.
C
S
R
SH
= 10
11
Ω
V
B
I
PHOTO
02924-062
R
F
C
F
V
OUT
C
M
R
F
C
M
C
D
C
F
+ C
S
Figure 62. Wideband Photodiode Preamp
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the summing junction of the amplifier, including
CS and the amplifier input capacitance. RF and the total capacitance
produce a pole in the loop transmission of the amplifier that
can result in peaking and instability. Adding CF creates a zero
in the loop transmission that compensates for the effect of the
pole and reduces the signal bandwidth. It can be shown that the
signal bandwidth resulting in a 45°phase margin (f(45)) is defined
by the expression
S
F
CR
CR
f
f××π
=2
)45(
where:
fCR is the amplifier crossover frequency.
RF is the feedback resistor.
CS is the total capacitance at the amplifier summing junction
(amplifier + photodiode + board parasitics).
The value of CF that produces f(45) is
CR
F
S
FfR
C
C××π
=2
The frequency response in this case shows about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half results in a flat frequency response, with
about 5% transient overshoot.
AD8033/AD8034
Rev. D | Page 22 of 24
02924-063
FREQUENCY (Hz)
VOLTAGE NOISE (nV/
√
Hz)
2πR
F
C
F
2πR
F
(C
F
+ C
S
+ C
M
+ 2C
D
)
(C
S
+ C
M
+ 2C
D
+ C
F
)/C
F
RF NOISE
VEN (C
F
+ C
S
+ C
M
+ 2C
D
)/C
F
f
3
f
2
f
3
=
VEN
f
1
f
2
=
f
1
= 1
1
f
CR
NOISE DUE TO AMPLIFIER
The output noise over frequency of the preamp is shown in
Figure 63.
The pole in the loop transmission translates to a zero in the
noise gain of the amplifier, leading to an amplification of the
input voltage noise over frequency. The loop transmission zero
introduced by CF limits the amplification. The bandwidth of the
noise gain extends past the preamp signal bandwidth and is
eventually rolled off by the decreasing loop gain of the amplifier.
Keeping the input terminal impedances matched is recommended
to eliminate common-mode noise peaking effects that add to
the output noise.
Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root results in the
total rms output noise of the preamp.
Figure 63. Photodiode Voltage Noise Contributions
AD8033/AD8034
Rev. D | Page 23 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 64. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-203-AA
0.30
0.15
0.10 MAX
1.00
0.90
0.70
0.46
0.36
0.26
SEATING
PLANE
0.22
0.08
1.10
0.80
45
123
PIN 1
0.65 BSC
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.10 COPLANARITY
0.40
0.10
Figure 65. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
13
56
2
8
4
7
2.90 BSC
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX 0.22
0.08 0.60
0.45
0.30
8°
4°
0°
2.80 BSC
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-B A
Figure 66. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
AD8033/AD8034
Rev. D | Page 24 of 24
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8033AR –40°C to +85°C 8-Lead SOIC_N R-8
AD8033AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD8033AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD8033ARZ1
–40°C to +85°C 8-Lead SOIC_N R-8
AD8033ARZ-REEL1
–40°C to +85°C 8-Lead SOIC_N R-8
AD8033ARZ-REEL71
–40°C to +85°C 8-Lead SOIC_N R-8
AD8033AKS-R2 –40°C to +85°C 5-Lead SC70 KS-5 H3B
AD8033AKS-REEL –40°C to +85°C 5-Lead SC70 KS-5 H3B
AD8033AKS-REEL7 –40°C to +85°C 5-Lead SC70 KS-5 H3B
AD8033AKSZ-R21
–40°C to +85°C 5-Lead SC70 KS-5 H3C
AD8033AKSZ-REEL1
–40°C to +85°C 5-Lead SC70 KS-5 H3C
AD8033AKSZ-REEL71
–40°C to +85°C 5-Lead SC70 KS-5 H3C
AD8034AR –40°C to +85°C 8-Lead SOIC_N R-8
AD8034AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8
AD8034AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8
AD8034ARZ1
–40°C to +85°C 8-Lead SOIC_N R-8
AD8034ARZ-REEL1
–40°C to +85°C 8-Lead SOIC_N R-8
AD8034ARZ-REEL71
–40°C to +85°C 8-Lead SOIC_N R-8
AD8034ART-R2 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA
AD8034ART-REEL –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA
AD8034ART-REEL7 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA
AD8034ARTZ-R21
–40°C to +85°C 8-Lead SOT-23 RJ-8 HZA#
AD8034ARTZ-REEL1
–40°C to +85°C 8-Lead SOT-23 RJ-8 HZA#
AD8034ARTZ-REEL71
–40°C to +85°C 8-Lead SOT-23 RJ-8 HZA#
AD8034CHIPS DIE
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
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D02924-0-9/08(D)
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