Lattice ae an ss8 Semiconductor seeae Corporation ispLSI 2128VE 3.3V In-System Programmable SuperFAST High Density PLD Features * SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC - 6000 PLD Gates 128 and 64 l/O Pin Versions, Eight Dedicated Inputs 128 Registers High Speed Globai Interconnect -~ Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional/JEDEC Upward Compatible with ispLS] 2128V Devices + 3.3V LOW VOLTAGE 2128 ARCHITECTURE Interfaces with Standard 5V TTL Devices 128 1/O Pin Version is Fuse Map Compatible with 5V ispLSI 2128 and 2128E * HIGH PERFORMANCE E*CMOS* TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power + IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexibie Bus Capability, Allowing Easy implementation of OR Bus Arbitration Logic Increased Manufacturing Yields Market and improved Produc; Reprogram Soidered Devic typing * 100% [EEE 1149.1 BOUND. LE * THE EASE OF USE AN PEED OF PLDs WITH THE DEN BILITY OF FPGAS Optimized Global Routing Pool Provides Global interconnectivity + ispEXPERT ~ LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools - Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms Functional Block Diagram* CE) ERS CES EE ee {_Output Routing Pool (ORP) | { Outnut Routing Pool (OAP) | 7) [Le feet Lele Le t | Aa outing t Routing Poo! (ORF) |[ Output R ee Si 2128VE is a High Density Programmable Device available in 128 and 64 1/O-pin versions. device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLS] 2128VE features in-system programmability through the Bound- ary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLS! 2128VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLSI 2128VE device is the Generic Logic Block (GLB). The GLBs are labeled AO, At .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 1998 Lattice Semiconductor Gort. AR brand or product names are trademarks or registered trademarks of thair respective holders. The specifications and informaticn herein are subject to change without netice LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, USA October 1998 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037: http:/Avww.latticesemi.com 77 Specifications ispLSI 2128VE Functional Block Diagram Figure 1. ispLS! 2128VE Functional Block Diagram (128-l/O and 64-I/O Versions) CEED Oo Ge Ee Global Aouting Pool {GRP connected to an VO pin and can be indivi grammed to be a combinatorial input, o bi-directional I/O pin with 3-state con can source 4mA or sink 8mA. programmed independently for4 pins can be safely drive mixed-voltage systems Eight GLBs, 320 two or one O Megablock (see 1), The outputs of the eight GLBs are connected to a f 32 or 16 universal 1/O cells by the two or one ORPS: Each ispLS! 2128VE device contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional 1/O cells. Allofthese signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized tc minimize timing skew. Clocks in the ispLS! 2128VE device are selected using the dedicated clock pins. Three dedicated clock pins (0, Globat Beuting or an asynchronous clock can be selected on a basis. The asynchronous or Product Term clock be generated in any GLB far its own clack Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128VE are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Voi levels, whereas the open-drain output drives only the specified Voi. The Voh ievel on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a pro- grammable fuse. When this fuse is erased (JEDEC 1), the output is configured as a totem-pole output. When this fuse is programmed (JEDEC O). the output is configured as an open-drain. The default configuration when the device is in buik erased state is totem-pole configuration. The open-drain/totem-pole option is se- lectable through the ispEXPERT software tools. 78 Semiconductor sauaas Corporation External Timing Parameters Over Recommended Operating Conditions Specifications ispLSI 2128VE 4 -180 -135 -100 i PARAMETER conn. # DESCRIPTION MIN. MAX. MIN. | MAX. MIN. IMAX. UNITS tod1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass| ~- | 5.0 - | 75 ~_[10.0; ns tpd2 A 2 | Data Propagation Delay -~ 175] - }100f [13.01 ns fax A 3 | Clock Frequency with Internal Feedback 180); - 135 ~ | 100) - MHz fmax (Ext.) - 4 | Clock Frequency with External Feedback (-e,) | 118 | ~ | 100| - | 77 | - | MHz | fmax (Tog.) - 5 | Clock Frequency, Max. Toggle 200; ~ | 143} - | 100) | Mz | tsul ~ 6 | GLB Reg. Setup Time before Clock, 4 FT Bypass 4.0 - 5.0 65 | - ns | tcot A 7 | GLB Reg. Clock to Output Delay, ORP Bypass - | 3.5 ~ - | 50 ns thi - 8 | GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 - i; 0.07; - ns | tsu2 - | 9 | GLB Reg. Setup Time before Clock 5.0 o| Wpeo| - | ns | tco2 ~ 10; GLB Reg. Clock to Output Delay _ 5 5.0 | - | 60 ns | the ~ |11/}GLBReg.HoldTimeafterClock Too oow | 00 ns | itr A | 12! Ext. Reset Pin to Output Delay 7.0 tool - 135| ns | trv 13 | Ext. Reset Pulse Duration 0 5.0 6.5 ns | tptoeen B | 14| input to Output Enable iol - }120| - (150/ ns tptoedis C | 15 | Input to Output Disable rr 10.0} - 1120] - 11801 ns tgoeen B | 16| Global OE Output Enable - |}50} - | 70) ~ |} 907] ns tgoedis C | 17] Global OE Output Disabie T- i501 - 70; - }90! ns twh Los 18 | External Synchronous Clock Pu ti igh 2.5 - 3.5 ~ 7} 50) - | ns twi 19, External Synchronous C , Low 2.5 3.5 5.0 | ns . Uniess noted otherwise, all parameters use the G 0 . Refer to Timing Modet in this data sheet for further i 4 2 3. Standard 16-bit counter using GRP feedbagy. 4. Reference Switching Test Conditions sectd : be h, ORP and YO clock. Table 2-0030/25 2BVE. 79 ho Q fon] GS a fel