AS7C33128FT32B-65TQIN - Integrated Silicon Solution, Inc.

December 2004

AS7C33128FT32B

3.3V 128K × 32/36 Flow Through Synchronous SRAM

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AS7C33128FT36B

Features

• Organization: 131,072 words × 32 or 36 bits

• Fast clock to data access: 6.5/7.5/8.0/10.0 ns

•Fast OE

access time: 3.5/4.0 ns

• Fully synchronous flow throug h operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte writ e and Glob al write

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate VDDQ

• Linear or interleaved burst control

• Snooze mode for reduced power standby

• Common data inputs and data output s

Selection guide –65 -75 -80 -10 Units

Minimum cycle time 7.5 8.5 10 12 ns

Maximum clock access time 6.5 7.5 8.0 10.0 ns

Maximum operating current 250 225 200 175 mA

Maximum standby current 120 100 90 90 mA

Maximum CMOS standby current (DC) 30 30 30 30 mA

Logic block diagram

Q1 128K × 32/36

Memory

array

Burst logic

CLK

CLR

Address

CLK

Byte w rite

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

Enable

CLK

Enable

CLK

delay

Output

buffer Input

registers

Power

down

DQ[a:d]

36/32

191719

GWE

BWE

ADV

ADSC

ADSP

CLK

CE0

CE1

CE2

LBO

CLK

36/32

[18:0]

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4 Mb Synchronous SRAM products list1,2

1 Core Power Supply: VDD = 3.3V + 0.165V

2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O

VDDQ = 2.5V + 0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect

PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect

FT : Flow-through Burst Syn chronous SRAM

NTD1-PL : Pipelined Burst Synchronous SRAM with NTDTM

NTD-FT : Flow-through Burst Synchronous SRAM with NTDTM

Org Part Number Mode Speed

256KX18 AS7C33256PFS18B PL-SCD 200/166/133 MHz

128KX32

AS7C33128PFS32B PL-SCD 200/166/133 MHz

128KX36 AS7C33128PFS36B PL-SCD 200/166/133 MHz

256KX18 AS7C33256PFD18B PL-DCD 200/166/133 MHz

128KX32

AS7C33128PFD32B PL-DCD 200/166/133 MHz

128KX36 AS7C33128PFD36B PL-DCD 200/166/133 MHz

256KX18 AS7C33256FT18B FT 6.5/7.5/8.0/10 ns

128KX32

AS7C33128FT32B FT 6.5/7.5/8.0/10 ns

128KX36 AS7C33128FT36B FT 6.5/7.5/8.0/10 ns

256KX18 AS7C33256NTD18B NTD-PL 200/166/133 MHz

128KX32

AS7C33128NTD32B NTD-PL 200/166/133 MHz

128KX36 AS7C33128NTD36B NTD-PL 200/166/133 MHz

256KX18 A S7C33256NTF18B NTD-FT 6.5/7.5/8.0/10 ns

128KX32

AS7C33128NTF32B NTD-FT 6.5/7.5 /8.0/10 ns

128KX36 A S7C33128NTF36B NTD-FT 6.5/7.5/8.0/10 ns

1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property

of their respective owners.

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AS7C33128FT36B

Pin arrangement

DQP

/NC

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

/NC

DQP

/NC

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

/NC

LBO

100

CE0

CE1

CE2

CLK

GWE

BWE

ADSC

ADSP

ADV

VDD

TQFP 14 × 20 mm

Note: Pins 1,30,51,80 are NC for ×32

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Functional description

The AS7C33128FT32B/36B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized

as 131,072 words × 32 or 36 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory

expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).

The burst advance pin (ADV) allows subsequ ent int ernally generated burst addresses.

Read cycles are initiate d wit h ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is

ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for

the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the

LBO

input. With

LBO

unconnected or driven high, burst operations use an interleaved count sequence. With

LBO

driven low, the device uses a linear count

sequence.

Write cy cles are performed by di sabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buf fers ar e disabled when

BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented

internally to the next burst address if BWn and ADV are sampled low.

Read or write cycles may a ls o be ini t ia te d wit h ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are

as follows:

•ADSP

must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

•WE

signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33128FT32B and AS7C33128FT36B family operates from a core 3.3V power supply. I/Os use a separate power supply that can

operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.

TQFP capacitance

*Guaranteed not tested

TQFP thermal resistance

Parameter Symbol Test conditions Min Max Unit

Input capacitance CIN*VIN = 0V - 5 pF

I/O capacitance CI/O*VOUT = 0V - 7 pF

Description Conditions Symbol Typical Units

Thermal resistance

(junction to ambient)1

1 This parameter is sampled

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer θJA 40 °C/W

4–layer θJA 22 °C/W

Thermal resistance

(junction to top of case)1θJC 8°C/W

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Signal descriptions

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

Pin I/O Properties Description

CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.

CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is in active,

ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE1, CE2 I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when

ADSC is active or when CE0 and ADSP are active.

ADSP I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.

ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.

ADV I SYNC Advance. Asserted low to continue burst read/write.

GWE I SYNC Global write enable. Asserted low to write all 32/36 bits. When hig h, BWE and BW[a:d] control write

enable.

BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.

BW[a,b,c,d] I SYNC Write enables. Used to cont rol write of individual bytes when GWE is high and BWE is low. If any of

BW[a:d] is active wit h GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,

the cycle is a read cycle.

OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.

LBO ISTATIC

Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When

driven Low, device follows linear Burst order. This signal is internally pulled High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC - - No connect

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Asynchronous Tr uth Table

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus content ion will occur.

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

Burst sequence table

Write enable truth table (per byte)1

1 Key: X = do n’t care, L = low, H = high, n = a, b, c, d;

BWE

BWn

= internal write signal.

Function GWE BWE BWa BWb BWc BWd

Write All Bytes LXXXXX

HLLLLL

Write Byte a HLLHHH

Write Byte c and d HLHHLL

Read HHXXXX

HLHHHH

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read L L Dout

L H High-Z

Write L X Din, High-Z

Deselected L X High-Z

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address 0 00 11 01 1

2nd Address 0 10 01 11 0

2nd Address 0 11 01 10 0

3rd Address 1 01 10 00 1

4th Address 1 11 00 10 0

4th Address 1 11 00 11 0

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Synchronous truth table[4]

CE01

1 X = don’t care, L = low, H = high

CE1 CE2 ADSP ADSC ADV

WRITE

[2]

2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE

HIGH. See "Write enable truth table (per byte)," on page 6 for more information.

OE Address accessed CLK Operation DQ

HXXXLX X X NA L to H DeselectHi−Z

L L X L X X X X NA L to H Deselect Hi−Z

L L X H L X X X NA L to H Deselect Hi−Z

L X H L X X X X NA L to H Deselect Hi−Z

L X H H L X X X NA L to H Deselect Hi−Z

L H L L X X X L External L to H Begin read Q

L H L L X X X H External L to H Begin read Hi−Z

L H L H L X H L External L to H Begin read Q

L H L H L X H H External L to H Begin read Hi−Z

XXXHHL H L Next L to HContinue readQ

XXXHHL H H Next L to HContinue readHi−Z

XXXHHH H L Current L to HSuspend readQ

XXXHHH H H Current L to HSuspend readHi−Z

HXXXHL H L Next L to HContinue readQ

HXXXHL H H Next L to HContinue readHi−Z

HXXXHH H L Current L to HSuspend readQ

HXXXHH H H Current L to HSuspend readHi−Z

L H L H L X L X External L to H Begin write D3

3 For write operation following a READ,

OE must be high before the input data set up time and held high th roughout the input hold time

4 ZZ pin is always Low.

XXXHHL L X Next L to HContinue writeD

HXXXHL L X Next L to HContinue writeD

XXXHHH L X Current L to HSuspend writeD

HXXXHH L X Current L to HSuspend writeD

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Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other con-

ditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.

Recommended operating conditions at 3.3V I/O

Recommended operating conditions at 2.5V I/O

Absolute maximum ratings

Parameter Symbol Min Max Unit

Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V

Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V

Input voltage relative to GND (I/O pi ns) VIN –0.5 VDDQ + 0.5 V

Power dissipation PD–1.8W

DC output current IOUT –50mA

Storage temperature (plastic) Tstg –65 +150 °C

Temperature under bias Tbias –65 +135 °C

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs VDD 3.135 3.3 3.465 V

Supply voltage for I/O VDDQ 3.135 3.3 3.465 V

Ground supply Vss 0 0 0 V

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs VDD 3.135 3.3 3.465 V

Supply voltage for I/O VDDQ 2.375 2.5 2.625 V

Ground supply Vss 0 0 0 V

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DC electrical characteristics for 3.3V I/O operation

DC electrical characteristics for 2.5V I/O operation

† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.

*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC

**VIL min = -1.5 for pulse width less than 0.2 X tCYC

IDD operating conditions and maximum limits

Parameter Sym Conditions Min Max Unit

Input leakage current† |ILI|V

DD = Max, 0V < VIN < VDD -2 2 µA

Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA

Input high (logic 1) voltage VIH Address and control pins 2* VDD+0.3 V

I/O pins 2* VDDQ+0.3

Input low (logic 0) voltage VIL Address and control pins -0.3** 0.8 V

I/O pins -0.5** 0.8

Output high voltage VOH IOH = –4 mA , VDDQ = 3.135V 2.4 – V

Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V

Parameter Sym Conditions Min Max Unit

Input leakage current† |ILI|V

DD = Max, 0V < VIN < VDD -2 2 µA

Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA

Input high (logic 1) voltage VIH Address and control pins 1.7* VDD+0.3 V

I/O pins 1.7* VDDQ+0.3 V

Input low (logic 0) voltage VIL Address and control pins -0.3** 0.7 V

I/O pins -0.3** 0.7 V

Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V

Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V

Parameter Sym Conditions -65 -75 -80 -10 Unit

Operating power supply current1

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.

ICC CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,

IOUT = 0 mA, ZZ < VIL 250 225 200 175 mA

Standby power supply current

ISB All VIN ≤ 0.2V or >

– 0.2V,

Deselected,

f = fMax, ZZ < VIL 120 100 90 90

ISB1 Deselected, f = 0, ZZ < 0.2V,

all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30 30

ISB2

Deselected, f = f

Max

, ZZ

≥

– 0.2V,

all VIN ≤ VIL or ≥ VIH 30 30 30 30

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Snooze Mode Electrical Characteristics

Timing characteristics over operating range

Parameter Sym

–65 -75 -80 –10

Unit Notes

1 See “Notes” on page 16.

Min Max Min Max Min Max Min Max

Cycle time tCYC 7.5 – 8.5 – 10 – 12 – ns

Clock access time tCD – 6.5 – 7.5 – 8.0 – 10 ns

Output enable LOW to data valid tOE – 3.5 – 3.5 – 4.0 – 4.0 ns

Clock HIGH to output Low Z tLZC 2.5 – 2.5 – 2.5 – 2.5 – ns 2,3,4

Data output invalid from clock HIGH tOH 2.5 – 2.5 – 2.5 – 2.5 – ns 2

Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – 0 – ns 2,3,4

Output enable HIGH to output High Z tHZOE – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4

Clock HIGH to output High Z tHZC – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4

Output enable HIGH to invalid output tOHOE 0–0–0– 0 –ns

Clock HIGH pulse width tCH 2.5 – 3.0 – 4.0 – 4.0 – ns 5

Clock LOW pulse width tCL 2.5 – 3.0 – 4.0 – 4.0 – ns 5

Address setup to clock HIGH tAS 1.5 – 2.0 – 2.0 – 2.0 – ns 6

Data setup to clock HIGH tDS 1.5 – 2.0 – 2.0 – 2.0 – ns 6

Write setup to clock HIG H tWS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,7

Chip select setup to clock HIGH tCSS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,8

Address hold from clock HIGH tAH 0.5 – 0.5 – 0.5 – 0.5 – ns 6

Data hold from clock HIGH tDH 0.5 – 0.5 – 0.5 – 0.5 – ns 6

Write hold from cloc k HIGH tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock HIGH tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock HIGH tADVS 1.5 – 2.0 – 2.0 – 2.0 – ns 6

ADSP setup to clock HIGH tADSPS 1.5 – 2.0 – 2.0 – 2.0 – ns 6

ADSC setup to clock HIGH tADSCS 1.5 – 2.0 – 2.0 – 2.0 – ns 6

ADV hold from clock HIGH tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSP hold from clock HIGH tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSC hold from clock HIGH tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns 6

Description Conditions Symbol Min Max Units

Current during Snooze Mode ZZ > VIH ISB2 30 mA

ZZ active to input ignored tPDS 2cycle

ZZ inactive to input sampled tPUS 2cycle

ZZ active to SNOOZE current tZZI 2cycle

ZZ inactive to exit SNOOZE current tRZZI 0

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Key to switching waveforms

Timing waveform of read cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

don’t careFalling inputRising input Undefined

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

CSS

ADVH

HZOE

ADSCS

ADSCH

LOAD NEW ADDRESS

ADV inserts wai t states

A2A1 A3

Dout

Q(A2Ý10) Q(A2Ý11) Q(A3)Q(A2Ý01) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

Q(A1)

HZC

LZOE

CSH

Read

Q(A1) Suspend

Read

Q(A1)

Read

Q(A2) Burst Read

Q(A2Ý01)Read

Q(A3) DSEL

Burst Read

Q(A2Ý10)Suspend

Read

Q(A2Ý10)

Burst Read

Q(A2Ý11)Burst Read

Q(A3Ý01)Burst Read

Q(A3Ý10)Burst Read

Q(A3Ý11)

CE1

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Timing waveform of write cycle

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

CYC

ADSPS

ADSPH

ADSCS

ADSCH

CSS

ADVS

CLK

ADSP

ADSC

Address

BWE

CE0, CE2

ADV

Din

CSH

ADVH

D(A2Ý01)

D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A1) D(A2Ý11)

ADV SUSPENDS BURST

ADSC LOADS NEW ADDRESS

A1 A2 A3

CE1

BW[a:d]

Read

Q(A1) Suspend

Write

D(A1)

Read

Q(A2) Suspend

Write

D(A2)

ADV

Burst

Write

D(A2Ý01)

Suspend

Write

D(A2Ý01)

ADV

Burst

Write

D(A2Ý10)

Write

D(A3)Burst

Write

D(A3Ý01)

ADV

Burst

Write

D(A2Ý11)

ADV

Burst

Write

D(A3Ý10)

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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

CYC

ADSPS

ADSPH

ADVS

CLK

ADSP

Address

BWE

CE0, CE2

ADV

Din

Dout

ADVH

LZOE

LZC

Q(A1)

Q(A3Ý01)

D(A2)

Q(A3)

Q(A3Ý10) Q(A3Ý11)

A1 A2 A3

CE1

HZOE

Suspend

Read

Q(A1)

Read

Q(A1) Suspend

Write

D(A2)

ADV

Burst

Read

Q(A3Ý01)

Suspend

Read

Q(A3Ý11)

ADV

Burst

Read

Q(A3Ý10)

ADV

Burst

Read

Q(A3Ý11)

Read

Q(A2) Read

Q(A3)

BW[a:d]

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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)

Note: ADV is don’t care here.

CYC

ADSCH

CLK

ADSC

ADDRESS

ADSCS

A3 A4 A6

A5 A7 A8 A9

BWE t

CSH

CE0,CE2

CSS

LZOE

HZOE

Q(A1) Q(A2) Q(A3) Q(A4) Q(A9) Q(A10)

D(A6) D(A7)

D(A5)

Dout

Din

READ

Q(A1) READ

Q(A2) READ

Q(A3) READ

Q(A4) WRITE

D(A5) WRITE

D(A6) WRITE

D(A7) WRITE

D(A8) READ

Q(A10)

CE1

A10

D(A8)

READ

Q(A9)

BW[a:d]

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Timing waveform of power down cycle

CYC

ADSPS

CLK

ADSP

DDRESS A1

ADSPS

BWE t

CSH

CE0,CE2

CSS

ADV

LZOE

HZOE

Q(A1) Q(A2)

Dout

Din

ADSC

HZC

PDS

Sleep

ZZ Setup Cycle

PUS

ZZ Recovery Cycle Normal Operation Mode

CE1

Q(A2(

01))

BW[a:d]

READ

Q(A1) READ

Q(A1Ý01) READ

Q(A2) READ

Q(A2Ý01)

State

ZZI

SB2

RZZI

supply

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AC test conditions

= 50

Ω

OUT

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

= 1.5V

for 3.3V I/O;

= V

DDQ

for 2.5V I/O

353

Ω / 1538Ω

5 pF*

319

Ω / 1667Ω

OUT

GND

Figure C: Output load (B)

*including scope

and jig capacitan

Thevenin equivalent:

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O

Notes

1 For test conditions, see AC Test Conditions, Figures A, B, C.

2 This parameter measured with output load condition in Figure C.

3 This parameter is sampled, but not 100% tested.

HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.

5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.

6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs

must meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to

GWE

BWE

BW[a:d].

8 Chip select refers to

CE0

CE1

CE2

AS7C33128FT32B

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AS7C33128FT36B

Package Dimensions

100-pin quad flat pack (TQFP)

TQFP

Min Max

A1 0.05 0.15

A2 1.35 1.45

b0.22 0.38

c0.09 0.20

D13.90 14.10

E19.90 20.10

e0.65 nominal

Hd 15.85 16.15

He 21.80 22.20

L0.45 0.75

L1 1.00 nominal

α0° 7°

Dimensions in

millimeters

He E

A1 A2

AS7C33128FT32B

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AS7C33128FT36B

Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C33128FT32B-65TQCN)

1. Alliance Semiconductor SRAM Prefix

2. Operating voltage: 33 = 3.3V

3. Organization: 128 = 128K

4. Flowthrough mode

5. Organization: 32 = X32; 36 = X36

6. Production version: B= product revision

7. Clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]

8. Package type: TQ = TQFP

9. Operating temperature: C = Commercial (

0° C to 70° C); I = Industrial (

-40

° C to 85° C)

10. N = Lead free part

Ordering information

Package Width –65 -75 –80 –10

TQFP x32 AS7C33128FT32B-

65TQC AS7C33128FT32B-

75TQC AS7C33128FT32B-

80TQC AS7C33128FT32B-

10TQC

TQFP x32 AS7C33128FT32B-

65TQI AS7C33128FT32B-

75TQI AS7C33128FT32B-

80TQI AS7C33128FT32B-

10TQI

TQFP x36 AS7C33128FT36B-

65TQC AS7C33128FT36B-

75TQC AS7C33128FT36B-

80TQC AS7C33128FT36B-

10TQC

TQFP x36 AS7C33128FT36B-

65TQI AS7C33128FT36B-

75TQI AS7C33128FT36B-

80TQI AS7C33128FT36B-

10TQI

Part numbering guide

AS7C 33 128 FT 32/36 B–XX TQ C/I X

12345678910

AS7C33128FT32B

trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make

changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.

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Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C33128FT32B

AS7C33128FT36B

Document Version: v.1.1

AS7C33128FT36B