General Description The Maxim ICL7106 and iCL7107 are monolithic analog to digital converters. They have very high input imped- ances and require no external display drive circuitry. On- board active components include polarity and digit driv- ers, segment decoders, voltage reference and a clock circuit. The ICL7106 will directly drive a non-multiplexed liquid crystal display (LCD) whereas the ICL7107 will di- rectly drive a common anode light emitting diode (LED) display. Versatility and accuracy are inherent features of these converters. The dual-slope conversion technique auto- matically rejects interference signals common in industri- al environments. The true differential input and reference are particularly useful when making ratiometric measure- ments (ohms or bridge transducers). Maxim has added a zero-integrator phase to the ICL7106 and ICL7107, elimi- nating overrange hangover and hysteresis effects. Final- ly, these devices offer high accuracy by lowering rollover error to less than one count and zero reading drift to less than 1pV/C. Applications These devices can be used in a wide range of digital panel meter applications. Most applications, however, in- volve the measurement and display of analog data: Conductance Current Speed Material Thickness Pressure Voltage Resistance Temperature Typical Operating Circuit | LCD Display ~(LILiLi anatog? J { Li Li Li INPUT I Li aR a 33 TO ANALOG COMMON {P32) Veer FULL SCALE INPUT ee 1.000 V | ___100.0 mv | [2.000 V (200.0 mv _ SAA ALSVI 3% Digit A/D Converter Features @ Improved 2nd Source! (See 3rd page for Maxim Advantage) @ Guaranteed first reading recovery from overrange @ On board Display Drive Capabilityno external circuitry required LCD-ICL7 106 LED-ICL7107 @ High impedance CMOS Differential Inputs @ Low Nolse (< 15, p-p) without hysteresis or overrange hangover @ Clock and Reference On-Chip @ True Differential Reference and Input @ True Polarity Indication for Precision Null Applications @ Monolithic CMOS design Ordering Information PART TEMP. RANGE PACKAGE ICL7106CPL OCto+70C 40 Lead Plastic DIP ICL7106CJL_ OCto+70C 40Lead CERDIP ICL7106CQH OCto+70C 44 Lead Plastic Chip Carrier ICL7106C/D OCto +70C Dice ICL7107CPL OCto +70C 40Lead Plastic DIP ICL7107GJL OCto +70C 40Lead CERDIP ICL7107CQH OCto +70C 44 Lead Plastic Chip Carrier ICL7107C/D OCto+70C Dice a Pin Configuration vt OSC 1 DI OSC 2 C1 osc 3 vs BI TEST Al REF HI Ft REF LO G1 Crer EI MAXIM REF D2 ict7106 COMMON c2 I1CL7107 IN HI te 82 IN LO 10S 42 A/Z F2 BUFF E2 [a INT 33 Ea & TENS) . 83 Eg G2 100'S Fs oy c3 E3 A3 100'S 1000'S-AB4 [3] G3__t POL Gy BP(7106) GND(7107) (MINUS SIGN) See fast page for Plastic Chip Carrier Pin Configuration. The Maxim Advantage signifies an upgraded quality level. At no additional cost we offer a second-source device that is subject to the following: guaranteed performance over temperature along with tighter test specifications on many key parameters; and device enhancements, when needed, that result in improved performance without changing the functionality. MAAINM Maxim integrated Products 1-119 ZOLL/9OLLTIONICL7106/7107 3% Digit A/D Converter ABSOLUTE MAXIMUM RATINGS Supply Voitage Power Dissipation (Note 2) 1CL7106, Vt toV~ oo cece eee e eee eee 15V Plastic Package .......0.0cece cece eee e cee 1000mW IGL7107, V+ toGND........-- 2 eee eee eee +6V Operating Temperature 0C to +70C 1CL7107, V~ to GND .... 06. cece ee eee eens 9V Storage Temperature ...........--555 -65C to +160C Analog input Voltage (either input)(Note 1)....... V+ toV- Lead Temperature (Soldering, 60 sec) ......... +300C Reference Input Voltage (either input)........... Vt toV- Clock Input ICL7106 0... ec eee cee eee eee eens TEST to V+ Co Uy fa | Y a GND to V+ Note 1: Input voltages may exceed the supply voitages, provided the input current is limited to + 100pA. Note 2: Dissipation rating assumes device is mounted with alt leads soldered to printed circuit board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS wore ) CHARACTERISTICS CONDITIONS MIN TYP MAX UNITS Zero input Reading Vin = 0.0V 000.0 +000.0 +000.0 Digital Reading Full Scate = 200.0mV . Ratiometric Reading Vin = VREF 999 999/1000 1600 Digital Reading Vrer = 100mV Rollover Error (Difference in Vin = +Vin = 200.0mV -1 #2 +1 Counts reading for equal positive and negative reading near Full Scale) Linearity (Max. deviation from Full scale = 200mV -1 2 +4 Counts best straight line fit) or full scale = 2.000V Common Mode Rejection Ratio Vom = +1V, Vin = OV. 50 uV/V (Note 4} Full Scale = 200.0mV Noise (Pk-Pk value not exceeded Vin = OV 15 uv 95% of time) Full Scale = 200.0mV Input Leakage Current Vin =O 1 10 pA Zero Reading Drift Vin = 0 0.2 1 nVv/C 0 < Ta < 70C Scale Factor Temperature Vin = 199.0mV 1 5 pem/c Coefficient 0 < Ta < 70C (Ext. Ref. OQppm/*C) V* Supply Current (Does not Vin =0 0.8 1.8 mA -include LED current for 7107) V~ supply current 7107 only 0.6 18 mA Analog Common Voltage (With 25kf between Common & 2.4 2.8 3.2 Vv respect to Pos. Supply) Pos. Supply Temp. Coeff. of Analog Common 25kN between Common & 80 pem/Cc (With respect to Pos. Supply! Pos. Supply 7106 ONLY V to V7 = 9V 4 5 6 V Pk-Pk Segment Drive Voitage, Pk-Pk Backplane Drive Voltage (Note 5) 7107 ONLY Vv" = 5.0V 5 8.0 mA Segment Sinking Current Segment voltage = 3V (Except Pin 19) (Pin 19 only) 10 16 mA Note 3: Uniess otherwise noted, specifications apply to both the 7106 and 7107 at Ta=25C, foLock = 48kHz. 7106 is tested in the circuit of Figure 1. 7107 is tested in the circuit of Figure 2. Note 4: Refer to Differential Input discussion. Note 5: Backpiane drive is in phase with segment drive for off segment, 180 out of phase for on segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. The electrical characteristics above are a reproduction of a portion of Intersils copyrighted (1983/1984) data book. This information Goes not constitute any representation by Maxim that Intersils products will perform in accordance with these specifications. The Electrical Characteristics Table along with the descriptive excerpts from the original manutacturers data sheet have been included in this data sheet solely for comparative purposes. 1-120 MAAIMMAAL/VI 3%2 Digit A/D Converter Guaranteed Overioad Recovery Time Key Parameters Guaranteed over Temperature @ Significantly improved ESD Protection (Note 7) Negligible Hysteresis @ Low Noise @ Maxim Quality and Reliability @ increased Maximum Rating for Input Current (Note 8) ABSOLUTE MAXIMUM RATINGS: This device conforms to the Absolute Maximum Ratings on adjacent page. ELECTRICAL CHARACTERISTICS: Specifications below satisfy or exceed all tested parameters on adjacent page. = 9V; Ta = 25C; fcLock = 48kHz; test circuit - Figure 1; unless noted) PARAMETERS CONDITIONS MIN TYP MAX UNITS ero input Reading Vin = 0.0V, Full Scale = 200.0mV - \ Ta = 25C (Note 6) 000.0 +000.0 + 000.0 Digital : : : @ < Tg < 70C (Note 10) 000.0 +000.0 +000.0 Reading Ratiometric Reading Vin = Vrer. Vrer = 100mV Ta = 25C (Note 6) ; 999 999/1000 1000 Digital a 2 Os Ta <.70C (Note 10) | 998. 9990/1000 1001 Reading ollover Error (Difference in Vin = +Vin = 200.0mV reading for equal positive and Ta = 25C (Note 6) -1 +.2 +1 Counts negative reading near Full Scale) 0 < T, = 70C (Note 10) +.2 Linearity (Max. deviation from Full Scale = 200.0mV -1 +.2 +1 Counts best straight line fit) or full scale = 2.000V Common Mode Rejection Ratio Vom = +1V, Vin = OV Full Scale = 200.0mV 50 pV/V Noise (Pk-Pk value not exceeded Vin = OV 95% of time) Full Scale = 200.0mV 15 pV Input Leakage Current: Vin = 0 ; 2 Ta = 25C (Note 6) 1 10 pA go Eee ea eo ees Bete 0's Ty: < 70C: : E20 200-8 Zero Reading Drift Vin = 0 0 < Ta < 70C (Note 6) 0.2 1 pVEC Scale Factor Temperature Vin = 199.0mV Coefficient 0 < Ta < 70C 1 5 ppm/C (Ext. Ref. Oppm/*C) (Note 6) V+ Supply Current: Vin = 0 {Does hat inotude LED curent Ta = 25C 0.6 1.8 mA for 7107) MS Ta <:70C: mae eee 2 V Supply Current (71 07 only) 0.6 1.8 mA Analog Common Voltage (with 25k. between Common & 2.4 2.8 3.2 Vv respect to Pos. Supply) Pos. Supply Temp. Coeff. of Analog Common 25kN. between Common & 75 ppm/C (with respect to Pos. Supply) Pos. Supply 7106 Only (Note 5) V+ toV- = 9V 4 5 6 Vv Pk-Pk Segment Drive Voltage, Pk-Pk Backplane Drive Voltage 7107 OnlySegment Sinking Current | V+ = 5.0V 5 8.0 mA (Except Pin 19) Segment Voltage = 3V (Pin 19 only) 10 16 mA [ With Respect to V+: ee eg - 6 MO . : _ Navohanging trom + 10 we eg 4 Measurement. Sto OV . : EEE fick Ee yet ees : Cycles Note 6: Test condition is V\,, applied between pin IH-HI and IN-LO through a 1M2 series resistor as shown in Figures 1 and 2. Note 7: All pins ara designed to withstand electrostatic discharge (ESD) levels in excess of 2000V. (Test circuit per Mil Std 883, Method 3015.1) Note &: Input voltages may exceed the supply voltage provided the input current is limited to +1mA (This revises Note 1 on adjacent page). Note 9: Number of measurement cycles for display to give accurate reading. Note 10: 1MQ resistor is removed in Figures 1 and 2. MAAINVI 1-121 LOLL/9OLLZIONICL7106/7107 3% Digit A/D Converter 0.1 uF LCD elm es Display say af Ber SF UCIT ane Tm ae secur TUTTI INPUT INLO po. pee___T 21 MINUSSIGN | BACKPLANE P DRIVE COMMON 1 a BUFF ud Ka > a7 kL? & 0.47 pF ng => 29 at 36 VREF REF HI 0.22nF 10K! [th > > INT REFLO ve losc2 Osc, OSC 39738 Cos [40 0.1 uF LED acligs Pee VME. nw CREF ar _(LILiLi OW in 2-19 J SEGMENT a a 0 { ANALOG got ye 22:25 | DRIVE f8 tS INPUT. 20 INLO POL 21 a COMMON 17> BUFF ark! & O47uF MAXIM Rosc TO ANALOG 1017106 NT 100 pF COMMON (P32) FULLSCALE Ver INPUT pee a 100.0 mv | | 2000 mv 29 KF AR ag VREF 4 REF HI LOK! 0.22uF a T2 38 > INT REFLO 26 loscg osc3 08cy 7 O sv 39738 cose Feo MAXIM H ICL7107 Rosc N TO ANALOG WA COMMON {P32) 100k! 100 pF FULL SCALE Vrer | ANPUT 200.0 mv 100.0 mv! : __I Figure 1. Maxim ICL7106 Typical Operating Circuit tC CAalog Section Figure 3 shows the Block Diagram of the Analog Section for the ICL7136. Each measurement cycle is divided into four phases: 1. Auto-Zero (A-Z) 2. Signal Integrate (INT) 3. Reference De-Integrate (Dl) 4. Zero Integrator (Zl) Auto-Zero Phase Three events occur during auto-zero. The inputs, IN-HI and IN-LO, are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. And lastly, a feedback loop is closed around the system to charge the auto-zero capacitor Caz to compensate for offset voltages in the comparator, buffer amplifier and integrator. The inherent noise of the system determines the A-Z accuracy. Signal Integrate Phase The internal input high (IN-H!) and input low (IN-LO) are connected to the external pins, the internal short is re- moved and the auto-zero loop is opened. The converter then integrates the differential voltage between IN-HI and IN-LO for a fixed time. This differential voltage can be within a wide common-mode range (within one volt of either supply). If, however, the input signal has no return with respect to the converter power supply, IN-LO can be tied to analog common to establish the correct common- mode voltage. The polarity of the integrated signal is de- termined at the end of this phase. Reference De-integrate IN-HI is connected across the previously charged refer- ence capacitor and IN-LO is internally connected to ana- log common. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The input signal determines the time required for the output to re- turn to zero. The digital reading displayed is: 1000 x SIN. VREF 1-122 Figure 2. Maxim ICL7107 Typical Operating Circuit Zero Integrator Phase Input low is shorted to analog COMMON and the refer- ence capacitor is charged to the reference voltage. A feedback loop is closed around the system to input high, causing the integrator output to return to zero. This phase normally lasts between 11 and 140 clock pulses but is extended to 740 clock pulses after a heavy over- range conversion. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common-mode error is a rollover voltage. This is caused by the reference capacitor losing or gaining charge to stray capacitance on its nodes. The reference capacitor can gain charge (increase voltage) if there is a large common-mode voltage. This happens during de-in- tegration of a positive signal. In contrast, the reference capacitor will lose charge (decrease voltage) when de-in- tegrating a negative input signal. Rollover error is caused by this difference in reference for positive or negative input voltages. This error can be held to less than half a count for the worst-case condition by selecting a refer- ence capacitor that is large enough in comparison to the stray capacitance. (See component value selection.) Differential Input Differential voltages anywhere within the common- mode range of the input amplifer can be accepted by the input (specifically from 1V below the positive supply to 1.5V above the negative supply). The sys- tem has a CMRR of 86dB (typ) in this range. Care must be exercised, however, to ensure that the integrator output does not saturate, since the in- tegrator follows the common-mode voltage. A large positive common-mode voltage with a near full-scale negative differential input voltage is a worst-case condition. When most of the integrator output swing has been used up by the positive common-mode voltage, the negative input signal drives the integra- tor more positive. The integrator swing can be re- duced to less than the recommended 2V full-scale swing with no loss of accuracy in these critical MAXIM3% Digit A/D Converter vi v REF 6.8 vot 2 5.Bk:: ZENER Ly err 106 |" A 1 DIGITAL aero A 1007107 \ SECTION Maxim | z REF HI A 1CL7106 104.7907 lav REFLO [* ? ner eRENce . common a To MAXIM 1L7106 1CL7107 Figure 3. Analog Section of ICL7106/HCL7107 applications. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Common The primary purpose of this pin is to set the common- mode voltage for battery operation. This is useful when using the ICL7106, or for any system where the input signals are floating with respect to the power supply. A voltage of approximately 2.8V less than the positive sup- ply is set by this pin. The analog common has some of the attributes of a reference voitage. If the total supply voltage is large enough to cause the zener to regulate (>7V), the common voltage will have a tow output im- pedance (approximately 150), a temperature coefficient of typically 80ppm/C, and a low voltage coefficient (.001%). The internal heating of the ICL7107 by the LED display drivers degrades the stability of Analog Common. The power dissipated by the LED display drivers changes with the displayed count, thereby changing the tempera- ture of the die, which in turn resuits in a small change in the Analog Common voltage. This combination of vari- able power dissipation, thermal resistance, and tempera- ture coefficient causes a 25-80nV increase in noise near full scale. Another effect of LED display driver pow- er dissipation can be seen at the transition between a full scale reading and an overload condition. Overload is a low power dissipation condition since the three least sig- nificant digits are blanked in overload. On the other hand, a near full scale reading such as 1999 has many seg- ments turned on and is a high power dissipation condi- tion. The difference in power dissipation between over- load and full scale may cause a ICL7107 with a negative temperature coefficient reference to cycle between over- load and a near full scale display as the die alternately heats and cools. An 1CL7107 with a positive TC refer- ence will exhibit hysteresis under these conditions: once put into overload by a voltage just barely more than full scale, the voltage must be reduced by several counts before the ICL7107 will come out of overload. MAAKIM Figure 4. Using an External Reference None of the above probiems are encountered when us- ing an external reference. The ICL7106, with its low pow- er dissipation, has none of these problems with either an external reference or when using Analog Common as a reference. During auto-zero and reference integrate the internal in- put low is connected to Analog Common. If IN-LO is dif- ferent from analog-common, a common-mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. In some. applications, however, IN-LO will be set at a fixed known voltage (e.g., power supply common). Whenever possible analog common should be tied to the same point, thus removing the com- mon-mode voltage from the converter. The same hoids true for the reference voltage. If convenient, REF-LO should be connected to analog common. This will re- move the common-mode voltage from the reference sys- tem. Analog Common is internally tied to an N-channel FET that can sink 30mA or more of current. This will hoid the Analog Common voltage 2.8V below the positive supply (when a source is trying to pull the common line positive). There is only 10;A of source current, however, so COM- MON may easily be tied to a more negative voltage, thus over-riding the internal reference. Test Two functions are performed by the test pin. The first is using this pin as the negative supply for externally gener- ated segment drivers or any other annunciators the user may want to include on the LCD. This pin is coupled to the internally generated digital supply through a 5000. resistor. This application is illustrated in Figures 5 & 6. A lamp test is the second function. All segments will be turned on and the display should read 1888, when TEST is pulled high (V+). Caution: in the lamp test mode, the segments have a constant dc voltage (no square wave). This can burn the LCD if left in this mode for several minutes. 1-123 LOKL/9OLLIONICL7106/7107 3% Digit A/D Converter vt MAXIM 1CL7106 To Lcd PR T DECIMAL POINT TEST oO TOLCD BACKPLANE Figure 5A. Fixed Decimal Point Drivers 1 yt Pps Ot HE - d TO LCD P > DECIMAL POINT MAXIM > 1CL7106 = Ma 21 BP BACKPLANE Figure 58. Fixed Decimal Point Drivers = 1 TOLCD maxim DECIMAL . t DECIMAL 1L7106 POINT ' POINTS SELECT ' The ICL7107 is identical to the ICL7106 except that the backplane and drivers have been replaced by N-channel segment drivers. The |CL7107 is designed to drive com- mon anode LEDs with a typical segment current of 8mA. Pin 19 (thousands digit output) sinks current from two LED segments, and has a 16mA drive capability. The polarity indication is on' for negative analog inputs, for both the 1CL7106 and ICL7107. If desired IN-HI and IN-LO can be reversed giving a on for positive analog inputs. System Timing The clocking circuitry for the ICL7106 and ICL7107 is illustrated in Figure 7. Three approaches can be used: 1. Accrystal between pins 39 and 40. 2. An external oscillator connected to pin 40. 3. An RC oscillator using all three pins. The decade counters are driven by the clock frequency divided by four. This frequency is then further divided to form the four convert-cycle phases, namely: signal inte- grate (1000 counts), reference de-integrate (0 to 2000 counts), auto-zero (260 to 2989 counts) and zero integra- tor (11 to 740). The signal integration should be a multiple of 60Hz to achieve a maximum rejection of 60Hz pickup. Oscillator frequencies of 30kHz, 40kHz, 48kHz, 60kHz, 80kHz, 120kHz, 240kHz, etc., should be selected. Similarly, for 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 66%4kHz, 50kHz, 40kHz, etc., are appropriate. Note that 40kHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and 440Hz). Auto-zero receives the unused portion of reference deintegrate for signals less than full-scale. A complete measurement cycle is 4,000 counts (16,000 clock puls- es), independent of input voltage. As an example, an os- cillator frequency of 48kHz would be used to obtain three readings per second. Figure 6. Exclusive OR Gate for Decimal Point Drive Digital Section The digital section for the 1CL7106 and ICL7107 is illus- trated in Figures 8 and 9. In Figure 8, an internal digital ground is generated from a 6V zener diode and a large P- channel source follower. This supply is made stiff to ab- sorb the large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is calculated by dividing the clock frequency by 800. For example, with a clock frequency of 48kHz (3 readings per second), the backplane will be a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude. Note that these are out-of- phase when the segment is ON and in-phase when OFF. Negligible dc voltage exists across the segments in ei- ther case. 1-124 To COUNTER 2-3M0 49 CRYSTAL 0 RC NETWORK EXTERNAL OSCILLATOR TO TEST PIN ON ICL7106 TO GROUND PIN ON ICL7107 Figure 7. Clock Circuits MAAIM3% Digit A/D Converter +O tle, (OO ot | L.CO PHASE DRIVER 7 SEGMENT 7 Ea 7 SEGMENT] DEC Ea DECOr 1 ' i ' t t ( 1 | 1 4 ' i | LATCH | ' ' ah Le anit rHousan | rene | rs | }-@ ' ! | ! I 6 i TYPICAL SEGMENT OUTPUT a SEGMENT OUTPUT INTERNAL DIGITAL GROUND. TO SWITCH DRIVERS J FROM COMPARATOR OUTPUT mn CLOCK + | LOGIC CONTROL INTERNAL DIGITAL GROUND. : osc1 osc2 > 4.0862 MAM TF ICL7 106 Figure 8. 1CL7106 Digital Section . a 7, a, ie i ee - m { im lt Display & . c 6 Eo $k Sarlientientientientientiantientionttenieattedindicdiedtetediediedtatenttetedtte arto tHriht--~----a 1 TYPICAL SEGMENT OUTPUT 1 1 7 SEGMENT | 17 SEGMENT 917 SEGMENT : O5mA, DECODE DECODE DECODE ; To ' SEGMENT LATCH ( amA I 1 1 OIGITAL GROUND THOUSAND 4 HUNDREDS TENS units ! | 1 1 TO SWITCH DRIVERS <J i FROM COMPARATOR OUTPUT VW } | ov Le test ! 5 2td cicitat crouno | 39 Ey - He 4; - ee ~----- ---- ~-- EE Ee J osc 3 ose 3 MAKI 4- ICL7107 Figure 9. 1CL7107 Digital Section MAKULM! 1-125 LOLL/9OKLTOIICL7106/7107. 3% Digit A/D Converter Component Value Selection Auto-Zero Capacitor The noise of the system is influenced by the auto-zero capacitor. For the 2V scale, a 0.047uF capacitor is ade- quate. A capacitor size of 0.47pF is recommended for 200mV full scale where low noise operation is very im- portant. Due to the ZI phase of Maxims |CL7106/7, noise can be reduced by using a larger auto-zero capaci- tor without causing hysteresis or overrange hangover problems seen in other manufacturers ICL7106/7 which do not have the ZI phase. ' Reference Capacitor For most applications, a 0.14F capacitor is acceptable. However, a large value is needed to prevent rollover er- ror where a large common-mode voltage exists (i.e., the REF-LO pin is not at analog common) and a 200mV scale is used. Generally, the roll over error will be heid half a count by using a 1.0uF capacitor. Integrating Capacitor To ensure that the integrator will not saturate (at approximately 0.3V from either supply), an appropri- ate integrating capacitor must be selected. A nominal +2V full-scale integrator swing is accept- able for the ICL7106 or ICL7107 when the analog common is used as a reference. A nominal +3.5 to 4 volt swing is acceptable for the ICL7107 with a +5V supply and analog common tied to supply ground. The nominal values for Cnt is 0.22uF for three read- ings per second. (48kHz clock). These values should be changed in inverse proportion to maintain the same output swing if different oscillator frequencies are used. The integrating capacitor must have low dielectric ab- sorption to minimize linearity errors. Polypropylene ca- pacitors are recommended for this application. Integrating Resistor The integrator and the buffer amplifier both have a class A output stage with 100A of quiescent current. 20,A of drive current can be supplied with negligible non-linearity. This resistor should be large enough to maintain the am- plifiers in the linear region over the entire input voltage range. The resistor value, however, should be low enough that undue leakage requirements are not placed on the PC boards. For a 200mvV scale, a 47K. resistor is recommended; (2V scale/470KQ). Oscillator Components A 100KQ resistor is recommended for all ranges of fre- quency. By using the equation f = 0.45/RC, the capaci- tor value can be calculated. For 48kHz clock, (3 read- ings/second), the oscillator capacitor plus stray capaci- tance should equal 100pF. 1-126 Reference Voltage An analog input voltage of Vin equal to 2 (Vref) is re- quired to generate full scale output of 2000 counts. Thus, for 2V and 200mvV scales, Vaer should equal 1V and 100mV respectively. However, there will exist a scale factor other than unity between the input voltage and the digital reading in many applications where the A/D is connected to a transducer. As an example, the designer may like to have a full scale reading in a weighing system when the voltage from the transducer is 0.682V. The designer should use the input voltage directly and select Vref at 0.341V instead of dividing the input down to 200mV. Suitable values of the capacitor and integrating resistor would be 0.22uF and 120KQ. This provides fora slightly quieter system and also avoids a divider network on the input. The 1CL7107 can accept input signals up to +3.5V with +5V supplies. Another advantage of this system occurs when the digital reading of zero is desired for Vin # zero. Examples are temperature and weighing systems with variable tare. By connecting the voltage transducer between Vin positive and common, and the variable (or fixed) offset voltage between common and Vin negative, the offset reading can be conveniently generated. 1CL7107 Power Supplies The ICL7107 is designed to operate from +5V supplies. However, when a negative supply is not available it can be generated from a clock output with two diodes, two capacitors, and an inexpensive IC. Refer to Figure 10. Alternatively a 5V supply can be generated using Max- ims ICL7660 and two capacitors. A negative supply is not required in selected applications. The conditions to use a single + 5V supply are: @ An external reference is used. @ The signal is less than + 1.5V. @ The input signal can be referenced to the center of the common-mode range of the converter. See Figure 18: osc 1 Osc 2 Osc 3 MAXIM 1047107 GND TL Figure 10. Generating Negative Supply from + 5V MAAIWI____ Applications Information Heat is generated within the ICL7107 IC package due to the sinking of LED display current. Fluctuating chip tem- perature can cause a display to change reading if the internal voltage reference is used. By reducing the power being dissipated such variations can be reduced. The ICL7107 power dissipation is reduced by reducing the LED common anode voltage. The curve tracer illustration showing the relationship between the output current and the output voltage for typical ICL7107 is seen in Figure 11. Note that the typical 1CL7107 output is 3.2V (point A), since the typical LED has 1.8V across it (@mA drive cur- rent) and its common anode is connected to + 5V. Maxi- mum power dissipation is: 8.1mMA X 3.2V x 24 segments = 622mW Once the ICL7107 output voltage is above 2V, the LED current is essentially constant as output voltage increas- es. Point B illustrates that reducing the output voltage by 0.7V results in 7.7mA of LED current, (only 5% reduc- tion). The maximum power dissipation is a reduction of 26% as calculated by: 7.7MA X 2.5V xX 24 segments = 462mW As illustrated in Figure 12, reduced power dissipation is easy to obtain. This can be accomplished by placing ei- ther a 5.10 resistor or a 1 amp diode in series with the display (but not in series with the ICL7107). Point C of Figure 18 illustrates that a resistor will reduce the ICL7107 output voltage when all 24 segments are On. The output voltage will increase when segments are turned Off. On the other hand, the diode will result in a relatively steady output voltage, around Point B. The re- sistor not only reduces the change in power dissipation as the display changes, but. also limits the maximum power dissipation. This is due to the fact that as fewer segments are On, each On output drops more volt- age and current. The resistor circuit will change about 230mW when changing from the best case of six seg- ments, a 111 display, to worst-case of a 1888 dis- play. If the resistor is removed, the power dissipation change will be 470mW. The resistor, therefore, will re- duce the effect of display dissipation on reference volt- age drift by about 50%. As more segments are turned off, the change in LED brightness caused by the resistor is almost unnoticeable. A diode may be used instead of the resistor if it is impor- tant to maintain a steady level of display brightness. MAALWI 3% Digit A/D Converter = "-~ NWHOAHN DO OO mA Lee 123 45 67 8 9 10 VSEGMENT Figure 11. 1CL7107 Output Current vs. Output Voltage CISPLAY tot l= 21 1 10 20 CTETEPT?t TP ri rrr iirt ces === 1 inaoor | _(LILiki LED Display Figure 12. Diode or Resistor Limits Package Power Dissipation 1-127 LOLL/9OILTOIICL7106/7107 3% Digit A/D Converter ____. Typical Applications TOPINI TOPINY Osc, 100 Kk osc, TOO Ka 082 f}- osc3t}"4 osc, f}} - TEST SET Var * 1.00 TEST SET Vpgr = 100.0mV REF Hi REF Mi AEF LO REF Li VA +5V Chee Caer ar kn 22kn Cree Caer LS TMS? + IN Ht IN HI =F IN MAXIMA MAXIMA __4-_o 1CL7106 INLO wci7107 NAO AZ an 0.47uF ATR ' BUFF BUFF } INT INT O225F ' v- vo 4 bY G2 G& ' Ss TO DISPLAY a TO DISPLAY ' Gs : TO BACKPLANE GNoP}$ ~~ > Figure 13. 1CL7106 using the Internal Reference. 2V Full Scale; 3 Readings Figure 14. 1CL7107 Internal Reference. 200mV Full Scale; 3 Readings per per Second. Second, Vin Tied to GND for Single Ended Inputs. (See discussion under Analog Common) . TO PIN 1 Ve aa vi osc, Dy ose, Cyc: oscaty Cia, TEST Ay REE HIE) TO LOGIE Veco q Fy REF LO r 10 & Caer) Sho Qe Crerb) Cp. common) MARIO (hc. INHID) 1CL7 106 Ce: iwcoft Az az) Ore euFFI) OPRANGE q al A oy A Bs &D yrs ea VIRANE rye: as TO DISPLAY tf} AB, Ga q te OR 74C10 = 04077 Figure 15. 1CL7107 Measuring Ratiometric Values of a Load Cell. Desired Figure 16. Circuit for Developing Under Range and Over Range Signals from Sensitivity is Determined by Resistor Values Within the Bridge. 1CL7106 Outputs. TOPINT TOPIN' __- wr ery OSC, 100 ki osc, = ose} oO osc: ss 086 BF Earring tn nv AEF HI REF Hi "Cie . nero vy ay nero 1 Cher rer OF Ca, Cper$}- WW COMMON COMMON }}-_# + IN HI arrriaed MAXIM IN Hi} "Wr . flr 107 INLO bg ON #eL7107 into per Vom 28 Aft az O.4IuF ATKR BUFF BUFF INT wt pal vo vo vo G2 ap TO DISPLAY Ss a TO DISPLAY 3 G3 GND + Figure 17. 1CL7107 with a 1.2V External Band-Gap Reference Vin tied to Figure 18. 1CL7107 Operated from Single + 5V Supply. An external Refer- common. ence must be used in this application. 1-128 MAAILM!3% Digit A/D Converter Typical Applications L eZ was r0kKas 3 3 3 REFERENCE THERMOCOUPLE iNLO TYPE J THERMOCOUPLE TEMP SENSOR 0.01uF SENSOR COLD we R6 JUNCTION [- A _ Ma 30 ka | COMPENSATION t-} ona $e hem 0 {20 TURN) A DISPLAY ZL 100 ka $. REF Hi - R?7 SILICON NPN (20 TURN) 3 (MOTOROLA MPS3704 ) FOR EXAMP!.. ] REF LO COMMON \ SCALE FACTOR ZERO AQJUST ADJUST SCALE FACTOR RI RS Figure 20. Digital Thermometer ADJUST S24ka AM R3 & |100pF : hooka> ara ase tes DISPLAY Pi le Pe dd ~+ 40, 38 36 34 32 30 28 26 24 22 39 3735 33 Bh 29 27 25 3 2d REF Hi maxim = Rrerenence Recrenenct D) ICL7106 REF LO 1 3. 5 7. 9 W138 15 179 2 4 6 8 10 12 14 16 18 20 HN Leo Leo PEPETEPPPr i Prrrrrrrrt peer vent a ann DISPLAY me $ F Rum COMMON Figure 19. Thermocouple Thermometer. This circuit operates with approxi- mately 50mvV reference, so the 50.4uV/C output of a Type J thermocouple 1CL7106 system setup ICL7106 system setup results in 1 count/C. for 2V reference for 200mV reference IN LO COMMON Figure 22. Ratiometric Ohms Measurement To LOGIC Ve d rea se 228 ucars t Be 5 +|oE @ INVERT Locic Be ND OF CONVERSION d 5 2 TACSIS e 9 INVERT, g INVERT als 100 7acgis BF 200 ch 400 DL 800 4 l * ICL7106/7 only. See data sheet for values for other parts. * For ICL7107, tie INVERT high, and omit EX-NOR gates. Figure 23. Simple End-of-Conversion Detector Figure 21. BCD Output from 7-Segment Drivers MAXL/VI 4-129 LOLL/9OLKLIONIICL7106/7107 3% Digit A/D Converter Chip Topographies ICL7T106 BUFF t 0.130" ~~ (3.30mm) ACLTI07 O3 f2 Fz Az By Cz O Fr Gy Fr AZ | INH | Cope | BUFF = INLO COMMON Cyr 0130" (3.30mm) Pin Configuration 1047107 ICL7126 10L7136 44 Lead Plastic Chip Carrier (Quad Pack) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 1-130 MAAKIM