_General Description The Maxim ICL7106 and ICL7107 are monolithic analog to digital converters. They have very high input imped- ances and require no external display drive circuitry. On- board active components include polarity and digit driv- ers, segment decoders, voltage reference and a clock circuit. The ICL7106 will directly drive a non-multiplexed liquid crystal display (LCD) whereas the ICL7107 will di- rectly drive a common anode light emitting diode (LED) display. Versatility and accuracy are inherent features of these converters. The dual-slope conversion technique auto- matically rejects interference signals common in industri- al environments. The true differential input and reference are particularly useful when making ratiometric measure- ments (ohms or bridge transducers). Maxim has added a zero-integrator phase to the ICL7106 and ICL7107, elimi- nating overrange hangover and hysteresis effects. Final- ly, these devices offer high accuracy by lowering rollover error to less than one count and zero reading drift to less than 1pV/C. _ Applications These devices can be used in a wide range of digital panel meter applications. Most applications, however, in- volve the measurement and display of analog data: Pressure Conductance Voltage Current Resistance Speed Temperature Material Thickness _____Typical Operating Circuit | LCD Display UII INPUT | =| It 4 4 8 rey VREF g TO ANALOG COMMON {P32} FULL SCALE VREF INPUT 2.900 V 1.000 V 200.0 mV 100.0 mv JA AALMVI 3% Digit A/D Converter Features @ Improved 2nd Source! (See 3rd page for Maxim Advantage) Guaranteed first reading recovery from overrange @ On board Display Drive Capabilityno external circuitry required LCD-ICL7106 LED-ICL7107 @ High Impedance CMOS Differential Inputs @ Low Noise (< 15.V p-p) without hysteresis or overrange hangover @ Clock and Reference On-Chip @ True Differential Reference and Input True Polarity Indication for Precision Null Applications @ Monolithic CMOS design __Ordering Information PART TEMP. RANGE PACKAGE ICL7106CPL OCto+70C 40 Lead Plastic DIP ICL7106CJL OCto+70C 40 Lead CERDIP ICL7106CQH OCto+70C 44 Lead Plastic Chip Carrier ICL7106C/D OCto+70C Dice IGL7107CPL OCto +70C 40 Lead Plastic DIP ICL7107CJL OCto +70C 40 Lead CERDIP ICL7107CQH OCto +70C 44 Lead Plastic Chip Carrier ICL7107C/D OCto +70C __Dice Pin Configuration 4 vt osc 1 D1 OSC 2 C1 OSC 3 vs 31 TEST Al REF HI FA REF LO G1 CREF Et MAXIM Crer D2 ICL7106 COMMON C2 1CL7107 IN HI re B2 IN LO 10'S 42 A/Z | F2 BUFF 2 INT D3 vo ) 1 BS G2(TENS. 100S F3 C3 A3 100'S ES 1000'SAB4 G3__| POL BP(7106) GND(7107) (MINUS SIGN) See fast page for Plastic Chip Carrier Pin Configuration The Maxim Advantage signifies an upgraded quality level. At no additional cost we offer a second-source device that is subject to the following: guaranteed performance over temperature along with tighter test specifications on many key parameters; and device enhancements, when needed, that result in improved performance without changing the functionality. MAXI _ Maxim Integrated Products 1 'ZOLL/9OKLION1CL7106/7107 3% Digit A/D Converter ABSOLUTE MAXIMUM RATINGS Supply Voltage Power Dissipation (Note 2) ICL7106, Vt tOVO~ Lo cece cee eens 15V Plastic Package ............. cc eae eee eee ee 1000mWw ICL7107, V+ toGND .... 0... cee cece eee ee eee +6V Operating Temperature ................. 0c to +70C ICL7107, V toGND ..... 0... eee eee eee 9V Storage Temperature ................ -65C to +160C Analog Input Voltage (either input)(Note 1)....... V+ toV- Lead Temperature (Soldering, 60 sec) ......... +300C Reference Input Voitage (either input)........... V+ tov Clock Input ICL7106 0.0 TEST to V+ ICL7107 2... cece ccc ences GND to V+ Note 1: input voltages may exceed the supply voltages, provided the input current is limited to + 100pA. Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (note 3) CHARACTERISTICS CONDITIONS MIN TYP MAX UNITS Zero Input Reading Vin = 0.0V 000.0 +000.0 +000.0 Digital Reading Full Scale = 200.0mV Ratiometric Reading Vin = VREF 999 999/1000 1000 Digital Reading Vrer = 100mV Rotlover Error (Difference in -Vin = +ViIn = 200.0mV -1 .2 +1 Counts reading for equal positive and negative reading near Fuil Scale) Linearity (Max. deviation from Full scale = 200mV -1 t.2 +1 Counts best straight line fit) or full scale = 2.000V Common Mode Rejection Ratio Vom = *1V, Vin = OV. 50 pV/V (Note 4) Full Scale = 200.0mV Noise (Pk-Pk value not exceeded VIN = OV 15 LV 95% of time) Full Scale = 200.0mV Input Leakage Current = dSd YT VN=O 1 10 pA Zero Reading Drift Vin =0 0.2 1 pV/S 0 < Ta < 70C Scale Factor Temperature Vin = 199.0mV 1 5 ppm/C Coefficient 0 <Ta< 70C (Ext. Ref. Oppm/C) V" Supply Current (Does not Vin = 0 0.8 1.8 mA include LED current for 7107) V~ supply current 7107 only. 0.6 1.8 mA Analog Common Voitage (With 25k between Common & 2.4 2.8 3.2 Vv respect to Pos. Supply) Pos. Supply Temp. Coeff. of Analog Common 25k. between Common & 80 ppm/C (With respect to Pos. Supply) Pos. Supply 7106 ONLY V7 to Vo = 9V 4 5 6 Vv Pk-Pk Segment Drive Voitage, Pk-Pk Backplane Drive Voltage (Note 5) 7107 ONLY Vv" =5.0V 5 8.0 mA Segment Sinking Current Segment voltage = 3V (Except Pin 19) {Pin 19 only) 10 16 mA Note 3: Uniess otherwise noted, specifications apply to both the 7106 and 7107 at Ta= 25C, fcLock = 48kHz. 7106 is tested in the circuit of Figure 1. 7107 is tested in the circuit of Figure 2. Note 4: Refer to Differential Input" discussion. Note 5: Backplane drive is in phase with segment drive for off segment, 180 out of phase for on segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. The electrical characteristics above are a reproduction of a portion of Intersit's copyrighted (1983/1984) data book. This information does not constitute any representation by Maxim that Intersils products will perform in accordance with these specifications. The Electrical Characteristics Table along with the descriptive excerpts from the original manufacturer's data sheet have been included in this data sheet solely for comparative purposes. 2 a _ _AWIAXKLSVI@ Guaranteed Overload Recovery Time @ Significantly Improved ESD Protection (Note 7) @ Low Noise @ Maxim Quality and Reliability MMAILSVI 3% Digit A/D Converter * Negligible Hysteresis @ Increased Maximum Rating for Input Current (Note 8) ABSOLUTE MAXIMUM RATINGS: This device conforms to the Absolute Maximum Ratings on adjacent page. @ Key Parameters Guaranteed over Temperature ELECTRICAL CHARACTERISTICS: Specifications below satisfy or exceed all tested parameters on adjacent page. (V+ = 9V; Ta = 25C; fcLock = 48KHz; test circuit - Figure 1; unless noted) PARAMETERS | CONDITIONS MIN TYP MAX UNITS Zero input Reading Vin = 0.0V, Full Scale = 200.0mV Ta = 25C (Note 6) 000.0 +000.0 + 000.0 Digital 0 < Ta < 70C (Note 10) 000.0 +000.0 + 000.0 Reading Ratiometric Reading Vin = Vrer, Vaer = 100mV Ta = 25C (Note 6) 999 999/1000 1000 Digital O < Ta < 70C (Note 10) | 998 999/1000 1001 Reading Rollover Error (Difference in Vin = +Vin = 200.0mvV | reading for equal positive and Ta = 25C (Note 6) | +.2 +1 Counts negative reading near Full Scale) 0 < T, = 70C (Note 10) | +2 L Linearity (Max. deviation from Full Scale = 200.0mV -1 +.2 +1 =) Counts best straight line fit) or full scale = 2.000V Common Mode Rejection Ratio Vom = +19, Vin = OV m Full Scale = 200.omV 50 pv Noise (Pk-Pk value not exceeded Vin = OV yt 95% of time) ~ Scale = 200.0mV | 15 | pV Input Leakage Current =0 7 | TA = 25C (Note 6) 1 10 pA ~ < Ta s 70C 20 200 Zero Reading Drift | Vin = | 0 Ta S 70C (Note 6) i 0.2 1 pve Scale Factor Temperature | Vin = 199.0mV | / Coettficient | 0 < Ta < 70C 1 5 | ppm/?C _| (Ext. Ref. oppm/*C) (Note 6) | | V+ Supply Current Vin = 0 I ; (Does not include LED current Ta = 25C 0.6 18000 mA for 7107) 0 < Ta < 70C 2 | V Supply Current (7107 only) 0.6 18 | mA Analog Common Voltage (with 25k. between Common & 2.4 2.8 32 | Vv respect to Pos. Supply) | Pos. Supply Temp. Coeff. of Analog Common 25kQ. between Common & i 75 ppm/C (with respect to Pos. Supply) _ Pos. Supply | 7106 Only (Note 5) V+ toV- = 9V | 4 5 6 Vv Pk-Pk Segment Drive Voltage, | Pk-Pk Backplane Drive Voltage | 7107 OnlySegment Sinking Current | V+ = 5.0V Ts 8.0 mA (Except Pin 19) Segment Voltage = 3V | (Pin 19 only) 10 16 i mA 7106 OnlyTest Pin Voltage With Respect to V+ 4 5 6 a Vv Overload Recovery Time Vin changing from + 10V 0 1 | Measurement (Note 9) to OV Cycles Note 6: Test condition is V\,, applied between pin IH-HI and IN-LO through a 1MQ series resistor as shown in Figures 1 and 2. Note ?: All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V. (Test circuit per Mil Std 883, Method 3015.1) Note 8: Input voltages may exceed the supply voltage provided the input current is limited to + 1mA (This revises Note 1 on adjacent page). Note 9: Number of measurement cycles for display to give accurate reading. Note 10: 1MQ resistor is removed in Figures 1 and 2. MAAAIMI LOLL/9OLLTOIICL 7106/7107 3% Digit A/D Converter fo cau LCO . He Display Cher Cher - O01 TM: 1 OY 2-19 | SEGMENT } iW fF) { auaoc?p aan [one Li - OT into po. PO | 21) MINUS SIGN BACKPLANE BP DRIVE 1 INPUT O1HE COMMON 1 28 BUFF 24 ark) & O47uF Ke ov 29 faz 36 VREF REF H) > a 35 Int REF LO 2 loscy asc3 asc 39738 case: [40 MAXIM Rose 17106 Ten 100 pF TQ ANALOG ! COMMON (P32) | FULL SCALE VAEr | INPUT | 200.0 mv 100.0. mv we Figure 1. Maxim ICL7106 Typical Operating Circuit _.. _._ ___ Analog Section Figure 3 shows the Block Diagram of the Analog Section for the ICL7136. Each measurement cycle is divided into four phases: . 1. Auto-Zero (A-Z) 2. Signal Integrate (INT) 3. Reference De-Iintegrate (DI) 4. Zero Integrator (Z!) Auto-Zero Phase Three events occur during auto-zero. The inputs, IN-Hi and IN-LO, are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. And lastly, a feedback loop is closed around the system to charge the auto-zero capacitor Caz to compensate for offset voitages in the comparator, buffer amplifier and integrator. The inherent noise of the system determines the A-Z accuracy. Signal integrate Phase The internal input high (IN-HI) and input low (IN-LO) are connected to the external pins, the interna{ short is re- moved and the auto-zero loop is opened. The converter then integrates the differential voltage between IN-HI and IN-LO for a fixed time. This differential voltage can be within a wide common-mode range (within one volt of either supply). If, however, the input signal has no return with respect to the converter power supply, IN-LO can be tied to analog common to establish the correct common- mode voltage. The polarity of the integrated signal is de- termined at the end of this phase. Reference De-integrate IN-HI is connected across the previously charged refer- ence capacitor and JN-LO is internally connected to ana- log common. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The input signal determines the time required for the output to re- turn to zero. The digital reading displayed is: 4000 x VIN. VREF O1,F LED , | 44 Fs Display tes Cher Cage Cee A 31 - as soar ERE TANT | INPUT 20 IN LO POL sls 9 2 Ai COMMON ; = | | BUFF 24 are & OME . az 36 VREF Ree Mt 0.2206 TOK | as iNT REF LOT | te 200.0 mv 100.0 mv _ [26 loscy ose; osc, O fv 38738 cose JO MAXIM 147107 Rose TG ANALOG oo WWA- . COMMON 17.32) | 100k 100 pF \ FULL SCALE Vrer tNPUT | Figure 2, Maxim (CL7107 Typical Operating Circuit Zero Integrator Phase Input low is shorted to analog COMMON and the refer- ence capacitor is charged to the reference voltage. A feedback loop is closed around the system to input high, causing the integrator output to return to zero. This phase normally lasts between 11 and 140 clock pulses but is extended to 740 clock pulses after a heavy over- range conversion. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common-mode error is a rollover voltage. This is caused by the reference capacitor losing or gaining charge to stray capacitance on its nodes. The reference capacitor can gain charge (increase voltage) if there is a large common-mode voltage. This happens during de-in- tegration of a positive signal. In contrast, the reference capacitor will lose charge (decrease voltage) when de-in- tegrating a negative input signal. Rollover error is caused by this difference in reference for positive or negative input voltages. This error can be held to less than half a count for the worst-case condition by selecting a refer- ence capacitor that is large enough in comparison to the stray capacitance. (See component value selection.) ~ _ Differential Input Differential voltages anywhere within the common- mode range of the input amplifer can be accepted by the input (specifically from 1V betow the positive supply to 1.5V above the negative supply). The sys- tem has a CMRR of 86dB (typ) in this range. Care must be exercised, however, to ensure that the integrator output does not saturate, since the in- tegrator follows the common-mode voltage. A large positive common-mode voltage with a near full-scale negative differential input voltage is a worst-case condition. When most of the integrator output swing has been used up by the positive common-mode valtage, the negative input signal drives the integra- tor more positive. The integrator swing can be re- duced to less than the recommended 2V full-scale swing with no loss of accuracy in these critical MIAXAILVI3% Digit A/D Converter Q > os | IN FW az &) QD DE(-} COMPARATOR MAXIM ICL7106 1CL7107 ve ve OT ve | GBR MAXIM | 20% INTEGRATOR we fens LU ICL7106 Sry |] seop-8 1e47107 SECTION MAXIMA \" REF HI A ICL7106 1CL7107 REF LO COMMON wer ; Figure 3. Analog Section of (CL7106/ICL7107 applications. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Common The primary purpose of this pin is to set the common- mode voltage for battery operation. This is useful when using the ICL7106, or for any system where the input signals are floating with respect to the power supply. A voltage of approximately 2.8V less than the positive sup- ply is set by this pin. The analog common has some of the attributes of a reference voltage. If the total supply voltage is large enough to cause the zener to regulate (>7V), the common voltage will have a low output im- pedance (approximately 152), a temperature coefficient of typically 80ppm/C, and a low voltage coefficient (.001%). The internal heating of the ICL7107 by the LED display drivers degrades the stability of Analog Common. The power dissipated by the LED display drivers changes with the displayed count, thereby changing the tempera- ture of the die, which in turn results in a small change in the Anaiog Common voltage. This combination of vari- able power dissipation, thermal resistance, and tempera- ture coefficient causes a 25-80uV increase in noise near full scale. Another effect of LED display driver pow- er dissipation can be seen at the transition between a full scale reading and an overload condition. Overload is a low power dissipation condition since the three least sig- nificant digits are blanked in overload. On the other hand, a near full scale reading such as 1999 has many seg- ments turned on and is a high power dissipation condi- tion. The difference in power dissipation between over- load and full scale may cause a ICL7107 with a negative temperature coefficient reference to cycle between over- load and a near full scale display as the die alternately heats and cools. An ICL7107 with a positive TC refer- ence will exhibit hysteresis under these conditions: once put into overload by a voltage just barely more than full scale, the voltage must be reduced by several counts before the ICL7107 will come out of overload. MAXAL/VI Figure 4. Using an External Reference None of the above problems are encountered when us- ing an external reference. The ICL7106, with its low pow- er dissipation, has none of these problems with either an external reference or when using Analog Common as a reference. TO During auto-zero and reference integrate the internal in- put low is connected to Analog Common. If IN-LO is dif- ferent from analog-common, a common-mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. In some applications, however, IN-LO will be set at a fixed known voltage (e.g., power supply common). Whenever possible analog common should be tied to the same point, thus removing the com- mon-mode voltage from the converter. The same holds true for the reference voltage. If convenient, REF-LO should be connected to analog common. This will re- move the common-mode voltage from the reference sys- tem. Analog Common is internally tied to an N-channel FET that can sink 30mA or more of current. This will hold the Analog Common voltage 2.8V below the positive supply (when a source is trying to pull the common line positive). There is only 104A of source current, however, so COM- MON may easily be tied to a more negative voltage, thus over-riding the internal reference. Test Two functions are performed by the test pin. The first is using this pin as the negative supply for externally gener- ated segment drivers or any other annunciators the user may want to include on the LCD. This pin is coupled to the internally generated digital supply through a 5000, resistor. This application is illustrated in Figures 5 & 6. A lamp test is the second function. All segments will be turned on and the display should read 1888, when TEST is pulled high (V+). Caution: In the lamp test mode, the segments have a constant de voltage (no square wave). This can burn the LCD if left in this mode for several minutes. ZOLZ/9OLZTOIICL7106/7107 3% Digit A/D Converter MAKIM 1617 106 TOLCD 21 DECIMAL POINT Lo 4 Tae TEST 37 TOLCD O BACKPLANE Figure 5A. Fixed Decimal Point Drivers 1 Ol ar TO LCD DECIMAL PO NT MAXIAA _ (L714 LEL7 106 _ Ma 21 TOLCD BP BACKPLANE = J Figure 58. Fixed Decimal Point Drivers r 1 1 lv ro -e--4 vt 1 1 +H) I 1 _I | 1 TO LCD 1 DECIMAL, POINTS MAXIM DECIMAL 1017106 POINT { SELECT ! t ' \ Tj} >-- 1 1 J 4030 TEST u t --@--d 37 > | GND l | Figure 6. Exclusive OR Gate for Decimal Point Drive : Digital Section The digital section for the ICL7106 and ICL7107 is illus- trated in Figures 8 and 9. In Figure 8, an internal digital ground is generated from a 6V zener diode and a large P- channel source follower. This supply is made stiff to ab- sorb the large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is calculated by dividing the clock frequency by 800. For example, with a clock frequency of 48kHz (3 readings per second), the backplane will be a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude. Note that these are out-of- phase when the segment is ON and in-phase when OFF. Negligible dc voltage exists across the segments in ei- ther case. The ICL7107 is identical to the ICL7106 except that the backplane and drivers have been replaced by N-channel segment drivers. The ICL7107 is designed to drive com- mon anode LEDs with a typical segment current of MA. Pin 19 (thousands digit output) sinks current from two LED segments, and has a 16mA drive capability. The polarity indication is on for negative analog inputs, for both the !CL7106 and ICL7107. If desired IN-HI and IN-LO can be reversed giving a on for positive analog inputs. System Timing The clocking circuitry for the 1CL7106 and ICL7107 is illustrated in Figure 7. Three approaches can be used: 1. Accrystal between pins 39 and 40. 2. An external oscillator connected to pin 40. 3. An RC oscillator using all three pins. The decade counters are driven by the clock frequency divided by four. This frequency is then further divided to form the four convert-cycle phases, namely: signal inte- grate (1000 counts), reference de-integrate (0 to 2000 counts), auto-zero (260 to 2989 counts) and zero integra- tor (11 to 740). The signal integration should be a multiple of 60Hz to achieve a maximum rejection of 60Hz pickup. Oscillator frequencies of 30kHz, 40kHz, 48kHz, 60kHz, 80kHz, 120kHz, 240kHz, etc., should be selected. Similarly, for 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 6624kHz, 50kHz, 40kHz, etc., are appropriate. Note that 40kHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and 440HZz). Auto-zero receives the unused portion of reference deintegrate for signals less than full-scale. A complete measurement cycle is 4,000 counts (16,000 clock puls- es), independent of input voltage. As an example, an os- cillator frequency of 48kHz would be used to obtain three readings per second. on Ro a a! MAXIM ICL7 106 1L7107 EXTERNAL OSCILLATOR AC NETWORK TQ TEST PIN ON ICL 7106 TO GROUND PIN ON ICL710? Figure 7. Clock Circuits MMAXAIL/VI3% Digit A/D Converter + OT Btls, Lt Lt Lt LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT SEGMENT OUTPUT INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT t CLOCK + | LOGIC CONTROL INTEANAL DIGITAL GROUND osc osc 2 osc 3 MAXIM Figure 8. 1(CL7106 Digital Section LED f Display a, i fant i aaa soe wena, 4 TO SWITCH DRIVERS + FROM COMPARATOR OUTPUT a. 3 ~--- ee LS t H+ti+ Ht pti I TYPICAL SEGMENT OUTPUT I \ 7 SEGMENT | |7 SEGMENT] If7 SEGMENT \ DECODE DECODE DECODE | \ TO SEGMENT \ LATCH |-___, \ \ I I DIGITAL GROUND THOUSAND [+4 HUNDREDS TENS UNITS i \ I I I 21g DIGITAL Y GROUND | Figure 9. 1CL7107 Digital Section MAXIM _ 7 ZLOLL/9OLLTOI\1CL 7106/7107 3% Digit A/D Converter ee _ Component Value Selection Auto-Zero Capacitor The noise of the system is influenced by the auto-zero capacitor. For the 2V scale, a 0.047F capacitor is ade- quate. A capacitor size of 0.47pF is recommended for 200mvV full scale where low noise operation is very im- portant. Due to the ZI phase of Maxim's ICL7106/7, noise can be reduced by using a larger auto-zero capaci- tor without causing hysteresis or overrange hangover problems seen in other manufacturers ICL7106/7 whic do not have the ZI phase. -- Reference Capacitor For most applications, a 0.1,.F capacitor is acceptable. However, a large value is needed to prevent rollover er- ror where a large common-mode voltage exists (i.e., the REF-LO pin is not at analog common) and a 200mV scale is used. Generally, the roll over error will be held half a count by using a 1.0uF capacitor. Integrating Capacitor To ensure that the integrator will not saturate (at approximately 0.3V from either supply), an appropri- ate integrating capacitor must be selected. A nominal +2V full-scale integrator swing is accept- able for the ICL7106 or ICL7107 when the analog common is used as a reference. A nominal +3.5 to 4 volt swing is acceptable for the ICL7107 with a +5V supply and analog common tied to supply ground. The nominal values for Cit is 0.22 uF for three read- ings per second. (48kHz clock). These values should be changed in inverse proportion to maintain the same output swing if different oscillator frequencies are used. The integrating capacitor must have low dielectric ab- sorption to minimize linearity errors. Polypropylene ca- pacitors are recommended for this application. Integrating Resistor The integrator and the buffer amplifier both have a class A output stage with 100A of quiescent current. 20,A of drive current can be supplied with negligible non-linearity. This resistor should be large enough to maintain the am- plifiers in the linear region over the entire input voltage range. The resistor value, however, should be low enough that undue leakage requirements are not placed on the PC boards. For a 200mV scale, a 47KQ. resistor is recommended; (2V scale/470KQ). Oscillator Components A 100K. resistor is recommended for all ranges ot tre- quency. By using the equation f = 0.45/RC, the capaci- tor value can be calculated. For 48kHz clock, (3 read- ings/second), the oscillator capacitor plus stray capaci- tance should equa! 100pF. 8 Reference Voltage An analog input voltage of Vij, equal to 2 (Veer) is re- quired to generate full scale output of 2000 counts. Thus, for 2V and 200mV scales, Vraer should equal 1V and 100mV respectively. However, there will exist a scale factor other than unity between the input voltage and the digital reading in many applications where the A/D is connected to a transducer. As an example, the designer may like to have a full scale reading in a weighing system when the voltage from the transducer is 0.682V. The designer should use the input voltage directly and select Veer at 0.341V instead of dividing the input down to 200mvV. Suitable values of the capacitor and integrating resistor would be 0.22uF and 120KQ. This provides foraslightly quieter system and also avoids a divider network on the input. The !CL7107 can accept input signals up to +3.5V with +5V supplies. Another advantage of this system occurs when the digital reading of zero is desired for Vin # zero. Examples are temperature and weighing systems with variable tare. By connecting the voltage transducer between Vin positive and common, and the variable (or fixed) offset voltage between common and Vin negative, the offset reading can be conveniently generated. 1L7107 Power Supplies The IGL7107 is designed to operate from +5V supplies. However, when a negative supply is not available it can be generated from a clock output with two diodes, two capacitors, and an inexpensive IC. Refer to Figure 10. Alternatively a 5V supply can be generated using Max- ims ICL7660 and two capacitors. A negative supply is not required in selected applications. The conditions to use a single + 5V supply are: @ An external reference is used. @ The signal is less than +1.5V. @ The input signal can be referenced to the center of the common-mode range of the converter. See Figure 18. es Co4009 Osc 1 OSC 2 OSC 3 maxim 1L7107 GNO Figure 10. Generating Negative Supply from + 5V MAXAI/VI3% Digit A/D Converter _. _Applications Information Heat is generated within the ICL7107 IC package due to the sinking of LED display current. Fluctuating chip tem- perature can cause a display to change reading if the internal voltage reference is used. By reducing the power being dissipated such variations can be reduced. The ICL7107 power dissipation is reduced by reducing the LED common anode voltage. The curve tracer illustration showing the relationship between the output current and mA the output voltage for typical ICL7107 is seen in Figure 11. Note that the typical |CL7107 output is 3.2V (point A), since the typical LED has 1.8V across it (mA drive cur- rent) and its common anode is connected to + 5V. Maxi- mum power dissipation is: 8.1MA X 3.2V x 24 segments = 622mW Once the [CL7107 output voltage is above 2V, the LED current is essentially constant as output voltage increas- 112/3/4 [5 /6}7|8 {9/10 es. Point B illustrates that reducing the output voltage by 0.7V results in 7.7mA of LED current, (only 5% reduc- VSEGMENT tion). The maximum power dissipation is a reduction of 26% as calculated by: Figure 11, 1CL7107 Output Current vs. Output Vollage 7.7MA X 2.5V X 24 segments = 462mW As illustrated in Figure 12, reduced power dissipation is easy to obtain. This can be accomplished by placing ei- ther a 5.19 resistor or a 1 amp diode in series with the display (but not in series with the ICL7107). Point C of Figure 18 illustrates that a resistor will reduce the 1CL7107 output voltage when all 24 segments are On. The output voltage will increase when segments are turned Off. On the other hand, the diode will result in a relatively steady output voltage, around Point B. The re- sistor not only reduces the change in power dissipation as the display changes, but also limits the maximum power dissipation. This is due to the fact that as fewer segments are On, each On output drops more volt- age and current. The resistor circuit will change about 230mW when changing from the best case of six seg- ments, a 111 display, to worst-case of a 1888 dis- play. If the resistor is removed, the power dissipation change will be 470mW. The resistor, therefore, will re- duce the effect of display dissipation on reference volt- Vec = o a ~ NWR HDN DO OO ga? k i) or (Fl GISPLAY Trti rt Titik 51 140 re 1 14001 AN age drift by about 50%. | pt tin As more segments are turned off, the change in LED bisplay _ brightness caused by the resistor is almost unnoticeable. 1 A diode may be used instead of the resistor if it is impor- aia tant to maintain a steady level of display brightness. Figure 12. Diode or Resistor Limits Package Power Dissipation MAAIM_ LOLL/9OLLTONICL7106/7107 3% Digit A/D Converter Typical Applications TOPIND SET Vae 1.00 a - MAXim I1CL7106 INLO 470kKD TO DISPLAY TO BACKPLANE TOPINT SET Vacr 100 omy wo sy MAXIM 1CL7107 TD UISE LAY Figure 13. 1CL7106 using the Internal Reference. 2V Full Scale; 3 Readings per Second. Figure 14. 1CL7107 Internal Reference. 200mV Full Scale; 3 Readings per Second, Viy Tied to GND for Single Ended Inputs. (See discussion under Analog Common) TURIN T TO DISPLAY S v Osc, Qp, osc, ja fe ose3 Qs TEST | Tu Lucie qa REF HIE] Gr REFLOP) ot. Oe Caer q A Cre ] C2 commont] MAXIM c 1607 106 ye innit Cs. InLtof] Q* a7 Gre BUFF] 'RANGE E2 (NT O'RANGE q bs y 483 ep Crs Gp VRANGE LH es ab -{] ABs G3 Q q POL BP e207 on 74c1G cba? Figure 15. ICL7107 Measuring Ratiometric Values of a Load Cell, Desired Sensitivity is Determined by Resistor Values Within the Bridge. Figure 16. Circuit tor Developing Under Range and Over Range Signals from 1017106 Outputs. TOPINY SET Veep 100 n-v MAXIM INHI (CL7107 TO DISPLAY TURIN SEUVpgp 190 dv MAXIM IN ar} 1047107 TO DISPLAY a Figure 17, ICL7107 with a 1.2V External Band-Gap Reference Vix tied to common. 10 Figure 18. 1CL7107 Operated from Single + 5V Supply. An external Refer- ence must be used in this application. MAAIM3% Digit A/D Converter REFERENCE THERMOCOUPLE TYP THERMOCOUPLE SENSOR \ COLD Re _: JUNCTION 30 kq | COMPENSATION R7 | 720.9 ! RB Ro RIG AMAAAAAAA oA 3000 20 ka zoonT\. SCALE FACTOR RI RSS ZERO ADJUST. $24ka/IMO> SV ADJUST \ N Ra Oy Tka ca > C5 4 [= Cyt h oa7HF Ras [00F Po ur 100 ik 1 R2 |c3 DISPLAY rh 47k . ern .22]aF L < List 40. 38 36 34 32 30 28 26 24 =~ 22 39 , 35 33 34 29 27 2 230 24 r) MAXIM 1CL7106 1 3 5 ? 9 W 3 15 17 19 2 a 6 8 10 12 14 16 18 20 DISPLAY Figure 19. Thermocouple Thermometer. This circuit operates with approxi- mately S0mV reference, so the 50.4nV/C output of a Type J thermocouple results in 1 count/C Typical Applications 5 | 2240 = 1Mo > 220 kn = 4 3 3 INO soul, oo | | TEMP SENSOR 1100 ka INH To (20 TURN} DISPLAY 100 ka REF _ SILICON NPN (26 TURN) > \ (MOTOROLA MPS37C4 . FOR EXAMP'E) % REF LO \ . a COMMON SCALE FACTO? ZERO ADJUST ADJUST Figure 20. Digital Thermometer REFERENCE Raererence Lcb LoD DISPLAY DISPLAY Runkwown Runancwn NiO NLO COMMON COMMON ICL7106 system setup for 2V reference ICL7106 system setup for 200mV reference Figure 22. Ratiometric Ohms Measurement maces * For ICL7107, tie INVERT high, and omit EX-NOR gates. Figure 21. BCD Output from 7-Segment Drivers MAALWVI * ICL7106/7 only. See data sheet for values for other parts. Figure 23. Simple End-of-Conversion Detector LOLL/9OFLTOIICL7106/7107 3% Digit A/D Converter KeL7106 D3 Ez Fy Az By Cy Dy E Gy Fy __. Chip Topographies ICL7107 Dz Ey Fp Az By C2 D2 Ey Gy Fy By Ay a, 16 Ay Fg 8B ROU Bi 3 c & (18 c) ABy Oy ag, = 19 ny] vo 20 yi POL = pp OSC, = vn 0 osc: BE f Be 2 & =R 33 Fl os As OSC, Se Ag | OSC2 OSCy OSC3 TEST TEST ts REF HI oy, REF Hi Gy Gy % iia : REF LO io he gg REF LO 2627 28 628 30 3137 33 34 2627 28 24 30 3132 33 34 INT AZ INH] peg INT ANZ INHI Core Vo BUFF INLO COMMON Cr, V> BUFF INLO. COMMON Cy, 0.130" 0.130" (3. 30mm) (3.30mm) . . . . 7 . . Pin Configuration eccha cee rp goede qtouarzoocrea Fi oO [3g] REF LO Gif 138) Crer Maxim cannot assume responsibility for use of any circuitry other than circuitry Maxim reserves the right to change the circuitry and specifications without not 12 ~ ___ 1987 Maxim Integrated Products 37) Crer 36] COMMON mal 35) tN HI ne GE] MAXIM a] NC Bs ICL7106 F3] in vo a 1CL7107 mae Fo 1CL7126 31] BUFF ICL7136 Ez 30] INT D3 [29] v- lalla eerie aege secs aa 44 Lead Plastic Chip Carrier (Quad Pack) entirely embodied in a Maxim product. No circuit patent licenses are implied. ice at any time. Maxim Integrated Products, 510 N. Pastoria Avenue, Sunnyvale, CA 94096 (408) 737-7600 Printed USA 2/87