ICS843011AG - Integrated Device Technology

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

GENERAL DESCRIPTION

The ICS843011 is a Fibre Channel Clock Gen-

erator and a member of the HiPerClocksTM

family of high performance devices from IDT.

The ICS843011 uses a 26.5625MHz crystal to

synthesize 106.25MHz or a 25MHz crystal to

synthesize 100MHz. The ICS843011 has excellent <1ps

phase jitter performance, over the 637kHz – 10MHz

integration range. The ICS843011 is packaged in a small

8-pin TSSOP, making it ideal for use in systems with limited

board space.

FEATURES

•One differential 3.3V LVPECL output

•Crystal oscillator interface designed for 26.5625MHz

18pF parallel resonant crystal

•Output frequency: 106.25MHz or 100MHz

•VCO range: 560MHz - 680MHz

•RMS phase jitter @ 100MHz, using a 25MHz crystal

(637kHz - 10MHz): 0.80ps (typical)

•RMS phase noise at 106.25MHz

Phase noise:

Offset Noise Power

100Hz ............... -92.8 dBc/Hz

1kHz ............. -119.6 dBc/Hz

10kHz ............. -129.5 dBc/Hz

100kHz ............. -130.5 dBc/Hz

•3.3V operating supply

•Available in both standard (RoHS 5) and lead-free

(RoHS 6) packages

•-40°C to 85°C ambient operating temperature

HiPerClockS™

ICS

FREQUENCY TABLE

)zHM(latsyrC)zHM(ycneuqerFtuptuO

5265.6252.601

52001

ICS843011

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body

G Package

Top View

VCCA

VEE

XTAL_OUT

XTAL_IN

VCC

nQ0

OSC Phase

Detector

VCO

637.5MHz w/

26.5625MHz Ref.

M = ÷24 (fixed)

÷6

BLOCK DIAGRAM PIN ASSIGNMENT

nQ0

XTAL_IN

XTAL_OUT

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

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ACC

rewoP.nipylppusgolanA

rewoP.nipylppusevitageN

,TUO_LATX

NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC

.tuptuoeht

siTUO_LATX

5cndesunU.tcennocoN

7,60Q,0QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD

rewoP.nipylppuseroC

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

ACC

tnerruCylppuSgolanAInidedulcni

21Am

tnerruCylppuSrewoP 39Am

TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

4.1-V

9.0-V

1ETON;egatloVwoLtuptuOV

0.2-V

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

.V2-

TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C

TABLE 4. CRYSTAL CHARACTERISTICS

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noitallicsOfoedoM latnemadnuF

ycneuqerF 525265.62zHM

)RSE(ecnat

siseRseireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 33.3933.311zHM

t)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

;zHM52.601

zHM01-zHK736:egnaRnoitargetnI 08.0sp

;zHM001

zHM01-zHK736:egnaRnoitargetnI 08.0sp

emiTllaF/esiRtuptuO%08ot%02003006sp

cdoelcyCytuDtuptuO 8425%

.tolPesioNesahPehtotreferesaelP:1ETON

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

TYPICAL PHASE NOISE AT 100MHZ

100MHz

RMS Phase Noise Jitter

637K to 10MHz = 0.80ps (typical)

TYPICAL PHASE NOISE AT 106.25MHZ

106.25MHz

RMS Phase Noise Jitter

637K to 10MHz = 0.80ps (typical)

OFFSET FREQUENCY (HZ)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100 1k 10k 100k 1M 10M 100M

Phase Noise Result by adding

a Filter to raw data

Raw Phase Noise Data

Filter

➤

OFFSET FREQUENCY (HZ)

dBc

NOISE POWER

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100 1k 10k 100k 1M 10M 100M

Phase Noise Result by adding

Fibre Channel Filter to raw data

Raw Phase Noise Data

Fibre Channel Filter

➤

dBc

NOISE POWER

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PARAMETER MEASUREMENT INFORMATION

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

-1.3V ± 0.165V

Clock

Outputs 20%

80% 80%

20%

SWING

Pulse Width

PERIOD

odc =

nQ0

VEE

VCC

RMS PHASE JITTER

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS843011 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 26.5625MHz, 18pF par-

allel resonant crystal and were chosen to minimize the ppm er-

ror. The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843011 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC, and VCCA should

be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VCCA pin.

POWER SUPPLY FILTERING T ECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

10Ω

VCCA

10μF

.01μF

3.3V

.01μF

VCC

33p

18pF Parallel Crystal

22p

XTAL_OUT

XTAL_IN

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

APPLICATION SCHEMATIC

Figure 3A shows a schematic example of the ICS843011. An

example of LVEPCL termination is shown in this schematic.

Additional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an 18 pF

parallel resonant 26.5625MHz crystal is used for generating

106.25MHz output frequency. The C1 = 27pF and C2 = 33pF

are recommended for frequency accuracy. For different board

layout, the C1 and C2 values may be slightly adjusted for opti-

mizing frequency accuracy.

FIGURE 3A. ICS843011 SCHEMATIC EXAMPLE

FIGURE 3B. ICS843011 PC BOARD LAYO U T EXAMPLE

PC BOARD LAYOUT EXAMPLE

Figure 3B shows an example of ICS843011 P.C. board layout.

The crystal X1 footprint shown in this example allows installa-

tion of either surface mount HC49S or through-hole HC49 pack-

age. The footprints of other components in this example are listed

in the Table 6. There should be at least one decoupling capacitor

per power pin. The decoupling capacitors should be located as

close as possible to the power pins. The layout assumes that

the board has clean analog power ground plane.

TABLE 6. FOOTPRINT TABLE

ecnerefeReziS

2C,1C2040

3C5080

5C,4C3060

2R3060

tnenopmocstsil,6elbaT:ETON

.elpmaxetuoyalsihtninwohssezis

18pF

VCC

Zo = 50 Ohm

VCC

82.5

10uF

33pF

82.5

133

ICS843011

VCCA

VEE

XTA L _OU T

XTA L_I N

VCC

nQ0

VCCA

133

0.1u

0.01u

VCC=3.3V

22pF

VCC

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS843011.

Equations and example calculations are also provided.

1. P ower Dissipation.

The total power dissipation for the ICS843011 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 93mA = 322.2mW

•Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θθ

θθ

θJA FOR 8-PIN TSSOP, FORCED CONVECTION

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 4.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

- 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCCO_MAX - VOH_MAX

) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX

– 1.7V

(VCCO_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOH_MAX) = [(2V - (V

CC_MAX - VOH_MAX

))/R

] * (VCC_MAX

- VOH_MAX) =

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOL_MAX) = [(2V - (V

CC_MAX - VOL_MAX

))/R

] * (VCC_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION

VOUT

VCC

VCC - 2V

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS843011 is: 2436

TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.201.3

ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

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843011AG www.icst.com/products/hiperclocks.html REV. B JANUARY 26, 2007

Integrated

Circuit

Systems, Inc.

ICS843011

FEMTOCLOCKS™ C RYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

TEEHSYROTSIHNOISIVER

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