CY7C4225-15ACT - Cypress Semiconductor

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

fax id: 5410

CY7C4425/4205/4215

CY7C4225/4235/4245

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 9 5 1 3 4 • 408-943-260 0

April 1 995 - Revised August 18, 1997

1CY7C4225

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64 x 18 (CY7C4425)

• 256 x 18 (CY7C4205)

• 512 x 18 (CY7C4215)

• 1K x 18 (CY7C4225)

• 2K x 18 (CY7C4235)

• 4K x 18 (CY7C4245)

• High-speed 100-MHz ope ration (10 ns read /write cyc le

time)

• Low power (ICC =45 mA)

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, Half Full, and Programmable Almost

Empty/Almost Full status flags

• TTL-compatible

• Retransmi t function

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP

• 68-pin PLCC

Functional Description

The CY7C42X5 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to

IDT722x 5. The CY7C42 X5 c an be c ascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. T hese FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data acquisition,

multiproce ssor interf a ces, and communi catio ns buffer ing.

These FIFOs have 18-bit i nput and output p orts that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is conti nually wri tten into t he FIFO on each cycle. T he output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applicatio ns. Clock fr equencies up to 100 MHz are

achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these d evices.

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next devic e, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to VSS and the

FL pin of all the remaining devices s hould be tied to VCC.

The CY7C42X5 pro vides five status pins. These pins are de-

coded to determine one of five states: Em pty, Almost Em pty,

Half Full, Almost Full, and Full (s ee

Table 2

). The Half Full flag

shares the WX O pin. This flag is vali d in the stan dalone a nd

width-expansion configurations. In the depth expansion, this

pin provides the expansion out ( WXO) information that is u sed

to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e. , they change

state relative to either the read clock (RCLK) or the w rite clock

(WCLK). Whe n entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one

clock cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

VCC/SMODE is tied to VSS. All configurations are fabricated

using an advanced 0.65µ N-Well CMOS technology. Input

ESD protection is g reater than 2001V, an d latch-up is p rev ent-

ed by the use of guard rings.

CY7C4425/4205/4215

CY7C4225/4235/4245

Logic Block Diagram

42X5–1

THREE–STATE

OUTPUT REGISTER READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER READ

POINTER

RESET

LOGIC

EXPANSION

LOGIC

INPUT

FLAG

PROGRAM

D0–17

RENRCLK

PAE

Q0–17

WENWCLK

FL/RT

WXI

DUAL PORT

RAM ARRAY

64 x 18

256 x 18

512 x 18

1K x 18

2K x 18

4K x 18

PAF

WXO/HF

RXI

RXO

SMODE

Pin Configurations

Top View

3132 33 34 35 36 37 38 3940 4142 43

5 4 3 2 1 68 666564636261

Q13

GND

Q12

Q11

VCC

Q10

GND

VCC

D14

D13

D12

D11

D10

VCC

GND

2728 2930

987 6

GND

D025

VCC/SMODE

42x5–2

TQFP

Top View

42X5–3

17 64

18 63

19 62

20 61

21 60

22 59

23 58

24 57

25 56

26 55

27 54

28 53

29 52

30 51

31 50

32 49

PLCC

PAE

FL/RT

WCLK

WEN

WXI

VCC

PAF

RXI

WXO/HF

RXO

GND

VCC Q15

GND

Q16

Q17

VCC

GND

VCC

REN

RCLK

GND

D17

D16

D15

D14

D13

D12

D11

D10

D15

Q15

GND

Q16

Q17

GND

VCC

REN

RCLK

GND

D17

D16

PAE

WCLK

WEN

WXI

VCC

PAF

RXI

WXO/HF

RXO

GND

Q14

Q13

GND

Q12

Q11

VCC

Q10

GND

VCC

VCC/SMODE

FL/RT

CY7C4425

CY7C4205

CY7C4215

CY7C4225

CY7C4235

CY7C4245

CY7C4425

CY7C4205

CY7C4215

CY7C4225

CY7C4235

CY7C4245

CY7C4425/4205/4215

CY7C4225/4235/4245

Selectio n G uide 7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35

Maximum Frequency (MHz) 100 66.7 40 28.6

Maximum Access Time (ns) 8 10 15 20

M inimum Cycle Time (ns) 10 15 25 35

M inimum Data or Enable Set-Up (ns) 3 4 6 7

M inimum Data or Enable Hold (n s) 0.5 1 1 2

Maximum Flag Delay (ns) 8 10 15 20

Operating Current (ICC2)

(mA) @ freq=20MHz Commercial 45 45 45 45

Industrial 50 50 50 50

CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245

Density 64 x 18 256 x 18 512 x 18 1K x 1 8 2K x 18 4K x 18

Packages 68-pin PLCC

64-pin TQFP

(10x10/14x14)

68-pin PLCC

64-pin TQFP

(10x10/14x14)

68-pin PLCC

64-pin TQFP

(10x10/14x14)

68-pin PLCC

64-pin TQFP

(10x10/14x14)

68-pin PLCC

64-pin TQFP

(10x10/14x14)

68-pin PLCC

64-pin TQFP

(10x10/14x14)

Pin Definitions

Signal Name Description I/O Function

D0–17 Data Inputs I Data input s for an 18-bit bu s

Q0–17 Data Outputs O Data outputs for an 18-bit b u s

WEN Write Enable I Enables the WCLK input

REN Read Enable I Enabl es the RCLK in put

WCLK Write Clock I The rising edge clocks data into t h e FIFO when WE N i s LOW and the FIFO is not

Full. When LD is asserted, WCLK writes data into the programmable flag-offset

RCLK Read Clock I The rising ed ge clock s data out of th e FIFO when REN is LOW and the FIFO is not

Empty. When LD is asser ted, RCLK reads da ta out of t he progr ammab le flag- of f-

set register.

WXO/HF Write Expansion

Out/Half F ull Flag ODual-Mode Pin:

Single device or width expansion - Half Full status flag.

Cascaded - Write Expansion Out signal, connected to W X I of next device.

EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

FF Full Flag O When FF is L O W, th e F IF O i s fu ll. FF is synchronized to WCLK.

PAE Programmable

Almost Empty OWhen PAE is LOW, the FIFO is almost empty based on the almost-empty offset

value programmed into the FIFO. P AE is asynchronous w hen VCC/SMODE is ti ed

to V CC; it is sync hro nized to R CLK w hen VCC/SMODE is tied to VSS.

PAF Programmable

Almost Full OWhen PAF is L OW, the F IF O is a lmost full ba s e d on the a lm o st fu ll o ffs et v alu e

programmed into the FIFO. PAF is asynchronous when VCC/SMODE is t ie d to

VCC; it is synchronized to WCLK when VCC/SMODE i s tie d to VSS.

LD Load I When LD is L OW, D0 - 1 7 (O0 - 1 7 ) are written (read) into (from) the programma-

ble-flag-offset register.

FL/RT First Load/

Retransmit IDual-Mode Pin:

Cascaded - T he first device in the daisy chain will have FL tied to VSS; all other

devices will have FL tied to V CC. In standard mode of width expansion, FL is t i ed

to V SS on al l devices.

Not Cascaded - Tied to VSS. Retransmit function is also available in standalone

mode by strobing RT.

WXI Wr ite Expansion

Input ICascaded - Connected to WXO of previous device.

Not Cascaded - Tied to VSS.

CY7C4425/4205/4215

CY7C4225/4235/4245

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ....................................−65°C to + 1 50°C

Ambient Temper ature with

Power Applied.................................................−55°C to + 1 25°C

Supply Volta ge to Ground Potential.................−0.5V t o +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

DC Input Voltage.................................................−3.0V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ...........................................>2001V

(per MIL-STD-883, Method 3015 )

Latch-Up Current.....................................................>200 mA

RXI Read Expansion

Input ICascaded - Connected to RX O of previous device.

Not Cascaded - Tied to VSS.

RXO Read Expansion

Output OCascaded - Connected to RX I of next device.

RS Reset I Resets device to empty conditio n. A reset is required before an initial read or write

operation after power-up.

OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-

nected. If OE i s HIGH, the FIFO’s output s are in High Z (high-impedance) state.

VCC/SMODE Synchronous

Almost Empty/

Almost Full Flags

IDual-Mode Pin

Asynchronous Almost Empty/Almost Full flags - tied to VCC.

Synchronous Almost Empty/Almost Full flags - tied to VSS.

(Almost E mp ty s ynchr oni zed to RCLK, Almos t Fu ll synchr oniz ed to WCLK.)

Pin Definitions (continued)

Signal Name Description I/O Function

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial[1] −40°C t o +85°C 5V ± 10%

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test Conditions

7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35

Min. Max. Min. Max. Min. Max. Min. Max. Unit

VOH Output HIGH Volt ag e VCC = Min.,

IOH = −2. 0 mA 2.4 2.4 2.4 2.4 V

VOL Output LOW Voltag e VCC = Min.,

IOL = 8.0 mA 0.4 0.4 0.4 0.4 V

VIH[3] Input HIGH Volt a ge 2.2 VCC 2.2 VCC 2.2 VCC 2.2 VCC V

VIL[3] Input LOW Voltage −3.0 0.8 −3.0 0.8 −3.0 0.8 −3.0 0.8 V

IIX Input Leakage

Current VCC = Max. −10 +10 −10 +10 −10 +10 −10 +10 µA

IOS[4] Output Short

Circuit Current VCC = Max.,

VOUT = GND −90 −90 −90 −90 mA

IOZL

IOZH Output OFF,

High Z Current OE > VIH,

VSS < VO < VCC −10 +10 −10 +10 −10 +10 −10 +10 µA

ICC2[5] Operating Current VCC = Max.,

IOUT = 0 mA Com’l 45 45 45 45 mA

Ind 50 50 50 50 mA

ISB[6] Standby Current VCC = Max.,

IOUT = 0 mA Com’l 10 10 10 10 mA

Ind 15 15 15 15 mA

Notes:

1. TA is the “instant on” case temperature.

2. See the last page of this specification for Group A su bgroup testing information.

3. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the

previous device or VSS.

4. Test no more than one output at a time for not more than one second.

5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switc h at 20 MHz, while the data inputs switch at 10 MHz.

Outputs are unloaded.

6. All input signals are connected to VCC. All outputs are unl oaded.

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

7. Tested initially and after any design or process changes that may affect these parameters.

8. CL = 30 pF for all AC parameters except for tOHZ.

9. CL = 5 pF for tOHZ.

Capacitance[7]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 M H z ,

VCC = 5. 0V 5pF

COUT Output Capacitance 7 pF

AC Test Loads and Waveforms[8, 9]

3.0V

OUTPUT

R11.1K Ω

680Ω

INCLUDING

JIGAND

SCOPE

GND

90%

10%

90%

10%

<3ns <3ns

OUTPUT 1.91V

E quival en tto: THÉ EVENIN EQUIVALENT

42X5–4

410Ω

ALL INPUT PULSES

42X5–5

Switching Characteristics Ove r the Operating Range

Parameter Description

7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35

Min. Max. Min. Max. Min. Max. Min. Max. Unit

tSClock Cycle Frequency 100 66.7 40 28.6 MHz

tAData Access Time 2 8 2 10 2 15 2 20 ns

tCLK Clock Cycle Time 10 15 25 35 ns

tCLKH Clock HIGH Time 4.5 6 10 14 ns

tCLKL Clock LOW Time 4.5 6 10 14 ns

tDS Data Set-Up Time 3 4 6 7 ns

tDH Data Hold Time 0.5 1 1 2 ns

tENS Enabl e Set-Up Time 3 4 6 7 ns

tENH Enable Hold Time 0.5 1 1 2 ns

tRS Reset Pulse Width[10] 10 15 25 35 ns

tRSR Reset Recovery Time 8 10 15 20 ns

tRSF Reset to Flag and Output Time 10 15 25 35 ns

tPRT Retransmit Pulse Width 12 15 25 35 ns

tRTR Retransmit Recovery Time 12 15 25 35 ns

tOLZ Output Enable to Output in L ow Z[11] 0 0 0 0 ns

tOE Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns

tOHZ Output Enable to Outp ut in High Z[12] 3 7 3 8 3 12 3 15 ns

tWFF Write Clock to Full Flag 8 10 15 20 ns

tREF Read Clock to Empty Flag 8 10 15 20 ns

tPAFasynch Clock to Programma ble Almost-Full Flag[12]

(Asynchronous mode, VCC/SMODE tied to VCC)12 16 20 25 ns

CY7C4425/4205/4215

CY7C4225/4235/4245

tPAFsynch Clock to Programmable Almost-Full Flag

(Synchronous mode , VCC/SMODE tied to VSS)810 15 20 ns

tPAEasynch Clock to Programmable Almost-Empty Flag[12]

(Asynchronous mode, VCC/SMODE tied to VCC)12 16 20 25 ns

tPAEsynch Clock to Programmable Almost-Full Flag

(Synchronous mode , VCC/SMODE tied to VSS)810 15 20 ns

tHF Clock to Half-Full Fl ag 12 16 20 25 ns

tXO Clock to Expansion Out 7 10 15 20 ns

tXI Expansion in Pulse Wi dth 3 6.5 10 14 ns

tXIS Expansion in Set-Up Time 4.5 5 10 15 ns

tSKEW1 Skew Time between Read Clock and Write

Clock for Full Flag 5 6 10 12 ns

tSKEW2 Skew Time between Read Clock and Write

Clock for Empty Flag 5 6 10 12 ns

tSKEW3 Skew Time between Read Clock and Write

Clock for Programmable Almost Empty and Pro-

grammable Almost Full Flags.

10 15 18 20 ns

Switching Characteristics O ver th e Ope rati ng Ra n g e (conti n ued)

Parameter Description

7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35

Min. Max. Min. Max. Min. Max. Min. Max. Unit

Switching Waveforms

Notes:

10. Pulse widths less than minimum values are not allowed.

11. Values guaranteed by design, not currently tested.

12. PAFasynch, tPAEasynch, after pro gram reg ister w rite will not be valid until 5 n s + tPAF(E).

13. tSKEW1 is the mi nimum t ime bet ween a r ising RCLK edge and a ris ing WC LK edge to guar antee that F F will go HIGH during the current clock cycle. If the time between the

ris ing edge of R CLK and the ri sing edge of W CLK is l ess than tSKEW1, th en FF may no t change state un til the ne xt WCLK edge .

Write Cycle Timing

tCLKH tCLKL

NO OPERATION

tDS

tSKEW1

tENS

WEN

tCLK

tDH

tWFF tWFF

tENH

WCLK

D0–D17

REN

RCLK

42X5–6

[13]

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

14. .tSKEW2 is the min imu m t im e b etween a ri sing WC LK edge and a rising RCL K edg e to guarantee that E F will go HIGH during the current clock cycle. It the time between the

ris ing edge of WCLK and th e rising ed ge of RCLK is less than tSKEW2, th en EF may not chan ge s tate until the nex t RCLK edge.

15. The clocks (RCLK, WCLK) can be free-running during res et.

16. After reset, the outputs will be LOW if OE = 0 and thr ee-st ate if OE = 1.

Switching Waveforms (continued)

Read Cycle Timing

tCLKH tCLKL

NO OPERATION

tSKEW2

WEN

tCLK

tOHZ

tREF tREF

RCLK

Q0–Q17

REN

WCLK

tOE

tENS

tOLZ

tENH

VALID DATA

42X5–7

[14]

tRS

tRSR

Q0- Q

tRSF

tRSF OE=1

OE=0

REN,WEN,

EF,PAE

FF,PAF,

42X5–8

Reset Timing[15]

[16]

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

17. When tSKEW2 > m in imu m specifica tion, tFRL ( maximum) = tCLK + t SKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.

The L atency T imin g applies only at the Empt y Boundary (EF = L OW).

18. The first word is available the cycle after EF goes H IGH, alw ays.

Switching Waveforms (continued)

D0(FIRSTVALIDWRITE)

First Data Word Latency after Reset with Simultaneous Read and Write

tSKEW2

WEN

WCLK

Q0–Q17

REN

OE tOE

tENS

tOLZ

tDS

RCLK

tREF

tFRL

D1D2D3D4

D0D1

D0–D17

42X5–9

tA[18]

[17]

D1D0

tENS

tSKEW2

Empty Flag Timing

WEN

WCLK

Q0–Q17

REN

tDS

tENH

RCLK

tREF

tFRL

D0–D17

tSKEW2

tFRL

tREF

tDS

tENS tENH

42X5–10

tREF

[17]

CY7C4425/4205/4215

CY7C4225/4235/4245

Switching Waveforms (continued)

NEXT DATA READ

DATA WRITE

NO WRITE

DATA IN OUTPUT REGISTER

Full Flag Timing

WCLK

Q0–Q17

REN

RCLK

D0–D17

DATAREAD

tSKEW1 tDS

tENS tENH

WEN

tWFF

tSKEW1

tENS tENH

tWFF

DATA WRITE

NO WRITE

tWFF

LOW

42X5–11

[13]

tENH

Half-Full Flag Timing

WCLK

REN

RCLK

tCLKH

tHF

tENS

HALF FULL+1

OR MORE

tCLKL

tENS

HALF FULLOR LESS HALFFULLOR LESS

tHF

42X5–12

WEN

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

19. PAE offset – n. Number of data words into FIFO already = n.

20. PAE offset – n.

21. tSKEW3 is the mini mum time between a rising W CLK and a r ising RCLK edge for P A E to c hange state during that c lo ck c ycle. If t he time between the edg e of WCLK and the

ris ing RC LK is le ss than tSKEW3, then P AE may not change state unti l the next R CLK.

22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes L OW .

Switching Waveforms (continued)

tENH

Programmable Almost Empty Flag Timing

WCLK

PAE]

REN

RCLK

tCLKH

tPAE

tENS

n+1 WORDS

IN FIFO

tCLKL

tENS

tPAE

n WORDS IN FIFO

42X5–13

[19]

WEN

Note

tENH

WCLK

PAE

RCLK

tCLKH

tENS

tCLKL

tENS

tPAEsynch

N + 1 WORDS

INFIFO

42X5–14

tENH

tENS

tENH

tENS

tPAEsynch

REN

WEN

WEN2

tSKEW3

Note

Programmable Almost Empty Fla g Timing (applies only in SMODE (SMODE is LOW)

[21] 22

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

23. PAF offset = m. Number of data words written into FIFO already = 64 – m + 1 for the CY7C4425, 256 – m + 1 for the CY7C4205, 512 – m + 1 for the

CY7C4215. 1024 – m + 1 for the CY7C4225, 2048 – m + 1 for the CY7C4235, and 4096 – m + 1 for the CY7C4245.

24. PAF is offset = m.

25. 64 – m words in CY7C4425, 256 – m words inCY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and

4096 – m words in CY7C4245.

26. 64 – m + 1 words in CY7C4425, 256 – m + 1 words in CY7C4205, 512 – m +1 words in CY7C4215, 1024 – m + 1 CY7C4225, 2048 – m + 1 in CY74235,

and 4096 – m + 1 words in CY7C4245.

27. If a write is performed on this rising edge of the write clock, there will be Full – (m – 1) words of the FIFO when PAF goes L OW .

28. PAF offset = m.

29. 64 – m words in CY7C4425, 256 – m words in FIF O for CY7C4205, 512 – m word i n CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235,

and 4096 – m words in CY7C4245.

30. tSKEW3 is the minimum time betwee n a r ising RC LK and a rising W CLK edge for PAF to c hange s ta te d uring that c lock cycle. If th e t ime bet ween the edge of RCLK and the

ris ing edge of WCLK is les s tha n tSKEW3, then PAF may no t change state unt il the next WCLK r ising edge.

Switching Waveforms (continued)

Note

tENH

WEN

WCLK

REN

RCLK

tCLKH

tPAF

tENS

tCLKL

tENS

tPAF

42X5–15

FULL −M WORDS

IN FIFO FULL −M + 1 WORDS

IN FIFO

Program mable Almost Full Flag Timing

[26]

PAF[24]

[25]

Note

tENH

WCLK

PAF

RCLK

tCLKH

tENS

FUL L −M WO RDS

IN FIFO

tCLKL

tENS

FULL- M+1Ω ORDS

INFIFO

42X5–16

tENH

tENS

tENH

tENS

tPAF

REN

WEN2

tSKEW3 tPAFsynch

[30]

WEN

Programmable Almost Ful l Flag Timing (ap plies only in SMOD E (SMODE in LOW))

[29]

CY7C4425/4205/4215

CY7C4225/4235/4245

Note:

31. Write to Last Physical Location.

Switching Waveforms (continued)

tENH

Write Programmable Registers

WCLK

tCLKH

tENS

tCLKL

PAE OFFSET

D0–D17

WEN

tENS

PAF OFFSET

PAE OFFS ET

tCLK

D0–D11

tDS tDH

42X5–17

tENH

Read Programmable Registers

RCLK

tCLKH

tENS

tCLKL

PAE OFFS ET

Q0–Q17

WEN

tENS

PAF OFFSET PAE OFFS ET

tCLK

UNKNOWN

42X5–18

Write Expansion Out Timing

WEN

WCLK

WXO

tCLKH

tENS

Note tXO

tXO

42X5–19

CY7C4425/4205/4215

CY7C4225/4235/4245

Notes:

32. Read from Last Physical Location.

33. Clocks are free running in this case.

34. The flags may change state during Retransmit as a result of the offset of the read and write po inters, but flags will be valid at tRTR.

35. For the synchronous PAE and PAF flags ( SMODE), an appropr iate cl ock c ycle is nec essar y after tRTR to updat e thes e fla gs.

Switching Waveforms (continued)

Read Expansion Out Timing

REN

WCLK

RXO

tCLKH

tENS

Note tXO

tXO

42X5–20

Write Expansion InTiming

WCLK

WXI

tXI

tXIS

42X5–21

Read Expansion In Timing

RCLK

RXI

tXI

tXIS

42X5–22

Retransmit Timing

REN/WEN

FL/RT

tPRT tRTR

42X5–23

EF/FF

an d all

async flags

HF/PAE/PAF

[33, 34, 35]

CY7C4425/4205/4215

CY7C4225/4235/4245

Architecture

The CY7C42X5 consists of an arra y of 64 to 4K word s of 18

bits each (implemented by a du al-port ar ray of SRAM cells), a

read pointer, a write pointer, control signals (RCLK, WCLK,

REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The

CY7C42X5 also includes the control signals WXI, RXI, WXO,

RXO for depth expansion.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)

cycle. This causes the FIFO to enter th e Empty conditio n sig-

nified by EF being LOW. All data outputs go LOW after the

falling edge of RS only if OE is asserted. In order for the FIFO

to reset to its default state, a falling edge must occur on RS

and the user must not r ead or write while RS is LOW.

FIFO Operation

When the WEN signal is active (LOW), data present on the

D0–17 pins is writte n into the FIFO on each rising edge of the

WCLK signal. Similarly, when the REN signal is active LOW,

data in the FIFO memor y will be presented on the Q0–17 out-

puts. New data w ill be presented o n each r ising edge of RCLK

while REN is active LOW and OE is LOW. REN must set up

tENS before RCLK for it to be a valid read fun ction . WEN must

occur tENS before WCLK for it to be a valid write function.

An output enable ( OE) pin is prov ided to three-state the Q0–17

outputs when OE is deass e rted. When OE is enabled (LOW),

data in the output register w ill be available to the Q0–17 outputs

after tOE. If devices are cascaded, the OE function will only

output data on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional

wr ites when the FIFO is full, and unde rflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains th e d ata of the last valid r ead on i ts Q0–17 output s

even after additional re ads occur.

Programming

The CY7C42X5 devices contain two 12-bit offset registers.

Data present on D 0–11 dur ing a program write wi ll d etermi ne

the distance from Empty (Full) that the Alm ost Empty (Almost

Full) flags bec ome active. If the user elects not to program the

FIFO’s flags, the defa ult offset values are used (see

Table 2

When the Load LD pin is set LOW and WEN is set LOW, data

on the i nputs D0–11 is written into the Empty offset re gister on

the first LOW-to-HIGH transition of the write clock (WCLK).

When the LD pin and WEN are held LOW then data is wri tten

into the Full offset register o n the second LOW-to-HIGH t ran-

sition of the write clock (WCLK). The third transition of the write

clock (WCLK) again writes to the Empty offset register (see

Table 1

). Writing all offs et registers does not have to occur at

one time. One or two offset registers can be writ ten and then,

by bringing the LD pin HI GH, the FIFO is returned to n ormal

read/write operat ion. W h en the L D pin is set LOW, and WEN

is LOW, the next offset register in sequence is written.

The contents of the offset registers can be rea d on the output

lines when the LD pin is set LOW and REN is set LOW; then,

data ca n be read on the LOW-to-HIGH transition of the read

clock (RCLK).

Flag Operat ion

The CY7C42X5 d evi ces provide five flag pins to indicate the

condition of the FIFO contents. Empty and Full are synchro-

nous. PAE and PAF are synchronous if VCC/SMODE is tied to

VSS.

Full Flag

The Full Flag (FF) will go LOW when device is Full. Write op-

erations are inhibited whenever FF is LO W regardless of the

state of WEN. FF is s ynch ronized to WCLK , i.e., it is exclusive-

ly updated by each rising edge of WCLK.

Empty Flag

The Empty Flag (EF) will go LOW when the device is empty.

Read operations ar e inhibited whenever EF is LOW, regard-

less of th e state o f REN. EF is sync hroniz ed to RCLK, i.e., i t is

exclusively updated by each rising edge of RCLK.

Programm abl e Almo st Empty/Al most Full Flag

The CY7C42X5 features programmable Almos t Empty an d Al-

most Full Flags. Each flag can be program med (described in

the Programming sectio n) a specific distance from the corre-

spon din g boundary flags (Empty or Full). Whe n the FIFO con-

tains the number of words or fewer for which the flags have

been programmed, the PAF or PAE will be asserted, s ign ifying

that the FIFO is either Almost Full or Almost Empty. See

Table

for a description of programm able flags.

When the SMODE pin is tied LOW, the PAF flag signal t ransi-

tion is caused by the risin g edge of the write clock and the PAE

flag transition is caused by the rising edge of the read clock.

Retransmit

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary.

The Retransmit (RT) input is active in the standalone and width

expansion modes. The retr ansmi t featur e is intended for use

when a number o f writes equal to or les s than the depth of the

FIFO have occurred since the last RS cycle. A HIGH pulse on

RT resets the internal read po inter to the first physical location

of the FIFO. WCLK and RCLK may be free running but must

be disabled during and tRTR after the retransmit pulse. With

Table 1. Write Offset Register

LD WEN WCLK[36] Selection

0 0 Writing to offset registers:

Empty Offset

Full Offset

0 1 No Operation

1 0 Write Into FIFO

1 1 No Operation

Note:

36. The same selection sequence appl ies to reading from the registers. RE N

is enab led and r ead is perf ormed on th e LO W-to- HIGH t ransition of RC LK.

CY7C4425/4205/4215

CY7C4225/4235/4245

every valid read cycle after retransmit, previously accessed

data is read and the read pointe r i s incremented u ntil it is e qual

to the write pointer. Flags are governed by the relative loca-

tions of the read an d write pointers and are updated during a

retransmit c ycle. Data writ ten to the FIFO a fter activation of R T

are transmitted also.

The full depth of the FIFO can be repeatedly retransmitted.

Width Expansion Configuration

The CY7C42X5 can be expanded in width to provide word

widths greater than 18 in increments of 18. During width ex-

pansion mode all control line inputs are comm on and all flags

are av ailab le. Empty (Full) flags should be c reated by ANDing

the Empty (Full) flags of every FIFO. This technique will avoid

ready data from the FIFO that is “staggered” by one cloc k cycle

due to the variations in skew between RCLK and WCLK.

Figure 1

demonstrat es a 36-wor d width by using two CY7C42X5.

Table 2. Flag Truth Table.

Number of Words in FIFO FF PAF HF PAE EF7C4425 - 64 x 18 7C4205 - 256 x 18 7C4215 - 512 x 18

0 0 0 H H H L L

1 to n[37 1 to n[37] 1 to n[37] H H H L H

(n+1) to 32 (n+1) to 128 (n + 1) to 256 H H H H H

33 to (64 – (m+1)) 129 to (256 – (m+1)) 257 to (512 – (m+1)) H H L H H

(64 – m)[38] to 63 (256 – m)[38] to 255 (512 – m)[38] to 511 H L L H H

64 256 512 L L L H H

Number of Words in FIFO FFPAFHFPAEEF 7C4225 - 1K x 18 7C4235 - 2K x 18 7C4245 - 4K x 18

000 HHHLL

1 to n[37] 1 to n[37] 1 to n[37] HHH LH

(n+1) to 512 (n+1) to 1024 (n+1) to 2048 H H H H H

513 to (1024 – (m+1)) 1025 to (2048 – (m+1)) 2049 to (4096 – (m+1)) H H L H H

(1024 – m)[38] to 1023 (2048 – m)[38] to 2047 (4096 – m)[38] to 4095 H L L H H

1024 2048 4096 L L L H H

Notes:

37. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).

38. m = F ull Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).

Figure 1 . Block Diagram of 64x36/256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a

Width Expansion Configur ation.

42X5–24

FF EF EF

WRITECLOCK(WCLK)

WRITEENABLE(WEN)

LOAD(LD)

PROGRAMMABLE(PAE)

HALFFULLFLAG(HF)

FULLFLAG(FF)

7C4425

7C4205

7C4215

7C4225

7C4235

7C4425

7C4205

7C4215

7C4225

7C4235

1836

DATAIN (D)

RESET(RS)

READCLOCK(RCLK)

READENABLE(REN)

OUTPUTENABLE(OE)

PROGRAMMABLE(PAF)

EMPTYFLAG(EF)

DATAOUT(Q)

18 36

FIRST LOAD(FL)

WRITE EXPANSION IN (WXI)

READ EXPANSION IN (RXI)

CY7C4425/4205/4215

CY7C4225/4235/4245

Depth Expansion Configuration

(with Prog rammable Flags)

The CY7C42X5 can easily be adapted to ap plications requir-

ing more than 64/256/512/1024/2048 /4096 words of buf fering.

Figure 2

shows Depth Expansion using three CY7C42X5s. Maxi-

mum depth is limited only by signal loading. Follow these steps:

1. The fi rst device must be de signated by grounding the First

Load (FL) control input.

2. All other devices must have FL in t h e HI GH s ta t e.

3. The Write Expansion Out (WXO) pin of each device must be

tied to the Write Expansion In (WXI) pin of the next device.

4. The Read Expansion Out (RXO) pin of each device must be

tied to the Read Expansion In (RXI) pin of the next device.

5. All Load (LD) pi ns are tied together .

6. The Half-Full Flag (H F) is not available in the Depth Expansion

Configuration.

7. EF, FF, PAE, and PAF a re c reated with co mposite flags by

ORin g together these respective flags for monitoring. The

composite PAE and PA F flags are not precise.

Figure 2. Blo ck Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchro nous FIFO Memory

with Pro grammable Flags used in Depth Expansion Configuration.

42X5–23

WRITECLOCK(WCLK)

WRITE ENABLE(WEN)

RESET(RS)

LOAD(LD)

PAF PAF

FF EF

PAE PAE

WXI RXI

FIRSTLOAD(FL)

READCLOCK(RCLK)

READ ENABLE (REN)

OUTPUT ENABLE(OE)

WXO RXO

7C4425

7C4205

7C4215

7C4225

7C4235

PAF

FF EF

PAE

WXI RXI

WXO RXO

7C4425

7C4205

7C4215

7C4225

7C4235

VCC

FIRSTLOAD(FL)

PAF

FF EF

PAE

WXI RXI

WXO RXO

7C4425

7C4205

7C4215

7C4225

7C4235

VCC

FIRSTLOAD(FL)

DATAIN (D) DATAOUT(Q)

CY7C4425/4205/4215

CY7C4225/4235/4245

Ty pical AC and DC Characteristics

SUPPLY VOLTAGE(V)

NORMALIZED tAvs.SUPPLY

VOLTAGE

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED tAvs.

AMBIENT TEMPERATURE

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

FREQUENCY (MHz)

NORMALIZED SUPPLY CURRENT

vs. FREQUENCY

SUPPLY VOLTAGE(V)

VCC =5.0V

NORMALIZED ICC

AMBIENT TEMPERATURE(°C)

VIN =3.0V

TA=25°C

f=100 MHz

VIN =3.0V

VCC =5.0V

f=100 MHz

NORMALIZED ICC

VCC =5.0V

TA=25°C

VIN =3.0V

CAPACITANCE(pF)

NORMALIZED tA

TYPICALtACHANGE vs.

OUTPUT LOADING

VCC =5.0V

TA=25°C

OUTPUT SOURCECURRENT

vs. OUTPUT VOLTAGE

OUTPUT VOLTAGE(V)

OUTPUT SINK CURRENT vs.

OUTPUT VOLTAGE

OUTPUT VOLTAGE(V)

OUTPUTS OURCE CURRENT (mA)

OUTPUT SINK CURENT (mA) NORMALIZED tA

AMBIENT TEMPERATURE

NORMALIZED tA

44.5 55.5 6

0.6

0.8

1.0

1.2

1.4

−55 25 125

0.8

0.9

1.0

1.1

1.2

0255075100

0.6

0.7

0.8

0.9

1.0

1.1

0.8

0.9

1.0

1.1

1.2

44.5 5 5.5 6−55 25 125

0.5

.75

1.0

1.25

1.50

TA=25°C

.50 275 550 825 1000

−5.0

012345 01234

100

120

140

120

TA=25°C

VCC =5.0V TA=25°C

VCC =5.0V

(°C)

CY7C4425/4205/4215

CY7C4225/4235/4245

Orde rin g Inf orm a tio n

64 x 18 Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

10 CY7C4425-10AC A65 64-Lead 14x14 T hin Quad Flatpack Commercial

CY7C4425-10ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425-10AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4425-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-10JI J81 68-Lead Plast ic Leaded Chip Carr ier

15 CY7C4425-15AC A65 64-Lead 14x14 T hin Quad Flatpack Commercial

CY7C4425-15ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425-15AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4425-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-15JI J81 68-Lead Plast ic Leaded Chip Carr ier

25 CY7C4425-25AC A65 64-Lead 14x14 T hin Quad Flatpack Commercial

CY7C4425-25ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425-25AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4425-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-25JI J81 68-Lead Plast ic Leaded Chip Carr ier

35 CY7C4425-35AC A65 64-Lead 14x14 T hin Quad Flatpack Commercial

CY7C4425-35ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425-35AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4425-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4425-35JI J81 68-Lead Plast ic Leaded Chip Carr ier

CY7C4425/4205/4215

CY7C4225/4235/4245

256 x 18 Synchronous FIFO

Speed

(ns) Orderi ng Cod e Package

Name Package

Type Operating

Range

10 CY7C4205-10AC A6 5 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4205-10ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4205-10AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4205-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-10JI J81 68-Lead Plastic Leaded Chip Car rier

15 CY7C4205-15AC A6 5 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4205-15ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4205-15AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4205-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-15JI J81 68-Lead Plastic Leaded Chip Car rier

25 CY7C4205-25AC A6 5 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4205-25ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4205-25AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4205-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-25JI J81 68-Lead Plastic Leaded Chip Car rier

35 CY7C4205-35AC A6 5 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4205-35ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4205-35AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4205-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4205-35JI J81 68-Lead Plastic Leaded Chip Car rier

CY7C4425/4205/4215

CY7C4225/4235/4245

512 x 18 Synchronous FIFO

Speed

(ns) Or dering Co de Package

Name Package

Type Operating

Range

10 C Y7C4215-10AC A 65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4215-10ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4215-10AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4215-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-10JI J81 68-Lead Plasti c Leaded Chip Carrier

15 C Y7C4215-15AC A 65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4215-15ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4215-15AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4215-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-15JI J81 68-Lead Plasti c Leaded Chip Carrier

25 C Y7C4215-25AC A 65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4215-25ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4215-25AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4215-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-25JI J81 68-Lead Plasti c Leaded Chip Carrier

35 C Y7C4215-35AC A 65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4215-35ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4215-35AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4215-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4215-35JI J81 68-Lead Plasti c Leaded Chip Carrier

CY7C4425/4205/4215

CY7C4225/4235/4245

1K x 18 Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

10 CY7C4225-10AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4225-10ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4225-10AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4225-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-10JI J81 68-Lead Plastic Leaded Chip Carrier

15 CY7C4225-15AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4225-15ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4225-15AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4225-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-15JI J81 68-Lead Plastic Leaded Chip Carrier

25 CY7C4225-25AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4225-25ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4225-25AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4225-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-25JI J81 68-Lead Plastic Leaded Chip Carrier

35 CY7C4225-35AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4225-35ASC A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4225-35AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4225-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4225-35JI J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425/4205/4215

CY7C4225/4235/4245

2K x 18 Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

10 CY7C4235-10AC A 6 5 64-Lead 1 4x14 Thin Quad Flatpack Commercial

CY7C4235-10ASC A64 64-Lead 10x10 Thin Quad Flatpa ck

CY7C4235-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4235-10AI A65 64-Lead 14x14 Thin Quad Flatpa ck Industrial

CY7C4235-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4235-10JI J81 68-Lead Plastic Leaded Chip Carrier

15 CY7C4235-15AC A 6 5 64-Lead 1 4x14 Thin Quad Flatpack Commercial

CY7C4235-15ASC A64 64-Lead 10x10 Thin Quad Flatpa ck

CY7C4235-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4235-15AI A65 64-Lead 14x14 Thin Quad Flatpa ck Industrial

CY7C4235-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4235-15JI J81 68-Lead Plastic Leaded Chip Carrier

25 CY7C4235-25AC A 6 5 64-Lead 1 4x14 Thin Quad Flatpack Commercial

CY7C4235-25ASC A64 64-Lead 10x10 Thin Quad Flatpa ck

CY7C4235-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4235-25AI A65 64-Lead 14x14 Thin Quad Flatpa ck Industrial

CY7C4235-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4235-25JI J81 68-Lead Plastic Leaded Chip Carrier

35 CY7C4235-35AC A 6 5 64-Lead 1 4x14 Thin Quad Flatpack Commercial

CY7C4235-35ASC A64 64-Lead 10x10 Thin Quad Flatpa ck

CY7C4235-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4235-35AI A65 64-Lead 14x14 Thin Quad Flatpa ck Industrial

CY7C4235-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4235-35JI J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425/4205/4215

CY7C4225/4235/4245

4K x 18 Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

10 CY7C4245-10AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4245-10ASC A 6 4 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-10JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4245-10AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4245-10ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-10JI J81 68-Lead Plastic Leaded Chip Carrier

15 CY7C4245-15AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4245-15ASC A 6 4 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-15JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4245-15AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4245-15ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-15JI J81 68-Lead Plastic Leaded Chip Carrier

25 CY7C4245-25AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4245-25ASC A 6 4 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-25JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4245-25AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4245-25ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-25JI J81 68-Lead Plastic Leaded Chip Carrier

35 CY7C4245-35AC A65 64-Lead 14x14 Thin Quad Flatpack Commercial

CY7C4245-35ASC A 6 4 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-35JC J81 68-Lead Plastic Leaded Chip Carrier

CY7C4245-35AI A65 64-Lead 14x14 Thin Quad Flatpack Industrial

CY7C4245-35ASI A64 64-Lead 10x10 Thin Quad Flatpack

CY7C4245-35JI J81 68-Lead Plastic Leaded Chip Carrier

CY7C4425/4205/4215

CY7C4225/4235/4245

Package Diagrams

64-Lead Thin Plastic Quad Flat Pack A65

64-Pin Thin Quad Flat Pack A64

CY7C4425/4205/4215

CY7C4225/4235/4245

of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (continued)

68-Lead Plastic Leaded Chip Carrier J81