© Semiconductor Components Industries, LLC, 2018
November, 2018 − Rev. 2
1Publication Order Number:
NCP51530/D
NCP51530
High and Low Side Gate
Driver, High Performance,
700 V, with 3.5 A Source
and 3 A Sink Currents
NCP51530 is a 700 V high side and low side driver with 3.5 A
source & 3 A sink current drive capability for AC−DC power supplies
and inverters. NCP51530 offers best in class propagation delay, low
quiescent current and low switching current at high frequencies of
operation. This device is tailored for highly efficient power supplies
operating at high frequencies. NCP51530 is offered in two versions,
NCP51530A/B. NCP51530A has a typical 60 ns propagation delay,
while NCP51530B has a typical propagation delay of 25 ns.
NCP51530 comes in SOIC8 and DFN10 packages.
Features
•High voltage range: Up to 700 V
•NCP51530A: Typical 60 ns Propagation Delay
•NCP51530B: Typical 25 ns Propagation Delay
•Low Quiescent and Operating Currents
•15 ns Max Rise and Fall Time
•3.5 A Source / 3 A Sink Currents
•Under−voltage Lockout for Both Channels
•3.3 V and 5 V Input Logic Compatible
•High dv/dt Immunity up to 50 V/ns
•Pin to Pin Compatible with Industry Standard Half−bridge ICs.
•Matched Propagation Delay (7 ns Max)
•High Negative Transient Immunity on Bridge Pin
•DFN10 Package Offers Both Improved Creepage and Exposed Pad
Applications
•High−density SMPS for Servers, Telecom and Industrial
•Half/Full−bridge & LLC Converters
•Active Clamp Flyback/Forward Converters
•Solar Inverters & Motor Controls
•Electric Power Steering
SOIC−8
D SUFFIX
CASE 751−07
MARKING
DIAGRAMS
NCP51530 = Specific Device Code
x = A or B version
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
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NCP51530x
ALYW
G
1
8
PINOUT INFORMATION
8 Pin Package
(Top View)
1
1
GND
LIN
HIN
LO
VB
HO
HB
VCC
See detailed ordering and shipping information on page 22 of
this data sheet.
ORDERING INFORMATION
DFN10
MN SUFFIX
CASE 506DJ
151530x
ALYWG
G
(Note: Microdot may be in either location)
10 Pin DFN Package
(Top View)
VB
HB
LO
NC
HO
LIN
HIN
VCC
GND
GND
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HIN
LIN
GND
LO
VB
HO
HB
VCC
SOIC8 DFN10
(Top View) (Top View)
VCC
HIN
LIN
GND
LO
NC
VB
HO
HB
GND
Table 1. PIN DESCRIPTION SOIC 8 PACKAGE
Pin Out Name Function
1 HIN High side input
2 LIN Low side input
3 GND Ground reference
4 LO Low side output
5 VCC Low side and logic supply
6 HB High side supply return
7 HO High side output
8 VB High side voltage supply
Table 2. PIN DESCRIPTION DFN10 PACKAGE
Pin Out Name Function
1 VCC Low side and logic supply
2 HIN High side input
3 LIN Low side input
4 GND Ground reference
5 GND Ground reference
6 LO Low side output
7 NC No Connect
8 HB High side supply return
9 HO High side output
10 VB High side voltage supply
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Figure 3. Internal Block Diagram for NCP51530
r
Pulse
Trigg er
Level
Shifter
UV
DETECT
DELAY
r
UV
Detect
S
R
Q
Q
VCC
VB
HO
LO
HB
VCC
HIN
LIN
GND
Table 3. ABSOLUTE MAXIMUM RATINGS All voltages are referenced to GND pin.
Rating Symbol Value Unit
Input voltage range VCC −0.3 to 20 V
High side boot pin voltage VB−0.3 to 720 V
High side floating voltage VB−VHB −0.3 to 20 V
High side drive output voltage VHO VHB – 0.3 to VB + 0.3 V
Low side drive output voltage VLO −0.3 to VCC + 0.3 V
Allowable hb slew rate dVHB/dt 50 V/ns
Drive input voltage VLIN,
VHIN
−5 to VCC + 0.3 V
Junction temperature TJ(MAX) 150°C
Storage temperature range TSTG −55° to 150°C
ESD Capability (Note 1)
Human Body Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
4000
1000
V
Lead Temperature Soldering
Reflow (SMD Styles ONLY), Pb−Free Versions (Note 2)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods. ESD Human Body Model tested per
AEC−Q100−002(EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11(EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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Table 4. THERMAL CHARACTERSTICS
Rating Symbol Value Unit
Thermal Characteristics, SOIC8 (Note 3)
Thermal Resistance, Junction to Air
RqJA 183 °C/W
Thermal Characteristics, DFN10
Thermal Resistance, Junction to Air (Note 4)
RqJA 162 °C/W
3. Refer to ELECTRICAL CHARACTERSTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Values based on copper area of 50 mm2 of 1 oz thickness and FR4 PCB substrate.
Table 5. RECOMMENDED OPERATING CONDITIONS
Rating Symbol Min Max Unit
Input Voltage Range VCC 10 17 V
High Side Floating Voltage VB−VHB 10 17 V
High Side Bridge pin Voltage VHB −1 700 V
High Side Output Voltage VHO VHB VBV
High Side Output Voltage VLO GND VCC V
Input Voltage on LIN and HIN pins VLIN,
VHIN
GND VCC−2 V
Operating Junction Temperature Range TJ−40 125 °C
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <TJ < 125°C, VCC =VB =12V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
Typical values are at TJ = 25°C.)
Parameters Test Conditions Symbol Min Typ Max Unit
SUPPLY SECTION
VCC quiescent current VLIN=VHIN=0 ICCQ 0.15 0.25 mA
VCC operating current f = 500 kHz, CLOAD = 0 ICCO 2 2.5 mA
Boot voltage quiescent current VLIN = VHIN = 0 V IBQ 0.1 0.15 mA
Boot voltage operating current f = 500 kHz, CLOAD = 0 IBO 2 2.5 mA
HB to GND quiescent current VHS = VHB = 700 V IHBQ 611 mA
INPUT SECTION
Input rising threshold VHIT 2.3 2.7 3.1 V
Input falling threshold VLIT 1 1.4 1.8 V
Input voltage Hysteresis VIHYS 1.3 V
Input pulldown resistance VXIN= 5 V RIN 100 175 250 kW
UNDER VOLTAGE LOCKOUT (UVLO)
VCC ON VCC Rising VCCon 8.6 9.1 9.6 V
VCC hysteresis VCChys 0.5 V
VB ON VB Rising VBon 8 8.5 9 V
VB hysteresis VBhyst 0.5 V
High Side Startup Time Time between VB > UVLO & 1st
HO Pulse
Tstartup 10 ms
LO GATE DRIVER
Low level output voltage ILO = 100 mA VLOL 0.125 V
High level output voltage ILO = −100 mA, VLOH = VCC
−VLO
VLOH 0.150 V
Peak source current VLO = 0 V ILOpullup 3.5 A
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Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <TJ < 125°C, VCC =VB =12V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
Typical values are at TJ = 25°C.)
Parameters UnitMaxTypMinSymbolTest Conditions
LO GATE DRIVER
Peak sink current VLO = 12 V ILOpulldown 3.0 A
HO GATE DRIVER
Low level output voltage IHO = 100 mA VHOL 0.125 V
High level output voltage IHO = −100 mA, VHOH = VHB
–VHO
VHOH 0.150 V
Peak source current VHO = 0 V IHOpullup 3.5 A
Peak sink current VHO = 12 V IHOpulldown 3.0 A
OUTPUT RISE AND FALL TIME
Rise Time LO, HO Cload = 1000 pF TR 8 15 ns
Fall Time LO, HO Cload = 1000 pF TF8 15 ns
DELAY MATCHING
LI ON, HI OFF Pulse width = 1 msTMON 7 ns
LI OFF, HI ON Pulse width = 1 msTMOFF 7 ns
TIMING
Minimum Input Filter (NCP51530A) VXIN = 5 V , Input pulse width
above which output change oc-
curs.
TFT 30 40 ns
PROPAGATION DELAY
NCP51530A
VLI falling to VLO falling Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLFF 60 100 ns
VHI falling to VHO falling Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHFF 60 100 ns
VLI rising to VLO rising Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLRR 60 100 ns
VHI rising to VHO rising Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHRR 60 100 ns
PROPAGATION DELAY
NCP51530B
VLI falling to VLO falling Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLFF 25 40 ns
VHI falling to VHO falling Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHFF 25 40 ns
VLI rising to VLO rising Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDLRR 25 40 ns
VHI rising to VHO rising Cload = 0, Minimum On/Off−time
to register as a valid change =
50 ns
TDHRR 25 40 ns
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Figure 8. VCCON vs Temperature
8.5
8.6
8.7
8.8
8.9
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
VCCON (V)
7.8
7.9
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
9.1
9.2
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
Figure 9. VCCOFF vs Temperature
TEMPERATURE (°C)
VCCOFF (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
Figure 10. VCCHyst vs Temperature
TEMPERATURE (°C)
VHystON (V)
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
9.1
9.2
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
Figure 11. VBON vs Temperature
TEMPERATURE (°C)
VBON (V)
7.4
7.5
7.6
7.7
7.8
7.9
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
VBOFF (V)
Figure 12. VBOff vs Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
VBHyst (V)
Figure 13. VbHyst vs Temperature
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0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
ICCQ (mA)
Figure 14. ICCQ vs Temperature
0
20
40
60
80
100
120
140
160
180
200
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
IBQ (mA)
Figure 15. IBQ vs Temperature
0
2
4
6
8
10
12
14
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
IHB_LEAK (mA)
Figure 16. IHB_Leakage vs Temperature
0
10
20
30
40
50
60
70
80
90
100
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TDLFF (ns)
Figure 17. Low Side Turn on Propagation
Delay vs Temperature
0
10
20
30
40
50
60
70
80
90
100
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TDLRR (ns)
Figure 18. Low Side Turn on Propagation
Delay vs Temperature
0
10
20
30
40
50
60
70
80
90
100
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TDHFF (ns)
Figure 19. High Side Turn off Propagation
Delay vs Temperature
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Figure 20. High Side Turn off Propagation
Delay vs Temperature
0
10
20
30
40
50
60
70
80
90
100
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TDHRR (ns)
0
2
4
6
8
10
12
14
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Tr_LO (ns)
Figure 21. Low Side Rise Time vs Temperature
0
2
4
6
8
10
12
14
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Tr_HO
Figure 22. High Side Rise Time vs
Temperature
0
2
4
6
8
10
12
14
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Tf_LO
Figure 23. Low Side Fall Time vs Temperature
0
2
4
6
8
10
12
14
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Tr_HO
Figure 24. High Side Fall Time vs Temperature
−120
−100
−80
−60
−40
−20
0
0 100 200 300 400 500 600
NEGATIVE PULSE WIDTH (ns)
NEGATIVE PULSE AMPLITUDE
Figure 25. Typical Safe Operating Area with
Negative Transient Voltage on HB Pin
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GENERAL DESCRIPTION
For popular topologies like LLC, half bridge converters,
full bridge converters, two switch forward converter etc.
low−side high−side drivers are needed which perform the
function of both buffer and level shifter. These devices can
drive the gate of the topside MOSFETs whose source node
is a dynamically changing node. The bias for the high side
driver in these devices is usually provided through a
bootstrap circuit.
In a bid to make modern power supplies more compact
and efficient, power supply designers are increasingly
opting for high frequency operations. High frequency
operation causes higher losses in the drivers, hence reducing
the efficiency of the power supply.
NCP51530 is a 700 V high side−low side driver for
AC−DC power supplies and inverters. NCP51530 offers
best in class propagation delay, low quiescent current and
low switching current at high frequencies of operation. This
device thus enables highly efficient power supplies
operating at high frequencies.
NCP51530 is offered in two versions, NCP51530A/B.
NCP51530A has a typical 60 ns propagation delay, while
NCP51530B has propagation delay of 25 ns.
NCP51530 comes in SOIC8 and DFN10 packages.
SOIC8 package of the device is pin to pin compatible with
industry standard solutions.
NCP51530 has two independent input pins HIN and LIN
allowing it to be used in a variety of applications. This device
also includes features wherein, in case of floating input, the
logic is still defined. Driver inputs are compatible with both
CMOS and TTL logic hence it provides easy interface with
analog and digital controllers. NCP51530 has under voltage
lock out feature for both high and low side drivers which
ensures operation at correct VCC and VB voltage levels. The
output stage of NCP51530 has 3.5 A/3 A current source/sink
capability which can effectively charge and discharge a 1 nF
load in 15 ns.
FEATURES
INPUT STAGES
NCP51530 has two independent input pins HIN and LIN
allowing it to be used in a variety of applications. The input
stages of NCP51530 are TTL and CMOS compatible. This
ensures that the inputs of NCP51530 can be driven with
3.3 V or 5 V logic signals from analog or digital PWM
controllers or logic gates.
The input pins have Schmitt triggers to avoid noise
induced logic errors. The hysteresis on the input pins is
typically 1.3 V. This high value ensures good noise
immunity.
NCP51530 comes with an important feature wherein
outputs (HO, LO) stays low in case any of the input pin is
floating. At both the input pins there is an internal pull down
resistor to define its logic value in case the pin is left open
or NCP51530 is driven by open drain signal. The input logic
is explained in the Table 7 below.
NCP51530 input pins are also tolerant to negative voltage
below the GND pin level as long as it is within the ratings
defined in the datasheet. This tolerance allows the use of
transformer as an isolation barrier for input pulses.
NCP51530A features a noise rejection function to ensure
that any pulse glitch shorter than 30 ns will not produce any
output. These features are well illustrated in the Figure 26
below.
NCP51530B has no such filters in the input stages. The
timing diagram NCP51530B is Figure 27 below.
Table 7. INPUT TABLE
S.No LIN HIN LO HO
10000
20101
31010
41111
5 X 0 0 0
6 X 1 0 1
7 X X 0 0
8 0 X 0 0
9 1 X 1 0
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Figure 28. UVLO Timing Diagram
VCCON
LIN
LO
HIN
HO
VBON
VCCOFF
VCC
VB − VHB
UNDER VOLTAGE LOCK−OUT
NCP51530 has under voltage lockout protection on both
the high side and the low side driver. The function of the
UVLO circuits is to ensure that there is enough supply
voltages (VCC and VB) to correctly bias high side and low
side circuits. This also ensures that the gate of external
MOSFETs are driven at an optimum voltage.
If the VCC is below the VCC UVLO voltage, the low side
driver output (LO) and high side driver output (HO) both
remain low.
If VB is below VB UVLO voltage the high side driver
output (HO) remains low. However if the VCC is above VCC
UVLO voltage level, the low side driver output (LO) can
still turn on and off based on the low side driver input (LI)
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and is not affected by the VB status. This ensures proper
charging of the bootstrap capacitor to bring the high side bias
supply VB above UVLO voltage.
Both the VCC and VB UVLO circuits are provided with
hysteresis feature. This hysteresis feature avoids errors due
to ground noise in the power supply. The hysteresis also
ensures continuous operation in case of a small drop in the
bias voltage. This drop in the bias can happen when device
starts switching MOSFET and the operating current of the
device increases. The UVLO feature of the device is
explained in the Figure 30.
Figure 29. NCP51530 Turn ON−OFF Paths
OUTPUT STAGES
The NCP51530 is equipped with two independent drivers.
The output stage of NCP51530 has 3.5 A/3 A current
source/sink capability which can effectively charge and
discharge a 1 nF load in 15 ns.
The outputs of NCP51530 can be turned on at the same
time and there is no internal dead−time built between them.
This allows NCP51530 to be used in topologies like two
switch forward converter.
The figure below show the output stage structure and the
charging and discharging path of the external power
MOSFET. The bias supply VCC or VB supply the energy to
charge the gate capacitance Cgs of the low side or the top
side external MOSFETs respectively. When a logic high is
received from input stage, Qsource turns on and VCC/VB
starts charging Cgs through Rg. Once the Cgs is charged to
the drive voltage level the external power MOSFET turns on
the external MOSFET to discharge to GND/HB level.
When a logic low signal is received from the input stage,
Qsource turns off and Qsink turns on providing a path for
gate terminal of
As seen in the figure, there are parasitic inductances in
charging and discharging path of the Cgs. This can result in
a little dip in the bias voltages VCC/VB. If the VCC/VB drops
below UVLO the power supply can shut down the device.
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Figure 30. Low Side Turn−ON Propagation Delay (NCP51530A)
FAST PROPAGATION DELAY
NCP51530 boasts of industry best propagation delay
between input and output. NCP51530A has a typical of
60 ns propagation delay. The best in class propagation delay
in NCP51530 makes it suitable for high frequency
operation.
Since NCP51530B doesn’t have the input filter included,
the propagation delay are even faster. NCP51530B offers
25 ns propagation delay between input and output.
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Figure 34. Bootstrap Circuit
COMPONENT SELECTION
CBOOT CAPACITOR VALUE CALCULATION
NCP51530 has two independent drivers for driving high
side and low side external MOSFETs. The bias for the high
side driver is usually provided through a bootstrap circuit. A
typical bootstrap circuit is shown in the figure 8 below.
The high side driver is biased by the Cboot (bootstrap
capacitor). As can be seen in the circuit, Cboot will charge
only when HB goes to GND level. Low value of Cboot can
result in a little dip in the bias voltages VB. If the VB drops
below UVLO the power supply can shut down the high side
driver. Therefore choosing the right value of Cboot is very
important for a robust design.
An example design for Cboot is given below.
Qg+30 nC, VCC +15 V (eq. 1)
Qb+IBQ *t
discharge +81 mC*5mS+405 pC (eq. 2)
Qtot +Qg)Qb+30 nC )405p +30.4 pC (eq. 3)
Cboot +
Qtot
Vripple
+
30.4 nC
150 mV +203 nF (eq. 4)
Qg is equivalent gate charge of the FET
IBQ is the boot quiescent current
tdishcharge is the discharge time for bootstrap capacitor
Vripple is the allowed ripple voltage in the bootstrap
capacitor
It is recommended to use a larger value so as to cover any
variations in the gate charge and voltage with temperature.
Rboot RESISTOR VALUE CALCULATION
Rboot resistor value is very important to ensure proper
function of the device. A high value of Rboot would slow
down the charging of the Cboot while too low a value would
push very high charging currents for Cboot. For NCP51530
a value between 2 W and 10 W is recommended for Rboot.
For example Rboot = 5 W
Iboot(pk) +
VCC *VD
Rboot
+
15 V *1V
5W+2.8 A (eq. 5)
Where VD is the bootstrap diode forward drop.
Thus, Rboot value of 5 W keeps the peak current below 2.8 A.
HIN AND LIN INPUT FILTER
For PWM connection on the LIN and HIN pin of the
NCP51530, a RC is recommended to filter high frequency
input noise.
This filter is particularly important in case of NCP51530B
where no internal filter is included.
The recommended value for RLIN/RHIN and CHIN/CLIN
are as below.
RLIN/RHIN = 100 W
CHIN/CLIN = 120 pF
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VCC CAPACITOR SELECTION
VCC capacitor value should be selected at least ten times
the value of Cboot. In this case thus CVCC > 2 mF.
Rgate SELECTION
Rgate are selected to limit the peak gate current during
charging and discharging of the gate capacitance. This
resistance also helps to damp the ringing due to the parasitic
inductances.
For example for a Rgate value of 5 W, the peak source and
sink currents would be limited to the following values.
Rgate +5W(eq. 6)
ILO_Source +
VCC
RLgate )RLOH
+
15 V
6.7 W+2.23 A (eq. 7)
ILO_Sink +
VCC
RLgate )RLOL
+
15 V
6.8 W+2.20 A (eq. 8)
IHO_Source +
VCC *VDboot
RLgate )RHOH
+
14 V
6.7 W+2.09 A (eq. 9)
IHO_Sink +
VCC *VDboot
RLgate )RHOL
+
15 V *1V
6.8 W+2.06 A
(eq. 10)
TOTAL POWER DISSIPATION
Total power dissipation of NCP51530 can be calculated as
follows.
1. Static power loss of device (excluding drivers)
while switching at an appropriate frequency.
Poperating +Vboot *I
BO )VCC *I
CCO (eq. 11)
+14 V * 0.4 mA )15 V * 0.4 mA +11.6 mW
IBO is the operating current for the high side driver
ICCO is the operating current for the low side driver
2. Power loss of driving external FET (Hard
Switching)
Pdrivers +ǒǒQg*V
boostǓ)ǒQg*V
CCǓǓf
(eq. 12)
+ǒǒ30 nC * 14 VǓ)ǒ30 nC * 15 VǓǓ* 100 kHz +87 mW
Qg is total gate charge of the MOSFET
3. Power loss of driving external FET (Soft
Switching)
Pdrivers +ǒǒQgs *V
bootǓ)ǒQgs *V
CCǓǓ*f (eq. 13)
+ǒǒ4nC*14V
Ǔ)ǒ4nC*15V
ǓǓ* 100 kHz +11 mW
4. Level shifting losses
Plevelshifting +ǒVr)VbǓ*Q*f (eq. 14)
+415 V * 0.5 nC * 100 kHz +20.75 mW
Vr is the rail voltage
Q is the substrate charge on the level shifter
5. Total Power Loss (Hard Switching)
Ptotal +Pdriver )Poperating )Plevelshifting (eq. 15)
+11.6 mW )87 mW )20.75 mW +119.35 mW
6. Junction temperature increase
tJ+RqJA *P
total +183 * 0.14 +25°C(eq. 16)
NCP51530
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22
LAYOUT RECOMMENDATIONS
NCP51530 is a high speed and high current high side and
low side driver. To avoid any device malfunction during
device operation, it is very important that there is very low
parasitic inductance in the current switching path. It is very
important that the best layout practices are followed for the
PCB layout of the NCP51530. An example layout is shown
in the figure below. Some of the layout rules to be followed
are listed below.
•Keep the low side drive path LO−Q1−GND as small as
possible. This reduces the parasitic inductance in the
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
•Keep the high side drive loop HO−Q2−HB as small as
possible. This reduces the parasitic inductance in the
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
•Keep CVCC as near to the VCC pin as possible and the
VCC−CVCC−GND loop as small as possible.
•Keep CVB as near to VB pin as possible and
VB−CVB−HB loop as small as possible.
•Keep the HB−GND−Q1 loop as small as possible. This
loop has the potential to produce a negative voltage
spike on the HB pin. This negative voltage spike can
cause damage to the driver. This negative spike can
increase the boot capacitor voltage above the maximum
rating and hence cause damage to the driver.
Figure 35. Example Layout
ORDERING INFORMATION
Device
Propagation Delay
(ns) Input filter Package Shipping†
NCP51530ADR2G 60 Yes SOIC−8
(Pb−Free) 2500 / Tape & Reel
NCP51530BDR2G 25 No SOIC−8
(Pb−Free) 2500 / Tape & Reel
NCP51530AMNTWG 60 Yes DFN10 4x4
(Pb−Free) 4000 / Tape & Reel
NCP51530BMNTWG 25 No DFN10 4x4
(Pb−Free) 4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
NCP51530
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23
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP51530
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24
PACKAGE DIMENSIONS
DFN10 4x4, 0.8P
CASE 506DJ
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A
ALTERNATE CONSTRUCTION A−2 AND DETAIL B AL-
TERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
D2
E2
C
C0.10
C0.10
C0.08
A1 SEATING
PLANE
e
NOTE 3
b
10X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
b0.25 0.35
D4.00 BSC
D2 2.90 3.10
E4.00 BSC
E2 1.85 2.05
e0.80 BSC
E3
L0.35 0.45
1
6
K
A3 0.20 REF
MOUNTING FOOTPRINT*
NOTE 4
A3
DETAIL B
DETAIL A
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
L1 0.00 0.15
ÉÉÉ
ÇÇÇ
ÇÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
A3
4.30
0.80
0.60
10X
DIMENSIONS: MILLIMETERS
0.42
3.20
PITCH
2.15
10X
1
PACKAGE
OUTLINE
RECOMMENDED
10X L
10
5
0.375 BSC
10X
2X
2X
K0.90 −−−
ALTERNATE A−1 ALTERNATE A−2
ALTERNATE B−1 ALTERNATE B−2
0.10 C A B
B
0.10 C A B
B
E3
0.75
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
NCP51530/D
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