Vishay Siliconix
Si9118, Si9119
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Programmable Duty Cycle Controller
FEATURES
• 10 to 200 V Input Range
• Current-Mode Control
• Internal Start-Up Circuit
• Buffer Slope Compensation Voltage
• Soft-Start
• 2.7 MHz Error Amp
• 500 mA Output Drive Current
• Light Load Frequency Fold-Back
• Low Quiescent Current
• Programmable Maximum Duty Cycle, with 80 % as
Default
DESCRIPTION
The Si9118/Si9119 are a BiC/DMOS current-mode pulse
width modulation (PWM) controller ICs for high-frequency
dc/dc converters. Single-ended topologies (forward and
flyback) can be implemented at frequencies up to 1 MHz.
The controller operates in constant frequency mode during
the full load and automatically switches to pulse skipping
mode under light load to maintain high efficiency throughout
the full load range. The maximum duty cycle is easily
programmed with a resistor divider for optimum control.
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
The high-voltage DMOS transistor permits direct operation
from bus voltages of up to 200 V. Other features include a
1.5 % accurate voltage reference, 2.7 MHz bandwidth error
amplifier, standby mode, soft-start and undervoltage lockout
circuits.
The Si9118/Si9119 are available in both standard and lead
(Pb)-free packages.
FUNCTIONAL BLOCK DIAGRAM
CS
+
–
+
–
+
–
Ref
Gen
100 mV
Undervoltage
8.6 V
Error
Amplifier
VCC
+VIN
4.6 V
23µA
Lockout
VREF
–VIN
-VIN
LIMIT
+
–
4
3
7
16
1
14
56 1110
Substrate
+
–
1.0 - 2.0 V
600 mV
PWM
IMAX
Pulse Skip
NI
SS/EN
–+
+
–
EN
+
–
2
R
S
Q
SYNC (Si9119)
12
MAX
13
15 DR
8COSC
9ROSC
9.3 V (VREG)
OSC
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
Vishay Siliconix
Si9118, Si9119
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C above 25 °C.
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating
may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one
Absolute Maximum rating should be applied at any one time.
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol Limit Unit
Voltage Reference VCC to VIN 18
V
+VIN ( Note: VCC < + VIN + 0.3 V) 200
Logic Input (SYNC) - 0.3 to Vcc + 0.3
Linear Input (FB, ICS, ILIMIT
, SS/EN) - 0.3 to Vcc + 0.3
HV Pre-Regulator Input Current (continuous) 5mA
Storage Temperature - 65 to 150
°C
Operating Temperature - 40 to 85
DMAX 3.2 V
Junction Temperature (TJ)150 °C
Power Dissipation (Package)a
16-Pin SOIC (Y Suffix)b 900 mW
Thermal Impedance (JA)
16-Pin SOIC 140 °C/W
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Voltage Reference Vcc to VIN 10 to 16.5
V
+VIN 10 to 200
fOSC 40 kHz to 1 MHz
ROSC 56 k to 1 M
COSC 47 to 200 pF
Linear Inputs 0 to Vcc - 4 V
Digital Inputs 0 to Vcc V
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Limits
D Suffix - 40 to 85 °C
Unit Temp.aMin. Typ.bMax.
Reference
Output Voltage VREF
OSC Disabled, TA = 25 °C Room 3.94 4.0 4.06
V
OSC Disabled, Over Voltage and
Temperature RangescFull 3.88 4.0 4.12
Short Circuit Current ISREF VREF = -VIN - 30 - 5 mA
Load Regulation VR/IRIREF = 0 to - 1mA 10 40 mV
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Vishay Siliconix
Si9118, Si9119
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Parameter Symbol
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Limits
D Suffix - 40 to 85 °C
Unit Temp.aMin. Typ.bMax.
Oscillator
Initial Accuracyd
fOSC ROSC = 374 k COSC = 200 pF 90 100 110
kHz
fOSCcROSC = 70 k COSC = 200 pF 450 500 550
Voltage Stabilitycf/f ROSC = 70 k COSC = 200 pF
f/f = [f(16.5 V) - f(9.5 V)] / f(9.5 V) 12%
Temperature CoefficientcOSC TC - 40 TA 85 °C, fOSC = 100 kHz 200 500 ppm/°C
Sync High Pulse Width (Si9119) 200
nsSync Low Pulse Width (Si9119) 200
Sync Rise/Fall Time (Si9119) 200
Sync Logic Low (Si9119) VIL 0.8
V
Sync Logic High (Si9119) VIH 4
Sync Rangec (Si9119) fEXT 1.05 x fOSC kHz
PWM/PSM
PWM/PSM Logic High VIH 4
V
PWM/PSM Logic Low VIL 0.8
DMAX
Accuracy fOSC = 100 kHz with 1 % Resistor ± 10 %
Error Amplifier (OSC Disabled)
Input BIAS Current IFB VFB = 5 V, NI = VREF < 1.0 ± 200 nA
Input OFFSET Voltage VOS2 ± 5 ± 25 mV
Open Loop Voltage GaincAVOL 65 80 dB
Unity Gain BandwidthcBW 1.8 2.7 MHz
Output Current IOUT
Source (VFB = 3.5 V, NI = VREF)- 1.0 - 2.7
mA
Sink (VFB = 4.5 V, NI = VREF)1.0 2.4
Power Supply Rejection PSRR 10 V VCC 16.5 V 50 80 dB
Pre-Regulator/Start-up
Input Voltagec+VIN IIN = 10 µARoom 200 V
Input Leakage Current +IIN VCC 10 V Room 10 µA
Pre-Regulator Start-Up Current ISTART Pulse Width 300 µs, VCC = VULVO Room 8 15 mA
VCC Pre-Regulator Turn-Off
Threshold Voltage VREG IPRE_REGULATOR = 15 µARoom 8.7 9.3 9.8
V
Undervoltage Lockout VUVLO Room 8.0 8.6 9.3
VREG - VUVLO VDELTA Room 0.3 0.7
Supply
Supply Current ICC CLOAD 50 pF, fOSC = 100 kHZ 1.9 3.0 mA
SPECIFICATIONS
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
Vishay Siliconix
Si9118, Si9119
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Room = 25 °C, Full = as determined by the operating temperature suffix.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Guaranteed by design, not subject to production test.
d. CSTRAY 5 pF on COSC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TIMING WAVEFORMS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Limits
D Suffix - 40 to 85 °C
Unit Temp.aMin. Typ.bMax.
Protection
Current Limit Treshold Voltage VI(Limit) VFB = 0, NI = VREF 0.5 0.6 0.7 V
Current Limit Delay to OutputctdVSENSE 0.85 V, See Figure 1 77 100 ns
Soft-Start Current ISS - 12 - 23 - 30 µA
Output Inhibit Voltage VSS(off) Soft-Start Voltage to Disable Driver Output 0.5 1.26 V
Pulse Skipping Threshold
Voltage
VPS 80 100 120 mV
Mosfet Driver
Output High Voltage VOH IOUT = - 10 mA Room
Full
VCC - 0.3
VCC - 0.5 V
Output Low Voltage VOL IOUT = 10 mA Room
Full
0.3
0.5
Output ResistancecROUT IOUT = 10 mA, Source or Sink Room
Full
20
25
30
50
Rise Timectr
CL = 500 pF
Room 40 75
ns
Fall TimectrRoom 40 75
SPECIFICATIONS
Figure 1.
90 %
0.85
50 %
0
td
tr 10 ns
VCC
0
Current
Sense
Output
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Vishay Siliconix
Si9118, Si9119
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless noted)
Oscillator Frequency
Supply Current vs. Output Frequency
)zHk(f TUO
2 x 1000
10
2 x 100
2 x 10
100 1000
47 pF
200 pF
100 pF
150 pF
Note: These curves were measured
in a board with 3.5 pF of
external parasitic
capacitance.
rOSC – Oscillator Resistance (k )
)Am( tnerruC
y
lppuS –
IC
C
fOUT – Output Frequency (kHz)
36
0 200 400 600 800 1000
28
20
12
4
0
32
24
16
8
CL = 2500 pF
CL = 1000 pF
CL = 0 pF
VCC = 12 V
COSC = 47 pF
Output Driver Rise and Fall Time
Supply Current vs. Supply Voltage
)sn( emiT llaF dna esiR tuptuO
VCC – Supply Voltage (V)
0
9 10111213141516
50
100
150
200
tr for CL = 2500 pF
tf for CL = 2500 pF
17
tr for CL = 1000 pF
tf for CL = 1000 pF
tr 10 % to 90 %
tf 90 % to 10 %
VCC – Supply Voltage (V)
)Am( tner
r
uC
y
l
pp
uS
–
IC
C
0
9 10111213141516
3
6
9
12
17
ROSC = 127 k
COSC = 47 pF
fs = 500 kHz
CL = 1000 pF
CL = 0 pF
Switching Frequency vs. Supply Voltage
)
zH
M
(
y
cneuqer
F gn
ih
c
ti
w
S
VCC – Supply Voltage (V)
89 10111213141516
0.85
0.90
1.00
1.05
17
0.95
ROSC = 56 k
COSC = 100 pF
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
Vishay Siliconix
Si9118, Si9119
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PIN CONFIGURATIONS AND ORDERING INFORMATION
ORDERING INFORMATION
Part Number Temperature Range Package
Si9118DY
- 40 to 85 °C SOIC-16
Si9118DY-T1
Si9118DY-T1-E3
Si9119DY
Si9119DY-T1
Si9119DY-T1-E3
PIN DESCRIPTION
Pin Number Symbol Description
1+VIN Input bus voltage ranging from 10 V to 200 V.
2 PWM/PSM Connected to VREF forces the converter into PWM mode. Connected to -VIN forces the converter into PSM
mode.
3VREF 4 V reference voltage. Decouple with 0.1 µF ceramic capacitor.
4NI Non-inverting input of an error amplifier.
5FB Inverting input of an error amplifier.
6COMP Error amplifier output for external compensation network.
7SS/EN Programmable soft-start with external capacitor or externally controlled disable mode.
8COSC External capacitor to determine the switching frequency.
9ROSC External resistor to determine the switching frequency.
10 ILIMIT
Pulse by pulse peak current limiting pin. When the current sense voltage exceeds the current limit threshold,
the gate drive signal is terminated. ILIMIT is also used to sense the current in pulse skipping mode.
11 ICS Current sense input to control feedback response.
12 SYNC or VSC Si9118: slope compensation pin. Si9119: clock synchronization pin. Logic high to low transition from external
signal synchronizes the internal clock frequency.
13 DMAX Sets the maximum duty cycle. Internally, the maximum duty cycle is clamped to 80 %.
14 -VIN Single point ground.
15 DRGate drive for the external MOSFET switch.
16 VCC Supply voltage for the IC after the startup transition.
SOIC
Si9118DY
13
14
15
16
2
3
4
1
10
11
125
6
7
9
8
Top View
+VINVCC
ILIMIT
ICS
VREF
DR
NI
-VIN
FB
COMP
SS/EN
VSC
COSC ROSC
DMAX
PWM/PSM
SOIC
Si9119DY
13
14
15
16
2
3
4
1
10
11
125
6
7
9
8
Top View
+VINVCC
ILIMIT
ICS
VREF
DR
NI
-VIN
FB
COMP
SS/EN
SYNC
COSC ROSC
DMAX
PWM/PSM
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Vishay Siliconix
Si9118, Si9119
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STANDARD APPLICATION CIRCUITS
Figure 2. Si9118 15 W Forward Converter Schematic
- 48 V (- 42 to - 56 V)
+V
IN
PWM/PSM
V
REF
NI
FB
COMP
SS/EN
V
CC
I
CS
DR
-V
IN
D
MAX
TL431
Si9420DY
I
LIMIT
C
OSC
R
OSC
V
SC
V
O
Figure 3. Si9119 Forward Converter With External Slope Compensation
- 48 V (- 42 to - 56 V)
+VIN
PWM/PSM
VREF
NI
FB
COMP
SS/EN
VCC
ICS
DR
-VIN
DMAX
ILIMIT
COSC
ROSC
SYNC
Si9420DY
TL431
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Document Number: 70815
S11-0975–Rev. E, 16-May-11
Vishay Siliconix
Si9118, Si9119
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DETAILED OPERATIONAL DESCRIPTION
Start-Up
Si9118/Si9119 are designed with internal depletion
mode MOSFET capable of powering directly from the
high input bus voltage. This feature eliminates the
typical external start-up circuit saving valuable space
and cost. But, most of all, this feature improves the
converter efficiency during full load and has an even
greater impact on light load. With an input bus voltage
applied to the +VIN pin, the VCC voltage is regulated to
9.3 V. The UVLO circuit prevents the controller output
driver section from turning on, until VCC voltage
exceeds 8.7 V. In order to maximize converter
efficiency, the designer should provide an external
bootstrap winding to override the internal VCC
regulator. If external VCC voltage is greater than 9.3 V,
the internal depletion mode MOSFET regulator is
disabled and power is derived from the external VCC
supply. The VCC supply provides power to the internal
circuity as well as providing supply voltage to the gate
drive circuit.
Soft-Start/Enable
The soft-start time is externally programmable with
capacitor connected to the SS/EN pin. A constant
current source provides the current to the SS/EN pin to
generate a linear start-up time versus the capacitance
value. The SS/EN pin clamps the error amplifier output
voltage, limiting the rate of increase in duty cycle. By
controlling the rate of rise in duty cycle gradually, the
output voltage rises gradually preventing the output
voltage from overshooting. The SS/EN pin can also be
used to enable or disable the output driver section with
an external logic signal.
Synchronization
The synchronization to external clock is easily
accomplished by connecting the external clock into the
SYNC pin (Si9119 only). The logic high to low
transition synchronizes the clock. The external clock
frequency must be at least 5 % faster than the internal
clock frequency.
Reference Voltage
The reference voltage for the Si9118/Si9119 are set at
4.0 V. The reference voltage is not connected to the
non-inverting inputs of the error amplifier, therefore,
the minimum output voltage is not limited to reference
voltage. The VREF pin requires a 0.1 µF decoupling
capacitor.
Error Amplifier
The error amplifier gain-bandwidth product is critical
parameter which determines the transient response of
converter. The transient response is function of both
small and large signal responses. The small signal
response is determined by the feedback compensation
network while the large signal response is determined
by the inductor di/dt slew rate. Besides the inductance
value, the error amplifier gain-bandwidth determine the
converter response time. In order to minimize the
response time, Si9118/Si9119 is designed with a
2.7 MHz error amplifier gain-bandwidth product to
provide the widest converter bandwidth possible.
PWM Mode
The converter operates in PWM mode if the PWM/
PSM pin is connected to VREF pin or logic high. As the
load current and line voltage vary, the Si9118/Si9119
maintain constant switching frequency until they reach
minimum duty cycle. Once the output voltage
regulation is exceeded with minimum duty cycle, the
switching frequency will continue to decrease until
regulation is achieved. The switching frequency is
controlled by the external Rosc and Cosc as shown by
the typical oscillator frequency curve. In PWM mode,
output ripple noise is constant reducing EMI concerns
as well as simplifying the filter to minimize the system
noise.
Pulse Skipping Mode
If the PWM/PSM pin is connected to -VIN pin (logic
low), the converter can operate in either PWM or PSM
mode depending on the load current. The converter
automatically transitions from PWM to PSM or vise
versa to maintain output voltage regulation. In PSM
mode, the MOSFET switch is turned on until the peak
current sensed voltage reaches 100 mV and the output
voltage meets or exceeds its regulation voltage. The
converter is operating in pulse skipping mode because
each pulse delivers excess energy into the output
capacitor forcing the output voltage to exceed its
regulation voltage. By forcing the output voltage to
exceed the regulation voltage, succeeding pulses are
skipped until the output voltage drops below the
regulation point. Therefore, switching frequency will
continue to reduce during PSM control as the demand
for output current decreases. The pulse skipping mode
cuts down the switching losses, the dominant power
consumed during low output current, thereby
maintaining high efficiency throughout the entire load
range. With PWM/PSM pin in logic low state, the
converter transitions back into PWM mode, if the peak
current sensed voltage of 100 mV does not generate
the required output voltage. In the region between
pulse skipping mode and PWM mode, the controller
may transition between the two modes, delivering
spurts of pulses. This may cause the current waveform
to look irregular, but this will not overly affect the ripple
voltage. Even in this transitional mode, efficiency
remains high.
Document Number: 70815
S11-0975–Rev. E, 16-May-11
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Vishay Siliconix
Si9118, Si9119
DETAILED OPERATIONAL DESCRIPTION (CONT’D)
Programmable Duty Cycle Control
The maximum duty cycle limit is controlled by the
voltage on DMAX pin. A DMAX voltage of 3.2 V
generates 80 % duty cycle while 0.0 V generates
0 % duty cycle. The 80 % duty cycle is maximum
default condition at 1 MHz switching frequency. The
DMAX voltage can be easily generated using resistor
divider from the reference voltage.The maximum duty
cycle limitation will be different when the converter is
synchronized by an external frequency. If the internal
free running frequency is much slower than the
external SYNC signal (SYNC signal causes the
internal clock to reset before the Cosc voltage ramps
to 3.2 V) , duty cycle is determined by the one shot
discharge time of the oscillator capacitor (100 ns).
Therefore, with 1 MHz SYNC signal, maximum duty
cycle of 90 % can be achieved (100 ns is 10 % of
1 MHz). If the internal free running frequency is very
close to the external SYNC frequency (SYNC signal
causes the internal clock to reset somewhere between
3.2 V to 4 V), duty cycle is determined by the ratio of
Cosc voltage at the SYNC point and the 3.2 V. At this
condition, the maximum duty cycle can be greater than
90 %. Therefore, DMAX voltage must be modified in
order to maintain desired maximum duty cycle.
Slope Compensation
Slope compensation is necessary for duty cycles
greater than 50 % to stabilize the inner current loop
and maintain overall loop stability. In order to simplify
the slope compensation circuitry, the Si9118 provides
the buffered oscillator ramp signal, VSC to be used for
external slope compensation. VSC is only available
when DR is high. The VSC signal super-imposed with
actual current sense signal should be used by the
PWM comparator to determine the duty cycle. The
summation of this signal should be fed into ICS pin. For
optimum performance, proper slope compensation is
required. The amount of slope compensation is
determined by the resistors connected to the ICS pin.
The amplitude of the VSC signal is same as the COSC
pin voltage (4 V). For designs which use with SYNC
pin, instead of VSC pin, the converter can still operate
at duty cycles greater than 50 % by generating an
external slope compensation ramp using a
simple RC circuit from the MOSFET driver output pin
as shown on the application circuit.
Over Current Protection
Si9118/Si9119 are designed with a pulse-to-pulse
peak
current limiting protection circuit to protect itself, and
the load in case of a failure. The voltage across the
sense resistor is monitored continuously and if the
voltage reaches its trigger level, the duty cycle is
terminated. This limits the maximum current delivered
to the load. In order to improve the accuracy of over
current protection from traditional controllers, Si9118/
Si9119 are designed with separate ILIMIT and ICS pins.
Voltage on the ILIMIT pin does not sum in the traditional
slope compensation voltage, which adds error into the
detection level. ICS pin is used to sum the current
sense signal and the slope compensation for loop
stability.
Output Driver Stage
The DR pin is designed to drive a low-side N-Channel
MOSFET. The driver stage is sized to sink and source
peak currents up to 500 mA with VCC = 12 V. This
provides ample drive capability for 50 W of output
power.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70815.
All Leads
0.101 mm
0.004 IN
E
H
C
D
e B A1 LĬ
4312 8756
131416 15 91012 11
Package Information
Vishay Siliconix
Document Number: 72807
28-Jan-04
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SOIC (NARROW): 16-LEAD (POWER IC ONLY)
JEDEC Part Number: MS-012
MILLIMETERS INCHES
Dim Min Max Min Max
A1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B0.38 0.51 0.015 0.020
C0.18 0.23 0.007 0.009
D9.80 10.00 0.385 0.393
E3.80 4.00 0.149 0.157
e1.27 BSC 0.050 BSC
H5.80 6.20 0.228 0.244
L0.50 0.93 0.020 0.037
Ĭ0_8_0_8_
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5912
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Revision: 12-Mar-12 1Document Number: 91000
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
