AMERICAN MICROSYSTEMS, INC.
November 2000
This document contains information on a new product. Specifications and information herein are subject to change without notice. 11.10.00
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC
LVPECL to HCSL/LVTTL Motherboard Clock Driver ICLVPECL to HCSL/LVTTL Motherboard Clock Driver IC
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC
Pr el i m inar y Infor ma tio n
Preliminary Infor mationPr el i m inar y Infor ma tio n
Preliminary Infor mation
1.0 Features
• Distributes one differential LVPECL reference clock
to six differential HCSL clock pairs and two single-
ended LVTTL MREF clocks
• HCSL current levels controlled by IREF current
reference and MULT_0:1 current multiplier pins
• Host clock frequency division selected via the
SEL_A, SEL_B, and SEL_U input signals
• Active-low PWR_DWN# signal disables all outputs
• Tristate output control via SEL_T facilitates board
testing
• Available in a 48-p in SSO P and TSSO P
Figure 1: Block Diagram
PWR_DWN#
FS6058
Current
Adjust
IREF
MULT_0:1
÷4
SEL_T
SEL_A
SEL_B
SEL_U
PECL_P
PECL_N
Divider
Control
÷
÷
VSS_H
VDD_H
HOST_P2:5
HOST_N2:5
VSS_H
VDD_H
HOST_P1,6
HOST_N1,6
VSS_M
VDD_M
MREF_P
MREF_N
Figure 2: Pin Configuration
148
2
3
4
5
6
7
8
47
46
45
44
43
42
41
VDD
VDD_R
VSS
PECL_N
VSS_R
VSS
VSS_H
VDD
9
10
11
12
13
14
15
16
VDD
VSS_L
SEL_T
MULT_0
MULT_1
VSS_L
VDD
SEL_A
17
18
19
20
21
22
23
SEL_B
MREF_P
MREF_N 40
39
38
37
36
35
34
33
VSS_H
HOST_N1
VSS_H
HOST_P2
32
31
30
29
IREF
HOST_P6
HOST_N6
VSS_H
24
FS6058-01
VDD_L
SEL_U
HOST_P5
HOST_P1
VDD_H
25
26
27
28
VDD_I
PECL_P
VSS_M
VSS_I
HOST_N2
VDD_L
PWR_DWN#
VDD_H
HOST_N5
VDD_H
HOST_N4
HOST_P4
HOST_N3
HOST_P3
VDD_H
VDD_M
Pair 1 Pair 2 Pair 3 Pair 4 Pair 5 Pair 6
Table 1: Divider and Power-Down Control
CONTROL INPUTS CLOCK OUTPUTS (MHz)
PWR_
DWN# SEL_
TSEL_
ASEL_
BSEL_
UHOST_P1
HOST_N1 HOST_P2
HOST_N2 HOST_P3
HOST_N3 HOST_P4
HOST_N4 HOST_P5
HOST_N5 HOST_P6
HOST_N6 MREF_P
MREF_N
1 0 0 0 0 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 4
1 0 0 0 1 tristate PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 tristate PECL ÷ 4
1 0 0 1 0 PECL ÷ 4 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 4 PECL ÷ 4
1 0 0 1 1 PECL ÷ 4 PECL ÷ 4 PECL ÷ 4 PECL ÷ 4 PECL ÷ 4 PECL ÷ 4 PECL ÷ 4
1 0 1 0 0 PECL PECL PECL PECL PECL PECL PECL ÷ 4
1 0 1 0 1 tristate PECL PECL PECL PECL tristate PECL ÷ 4
1 0 1 1 0 PECL ÷ 2 PECL PECL PECL PECL PECL ÷ 2 PECL ÷ 4
1 0 1 1 1 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2 PECL ÷ 2
1 1 X X X tristate tristate tristate tristate tristate tristate tristate
HOST_P1 =
2× IREF HOST_P2 =
2× IREF HOST_P3 =
2× IREF HOST_P4 =
2× IREF HOST_P5 =
2× IREF HOST_P6 =
2× IREF MREF_P
= high
0XXXX
HOST_N1 =
tristate HOST_N2 =
tristate HOST_N3 =
tristate HOST_N4 =
tristate HOST_N5 =
tristate HOST_N6 =
tristate MREF_N
= low
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
2
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Preliminary Information
Preliminary InformationPreliminary Information
Preliminary Information
Table 2: Pin Descriptions
AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground;
# = Active-low pin
PIN TYPE NAME DESCRIPTION SUPPLY
44 HOST_N1
45 AO HOST_P1 Differential
output pair 1 Outside
Pair
41 HOST_N2
42 AO HOST_P2 Differential
output pair 2
38 HOST_N3
39 AO HOST_P3 Differential
output pair 3
35 HOST_N4
36 AO HOST_P4 Differential
output pair 4
32 HOST_N5
33 AO HOST_P5 Differential
output pair 5
Inside
Pairs
29 HOST_N6
30 AO HOST_P6 Differential
output pair 6 Outside
Pair
Current-st eeri ng di ff erent i a l current-mode (HCSL) outputs
provided for clocking the CPU.
The output drive current is establis hed vi a a referenc e
current at IREF and a multiplying factor set by MULT_0:1
VDD_H
27 AI IREF A fixed precision resistor from this pin to ground provides a ref erence current used f or the
differential current-mode HOST clock outputs VDD_I
9DOMREF_N
Single-ended c l ock (180° out of phase with MREF_P ) provided as a reference clock to a
memory clock driver
8 DO MREF_P Single-ended c l ock in a pair of outputs reference clock to a memory clock driver VDD_M
17, 18 DI MULT_0
MULT_1 The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs VDD_L
5 PECL_N LVPECL input (com plementary)
4AI PECL_P Dif ferential Input LVPECL input (true) VDD_R
24 DI PWR_DWN# A synchronous active-low LVTTL power-down signal f orces MREF outputs l ow, tristates
HOST_N outputs, and drives HOST_P out put currents to 2xIREF VDD_I
21 DI SEL_A Used in conjunction with SEL_B and SEL_U to select desired output frequenci es
22 DI SEL_B Used in conjunction with SEL_A and SEL_U to select desired output frequenci es
16 DI SEL_T Active high input tristates all outputs
23 DI SEL_U Used in conjunction with SEL_A and SEL_B to select desired output frequenci es
VDD_L
2, 11, 14, 48 P VDD 3.3V core power supply
28, 34, 40, 46 P VDD_H 3. 3V power suppl y f or the differential HOST clock outputs
25 P VDD_I 3.3V power supply for IREF current reference input
13, 19 P VDD_L 3.3V power supply for logic input pins
7 P VDD_M 3.3V power supply f or MREF clock outputs
3 P VDD_R 3. 3V power supply for PECL reference clock input s
1, 12 P VSS Core ground
31, 37, 43, 47 P VSS_H Ground for the differential HOST cl ock outputs
26 P VSS_I Ground for IREF current reference i nput
15, 20 P VDD_L Ground for logic input pins
10 P VSS_M Ground for the MREF clock outputs
6 P VSS_R Ground for PECL inputs
-
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
3
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Pr el i m inar y Infor ma tio n
Preliminary Infor mationPr el i m inar y Infor ma tio n
Preliminary Infor mation
2.0 HOST Buffer Current Contr ol
The c urr ent supplied at the HO ST outputs is c on tr ol led by
two parameters: (1) the value of the programming resistor
from the IREF pin to ground (VSS), and (2) the multiplier
factor determ ined b y the logic setti ng of the MULT _0 and
MULT_1 pins.
The HOST output current is a mirrored and scaled copy
of the ref erence curr ent flowing t hrough th e pro gramm ing
resistor on the IREF pin. The voltage that appears at the
IREF pin is one-third of the voltage at the VDD_I pin.
Therefore, the reference current is
IREF
REF R
I
×
=VDD_I
3
1
.
The mirrored reference current can be increased by
adding one or mor e copies of the m irror cur rent together.
The additional current is controlled by the logic settings
on the MULT_0 and MULT_1 pins.
Table 3: Current Multiplier
MULT_0 MULT_1 MULTPLIER
00
IO = 5 × IREF
01
IO = 6 × IREF
10
IO = 4 × IREF
11
IO = 7 × IREF
Table 4: HOST Current Selection
PROGRAM
RESISTOR REFERENCE
CURRENT CURRENT
MULTIPLIER TRACE
IMPEDANCE OUTPUT
VOLTAGE
60Ω0.71V
475Ω (1%) 2.32mA IO = 5 × IREF 50Ω0.59V
60Ω0.85V
475Ω (1%) 2.32mA IO = 6 × IREF 50Ω0.71V
60Ω0.56V
475Ω (1%) 2.32mA IO = 4 × IREF 50Ω0.47V
60Ω0.99V
475Ω (1%) 2.32mA IO = 7 × IREF 50Ω0.82V
30Ω0.75V
221Ω (1%) 5mA IO = 5 × IREF 25Ω0.62V
30Ω0.90V
221Ω (1%) 5mA IO = 6 × IREF 25Ω0.75V
30Ω0.60V
221Ω (1%) 5mA IO = 4 × IREF 25Ω0.50V
30Ω1.05V
221Ω (1%) 5mA IO = 7 × IREF 25Ω0.84V
NOTE: Shaded row indicates the Primary System Configuration
Table 5: HOST Buffer Clock Outputs
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
Output
Voltage (V) MIN. TYP. MAX.
3.30 0.00 0.00 0.00
3.14 -3.03 -4.22 -5.76
2.97 -5.66 -7.68 -9.86
2.81 -7.87 -10.30 -11.85
2.64 -9.67 -11.91 -12.45
2.48 -11.05 -12.56 -12.84
2.31 -11.98 -12.85 -13.16
2.14 -12.52 -13.07 -13.45
1.98 -12.77 -13.26 -13.72
1.81 -12.91 -13.42 -13.96
1.65 -12.99 -13.54 -14.17
1.48 -13.04 -13.64 -14.36
1.32 -13.07 -13.70 -14.52
1.15 -13.08 -13.73 -14.64
0.99 -13.09 -13.75 -14.71
0.82 -13.11 -13.76 -14.74
0.66 -13.12 -13.78 -14.76
0.49 -13.13 -13.79 -14.78
0.33 -13.13 -13.80 -14.80
0.16 -13.14 -13.81 -14.82
0.00 -13.15 -13.82 -14.83
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
00123
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Max VOH
Data in this table represents nominal characterization data only
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
4
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Preliminary Information
Preliminary InformationPreliminary Information
Preliminary Information
3.0 Electrical Specifications
Table 6: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (V I < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy
electrost a tic discharge.
Table 7: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Core (VDD) 3.135 3.3 3.465 V
Supply Voltage VDD Cloc k B uffers
(VDD_H, V DD_I, VDD_M, VDD_R, VDD_L) 3.135 3.3 3.465 V
Operating Temperature Range TA070°C
Reference Frequenc y Range MHz
Input Rise/Fall Time 200 ps
Input Dut y Cycle 40 60 %
Input High-Level V olt age 2.135 2.420 V
Input Low-Level Volt age Required LVPECL signalling parameters 1.490 1.825 V
Load Capacitance CLMREF_P, MREF_N 10 30 pF
Load Resistance RLHO ST _P1 to HOST_P 6,
HOST_N1 to HOST_N6 20 105 Ω
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
5
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Pr el i m inar y Infor ma tio n
Preliminary Infor mationPr el i m inar y Infor ma tio n
Preliminary Infor mation
Table 8: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs IDD fHOST = 133MHz; all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF mA
Supply Current, Static IDDs PWR_DWN# low, all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF µA
LVTTL Digital Inputs (PWR_DWN#, MULT_0, MULT_1, SEL_U, SEL_A, SEL_B, SEL_T)
High-Level Input V olt age VIH 2.0 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
Input Leakage Current IIL -5 +5 µA
PECL Reference Inputs (PECL_P, PECL_N)
High-Level Input V olt age VIH
Low-Level Input V oltage VIL
Input Leakage Current IIL
Current Reference (IREF)
Bias Voltage VOH no load 1.1 V
Short Circuit Out put Source Current IOH VO = 0V mA
MREF_P, MREF_N Clock Outputs (Type 5 Clock Driver)
IOH min VDD_M, VDD_R, V DD_66 = 3.135V,
VO = 1.0V -33
High Level Output Source Current IOH ma x VDD_M, VDD_R, VDD_66 = 3.465V,
VO = 3.135V -33 mA
IOL min VDD_M, VDD_R, VDD_66 = 3.135V,
VO = 1.95V 30
Low Level Output Sink Current IOL max VDD_M, VDD_R, VDD_66 = 3.465V,
VO = 0.4V 38 mA
zOL Measured at 1.65V, output driving low 12 55
Output Impedance zOH Measured at 1.65V, output driving high 12 55 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Out put Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA
Short Circuit Out put Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA
HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Buffer)
Crossover V olt age VXRS = 33.2Ω, RP = 49.9Ω,
RIREF = 475Ω, IOH = 6 × IREF 45 55 %VOH
VO = 0.65V, RIREF = 475Ω, IOH = 6 × IREF 12.9
High-Level Output Sourc e Current IOH VO = 0.74V, RIREF = 475Ω, IOH = 6 × IREF 14.9 mA
VDD = 3.30V, over settings in Table 4 -7 +7
Output Source Current Toleranc e ∆IOH VDD_I=3.3V±5%, over settings in Table 4 -12 +12 %IOH
Output Impedance zOH ∆VO/∆IO, where VO1 = 1.0V, V O2 = VSS,
RIREF = 475Ω, IOH = 6 × IREF 3000 Ω
Tristate Output Current IOZ -10 10 µA
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
6
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Preliminary Information
Preliminary InformationPreliminary Information
Preliminary Information
Table 9: MCLK_P, MCLK_N Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX. Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -49 -83 -132
0.2 11 17 24 0.2 -48 -83 -131
0.4 21 32 45 0.4 -48 -82 -130
0.6 30 45 64 0.6 -47 -81 -129
0.8 37 56 79 0.8 -47 -80 -127
1.0 43 65 92 1.0 -46 -79 -126
1.2 47 73 103 1.2 -46 -78 -124
1.4 50 78 112 1.4 -45 -76 -121
1.6 53 82 117 1.6 -43 -74 -117
1.8 54 84 120 1.8 -41 -70 -112
2.0 55 85 121 2.0 -37 -65 -105
2.2 55 85 122 2.2 -33 -59 -97
2.4 55 86 123 2.4 -28 -52 -87
2.6 56 86 123 2.6 -22 -43 -74
2.8 56 86 124 2.8 -14 -32 -60
3.0 56 87 124 3.0 -6 -20 -45
3.2 87 124 3.2 -7 -27
3.4 125 3.4 -7
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
00.511.522.533.5
Outpu t Voltag e (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
7
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Pr el i m inar y Infor ma tio n
Preliminary Infor mationPr el i m inar y Infor ma tio n
Preliminary Infor mation
Table 10: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Tristate Enable Delay * tDZL, tDZH SEL_A:B=00, SEL133/100#=0 1.0 10 ns
Tristate Disable Delay * tDLZ, tDHZ SEL_A:B=11, SEL133/100#=0 1.0 10 ns
Clock Stabilization (on power-up) * tSTB via PWR_DWN# 3.0 ms
HOST_P1:6, HOST_N1:6 Clock Outputs
Duty Cycle * dtRatio of high pulse width to one clock period at VX,
RIREF = 475Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω45 55 %
Clock Skew * tsk(o) HOST pai r to HOST pair @ VX, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω100 ps
Jitter, Additive Period
(peak-peak) * tj(∆P) Rising edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9ΩtJ(IN)+
100 ps
Rise Time * t rRi sing edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω175 450 ps
Rise/F all Time Matchi ng* Rising edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω20 %
MR EF_P, MR EF_N C l ock Ou tp uts
Duty Cycle * dtRatio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Additive Period
(peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=30pF tJ(IN)+
100 ps
tr min Measured @ 0.4V – 2.4V; CL=10pF 0.4
Rise Time * tr ma x Measured @ 0.4V – 2.4V; CL=30pF 1.6 ns
tf mi n Measured @ 2.4V – 0.4V; CL=10pF 0.4
Fall Time * tf max Measured @ 2.4V – 0.4V; CL=30pF 1.6 ns
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
8
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Preliminary Information
Preliminary InformationPreliminary Information
Preliminary Information
4.0 Package Information
Table 11: 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.095 0.110 2.41 2.79
A10.008 0.016 0.20 0.41
b 0.008 0.0135 0.20 0.34
c 0.005 0.010 0.13 0.25
D 0.620 0.630 15.75 16.00
E 0.395 0.420 10.03 10.67
E10.291 0.299 7.39 7.59
e 0.025 BSC 0. 64 BSC
h 0.015 0.025 0.38 0.64
L 0.020 0.040 0.51 1.01
θ0°8°0°8°
E
E
1
48
1
AMERICAN MICROSYSTEMS, INC.
b
DA
1
SEATING PLANE
A
e
c
L
θ
h × 45°
Table 12: 48-pin SSOP (0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Ai r flow = 0 m/s 93 °C/W
Lead Inductanc e, Self L11 Longest lead 5.5 nH
L12 Longest lead to any 1st adjacent lead 3.0
Lead Inductanc e, Mutual L13 Longest lead to any 2nd adjacent lead 2.1 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.94 pF
C12 Longest lead to any 1st adjacent lead 0.46
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.05 pF
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
9
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Pr el i m inar y Infor ma tio n
Preliminary Infor mationPr el i m inar y Infor ma tio n
Preliminary Infor mation
Table 13: 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A10.002 0.006 0.05 0.15
b 0.0067 0.011 0.17 0.27
c 0.0035 0.008 0.09 0.20
D 0.488 0.496 12.40 12.60
E 0. 318 BSC 8.10 BSC
E10.236 0.244 6.00 6.20
e 0.019 BSC 0. 50 BSC
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
θ10°8°0°8°
θ212° REF 12° REF
θ312° REF 12° REF
E
1
AMERICAN MI CROSY STEM S, IN C.
E
1
48
be
DA
1
SEATING PLA NE
Ac
L
θ
1
θ
3
θ
2
S
Table 14: 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Ai r flow = 0 m/s 89 °C/W
Lead Inductanc e, Self L11 Longest lead 3.50 nH
L12 Longest lead to any 1st adjacent lead 1.82
Lead Inductanc e, Mutual L13 Longest lead to any 2nd adjacent lead 1.17 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.63 pF
C12 Longest lead to any 1st adjacent lead 0.30
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.03 pF
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
ISO9001ISO9001
ISO9001
QS9000
QS9000QS9000
QS9000
10
FS6058-01
FS6058-01FS6058-01
FS6058-01
LVPECL to HCS L/LVTTL
LVPECL to HCS L/LVTTL LVPECL to HCS L/LVTTL
LVPECL to HCSL/LVTTL Mother board Clock Driver
Motherboard Clock Driver Motherboard Clock Driver
Motherboard Clock Driver I C
ICIC
IC
Preliminary Information
Preliminary InformationPreliminary Information
Preliminary Information
5.0 Ordering Information
Table 15: Device Ordering Codes
DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11915-802 48-pin (0.300”) SS OP 0°C to 70°C (Commercial) Tape and Reel
FS6058-01 11915-202 48-pin (6.1mm ) TSSOP 0°C to 70°C (Commercial) Tape and Reel
6.0 Revision Information
DATE PAGE DESCRIPTION
8/4/00 - This document contains information on a new product. Specific ations and information herein are subject to
change without notic e.
Copyright © 2000 American Microsystems, Inc.
Devices sold by AMI are covered b y the warranty and pat ent indem nific ation pro visions ap pearing in its T erms of Sale
only. AMI m akes no warrant y, express, s tatutory im plied or b y descript ion, r egarding the i nfor m ation set f orth here in or
regarding t he f r eed om of the desc r ibed de vices f r om patent inf r ingement. AMI makes no warranty of merchantabi l ity or
fitness for any pur poses. AMI reser ves the right to discont inue pro duction and c hange s pecific ations and prices a t any
time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by
AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Add ress: http://www.amis.com E-mail: tgp@amis.com
