FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 1.0 * Figure 2: Pin Configuration Features Distributes one differential LVPECL reference clock to six differential HCSL clock pairs and two singleended LVTTL MREF clocks HCSL current levels controlled by IREF current reference and MULT_0:1 current multiplier pins Host clock frequency division selected via the SEL_A, SEL_B, and SEL_U input signals Active-low PWR_DWN# signal disables all outputs * Tristate output control via SEL_T facilitates board testing 45 HOST_P1 PECL_N 5 44 HOST_N1 VSS_R 6 43 VSS_H VDD_M 7 42 HOST_P2 MREF_P 8 41 HOST_N2 MREF_N 9 40 VDD_H VSS_M 10 VDD 11 VSS 12 Available in a 48-pin SSOP and TSSOP VDD_L 13 VDD 14 Figure 1: Block Diagram VSS_L 15 VDD_H HOST_P1,6 HOST_N1,6 / VSS_H PWR_DWN# SEL_T VDD_H PECL_P PECL_N HOST_P2:5 HOST_N2:5 / 37 VSS_H 36 HOST_P4 35 HOST_N4 34 VDD_H SEL_T 16 33 HOST_P5 MULT_0 17 32 HOST_N5 MULT_1 18 31 VSS_H VDD_L 19 30 HOST_P6 VSS_L 20 29 HOST_N6 SEL_A 21 28 VDD_H SEL_B 22 27 IREF SEL_U 23 26 VSS_I PWR_DWN# 24 25 VDD_I Pair 6 MULT_0:1 IREF 38 HOST_N3 Pair 5 Current Adjust 39 HOST_P3 Pair 4 FS6058-01 * 46 VDD_H PECL_P 4 Pair 3 * 47 VSS_H VDD_R 3 Pair 2 * 48 VDD Pair 1 * VSS 1 VDD 2 VSS_H Divider Control SEL_A SEL_B SEL_U VDD_M MREF_P MREF_N /4 VSS_M FS6058 Table 1: Divider and Power-Down Control CONTROL INPUTS CLOCK OUTPUTS (MHz) PWR_ DWN# SEL_ T SEL_ A SEL_ B SEL_ U HOST_P1 HOST_N1 HOST_P2 HOST_N2 HOST_P3 HOST_N3 HOST_P4 HOST_N4 HOST_P5 HOST_N5 HOST_P6 HOST_N6 MREF_P MREF_N 1 0 0 0 0 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 4 1 0 0 0 1 tristate PECL / 2 PECL / 2 PECL / 2 PECL / 2 tristate PECL / 4 1 0 0 1 0 PECL / 4 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 4 PECL / 4 1 0 0 1 1 PECL / 4 PECL / 4 PECL / 4 PECL / 4 PECL / 4 PECL / 4 PECL / 4 1 0 1 0 0 PECL PECL PECL PECL PECL PECL PECL / 4 1 0 1 0 1 tristate PECL PECL PECL PECL tristate PECL / 4 1 0 1 1 0 PECL / 2 PECL PECL PECL PECL PECL / 2 PECL / 4 1 0 1 1 1 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 2 PECL / 2 1 1 X X X 0 X X X X tristate tristate tristate tristate tristate tristate tristate HOST_P1 = 2x IREF HOST_P2 = 2x IREF HOST_P3 = 2x IREF HOST_P4 = 2x IREF HOST_P5 = 2x IREF HOST_P6 = 2x IREF MREF_P = high HOST_N1 = tristate HOST_N2 = tristate HOST_N3 = tristate HOST_N4 = tristate HOST_N5 = tristate HOST_N6 = tristate MREF_N = low This document contains information on a new product. Specifications and information herein are subject to change without notice. ISO9001 QS9000 11.10.00 FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 Table 2: Pin Descriptions AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground; # = Active-low pin PIN 44 45 41 42 38 39 35 36 32 33 29 30 TYPE AO AO AO AO AO AO NAME HOST_N1 HOST_P1 HOST_N2 HOST_P2 HOST_N3 HOST_P3 HOST_N4 HOST_P4 HOST_N5 HOST_P5 HOST_N6 HOST_P6 DESCRIPTION Differential output pair 1 Outside Pair Differential output pair 2 Differential output pair 3 Differential output pair 4 Current-steering differential current-mode (HCSL) outputs provided for clocking the CPU. Inside Pairs The output drive current is established via a reference current at IREF and a multiplying factor set by MULT_0:1 Differential output pair 6 Outside Pair AI IREF A fixed precision resistor from this pin to ground provides a reference current used for the differential current-mode HOST clock outputs 9 DO MREF_N Single-ended clock (180 out of phase with MREF_P) provided as a reference clock to a memory clock driver 8 DO MREF_P Single-ended clock in a pair of outputs reference clock to a memory clock driver 17, 18 DI MULT_0 MULT_1 The logic setting on these two pins selects the multiplying factor of the IREF reference current for the HOST pair outputs 4 AI PECL_N PECL_P Differential Input LVPECL input (complementary) LVPECL input (true) Asynchronous active-low LVTTL power-down signal forces MREF outputs low, tristates HOST_N outputs, and drives HOST_P output currents to 2xIREF 24 DI PWR_DWN# 21 DI SEL_A Used in conjunction with SEL_B and SEL_U to select desired output frequencies 22 DI SEL_B Used in conjunction with SEL_A and SEL_U to select desired output frequencies 16 DI SEL_T Active high input tristates all outputs Used in conjunction with SEL_A and SEL_B to select desired output frequencies 23 DI SEL_U 2, 11, 14, 48 P VDD 28, 34, 40, 46 P VDD_H VDD_I VDD_M VDD_L VDD_R VDD_I VDD_L 3.3V core power supply 3.3V power supply for the differential HOST clock outputs 25 P VDD_I 3.3V power supply for IREF current reference input 13, 19 P VDD_L 3.3V power supply for logic input pins 7 P VDD_M 3.3V power supply for MREF clock outputs 3 P VDD_R 3.3V power supply for PECL reference clock inputs 1, 12 P VSS 31, 37, 43, 47 P VSS_H Ground for the differential HOST clock outputs 26 P VSS_I Ground for IREF current reference input 15, 20 P VDD_L Ground for logic input pins 10 P VSS_M Ground for the MREF clock outputs 6 P VSS_R Ground for PECL inputs ISO9001 QS9000 VDD_H Differential output pair 5 27 5 SUPPLY Core ground 2 - FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 2.0 Table 5: HOST Buffer Clock Outputs HOST Buffer Current Control The current supplied at the HOST outputs is controlled by two parameters: (1) the value of the programming resistor from the IREF pin to ground (VSS), and (2) the multiplier factor determined by the logic setting of the MULT_0 and MULT_1 pins. MIN. The HOST output current is a mirrored and scaled copy of the reference current flowing through the programming resistor on the IREF pin. The voltage that appears at the IREF pin is one-third of the voltage at the VDD_I pin. Therefore, the reference current is I REF 1 x VDD_I 3 . = R IREF The mirrored reference current can be increased by adding one or more copies of the mirror current together. The additional current is controlled by the logic settings on the MULT_0 and MULT_1 pins. Table 3: Current Multiplier MULT_0 MULT_1 MULTPLIER 0 0 IO = 5 x IREF 0 1 IO = 6 x IREF 1 0 IO = 4 x IREF 1 1 IO = 7 x IREF 475 (1%) 2.32mA IO = 5 x IREF 475 (1%) 2.32mA IO = 6 x IREF 475 (1%) 2.32mA IO = 4 x IREF 475 (1%) 2.32mA IO = 7 x IREF 221 (1%) 5mA IO = 5 x IREF 221 (1%) 5mA IO = 6 x IREF 221 (1%) 5mA IO = 4 x IREF 221 (1%) 5mA IO = 7 x IREF 0.00 0.00 0.00 -3.03 -4.22 -5.76 2.97 -5.66 -7.68 -9.86 2.81 -7.87 -10.30 -11.85 2.64 -9.67 -11.91 -12.45 2.48 -11.05 -12.56 -12.84 2.31 -11.98 -12.85 -13.16 2.14 -12.52 -13.07 -13.45 1.98 -12.77 -13.26 -13.72 1.81 -12.91 -13.42 -13.96 1.65 -12.99 -13.54 -14.17 1.48 -13.04 -13.64 -14.36 1.32 -13.07 -13.70 -14.52 1.15 -13.08 -13.73 -14.64 0.99 -13.09 -13.75 -14.71 0.82 -13.11 -13.76 -14.74 0.66 -13.12 -13.78 -14.76 0.49 -13.13 -13.79 -14.78 0.33 -13.13 -13.80 -14.80 0.16 -13.14 -13.81 -14.82 0.00 -13.15 -13.82 -14.83 Output Voltage (V) 0 1 2 3 0 TRACE IMPEDANCE OUTPUT VOLTAGE 60 0.71V 50 0.59V 60 0.85V 50 0.71V 60 0.56V 50 0.47V 60 0.99V 50 0.82V 30 0.75V 25 0.62V 30 0.90V 25 0.75V 30 0.60V 25 0.50V 30 1.05V 25 0.84V -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 30 50 90 Max VOH Data in this table represents nominal characterization data only NOTE: Shaded row indicates the Primary System Configuration ISO9001 QS9000 MAX. 3.14 Output Current (mA) REFERENCE CURRENT CURRENT MULTIPLIER TYP. 3.30 Table 4: HOST Current Selection PROGRAM RESISTOR HIGH DRIVE CURRENT (mA) AT PRIMARY SYSTEM CONFIGURATION Output Voltage (V) 3 FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information 3.0 November 2000 Electrical Specifications Table 6: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C Supply Voltage (VSS = ground) Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 260 C 2 kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 7: Operating Conditions PARAMETER SYMBOL Supply Voltage VDD Operating Temperature Range TA CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Core (VDD) 3.135 3.3 3.465 V Clock Buffers (VDD_H, VDD_I, VDD_M, VDD_R, VDD_L) 3.135 3.3 3.465 V 70 C 0 Reference Frequency Range MHz Input Rise/Fall Time 200 Input Duty Cycle Input High-Level Voltage Required LVPECL signalling parameters Input Low-Level Voltage ps 40 60 % 2.135 2.420 V 1.490 1.825 V Load Capacitance CL MREF_P, MREF_N 10 30 pF Load Resistance RL HOST_P1 to HOST_P6, HOST_N1 to HOST_N6 20 105 ISO9001 QS9000 4 FS6058-01 AMERICAN MICROSYSTEMS, INC. LVPECL to HCSL/LVTTL Motherboard Clock Driver IC Preliminary Information November 2000 Table 8: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded Outputs IDD fHOST = 133MHz; all supplies = 3.465V, RIREF= 475, IOH = 6 x IREF mA Supply Current, Static IDDs PWR_DWN# low, all supplies = 3.465V, RIREF= 475, IOH = 6 x IREF A Overall LVTTL Digital Inputs (PWR_DWN#, MULT_0, MULT_1, SEL_U, SEL_A, SEL_B, SEL_T) High-Level Input Voltage VIH 2.0 VDD+0.3 V Low-Level Input Voltage VIL VSS-0.3 0.8 V Input Leakage Current IIL -5 +5 A PECL Reference Inputs (PECL_P, PECL_N) High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Leakage Current IIL Current Reference (IREF) Bias Voltage VOH no load Short Circuit Output Source Current IOH VO = 0V 1.1 V mA MREF_P, MREF_N Clock Outputs (Type 5 Clock Driver) IOH min VDD_M, VDD_R, VDD_66 = 3.135V, VO = 1.0V IOH max VDD_M, VDD_R, VDD_66 = 3.465V, VO = 3.135V IOL min VDD_M, VDD_R, VDD_66 = 3.135V, VO = 1.95V IOL max VDD_M, VDD_R, VDD_66 = 3.465V, VO = 0.4V zOL Measured at 1.65V, output driving low 12 55 zOH Measured at 1.65V, output driving high 12 55 -10 10 High Level Output Source Current Low Level Output Sink Current Output Impedance -33 mA -33 30 mA 38 A Tristate Output Current IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Buffer) Crossover Voltage VX High-Level Output Source Current IOH Output Source Current Tolerance IOH Output Impedance zOH Tristate Output Current IOZ ISO9001 QS9000 RS = 33.2, RP = 49.9, RIREF = 475, IOH = 6 x IREF VO = 0.65V, RIREF = 475, IOH = 6 x IREF 45 55 12.9 VO = 0.74V, RIREF = 475, IOH = 6 x IREF 14.9 VDD = 3.30V, over settings in Table 4 -7 +7 VDD_I=3.3V5%, over settings in Table 4 -12 +12 VO/IO, where VO1 = 1.0V, VO2 = VSS, RIREF = 475, IOH = 6 x IREF 5 mA %IOH 3000 -10 %VOH 10 A FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 Table 9: MCLK_P, MCLK_N Clock Outputs High Drive Current (mA) MIN. TYP. MAX. Voltage (V) 0 11 21 30 37 43 47 50 53 54 55 55 55 56 56 56 0 17 32 45 56 65 73 78 82 84 85 85 86 86 86 87 87 0 24 45 64 79 92 103 112 117 120 121 122 123 123 124 124 124 125 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 ISO9001 QS9000 Low Drive Current (mA) MIN. TYP. MAX. -49 -48 -48 -47 -47 -46 -46 -45 -43 -41 -37 -33 -28 -22 -14 -6 -83 -83 -82 -81 -80 -79 -78 -76 -74 -70 -65 -59 -52 -43 -32 -20 -7 -132 -131 -130 -129 -127 -126 -124 -121 -117 -112 -105 -97 -87 -74 -60 -45 -27 -7 6 150 125 100 75 Output Current (mA) Voltage (V) 50 25 0 -25 0 0.5 1 1.5 2 2.5 3 3.5 -50 -75 -100 -125 30 -150 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 Table 10: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Tristate Enable Delay * tDZL, tDZH SEL_A:B=00, SEL133/100#=0 1.0 10 ns Tristate Disable Delay * tDLZ, tDHZ SEL_A:B=11, SEL133/100#=0 1.0 10 ns 3.0 ms 55 % Clock Stabilization (on power-up) * tSTB via PWR_DWN# HOST_P1:6, HOST_N1:6 Clock Outputs Ratio of high pulse width to one clock period at VX, RIREF = 475, IOH = 6 x IREF, RS=33.2, RP=49.9 Duty Cycle * dt Clock Skew * tsk(o) HOST pair to HOST pair @ VX, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 100 ps Jitter, Additive Period (peak-peak) * tj(P) Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 tJ(IN)+ 100 ps tr Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 450 ps 20 % 55 % tJ(IN)+ 100 ps Rise Time * 45 175 Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle * Jitter, Additive Period (peak-peak) * Rise Time * Fall Time * ISO9001 QS9000 dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL=30pF tr min Measured @ 0.4V - 2.4V; CL=10pF tr max Measured @ 0.4V - 2.4V; CL=30pF tf min Measured @ 2.4V - 0.4V; CL=10pF tf max Measured @ 2.4V - 0.4V; CL=30pF 7 45 0.4 1.6 0.4 1.6 ns ns FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information 4.0 November 2000 Package Information Table 11: 48-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES 48 MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 0.110 2.41 2.79 A1 0.008 0.016 0.20 0.41 b 0.008 0.0135 0.20 0.34 c 0.005 0.010 0.13 0.25 D 0.620 0.630 15.75 16.00 E 0.395 0.420 10.03 10.67 E1 0.291 0.299 7.39 7.59 e 0.025 BSC 0.64 BSC h 0.015 0.025 0.38 0.64 L 0.020 0.040 0.51 1.01 0 8 0 8 E1 E AMERICAN MICROSYSTEMS, INC. 1 b SEATING PLANE e A h x 45 c L D A1 Table 12: 48-pin SSOP (0.300") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 93 C/W nH Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s Lead Inductance, Self L11 Longest lead 5.5 L12 Longest lead to any 1st adjacent lead 3.0 L13 Longest lead to any 2nd adjacent lead 2.1 C11 Longest lead to VSS 0.94 C12 Longest lead to any 1st adjacent lead 0.46 C13 Longest lead to any 2nd adjacent lead 0.05 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 QS9000 8 nH pF pF FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information November 2000 Table 13: 48-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES A MILLIMETERS MIN. MAX. MIN. MAX. - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 D 0.488 0.496 12.40 12.60 E E1 e L 0.318 BSC 0.236 0.244 0.030 E1 E AMERICAN MICROSYSTEMS, INC. 8.10 BSC 6.00 0.019 BSC 0.018 48 6.20 1 0.50 BSC 0.45 0.75 S 0.008 - 0.20 - 1 0 8 0 8 2 12 REF 12 REF 3 12 REF 12 REF b SEATING PLANE e A D 2 S c A1 3 L 1 Table 14: 48-pin TSSOP (6.1mm) Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 89 C/W nH Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s Lead Inductance, Self L11 Longest lead 3.50 L12 Longest lead to any 1st adjacent lead 1.82 L13 Longest lead to any 2nd adjacent lead 1.17 C11 Longest lead to VSS 0.63 C12 Longest lead to any 1st adjacent lead 0.30 C13 Longest lead to any 2nd adjacent lead 0.03 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 QS9000 9 nH pF pF FS6058-01 LVPECL to HCSL/LVTTL Motherboard Clock Driver IC AMERICAN MICROSYSTEMS, INC. Preliminary Information 5.0 November 2000 Ordering Information Table 15: Device Ordering Codes DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11915-802 48-pin (0.300") SSOP 0 C to 70 C (Commercial) Tape and Reel 11915-202 48-pin (6.1mm) TSSOP 0 C to 70 C (Commercial) Tape and Reel FS6058-01 6.0 Revision Information DATE PAGE 8/4/00 - DESCRIPTION This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright (c) 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 QS9000 10