300 MHz to 1000 MHz
Quadrature Modulator
ADL5370
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency range: 300 MHz to 1000 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 11 dBm @ 450 MHz
Noise floor: −160 dBm/Hz
Sideband suppression: −41 dBc @ 450 MHz
Carrier feedthrough: −50 dBm @ 450 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP_VQ package
APPLICATIONS
Cellular communication systems at 450 MHz
CDMA2000/GSM
WiMAX/broadband wireless access systems
Cable communication equipment
Satellite modems
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
VOUT
LOIP
LOIN
QBBN
QBBP
QUADRATURE
PHASE
SPLITTER
06117-001
Figure 1.
GENERAL DESCRIPTION
The ADL5370 is the first in the fixed-gain quadrature modulator
(F-MOD) family designed for use from 300 MHz to 1000 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.
The ADL5370 provides a greater than 500 MHz, 3 dB baseband
bandwidth, making it ideally suited for use in broadband zero
IF or low IF-to-RF applications and in broadband digital
predistortion transmitters.
The ADL5370 accepts two differential baseband inputs and
a single-ended LO and generates a single-ended 50 Ω output.
The ADL5370 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in
a 24-lead, exposed-paddle, Pb-free, LFCSP_VQ package. Perform-
ance is specified over a −40°C to +85°C temperature range.
A Pb-free evaluation board is available.
ADL5370
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Theory of Operation ...................................................................... 10
Circuit Description..................................................................... 10
Basic Connections .......................................................................... 11
Optimization ............................................................................... 12
Applications Information.............................................................. 13
DAC Modulator Interfacing ..................................................... 13
Limiting the AC Swing .............................................................. 13
Filtering........................................................................................ 13
Using the AD9779 Auxiliary DAC for Carrier Feedthrough
Nulling ......................................................................................... 14
GSM Operation .......................................................................... 14
LO Generation Using PLLs ....................................................... 15
Evaluation Board ............................................................................ 16
Characterization Setup .................................................................. 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
10/06—Revision 0: Initial Version
ADL5370
Rev. 0 | Page 3 of 20
SPECIFICATIONS
VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
ADL5370 LO = 450 MHz
Operating Frequency Range Range over which uncompensated sideband suppression < −30 dBc
Low frequency 300 MHz
High frequency 1000 MHz
Output Power VIQ = 1.4 V p-p differential 6.2 dBm
Output P1 dB 11 dBm
Carrier Feedthrough −50 dBm
Sideband Suppression −41 dBc
Quadrature Error 0.76 Degrees
I/Q Amplitude Balance 0.03 dB
Second Harmonic POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm −65 dBc
Third Harmonic POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm −54 dBc
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone 60 dBm
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone 24 dBm
Noise Floor I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
−160 dBm/Hz
GSM 6 MHz carrier offset, POUT = 6 dBm, PLO = 6 dBm −157 dBc/Hz
LO INPUTS
LO Drive Level1 Characterization performed at typical level −7 0 +7 dBm
Input Return Loss See Figure 9 for a plot of return loss vs. frequency 6 dB
BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
I and Q Input Bias Level 500 mV
Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc2 45 μA
Input Offset Current 0.1 μA
Differential Input Impedance 2900 kΩ
Bandwidth (0.1 dB) LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 70 MHz
Bandwidth (1 dB) LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 350 MHz
POWER SUPPLIES Pin VPS1 and Pin VPS2
Voltage 4.75 5.25 V
Supply Current 205 mA
1 High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
2 See V-to-I converter discussion in the Circuit Description section for architecture information.
ADL5370
Rev. 0 | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V to 2 V
LOIP and LOIN 13 dBm
Internal Power Dissipation 1375 mW
θJA (Exposed Paddle Soldered Down) 54°C/W
Maximum Junction Temperature 159°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADL5370
Rev. 0 | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5370
TOP VIEW
(Not to Scale)
COM1
VPS1
COM1
VPS1
VPS1
VPS1
VPS5
VPS3
VPS4
VPS2
VPS2
V
OUT
1
3
2
4
5
6
18
16
17
15
14
13
COM2
LOIN
LOIP
COM2
COM3
COM3
QBBP
COM4
QBBN
COM4
IBBN
IBBP
7
9
8
10
11
12
24
22
23
21
20
19
06117-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 7, 10 to 12,
21, 22
COM1, COM2,
COM3, COM4
Input Common Pins. Connect to ground plane via a low impedance path.
3 to 6, 14 to 18 VPS1, VPS2, VPS3,
VPS4, VPS5
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground. Adjacent
power supply pins of the same name can share one capacitor (see Figure 25).
19, 20, 23, 24 IBBP, IBBN, QBBN,
QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to 500 mV dc, and must be driven from a low impedance source. Nominal characterized
ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a
500 mV dc bias. These inputs are not self-biased and must be externally biased.
8, 9 LOIP, LOIN 50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled. AC-couple
LOIN to ground and drive LO through LOIP.
13 VOUT Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the load.
Exposed Paddle Connect to ground plane via a low impedance path.
ADL5370
Rev. 0 | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
8
0
1
2
3
4
5
6
7
250 450 650 850 1050 1250 1450
SSB OUTPUT POWER (dBm)
06117-003
LO FREQUENCY (MHz)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Temperature
8
0
1
2
3
4
5
6
7
250 450 650 850 1050 1250 1450
06117-004
SSB OUTPUT POWER (dBm)
VS = 5.25V
VS = 5V
VS = 4.75V
LO FREQUENCY (MHz)
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Supply
5
0
–5 1 10 100 1000
06117-035
OUTPUT POWER VARIANCE (dB)
BASEBAND FREQUENCY (MHz)
Figure 5. I and Q Input Bandwidth Normalized to Gain @ 1 MHz
(fLO = 500 MHz)
250 450 650 850 1050 1250 1450
14
10
12
6
8
2
0
4
06117-006
OUTPUT P1dB (dBm)
LO FREQUENCY (MHz)
T
A
= –40°C
T
A
= +85°C
T
A
= +25°C
Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Temperature
250 450 650 850 1050 1250 1450
14
10
12
6
8
2
0
4
06117-007
OUTPUT P1dB (dBm)
LO FREQUENCY (MHz)
V
S
= 5.25V
V
S
= 4.75V
V
S
= 5V
Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Supply
0180
30
330
60
90
270
300
120
240
150
210
S22 OF OUTPUT
S11 OF LOIP
06117-008
250MHz
250MHz
1450MHz
1450MHz
Figure 8. Smith Chart of LOIP S11 and VOUT S22 .
(fLO from 250 MHz to 1450 MHz)
ADL5370
Rev. 0 | Page 7 of 20
250 450 650 850 1050 1250 1450
0
–5
–10
–15
–20
–25
06117-009
RETURN LOSS (dB)
LO FREQUENCY (MHz)
Figure 9. Return Loss (S11) of LOIP
250 450 650 850 1050 1250 1450
0
–10
–20
–90
–30
–40
–50
–60
–70
–80
06117-010
CARRIER FEEDTHROUGH (dBm)
LO FREQUENCY (MHz)
Figure 10. Carrier Feedthrough vs. fLO and Temperature
Multiple Devices Shown
250 450 650 850 1050 1250 1450
0
–10
–20
–90
–30
–40
–50
–60
–70
–80
06117-011
CARRIER FEEDTHROUGH (dBm)
LO FREQUENCY (MHz)
Figure 11. Carrier Feedthrough vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
250 450 650 850 1050 1250 1450
0
–10
–20
–90
–30
–40
–50
–60
–70
–80
06117-012
SIDEBAND SUPPRESSION (dBc)
LO FREQUENCY (MHz)
TA = –40°C
TA = +85°C
TA = +25°C
Figure 12. Sideband Suppression vs. fLO and Temperature
Multiple Devices Shown
250 450 650 850 1050 1250 1450
0
–10
–20
–90
–30
–40
–50
–60
–70
–80
06117-013
SIDEBAND SUPPRESSION (dBc)
LO FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40°C
Figure 13. Sideband Suppression vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4
–
20
–80
–30
–40
–50
–60
–70
15
–15
10
5
0
–5
–10
06117-014
SSB OUTPUT POWER (dBm)
SECOND ORDER DISTORTION, THIRD ORDE
R
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
BASEBAND INPUT VOLTAGE (V p-p)
SECOND ORDER (dBc)
CARRIER
FEEDTHROUGH
(dBm)
SSB OUTPUT POWER
SIDEBAND
SUPPRESSION (dBc)
THIRD ORDER (dBc)
Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 450 MHz)
ADL5370
Rev. 0 | Page 8 of 20
0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4
–
20
–80
–30
–40
–50
–60
–70
15
–15
10
5
0
–5
–10
06117-015 SSB OUTPUT POWER (dBm)
BASEBAND INPUT VOLTAGE (V p-p)
SECOND ORDER (dBc)
CARRIER
FEEDTHROUGH
(dBm)
SIDEBAND
SUPPRESSION (dBc)
THIRD ORDER (dBc)
SSB OUTPUT POWER
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 900 MHz)
–
20
–80
–30
–40
–50
–60
–70
06117-016
SECOND AND THIRD ORDER DISTORTION (dBc)
250 450 650 850 1050 1250 1450
LO FREQUENCY (Hz)
SECOND ORDER = +85°C
SECOND ORDER = +25°C
SECOND ORDER = –40°C
THIRD
ORDER = +25°C
THIRD
ORDER = +85°C THIRD
ORDER = –40°C
Figure 16. Second- and Third-Order Distortion vs. fLO and Temperature
(Baseband I/Q Amplitude = 1.4 V p-p differential)
06117-034
–
20
–70
–60
–50
–40
–30
–80
–90
7
2
3
4
5
6
1
0
1 10 100
SSB OUTPUT POWER (dBm)
BASEBAND FREQUENCY (Hz)
CARRIER FEEDTHROUGH (dBm)
SSB OUTPUT POWER
SIDEBAND SUPPRESSION (dBc)
SECOND ORDER DISTORTION, THIRD ORDE
R
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
THIRD ORDER (dBc)
SECOND ORDER (dBc)
Figure 17. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. fBB and Temperature (fLO = 450 MHz)
250 450 650 850 1050 1250 1450
30
25
15
20
5
0
10
06117-023
OUTPUT THIRD ORDER INTERCEPT (dBm)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
Figure 18. OIP3 vs. Frequency and Temperature
70
60
30
40
50
20
0
10
06117-024
OUTPUT SECOND ORDER INTERCEPT (dBm)
T
A
= +25°C
T
A
= –40°C
T
A
= +85°C
250 450 650 850 1050 1250 1450
LO FREQUENCY (MHz)
Figure 19. OIP2 vs. Frequency and Temperature
–
20
–70
–60
–50
–40
–30
–80
–90
15
–10
–5
0
5
10
–15
–20
–7–5–3–11357
06117-018
SSB OUTPUT POWER (dBm)
LO AMPLITUDE (dBm)
SECOND ORDER (dBc)
CARRIER
FEEDTHROUGH (dBm)
SSB OUTPUT POWER
SIDEBAND
SUPPRESSION (dBc)
THIRD ORDER (dBc)
SECOND ORDER DISTORTION, THIRD ORDE
R
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 450 MHz)
ADL5370
Rev. 0 | Page 9 of 20
–
20
–70
–60
–50
–40
–30
–80
–90
15
–10
–5
0
5
10
–15
–20
–7–5–3–11357
06117-019
SSB OUTPUT POWER (dBm)
LO AMPLITUDE (dBm)
SECOND ORDER (dBc)
SSB OUTPUT POWER
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
THIRD ORDER (dBc)
SECOND ORDER DISTORTION, THIRD ORDE
R
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 900 MHz)
0.23
0.22
0.21
0.20
0.19
0.17
0.18
0.16
0.15
06117-020
SUPPLY CURRENT (A)
TEMPERATURE (°C)
–40 25 85
V
S
= 5.25V
V
S
= 5V
V
S
= 4.75V
Figure 22. Power Supply Current vs. Temperature
06117-036
16
4
6
8
10
12
14
2
0
NOISE (dBm/Hz) AT 20MHz OFFSET
QUANTITY
–161.4
–161.2
–161.0
–160.8
–160.6
–160.4
–160.2
–160.0
–159.8
–159.6
–159.4
–159.2
–159.0
–158.8
–158.6
F
LO
= 450MHz
Figure 23. 20 MHz Offset Noise Floor Distribution at fLO = 450 MHz
(I/Q Amplitude = 0 mV p-p with 500 mV dc bias)
ADL5370
Rev. 0 | Page 10 of 20
THEORY OF OPERATION
CIRCUIT DESCRIPTION
Overview
The ADL5370 can be divided into five circuit blocks: the local
oscillator (LO) interface, the baseband voltage-to-current(V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 24.
PHASE
SPLITTER
OUT
LOIP
LOIN
IBBP
IBBN
QBBP
QBBN
Σ
06117-032
Figure 24. Block Diagram
The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I and Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the differential-to-single-ended amplifier, which
provides a 50 Ω output interface. The bias cell generates
reference currents for the V-to-I stage and the D-to-S amplifier.
LO Interface
The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. The LO can be driven either single-ended or
differentially. When driven single-ended, the LOIN pin should
be ac-grounded via a capacitor. Each quadrature LO signal then
passes through a limiting amplifier that provides the mixer with
a limited drive signal.
V-to-I Converter
The differential baseband inputs (QBBP, QBBN, IBBN, IBBP)
consist of the bases of PNP transistors, which present a high
impedance. The voltages applied to these pins drive the V-to-I
stage that converts baseband voltages into currents. The differential
output currents of the V-to-I stages feed each of their respective
Gilbert-cell mixers. The dc common-mode voltage at the baseband
inputs sets the currents in the two mixer cores. Varying the
baseband common-mode voltage varies the current in the mixer
and affects overall modulator performance. The recommended
dc voltage for the baseband common-mode voltage is 500 mV dc.
Mixers
The ADL5370 has two double-balanced mixers: one for the in-
phase channel (I channel) and one for the quadrature channel
(Q channel). Both mixers are based on the Gilbert-cell design of
four cross-connected transistors. The output currents from the
two mixers sum together into a load. The signal developed
across this load is used to drive the D-to-S amplifier.
D-to-S Amplifier
The output D-to-S amplifier consists of a totem pole output
stage. The 50 Ω output impedance is established by an on-chip
resistor. The D-to-S output is internally dc-biased and should be
ac-coupled at its output (VOUT).
Bias Circuit
An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage and a temperature independent current for
the D-to-S output stage.
ADL5370
Rev. 0 | Page 11 of 20
BASIC CONNECTIONS
Figure 25 shows the basic connections for the ADL5370.
VPS5
VPS3
VPS4
VPS2
VPS2
VOUT
COM2
LOIN
LOIP
COM2
COM3
COM3
QBBP
COM4
QBBN
COM4
IBBN
IBBP
06117-033
COM1
VPS1
COM1
VPS1
VPS1
VPS1
1
2
3
4
5
6
18
17
16
15
14
13
VOUT
C13
0.1µF C11
OPEN
C12
0.1µF
CLON
100pF
C14
0.1µF
C15
0.1µF
C16
0.1µF
24
23
22
21
20
19
7
8
9
10
11
12
COUT
100pF
VPOS
VPOS
QBBP QBBN IBBN IBBP
EXPOSED PADDLE
CLOP
100pF
LO
GND
Z1
ADL5370
Figure 25. Basic Connections for the ADL5370
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Analog Devices AN-772 application note
discusses the thermal and electrical grounding of the
LFCSP_VQ in greater detail.
Baseband Inputs
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs may
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5370 input range and on the top end by the output compliance
range on most digital-to-analog converters (DAC) from Analog
Devices.
LO Input
A single-ended LO signal should be applied to the LOIP pin
through an ac-coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 7 dBm
to realize an improvement in the noise performance of the
modulator. This improvement is tempered by degradation in
the sideband suppression performance (see Figure 20) and,
therefore, should be used judiciously. If the LO source cannot
provide the 0 dBm level, then operation at a reduced power
below 0 dBm is acceptable. Reduced LO drive results in slightly
increased modulator noise. The effect of LO power on sideband
suppression and carrier feedthrough is shown in Figure 20. The
effect of LO power on GSM noise is shown in Figure 35.
RF Output
The RF output is available at the VOUT pin (Pin 13). This pin
must also be ac-coupled. The VOUT pin has a nominal
broadband impedance of 50 Ω and does not need further
external matching.
ADL5370
Rev. 0 | Page 12 of 20
OPTIMIZATION
The carrier feedthrough and sideband suppression performance
of the ADL5370 can be improved through the use of optimiza-
tion techniques.
Carrier Feedthrough Nulling
Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN) are
equal to zero, and this results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero; and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5370 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (VIOPP − VIOPN)
and (VQOPP − VQOPN) offsets. The I-channel offset is held constant
while the Q-channel offset is varied, until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant while the offset on the I-
channel is adjusted, until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 26 shows the relationship of carrier feedthrough vs. dc
offset as null.
–
60
–88
–84
–80
–76
–72
–68
–64
–300 –240 –180 –120 –60 0 60 120 180 240 300
06117-027
CARRIER FEEDTHROUGH (dBm)
V
P
–V
N
OFFSET (µV)
Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz
Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied
VIOPP = VIOPN = 500 mV, or
VIOPP − VIOPN = VIOS = 0 V
When an offset of +VIOS is applied to the I-channel inputs
VIOPP = 500 mV + VIOS/2, and
VIOPN = 500 mV − VIOS/2, such that
VIOPP − VIOPN = VIOS
The same applies to the Q channel.
It is often desirable to perform a one-time carrier null calibra-
tion. This is usually performed at a single frequency. Figure 27
shows how carrier feedthrough varies with LO frequency over a
range of ±50 MHz on either side of a null at 450 MHz.
–
25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
400 410 420 430 440 450 460 470 480 490 500
06117-028
CARRIER FEEDTHROUGH (dBm)
LO FREQUENCY (MHz)
Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 450 MHz
Sideband Suppression Optimization
Sideband suppression results from relative gain and relative
phase offsets between the I and Q channels and can be
suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by the
gain and phase imbalances.
0dB
0.0125dB
0.025dB
0.05dB
0.125dB
0.25dB
0.5dB
1.25dB
2.5dB
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.01 0.1 1 10 100
06117-026
SIDEBAND SUPPRESSION (dBc)
PHASE ERROR (Degrees)
Figure 28. Sideband Suppression vs. Quadrature Phase Error for Various
Quadrature Amplitude Offsets
Figure 28 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.
The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.
ADL5370
Rev. 0 | Page 13 of 20
APPLICATIONS INFORMATION
DAC MODULATOR INTERFACING
The ADL5370 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.
Driving the ADL5370 with an Analog Devices TxDAC®
An example of the interface using the AD9779 TxDAC is shown
in Figure 31. The baseband inputs of the ADL5370 require a dc
bias of 500 mV. The average output current on each of the
outputs of the AD9779 is 10 mA. Therefore, a single 50 Ω
resistor to ground from each of the DAC outputs results in an
average current of 10 mA flowing through each of the resistors,
thus producing the desired 500 mV dc bias for the inputs to the
ADL5370.
06117-029
RBIP
50Ω
RBIN
50Ω
93
92
19
20
OUT1_N
OUT1_P
IBBN
IBBP
AD9779 ADL5370
RBQN
50Ω
RBQP
50Ω
84
83
23
24
OUT2_P
OUT2_N
QBBP
QBBN
Figure 29. Interface Between the AD9779 and ADL5370 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5370 Baseband Inputs
The AD9779 output currents have a swing that ranges from 0 mA
to 20 mA. With the 50 Ω resistors in place, the ac voltage swing
going into the ADL5370 baseband inputs ranges from 0 V to 1 V.
A full-scale sine wave out of the AD9779 can be described as a
1 V p-p single-ended (or 2 V p-p differential) sine wave with a
500 mV dc bias.
LIMITING THE AC SWING
There are situations in which it is desirable to reduce the ac
voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the interface.
This resistor is placed in shunt between each side of the
differential pair, as shown in Figure 30. It has the effect of
reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.
06117-030
RBIP
50Ω
RBIN
50Ω
93
92
19
20 IBBN
IBBP
AD9779 ADL5370
RBQN
50Ω
RBQP
50Ω
84
83
23
24
RSLI
100Ω
RSLQ
100Ω
OUT1_N
OUT1_P
OUT2_P
OUT2_N
QBBP
QBBN
Figure 30. AC Voltage Swing Reduction Through the Introduction
of a Shunt Resistor Between Differential Pair
The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing. Figure 31 shows the
relationship between the swing-limiting resistor and the peak-
to-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
010 100 1000 10000
06117-025
DIFFERENTIAL SWING (V p-p)
R
L
(Ω)
Figure 31. Relationship Between the AC Swing-Limiting Resistor and the
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
FILTERING
It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing that was discussed in the Limiting the
AC Swing section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting
resistors and the ac swing-limiting resistor. Doing so establishes
the input and output impedances for the filter.
An example is shown in Figure 32 with a third-order elliptical
filter with a 3 dB frequency of 3 MHz. Matching input and output
impedances makes the filter design easier, so the shunt resistor
chosen is 100 Ω, producing an ac swing of 1 V p-p differential.
ADL5370
Rev. 0 | Page 14 of 20
06117-031
RBIP
50Ω
RBIN
50Ω
93
92
19
20 IBBN
IBBP
AD9779 ADL5370
RBQN
50Ω
RBQP
50Ω
84
83
23
24
RSLI
100Ω
RSLQ
100Ω
OUT1_N
OUT1_P
OUT2_P
OUT2_N
QBBP
QBBN
LPI
2.7nH
LNI
2.7nH
1.1nF
C1I
1.1nF
C2I
LNQ
2.7nH
LPQ
2.7nH
1.1nF
C1Q
1.1nF
C2Q
Figure 32. DAC Modulator Interface with 3 MHz Third-Order Low-Pass Filter
USING THE AD9779 AUXILIARY DAC FOR CARRIER
FEEDTHROUGH NULLING
The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator. Figure 33 shows the interface required
to utilize the auxiliary DACs. This adds four resistors to the
interface.
06117-041
RBIP
50Ω
RBIN
50Ω
93
90
92
19
20 IBBN
IBBP
AD9779 ADL5370
RBQN
50Ω
RBQP
50Ω
84
87
89
83
86
23
24
RSLI
100Ω
RSLQ
100Ω
OUT1_N
AUX1_N
AUX2_N
OUT1_P
AUX1_P
OUT2_P
AUX2_P
OUT2_N
QBBP
QBBN
LPI
2.7nH
LNI
2.7nH
1.1nF
C1I
1.1nF
C2I
LNQ
2.7nH
LPQ
2.7nH
1.1nF
C1Q
1.1nF
C2Q
250Ω
500Ω
500Ω
500Ω
500Ω
250Ω
250Ω
250Ω
Figure 33. DAC Modulator Interface with Auxiliary DAC Resistors
GSM OPERATION
Figure 34 shows the GSM EVM and spectral mask performance
vs. output power for the ADL5370 at 450 MHz. For a given LO
amplitude, the performance is independent of output power.
–
35
–56
–49
–42
–63
–70
–77
–84
–91
2.0
1.5
1.0
0.5
0
01234567
06117-039
250kHz, 400kHz, 600kHz, AND 1200kHz
SPECTRAL MASK (dBc/30KHz)
RMS AND PEAK EVM (%)
OUTPUT POWER (dBm)
250kHz
400kHz
600kHz
EVM
RMS
(%)
EVM
PK
(%)
1200kHz
Figure 34. GSM EVM and Spectral Performance vs. Channel Power at
450 MHz vs. Output Power; LO Power = 0 dBm
Figure 35 shows the GSM EVM, spectral mask performance
and 6 MHz offset noise vs. LO amplitude at 450 MHz with an
output power of 6 dBm. Increasing the LO drive level improves
the noise performance but degrades EVM performance.
–
35
–56
–49
–42
–63
–70
–77
–84
–112
–105
–98
–91
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
–6–4–20246
06117-040
6MHz NOISE (dBc/100kHz)
250kHz, 400kHz, 600kHz AND 1200kHz
SPECTRAL MASK (dBc/30kHz)
RMS AND PEAK EVM (%)
LO AMPLITUDE (dBm)
250kHz
400kHz
600kHz
1200kHz
EVM
RMS
(%)
EVM
PK
(%)
6 MHz OFFSET NOISE
Figure 35. GSM EVM, Spectral Performance, and 6 MHz Noise Floor vs.
LO Power at 450 MHz; Output Power = 6 dBm
Figure 35 illustrates that an LO amplitude of 0 dBm provides
the ideal operating point for noise and EVM for a GSM signal
at 450 MHz.
ADL5370
Rev. 0 | Page 15 of 20
LO GENERATION USING PLLS
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with
their maximum frequency and phase noise performance.
Table 4. ADI PLL Selection Table
Part Frequency FIN (MHz)
Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)
ADF4110 550 −91 @ 540 MHz
ADF4111 1200 −87@ 900 MHz
ADF4112 3000 −90 @ 900 MHz
ADF4113 4000 −91 @ 900 MHz
ADF4116 550 −89 @ 540 MHz
ADF4117 1200 −87 @ 900 MHz
ADF4118 3000 −90 @ 900 MHz
The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One is chosen, depending on the local
oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5370, it can be a cheaper alternative
to a separate PLL and VCO solution. Table 5 shows the options
available.
Table 5. ADF4360 Family Operating Frequencies
Part Output Frequency Range (MHz)
ADF4360-0 2400 to 2725
ADF4360-1 2050 to 2450
ADF4360-2 1850 to 2150
ADF4360-3 1600 to 1950
ADF4360-4 1450 to 1750
ADF4360-5 1200 to 1400
ADF4360-6 1050 to 1250
ADF4360-7 350 to 1800
ADF4360-8 65 to 400
TRANSMIT DAC OPTIONS
The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
ADL5370. There are other appropriate DACs, depending on the
level of performance required. Table 6 lists the dual Tx-DACs
offered by Analog Devices.
Table 6. Analog Devices Dual Tx—DAC Selection Table
Part Resolution (Bits) Update Rate (MSPS Min)
AD9709 8 125
AD9761 10 40
AD9763 10 125
AD9765 12 125
AD9767 14 125
AD9773 12 160
AD9775 14 160
AD9777 16 160
AD9776 12 1000
AD9778 14 1000
AD9779 16 1000
All DACs listed have nominal bias levels of 0.5 V and use the same
simple DAC-modulator interface that is shown in Figure 31.
MODULATOR/DEMODULATOR OPTIONS
Tabl e 7 lists other Analog Devices modulators and demodulators.
Table 7. Modulator/Demodulator Options
Part Mod/Demod
Frequency
Range (MHz) Comments
AD8345 Mod 140 to 1000
AD8346 Mod 800 to 2500
AD8349 Mod 700 to 2700
ADL5390 Mod 20 to 2400 External quadrature
ADL5385 Mod 50 to 2200
ADL5371 Mod 700 to 1300
ADL5372 Mod 1600 to 2400
ADL5373 Mod 2300 to 3000
ADL5374 Mod 3000 to 4000
AD8347 Demod 800 to 2700
AD8348 Demod 50 to 1000
AD8340 Vector mod 700 to 1000
AD8341 Vector mod 1500 to 2400
ADL5370
Rev. 0 | Page 16 of 20
EVALUATION BOARD
Populated RoHS-compliant evaluation boards are available for
evaluation of the ADL5370. The ADL5370 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the Power Supply and Grounding
discussion in the Basic Connections section). The evaluation
board is designed without any components on the underside
so heat can be applied to the underside for easy removal and
replacement of the ADL5370.
VPS5
VPS3
VPS4
VPS2
VPS2
VOUT
COM2
LOIN
LOIP
COM2
COM3
COM3
QBBP
COM4
QBBN
COM4
IBBN
IBBP
06117-021
COM1
VPS1
COM1
VPS1
VPS1
VPS1
VPOS
1
2
3
4
5
6
18
17
16
15
14
13
VOUT
C13
0.1µF C11
OPEN
C12
0.1µF
CLON
100pF
C14
0.1µF
C15
0.1µF
C16
0.1µF
24
23
22
21
20
19
7
8
9
10
11
12
COUT
100pF
L12
0Ω
L11
0Ω
VPOS
RFNQ
0Ω
RFPQ
0Ω
QBBP QBBN IBBN IBBP
RFNI
0Ω
RFPI
0Ω
CFNQ
OPEN
CFPQ
OPEN
CFPI
OPEN
CFNI
OPEN
RTI
OPEN
RTQ
OPEN
EXPOSED PADDLE
CLOP
100pF
LO
GND
Z1
ADL5370
Figure 36. ADL5370 Evaluation Board Schematic
0
6117-022
Figure 37. Evaluation Board Layout, Top Layer.
Table 8. Evaluation Board Configuration Options
Component Description Default Condition
VPOS, GND Power Supply and Ground Clip Leads. Not applicable
RFPI, RFNI, RFPQ, RFNQ, CFPI,
CFNI, CFPQ, CFNQ, RTQ, RTI
Baseband Input Filters. These components can be used
to implement a low-pass filter for the baseband signals.
See the Filtering discussion in the Applications
Information section.
RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = Open (0402)
RTQ, RTI = Open (0402)
ADL5370
Rev. 0 | Page 17 of 20
CHARACTERIZATION SETUP
FMOD TEST SETUP
IP
IN
QP
QN
OUT
GNDVPOS
FMOD
LO
I OUT Q OUT
VPOS +5V
LO
OUTPUT
90° 0°
IQ
R AND S SPECTRUM ANALYZER
FSU 20Hz TO 8GHz
I/AM Q/FM
AGILENT 34401A
MULTIMETER
0.175 ADC
AGILENT E3631A
POWER SUPPLY
5.000 0.175A
COM
6V ±25V
+–
+–
AEROFLEX IFR 3416
250kHz TO 6GHz SIGNAL GENERATOR
RF
OUT
FREQ 4MHz LEVEL 0dBm
BIAS 0.5V
BIAS 0.5V
GAIN 0.7V
GAIN 0.7V
0
6117-037
CONNECT TO BACK OF UNIT
+6dBm
RF
IN
Figure 38. Characterization Bench Setup
The primary setup used to characterize the ADL5370 is shown
in Figure 38. This setup was used to evaluate the product as a
single-sideband modulator. The Aeroflex signal generator supplied
the local oscillator (LO) and differential I and Q baseband
signals to the device under test, DUT. The typical LO drive was
0 dBm. The I channel is driven by a sine wave, and the Q channel
is driven by a cosine wave. The lower sideband is the single
sideband (SSB) output.
The majority of characterization for the ADL5370 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the VIOS1 and VQOS
offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT.
1 See the Carrier Feedthrough Nulling section for the definitions of VIOS
and VQOS.
ADL5370
Rev. 0 | Page 18 of 20
FMOD TEST RACK
SINGLE TO DIFFERENTIAL
CIRCUIT BOARD
Q IN DCCM
AGND
I IN DCCM
VN1 VP1
I IN AC
Q IN AC
VPOS +5V
LO
0° 90°
IQ
QP
QN
AGILENT 34401A
MULTIMETER
0.200 ADC
AGILENT E3631A
POWER SUPPLY
5.000 0.350A
COM
6V ±25V
+–
+–
AGILENT E3631A
POWER SUPPLY
0.500 0.010A
COM
VCM = 0.5V
6V ±25V
+–
+–
06117-038
R AND S FSEA 30
SPECTRUM ANALYZER
100MHz TO 4GHz
+6dBm
RF
IN
TEKTRONIX AFG3252
DUAL FUNCTION
ARBITRARY FUNCTION GENERATOR
1MHz
AMPL 700mV p-p
PHASE 0°
1MHz
AMPL 700mV p-p
PHASE 90°
CH1
CH1 OUTPUT
CH2 OUTPUT
CH2 RF
OUT
R AND S SMT 06
SIGNAL GENERATOR
FREQ 4MHz TO 4GHz
LEVEL 0dBm
IN1 IN1
TSEN GND
VPOSB VPOSA
IP
IN
IP
IN
QP
QN
LO
OUT OUTPUT
GND
VPOS
+5V
VPOS +5V
–5V
FMOD
CHAR BD
Figure 39. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling
The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5370 is shown in Figure 39.
The interface board has circuitry that converts the single-ended
I and Q inputs from the arbitrary function generator to differ-
ential I and Q baseband signals with a dc bias of 500 mV.
Undesired sideband nulling was achieved through an iterative
process of adjusting amplitude and phase on the Q channel.
See Sideband Suppression Optimization in the Optimization
section for a more detailed discussion on sideband nulling.
ADL5370
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
1
24
6
7
13
19
18
12
*2.45
2.30 SQ
2.15
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR TOP
VIEW 3.75
BSC SQ
4.00
BSC SQ PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
0.20 REF
0.23 MIN
EXPOSED
PA D
(BOTTOMVIEW)
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Ordering Quantity
ADL5370ACPZ-R21–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 250
ADL5370ACPZ-R71–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 1,500
ADL5370ACPZ-WP1–40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64
ADL5370-EVALZ1 Evaluation Board
1 Z = Pb-free part.
ADL5370
Rev. 0 | Page 20 of 20
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06117-0-10/06(0)
