re aL TO Ne Features * Organization: 131,072 words x 8 bits * High speed ~ 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time * Low power consumption available - Active: 180 mW max (3V, 15 ns) - Standby: 1.8 mW max. CMOS I/O - Very low DC component in active power * 2.0V data retention Equal access and cycle times + Easy memory expansion with CET, CE2, DE inputs Logic block diagram * TTL/LVTTL-compatible, three-state 1/O * 32-pin JEDEC standard packages ~ 300 mil PDIP and SO] Socket compatible with 7C512 (64Kx8) - 400 mil SO] - 8mm x 20mm TSOP ESD protection 2 2000 volts * Latch-up current 2 200 mA * 3.3V and 5.0V versions available + Industrial and commercial temperature available + Intelliwatt" low power and CPG versions available Pin arrangement TSOP DIP. 50] Veco > GND + Input buffer AlL Coy! Pro ag 42 O 31 fea k oe 2B A 29 fea Ag WE Cos Al | 07 cE? E6 Fa A2 5 . AIS Co? 2fo A3 3 5122568 zg . Vee oS 8 35 =) Ad 2 Array bs B . ais E10 2 = . (1,048,576) 3 an yi: = AT L Ly ey 19 A8 a 4 8 cys Bey vy As Cle Fa Column decoder Control r ae circuit je- CET i fe CED ee2nrwertas Keene Selection guide 10 -12 -15 -20 Unit Maximum address access time 10. 12 15 20 ns Maximum output enable access time 3 4 5 ns AS7C1024 160 120 110 mA ASTC1024L 120 95 80 mA Maximum operating current - AS7C3 1024 100 70 65 mA AS7C31024L 60 50 45 mA Maximum static standby current (L) 0.1 0.1 0.1 mA Shaded areas contain advance information. Copyright 1998 Atianice Semiconductor. AB rights reserved.AS7C1024 family Functional description The AS7C1024 and AS7C31024 are high performance CMOS 1.048,576-bit Static Random Access Memories (SRAM) organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tq. tpc, two) of 10/12/15/20 ns with output enable access times (tgg) of 3/3/4/5 ns are ideal for high performance applications. Active high and low chip enables (CET, CE2) permit easy memory expansion with multiple-bank systems. When CET is HIGH or CE2 is LOW the device enters standby mode. If inputs are still toggling, the devices will consume Isp power. If the bus is static, then full standby power is reached (Isp1 or Iggo). The 310241 for example, is guaranteed not to exceed 0.33mW under nominal full standby conditioris. All devices in this family will retain data when Vcc is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CET, CE2). Data on the input pins 1/O0-1/07 is written on the rising edge of WE (write cycle 1) or the active-to-inactive ecige of CET or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have beer: disabled with output enable (OF) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CET, CE2), with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL/LVITL-compatible, and operation is from a single 5V supply or 3.3V supply. 128Kx8 and 64Kx16 SRAMs are also available in ultra-low power Inteliiwact' versions. For Intelliwatt specifications, please see the AS7C31024LL and AS7C31026LL datasheets respectively. The revolutionary pinout (CPG) version of the 128Kx8 may be found as AS7C1025, AS7C31025. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on any pin relative to GND Vv. ~0.5 +7.0 Vv Power dissipation Pp - 1.0 Ww Storage temperature (plastic) Tyg ~55 +150 C Temperature under bias Trias ~10 +85 C DC output current lout - 20 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Expasure ro absolute max- imum rating conditions for extended periods miay affect reliability. Truth table CET CE2 WE DE Data Mode H X X X High Z Standby (Isp, isgr} xX L X Xx High Z Standby (Isp. Iggy) L H H H High Z Output disable L H H L Dour Read L H L xX D Write in Key: X = Dont Care, L = LOW H = HIGHAS7C1024 family Recommended operating conditions Parameter Symbol Min Norninal Max Unit 5V devices Vec 45 5.0 53.9 V Supply voltage 3.3V devices Vec 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V AS7C1024 Vin 2.2 - Veo + 0.5 V Input voltage AS7C31024 Vin 2.0 - Vec + 0.5 V Va -0.5 - 0.8 Vv Va min = ~3.0V for pulse width less than tre /2. DC input/output characteristics, AS7C 1024 family -10 12 15 -20 Parameter Symbol Test conditions Min Max Min Max | Min Max | Min) Max |] Unit Input leakage Vec = Max, : ee current Mu Vin = GND to Voc coe 4 ~ I ~ | ~ I BA Output leakage CET = Vip or CE = Vi, if - : ae t | lo | Vec = Max, og OE = 1 ~ 1 ~ ! LA curren r= GND to Voc ees Vor lo, = 8 mA, Voc = Min -- O4 - O47 - O4f ~ O4] V Output voltage Vou lon =-4 mA, Vec = Min 2:4 = 24 2.4 - 2.4 _ Vv Shaded areas contain advance information. Power supply characteristics, AS7C 1024 and AS7C 1024 -10 -12 -15 -20 Parameter Symbol Test conditions Min) Max Min Max | Min Max | Min Max | Unit . 2 ie og _ _ % _ Opersting , ; CET = Vy, CE2 = Vip. a 8 160 120 110 | mA current aad f= fmax, four = 9 mA L a : - ~ 120] - 95 - 80 | mA jeg CET = Vin or CB2 = Vy. = 55 - 650 | - 40 | - 40 | mA SB f = fay, all inputs toggling | L gee e _ 35 _ 25 ~ 95 | mA ae ply I Chip disabled, f = 0, =o 5 - 5 - 5 . 5 | mA current SBE Vj, $0.2V or Vin 2 Voe-O.2V bo- =~ 05] - 05] - 05 | mA Chip disabled, f = Otq = 25 CT oe eo . ~ . - sB2 y, <0.2V or Vj, 2 Vec-0.2V bee o 0.1 1 | mA Shaded areas contain advance information.AS7C1024 family or Power supply characteristics, AS7C31024 and AS7C31024U 10 12 15 20 Parameter Symbol Test conditions Min Max Min Max | Min Max | Min) Max | Unit er aly lee CEE = Vin. CEA = Vin. Seboy - loo] - 70 | = 65 | mA current P= fmax, Four = 0 mA Le ore 60 | - SO 4 45 | mA Isp CET = Vyy or CE2 = Vi. - $50] - 40} - 40 | mA f= fax L - 35 | ~ 25 1 ~ 25 | mA sae ply Ise Chip disabled, f = 0, a 5S [= 5 | - 5 | mA current Vin $0.2V or Vi, 2 Veg~0.2V bows. - O57 - O58} - 05} mA ea ee Shaded areas contain advance information. Capacitance 7 (f = 1 MHz, T, = Roam temperature, Vcc = 5V) Parameter Symbol Signals Test conditions Max Unit Input capacitance Cin A, CET, CE2. WE, OE Vin = OV 5 pF 1/O capacitance Ciro VO Vin = Vour = OV 7 pF Read cycle 391? -10 12 15 -20 Parameter Symbol Min Max Min Max | Min Max} Min Max] Unit Notes Read cycle time tre 10 12 ~ 15 - 20 - ns Address access time taa = 7 10. ~ 12 - 15 - 20 ns 3 Chip enable (CET) access time tackl = 4000 - 12 - 15 - 20 ns 3, 12 Chip enable (CE2) access time tack2 . ae 10. _ 12 - 15 - 20 ns 3.12 Output enable (OE) access time tog = aS 3 Cos 3 - 4 ~ 5 ns Output hold from address change toy OB 3 ~ 3 ~ 3 - ns 3 CET LOW to output in Low Z tn BOO HL 8H os 45 12 CE2 HIGH to output in Low Z teLz2 3 om 3 - 3 - 3 - ns 4,5, 12 CET HIGH to output in High Z tcHz1 a ~ 4 - 5 ns 4,5, 12 CE2 LOW to output in High Z tcHz2 Oe oe ~ 3 - 4 - 5 ns 4,5, 12 OE LOW to output in Low Z toLz i o- = 0 - 0 ~ 0 - ns 4,5 OE HIGH to output in High Z loHz : = : 3 ~ 3 - 4 ~ 5 ns 4.5 Power up time tp =: 0 : : a 0 - 0 - 0 - ns 4.5.12 Power down time tp ee AQ - 12 - 15 - 20 ns 4,5, 12 ONDUCTORAS7C1024 family Ae: Falling input Key to switching waveforms Rising input Undefined output/dont care Read waveform ] 457.942 Address controlled tre Address > ok D out | CET and CE2 controlled I touz tonzi. tcHz2 D, H# tacei, TACE2 Td OT Data valid Lam ICLZL,tCLZ2 tpp t lee PU | Current : AS 50% 50% ] supplyAS7C1024 family ae: Write cycle 747? -10 12 AS -29 Parameter Symbol Min Max Min Max | Min Max | Min) Max | Unit Notes Write cycle time twe 10 oes 2 = 15 20 - ns Chip enable (CET) to writeend tow) g oe 10 ~ 12 - 12 - ns 12 Chip enable (CE2) towriteend two 9 = 10 ~ {12 - | 12) - ns 12 Address setup to write end taw g 2 10 ~ 12 ~ 12 - ns Address setup time tas Oo 0 - 0 ~ 0 - ns 12 Write pulse width twp : 7 eee 8 ~ 9 ~ 12 - ns Address hold from end of write tay Oo = 0 - 0 ~ 0 - ns Data valid to write end tpw 6 a ~ 6 ~ 9 ~ 10 - ns Data hold time tpbH 0 Se 0 - 0 ~ 0 - ns 4.5 Write enable to output in High Z tz Eg - 5 - 5 - 5 ns a) Output active from write end tow = BS 3 ~ 3 ~ 3 ~ ns 4,5 Shaded areas contain advance information. Write waveform 1] 744442 WE controlied Address WE pw Din Data valid tow D out Write waveform 2 /@JL12 CET and CE2 controlled two law taH town. few? poe twz tow D Data valid T in Dour {DUCTORAS7C1024 family or: Dota retention characteristics #4 Parameter Symbol Test conditions Min Max Unit Vec for data retention Vopr Veo = 2.0V 2.0 - V Data retention current Iecpr CET = Vep-0.2V or 500 (100L) pA Chip deselect to data retention time tepr CE2 < 0.2V 0 ~ ns Operation recovery time tr Vin 2 Vcc-0.2V or tre - ons Vin 2 0.2V Input leakage current thir in - 1 pA Data retention waveform Data retention mode a sg ee Pay ; Vec 4.5V or 2.7V K. Vopr 2 2.0V J) ASN or 2.7V cpr 7 Vv CEL ER AC test conditions - 5V output load: see Figure B. except as noted see Figure C. - 3.3V output load: see Figure D, except as noted see Figure E. Thevenin equivalent: ~ Input pulse level: GND to 3.0V. See Figure A. D 168Q Lav oh ~ Input rise and fall times: 5 ns. See Figure A. u ~ Input and output timing reference levels: 1.5V. +5 +5V 480Q 48002 D, D, +3.0V out out 90% 90% 255 30 pF* 255 SpF* sinctuding scope a , and jig capacitance GND 10% 10% IND GND Figure A: Input waveform Figure B: Output load +3.3V 32002 D, out 35022 30 pF* GND Figure D: Output load Figure C: Output load for to_z. toyz, toz toyz: Low +3.3V 3202 D out 3502 5 pF* GND including scope and jig capacitance Figure C: Output load for teyz. toyz: torz: tonz: tow ALLIANCE SEMICONDUCTORAS7C1024 family oe: Typical DC and AC characteristics Normatized Ice, Isp Normalized access time Output source current (mA) Normalized supply current Icc, Isp vs, supply voltage Voc c 40 45 50 55 Supply voltage (V) 6.0 Normalized access time ta, vs. supply voltage Voc 1.3 4 T, =25T Li 1.0 0.9 0.8 0.7 0.6 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) Output source current [oy vs. output voltage Voy 140 _ mM Q Vec = 5.0V 100 T= 25 nm oS Dm w o oc & & Qo 1.25 2.5 3.75 Output valtage (V) 2 o 5.0 Normalized supply current Ieee Isp a vs. ambient temperature Normalized Ipc, Isg 55-10 35 80 Ambient temperature (C) 125 Normalized access time a vs. ambient temperature TF, 0.9 0.8 Normalized access time 7 07 0.6 ~55 -10 35 80 Ambient temperature ( T) 125 Output sink current lop vs, output voltage Voy 140 120 100 om GR w o oOo ss Output sink current (mA) m~N co 0 0.0 1.25 2.5 3.75 5 Output voitage (V) 0 ALLIANCE SEMICONDUCTOR Normalized supply current Isp, vs, ambient temperature T, {log scaie) mH rm WwW ar an Normalized Ispy be a 2 8 a6 , on wn -10 35 80 i Ambient temperature (T) 29 Normalized supply current lec vs, cycle frequency Normalized Ie V/ (2tpe) Cycle frequency (MHz) 1 tre Typical access time change Ata, vs. output capacitive loading Change in tga (ns) 0 0 250 300 86750 Capacitance (pF) 1000ds. AS7C1024 family Notes 1 During Veg power-up, a pull-up resistor to Voc on CET is required to meet Isp specification 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tcp and toyz are specified with CL = SpF as in Figure C. Transition is measured t500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 WEis HIGH for read cycle. 7 CET and OE are LOW and CE2 is HIGH for read cycle. 8 Address valid prior to or coincident with CE transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10. CET or WE must be HIGH or CE2 LOW during address transitions {1 All write cycle tiniings are referenced from the last valid address to the first transitioning address. 12 CET and CE2 have identical timing. 13 This data applicable to the AS7C1024. The AS7C31024 functions similarly 14 2V data retention applies to cornmercial temperature operating range only. AS7C1024 family ordering codes Package \ Access time 19 ns IZ ons 15 ns 20 ns Plastic DIP, 300 mil New designs using PDIP are discouraged. Contact Alliance Sales for PDIP availability of limited production. AS7C1024-12TJC AS7C1024-15TJC AS7C1024-20TJC AS7C1024L-12TIC AS7C1024L-15TJC AS7C10241-20TJC ASTC31024-12TIC AS7C31024-15TJC AS7C31024-15TIL AS7C31024-20TjC AS7C31024-20T]l AS7C31024L-12TJC AS7C31024L- 15 TJC AS7C31024L-20TIC AS7C1024-12)C AS7C1024-15JC AS7C1024-15]I AS7C1024-20}C AS7C1024-20]1 ASTC1L024L-12]C AS7CLOZ4L-15JC AS7C1L024L-20jC _ASTC1O24-10TIC Plastic SOJ, 300 mil Biss foe Ess astic SO} mi ~(AS7C31024-10TIC ~~ ASTCIO24-10)0- Plastic SOJ, 400 mil area ASTC31024-10/0. AS7C3 1024-1 2JC AS731024-15JC AS7C3 1024-1 5]f AS7C31024-20)C AS7C31024-20]1 AS7C31024L-12)C AS7C31024L-15JC AS7C3 1024L-20)C A$7C1024-12TC AS7C1024-15TC AS7C1024-20TC AS7C1LO24L-12TC AS7C10241-15TC AS7C10241-20TC TSOP 8x20 - ASTC31024-12TC. AS7C031024-15TC AS7C31024-20TC _ASTCAL024L-12TC . ASTC31024L-15TC AS7C31024L-20TC Shaded areas contain advance information. AS7C1024 family part numbering system ASIC x 1024 x KR x PA SRAM _Blank=5V CMOS prefix 3=3.3V CMOS Temperature range C = Commercial, 0 C to 70 T [= Industrial, 40 T to 85 T Package:TP =PDIP 300 mil T =TSOP 8x20 J=SOf400 mil TJ =SOJ 300 mii Device L=low Access number power timeAS7C1024 family