AR0141CS: 1/4-Inch Digital Image Sensor
Features
‡
AR0141CS/D Rev. 6, 4/16 EN 1©Semiconductor Components Industries, LLC 2016,
1/4-Inch Digital Image Sensor
AR0141CS Datasheet, Rev. 6
For the latest datasheet, please visit: www.onsemi.com
Features
• Superior low-light performance
• Latest 3.0 m pixel with ON Semiconductor
DR-Pix technology
• Linear range capture
• 1.0 Mp and 720p (16:9) images
• Support for external mechanical shutter
• Support for external LED or xenon flash
• On-chip phase-locked loop (PLL) oscillator
• Integrated position-based color and lens shading
correction
• Slave mode for precise frame-rate control
• Stereo/3D camera support
• Statistics engine
• Data interfaces: four-lane serial high-speed pixel
interface (HiSPi) differential signaling (SLVS and
HiVCM), or parallel
• Auto black level calibration
• High-speed context switching
• Temperature sensor
Applications
• Video surveillance
• Scanning
•Industrial
•Stereo vision
• 720p60 video applications
General Description
The ON Semiconductor AR0141CS is a 1/4-inch CMOS
digital image sensor with an active-pixel array of
1280Hx800V. It captures images in linear mode, with a
rolling-shutter readout. It includes sophisticated cam-
era functions such as in-pixel binning, windowing and
both video and single frame modes. It is designed for
low light scene performance. It is programmable
through a simple two-wire serial interface. The
AR0141CS produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous
video and single frames makes it the perfect choice for
a wide range of applications, including surveillance
and HD video.
Table 1: Key Parameters
Parameter Typical Value
Optical format 1/4-inch
Active pixels 1280(H) x 800(V) (entire
array)
Pixel size 3.0 m x 3.0 m
Color filter array RGB Bayer, Monochrome,
RGB-IR
Shutter type Electronic rolling shutter
and GRR
Input clock range 6 – 50 MHz
Output clock maximum 148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output Serial HiSPi, 12-bit
Parallel 10-, 12-bit
Frame rate 720p 60 fps
Responsivity 4.0 V/lux-sec
SNRMAX 41 dB
Max Dynamic range Up to 79 dB
Supply
voltage
I/O 1.8 or 2.8 V
Digital 1.8 V
Analog 2.8 V
HiSPi 0.3 V - 0.6 V, 1.7 V - 1.9 V
Power consumption (typical) 326 mW (Linear Mode
1280x720 60 fps)
Operating temperature (ambient) -TA–30°C to + 70° C
Package options 9x9mm 63-ball iBGA
AR0141CS/D Rev. 6, 4/16 EN 2©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Ordering Information
Ordering Information
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full
description of the naming convention used for image sensors. For reference documenta-
tion, including information on evaluation kits, please visit our web site at
www.onsemi.com.
Table 2: Available Part Numbers
Part Number Product Description Orderable Product Attribute Description
AR0141CS2C00SUEA0-DP Color IBGA Dry Pack with Protective Film
AR0141CS2C00SUEA0-DR Color IBGA Dry Pack without Protective Film
AR0141CS2C00SUEAD3-GEVK Color IBGA Demo3 Kit
AR0141CS2C00SUEAH-GEVB Color IBGA Headboard
AR0141CS2M00SUEA0 - TPBR Mono iBGA Tape and Reel with Protective Film
AR0141CS2M00SUEA0 - DPBR Mono iBGA Dry Pack with Protective Film
AR0141CS2M00SUEAD3-GEVK Mono IBGA Demo3 Kit
AR0141CS2M00SUEAH-GEVB Mono IBGA Headboard
AR0141IRSH00SUEA0-DR RGB-IR, iBGA, Production Dry Pack without Protective Film
AR0141IRSH00SUEA0D3-GEVK RGB-IR, Demo3 Kit
AR0141IRSH00SUEA0H3-GEVB RGB-IR, Head Board
AR0141CSSM21SUEA0-TPBR Mono, iBGA, 21 deg shift Engineering Sample
AR0141CS/D Rev. 6, 4/16 EN 3©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
.Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Differentiation from AR0141CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pixel Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pixel Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Data Pedestals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sensor PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sensor Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Sensor Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Frame Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Changing Sensor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
AR0141CS/D Rev. 6, 4/16 EN 4©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
General Description
General Description
The ON Semiconductor AR0141CS can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode output is a 720p-
resolution image at 60 frames per second (fps). In linear mode, it outputs 12-bit raw
data, using either the parallel or serial (HiSPi) output ports. The device may be operated
in video (master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a
synchronized pixel clock in parallel mode.
The AR0141CS includes additional features to allow application-specific tuning:
windowing and offset, auto black level correction, and on-board temperature sensor.
Optional register information and histogram statistic information can be embedded in
the first and last 2 lines of the image frame.
.Functional Overview
The AR0141CS is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master input clock running between
6 and 50 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock
rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1: Block Diagram
User interaction with the sensor is through the two-wire serial bus, which communi-
cates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 1.1 Mp Active- Pixel Sensor array. The timing and control circuitry sequences
through the rows of the array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the pixels in the row integrate
Digital gain and
pedestal
12
12 bits
Parallel HiSPi
12 or 10 bits
Row noise correction
Black level correction
Pixel defect correction
Test pattern generator
12
ADC data
Adaptive CD filter
AR0141CS/D Rev. 6, 4/16 EN 5©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
incident light. The exposure is controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the columns is sequenced through an
analog signal chain (providing offset correction and gain), and then through an analog-
to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in
the array. The ADC output passes through a digital processing signal chain (which
provides further data path corrections and applies digital gain).
Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the AR0141CS demo headboard schematics for circuit recom-
mendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
VDD_IO VDD_SLVS VDD_PLLVDD VAA
VDD VAA VAA_PIX
Master clock
(6–50 MHz)
SDATA
SCLK
RESET_BAR
TEST
EXTCLK
DGND AGND
Digital
ground
Analog
ground
Digital
Core
power1
HiSPi
power1
Analog
power1
To
controller
From
controller
VDD_IO VDD_PLL
PLL
power1
Digital
I/O
power1
1.5kΩ
2
1.5kΩ
2
Analog
power1
VAA_PIX
SLVSC_N
SLVSC_P
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
VDD_SLVS
TRIGGER
OE_BAR
SADDR
SHUTTER
FLASH
AR0141CS/D Rev. 6, 4/16 EN 6©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Figure 3: Typical Configuration: Parallel Pixel Data Interface
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-
face is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the AR0141CS demo headboard schematics for circuit recom-
mendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6-50 MHz.
V
DD
Master clock
(6-50 MHz)
S
DATA
S
CLK
TEST
FRAME_VALID
D
OUT
[11:0]EXTCLK
D
GND
Digital
ground
Analog
ground
Digital
core
power
1
To
controller
From
Controller
LINE_VALID
PIXCLK
RESET_BAR
V
DD
_IO
Digital
I/O
power
1
1.5kΩ
2
1.5kΩ
2,
V
AA
V
AA
_PIX
Analog
power
1
VDD_PLL
PLL
power
1
Analog
power
1
V
AA
_PIX
V
DD
_IO VDD_PLLV
DD
V
AA
TRIGGER
OE_BAR
AGND
SADDR
SHUTTER
FLASH
AR0141CS/D Rev. 6, 4/16 EN 7©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Figure 4: 9 x 9 mm 63-Ball IBGA Package
Table 3: Ball Descriptions, 9 x 9 mm, 63-ball iBGA
Name iBGA Pin Type Description
SLVS0_N A2 Output HiSPi serial data, lane 0, differential N.
SLVS0_P A3 Output HiSPi serial data, lane 0, differential P.
SLVS1_N A4 Output HiSPi serial data, lane 1, differential N.
SLVS1_P A5 Output HiSPi serial data, lane 1, differential P.
STANDBY A8 Input STANDBY (active high)
VDD_PLL B1 Power PLL power.
SLVSC_N B2 Output HiSPi serial DDR clock differential N.
SLVSC_P B3 Output HiSPi serial DDR clock differential P.
SLVS2_N B4 Output HiSPi serial data, lane 2, differential N.
SLVS2_P B5 Output HiSPi serial data, lane 2, differential P.
VAA B7, B8 Power Analog power.
EXTCLK C1 Input External input clock.
VDD_SLVS C2 Power 0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM
(R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V.
SLVS3_N C3 Output HiSPi serial data, lane 3, differential N.
SLVS3_P C4 Output HiSPi serial data, lane 3, differential P.
A
B
C
D
E
F
G
H
Top View
(Ball Down)
SLVS0_N SLVS0_P SLVS1_N SLVS1_P VDD STANDBY
VDD_PLL SLVS_CN SLVSC_P SLVS2_N SLVS2_P VDD VAA VAA
EXTCLK VDD_
SLVS SLVS3_N SLVS3_P DGND VDD AGND
SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX
LINE_
VALID
FRAME_
VALID PIXCLK FLASH DGND VDD_IO NC
DOUT8DOUT9DOUT10 DOUT11 DGND VDD_IO TEST
DOUT4DOUT5DOUT6DOUT7DGND VDD_IO TRIGGER OE_BAR
DOUT0DOUT1DOUT2DOUT3DGND VDD_IO VDD_IO RESET_
BAR
12 3 567 84
VDD
AGND
NC
Reserved
AR0141CS/D Rev. 6, 4/16 EN 8©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
DGND C5, D4, D5, E5, F5, G5,
H5
Power Digital ground.
VDD A6, A7, B6, C6, D6 Power Digital power.
AGND C7, C8 Power Analog ground.
SADDR D1 Input Two-Wire Serial address select. 0: 0x20. 1: 0x30
SCLK D2 Input Two-Wire Serial clock input.
SDATA D3 I/O Two-Wire Serial data I/O.
VAA_PIX D7, D8 Power Pixel power.
LINE_VALID E1 Output Asserted when DOUT line data is valid.
FRAME_VALID E2 Output Asserted when DOUT frame data is valid.
PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock.
VDD_IO E6, F6, G6, H6, H7 Power I/O supply power.
DOUT8 F1 Output Parallel pixel data output.
DOUT9 F2 Output Parallel pixel data output.
DOUT10 F3 Output Parallel pixel data output.
DOUT11 F4 Output Parallel pixel data output (MSB)
TEST F7 Input. Manufacturing test enable pin (connect to DGND).
DOUT4 G1 Output Parallel pixel data output.
DOUT5 G2 Output Parallel pixel data output.
DOUT6 G3 Output Parallel pixel data output.
DOUT7 G4 Output Parallel pixel data output.
TRIGGER G7 Input Exposure synchronization input.
OE_BAR G8 Input Output enable (active LOW).
DOUT0 H1 Output Parallel pixel data output (LSB)
DOUT1 H2 Output Parallel pixel data output.
DOUT2 H3 Output Parallel pixel data output.
DOUT3 H4 Output Parallel pixel data output.
RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory
default.
NC E8
FLASH E4 Output Flash control output.
NC E7
Reserved F8
Table 3: Ball Descriptions, 9 x 9 mm, 63-ball iBGA (continued)
Name iBGA Pin Type Description
AR0141CS/D Rev. 6, 4/16 EN 9©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The AR0141CS pixel array consists of 1280 columns by 800 rows of optically active
pixels.While the sensor's format is 1344 x 848, additional active columns and active rows
are included for use when horizontal or vertical mirrored readout is enabled, to allow
readout to start on the same pixel. The pixel adjustment is always performed for mono-
chrome or color versions. The active area is surrounded with optically transparent
dummy pixels to improve image uniformity within the active area. Not all dummy pixels
or barrier pixels can be read out.
Figure 5: Pixel Array Description
NOT TO SCALE
All dimensions in PIXELS
unless otherwise stated
1348 ( 2+ 1344 + 2)
Active pixels
total = 1348
total = 86 8
86 8 (8+ 2+ 4+ 848 +6 )
Transport pixels
8
AR0141CS/D Rev. 6, 4/16 EN 10 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Differentiation from AR0141CS
Figure 6: RGB Pixel Color Pattern Detail (Top Right Corner) - AR0141CS
Figure 7: RGB-IR Pixel Color Pattern Detail (Top Right Corner) - ARO141IR
Differentiation from AR0141CS
The AR0141IR can be electrically differentiated from the AR0141CS by reading bits 11:9
in R0x31FA. The AR0141IR contains a unique value of 4 in these bits. It is necessary to set
R0x301A[5]=1 prior to reading R0x31FA[11:9].
Active Pixel (0,0)
Array Pixel (0, 0)
Row
Reado
ut Direction
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
Column Readout Direction
Active Pixel (0,0)
Array Pixel (0, 0)
Row
Reado
ut Direction
IR
B
IR
B
IR
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
IR
B
IR
B
IR
B
IR
B
IR
B
IR
B
IR
B
IR
B
IR
B
Column Readout Direction
AR0141CS/D Rev. 6, 4/16 EN 11 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Differentiation from AR0141CS
Default Readout Order
By convention, the sensor core pixel array is shown with pixel (0,0) in the top right
corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first
pixel data read out of the sensor in default condition is that of pixel (0, 0).
When the sensor is imaging, the active surface of the sensor faces the scene as shown in
Figure 8. When the image is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 8.
Figure 8: Imaging a Scene
Lens
Pixel (0,0)
Row
Readout
Order
Column Readout Order
Scene
Sensor (rear view)
AR0141CS/D Rev. 6, 4/16 EN 12 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
Pixel Output Interfaces
Parallel Interface
The parallel pixel data interface uses these output-only signals:
•FRAME_VALID
•LINE_VALID
•PIXCLK
•D
OUT[11:0]
The parallel pixel data interface is disabled by default at power up and after reset. It can
be enabled by programming R0x301A. Table 5 shows the recommended settings.
When the parallel pixel data interface is in use, the serial data output signals can be left
unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while
in parallel output mode.
Output Enable Control
When the parallel pixel data interface is enabled, its signals can be switched asynchro-
nously between the driven and High-Z under pin or register control, as shown in Table 4.
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of the pixel data interface. The
supported combinations are shown in Table 5.
Table 4: Output Enable Control
OE_BAR Pin Drive Pins R0x301A[6] Description
Disabled 0 Interface High-Z
Disabled 1 Interface driven
1 0 Interface High-Z
X 1 Interface driven
0 X Interface driven
Table 5: Configuration of the Pixel Data Interface
Serializer Disable
R0x301 A[12] Parallel Enable
R0x301 A[7] Description
0 0 Power up default.
Serial pixel data interface and its clocks are enabled. Transitions to soft standby are
synchronized to the end of frames on the serial pixel data interface.
1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its
clocks disabled to save power. Transitions to soft standby are synchronized to the end of
frames in the parallel pixel data interface.
AR0141CS/D Rev. 6, 4/16 EN 13 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
High Speed Serial Pixel Data Interface
The High Speed Serial Pixel (HiSPi) interface uses four data lanes and one clock as
output.
•SLVSC_P
•SLVSC_N
•SLVS0_P
•SLVS0_N
•SLVS1_P
•SLVS1_N
•SLVS2_P
•SLVS2_N
•SLVS3_P
•SLVS3_N
The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized
SP. The streaming protocols conform to a standard video application where each line of
active or intra-frame blanking provided by the sensor is transmitted at the same length.
The Packetized SP protocol will transmit only the active data ignoring line-to-line and
frame-to-frame blanking data.
These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface
Protocol Specification V1.50.00.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. Figure 9 shows the
configuration between the HiSPi transmitter and the receiver.
Figure 9: HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
Tx
PHY0
Rx
PHY0
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
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AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
HiSPi Physical Layer
The HiSPi physical layer is partitioned into blocks of four data lanes and an associated
clock lane. Any reference to the PHY in the remainder of this document is referring to
this minimum building block.
The PHY will serialize 12-bit data words and transmit each bit of data centered on a
rising edge of the clock, the second on the falling edge of the clock. Figure 10 shows bit
transmission. In this example, the word is transmitted in order of MSB to LSB. The
receiver latches data at the rising and falling edge of the clock.
Figure 10: Timing Diagram
DLL Timing Adjustment
The specification includes a DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each data lane, which acts as a
control master for the output delay buffers. Once the DLL has gained phase lock, each
lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user
to increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design.
Delay compensation may be set for clock and/or data lines in the hispi_timing register
R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-
tion.
Figure 11: Block Diagram of DLL Timing Adjustment
c
p
dn
….
….
MSB LSB
TxPost
dp
cn
1 UI
TxPre
AR0141CS/D Rev. 6, 4/16 EN 15 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
Figure 12: Delaying the Clock with Respect to Data
Figure 13: Delaying Data with Respect to the Clock
HiSPi Protocol Layer
The HiSPi protocol is described in the HiSPi Protocol Specification document.
dataN (DATAN_DEL = 000)
cp (CLOCK_DEL = 000)
cp (CLOCK_DEL = 001)
cp (CLOCK_DEL = 010)
cp (CLOCK_DEL = 011)
cp (CLOCK_DEL = 100)
cp (CLOCK_DEL = 101)
cp (CLOCK_DEL = 110)
cp ( CLOCK_DEL =111)
increasing CLOCK_DEL[2:0] increases clock delay
1 UI
1 UI
tDLLSTEP
cp (CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
dataN(DATAN_DEL = 001)
dataN(DATAN_DEL = 010)
dataN(DATAN_DEL = 011)
dataN(DATAN_DEL = 100)
dataN(DATAN_DEL = 101)
dataN(DATAN_DEL = 110)
dataN(DATAN_DEL = 111)
increasing DATAN_DEL[2:0] increases data delay
AR0141CS/D Rev. 6, 4/16 EN 16 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Sensitivity
Serial Configuration
The serial format should be configured using R0x31AC. Refer to the AR0141CS Register
Reference document for more detail regarding this register.
The serial_format register (R0x31AE) controls which serial format is in use when the
serial interface is enabled (reset_register[12] = 0). The following serial formats are
supported:
• 0x0304 - Sensor supports quad-lane HiSPi operation
• 0x0302 - Sensor supports dual-lane HiSPi operation
Pixel Sensitivity
Figure 14: Integration Control in ERS Readout
A pixel's integration time is defined by the number of clock periods between a row's
reset and read operation. Both the read followed by the reset operations occur within a
row period (TROW) where the read and reset may be applied to different rows. The read
and reset operations will be applied to the rows of the pixel array in a consecutive order.
The coarse integration time is defined by the number of row periods (TROW) between a
row's reset and the row read. The row period is defined as the time between row read
operations (see Sensor Frame Rate).
TCOARSE = TROW * coarse_integration_time (EQ 1)
Figure 15: Example of 8.33ms Integration in 16.6ms Frame
Row Integration
(T
INTEGRATION
)
Row Reset
(Start of Integration) Row Readout
Vertical Blanking
Read
Reset
Vertical Blanking
Horizontal Blanking
TFRAME = frame_length_lines x TROW
16.6 ms = 750 rows x 22.22 μs/row
TCOARSE = coarse_integration_time x TROW
8.33 ms =563 rows x 22.22 μs/row
Time
AR0141CS/D Rev. 6, 4/16 EN 17 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Sensitivity
Figure 16: Row Read and Row Reset Showing Fine Integration
TFINE = fine_integration_time/clk_pix (EQ 2)
The maximum allowed value for fine_integration_time is
line_length_pck - fine_integration_time_max_margin (EQ 3)
Figure 17: Row Integration Time is Greater Than the Frame Readout Time
The minimum frame-time is defined by the number of row periods per frame and the
row period. The sensor frame-time will increase if the coarse_integration_time is set to a
value equal to or greater than the frame_length_lines.
Read Row N Reset Row K
TFINE = fine_integration _time x (1/CLK_PIX)
Start of Read Row N
and Reset Row K
Start of Read Row N + 1
and Reset Row K + 1
TROW = line_length _pck x (1/CLK_PIX)
Image
Vertical Blanking
Vertical Blanking
Shutter
Pointer
Read
Pointer
Time
Extended Vertical Blanking
Image
4.1 m s
TFRAME = frame_length_lines x TROW
16.6ms = 750 rows x 22.22 μs/row
TCOARSE=coarse_integration_time x TROW
20.7ms = 930 rows x 22.22 μs/row
Horizontal B lank ing Horizontal B lank ing
AR0141CS/D Rev. 6, 4/16 EN 18 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Gain Stages
Gain Stages
The sensor analog gain stage will apply the same analog gain to each color channel.
Digital gain can be configured to separate levels for each color channel.
The level of analog gain applied is controlled by the coarse_gain and fine_gain at
R0x3060 analog gain register. The analog readout circuitry can be configured differently
for each analog gain level. Total analog gain is (2coarse_gain) x(1+fine_gain/16), where
coarse_gain = R0x3060[6:4], fine_gain = R0x3060[3:0]. ON Semiconductor recommends
limiting maximum analog gain up to 12x gain for optimal image quality.
Each digital gain can be configured from a gain of 0 to 15.992 using R0x3056, R0x3058,
R0x305A, R0x305C, and R0x305E digital gain registers. The digital gain supports 128 gain
steps per 6dB of gain. The format of each digital gain register is “xxxx.yyyyyyy” where
“xxxx” refers an integer gain of 1 to 15 and “yyyyyyy” is a fractional gain ranging from 0/
128 to 127/128.
The sensor includes a digital dithering feature to reduce quantization noise resulting
from using digital gain. It can be implemented by setting R0x30BA[5] to 1. The default
value is 0.
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AR0141CS: 1/4-Inch Digital Image Sensor
Data Pedestals
Data Pedestals
The data pedestal is a constant offset that is added to pixel values at the end of the data-
path. The default offset is 168 and is a 12-bit offset. This offset matches the maximum
range used by the corrections in the digital readout path. The purpose of the data
pedestal is to convert negative values generated by the digital datapath into positive
output data.
Reset
The AR0141CS may be reset by the RESET_BAR pin (active LOW) or the reset register.
Hard Reset of Logic
The host system can reset the image sensor by bringing the RESET_BAR pin to a LOW
state. Alternatively, the RESET_BAR pin can be connected to an external RC circuit for
simplicity. Registers written via the two-wire interface will not be preserved following a
hard reset.
Soft Reset of Logic
Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the
digital logic of the sensor. Furthermore, by asserting the soft reset, the sensor aborts the
current frame it is processing and starts a new frame. This bit is a self-resetting bit and
also returns to “0” during two-wire serial interface reads.
Clocks
The AR0141CS requires one clock input (EXTCLK).
Sensor PLL
VCO
Figure 18: PLL Dividers Affecting VCO Frequency
The sensor contains a phase-locked loop (PLL) that is used for timing generation and
control. The required VCO clock frequency is attained through the use of a pre-PLL clock
divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd
integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an
even multiplier value. The multiplier is followed by a set of dividers used to generate the
output clocks required for the sensor array, the pixel analog and digital readout paths,
and the output parallel and serial interfaces.
EXTCLK
(6-50 MHz) pre_pll_clk_div
2 (1-64) pll_multiplier
58 (32-384) F
VCO
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Parallel PLL Configuration
Figure 19: PLL for the Parallel Interface
.
The maximum output of the parallel interface is 74.25 MPixel/s. The sensor will not use
the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface.
Table 6: PLL Parameters for the Parallel Interface
Parameter Symbol Min Max Unit
External Clock EXTCLK 6 50 MHz
VCO Clock FVCO 384 768 MHz
Output Clock CLK_OP 74.25 Mpixel/s
Table 7: Example PLL Configuration for the Parallel Interface
Parameter Value Output
FVCO 445.5 MHz (Max)
vt_sys_clk_div 1
vt_pix_clk_div 6
CLK_OP 74.25 MPixel/s (= 445.5 MHz / 6)
Output pixel rate 74.25 MPixel/s
F
VCO
CLK_OP
(Max 74.25 Mp/s)
vt_pix_clk_div
6 (4-16)
vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10, 12, 14, 16)
pre_pll_clk_div
2 (1-64)
pll_multiplier
58 (32-384)
EXTCLK
(6-50 MHz)
AR0141CS/D Rev. 6, 4/16 EN 21 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Serial PLL Configuration
Figure 20: PLL for the Serial Interface
The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per
lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)
configured. To configure the sensor protocol and number of lanes, refer to “Serial
Configuration” on page 16.
Configure the serial output so that it adheres to the following rules:
• The maximum data-rate per lane (FSERIAL) is 600Mbps/lane (HiSPi).
• Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate
matches the peak pixel rate (2 x CLK_PIX).
– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s)
– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s)
Table 8: PLL Parameters for the Serial Interface
Parameter Symbol Min Max Unit
External Clock EXTCLK 6 50 MHz
VCO Clock FVCO 384 768 MHz
Readout Clock CLK_PIX 74.25 Mpixel/s
Output Serial Data Rate Per Lane FSERIAL 300 (HiSPi) 600 (HiSPi) Mbps
Output Serial Clock Speed Per Lane FSERIAL_CLK 150 (HiSPi) 350(HiSPi) MHz
Table 9: Example PLL Configurations for the Serial Interface
Parameter
4-lane 2-lane
Units12-bit 12-bit
FVCO 445.5 445.5 MHz
vt_sys_clk_div 1 1
vt_pix_clk_div 6 12
op_sys_clk_div 1 1
FSERIAL
FVCO
FVCO
CLK_PIX
CLK_OP
EXTCLK
(6-50 MHz)
FSE RIAL_CLK
1/2
pre_pll_clk_div
2 (1-64)
vt_pix_clk_div
6 (4-16)
vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10, 12, 14, 16)
pll_multiplier
58 (32-384)
op_sys_clk_div
(default = 1)
op_pix_clk_div
12 (8, 10, 12, 14, 16)
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Stream/Standby Control
The sensor supports a soft standby mode. In this mode, the external clock can be option-
ally disabled to further minimize power consumption. If this is done, then the “Power-
Up Sequence” on page 59 must be followed.
Soft Standby
Soft Standby is a low-power state that is controlled through register R0x301A[2].
Depending on the value of R0x301A[4], the sensor will go to Standby after completion of
the current frame readout. When the sensor comes back from Soft Standby, previously
written register settings are still maintained. Soft Standby will not occur if the Trigger pin
is held high.
A specific sequence needs to be followed to enter and exit from Soft Standby.
Entering Soft Standby:
1. Set R0x301A[12] = 1 if serial mode was used
2. Set R0x301A[2] = 0 and drive Trigger pin low.
3. Turn off external clock to further minimize power consumption
Exiting Soft Standby:
1. Enable external clock if it was turned off
2. Set R0x301A[2] = 1 or drive Trigger pin high.
3. Set R0x301A[12] = 0 if serial mode is used
op_pix_clk_div 12 12
FSERIAL 445.5 445.5 MHz
FSERIAL_CLK 222.75 222.75 MHz
CLK_PIX 74.25 37.125 Mpixel/s
CLK_OP 37.125 37.125 Mpixel/s
Pixel Rate 148.5 74.25 Mpixel/s
Table 9: Example PLL Configurations for the Serial Interface
Parameter
4-lane 2-lane
Units12-bit 12-bit
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Readout
Sensor Readout
Image Acquisition Modes
The AR0141CS supports two image acquisition modes:
• Electronic rolling shutter (ERS) mode
This is the normal mode of operation. When the AR0141CS is streaming, it generates
frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the
ERS is in use, timing and control logic within the sensor sequences through the rows
of the array, resetting and then reading each row in turn. In the time interval between
resetting a row and subsequently reading that row, the pixels in the row integrate inci-
dent light. The integration (exposure) time is controlled by varying the time between
row reset and row readout. For each row in a frame, the time between row reset and
row readout is the same, leading to a uniform integration time across the frame. When
the integration time is changed (by using the two-wire serial interface to change regis-
ter settings), the timing and control logic controls the transition from old to new inte-
gration time in such a way that the stream of output frames from the AR0141CS
switches cleanly from the old integration time to the new while only generating
frames with uniform integration. See “Changes to Integration Time” in the AR0141CS
Register Reference.
• Global reset mode
This mode can be used to acquire a single image at the current resolution. In this
mode, the end point of the pixel integration time is controlled by an external electro-
mechanical shutter, and the AR0141CS provides control signals to interface to that
shutter.
The benefit of using an external electromechanical shutter is that it eliminates the visual
artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particu-
larly at low frame rates, because an ERS image effectively integrates each row of the pixel
array at a different point in time.
Window Control
The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_ad-
dr_end, and y_addr_end registers.
Readout Modes
Horizontal Mirror
When the horiz_mirror bit (R0x3040[14]) is set in the read_mode register, the order of
pixel readout within a row is reversed, so that readout starts from x_addr_end + 1 and
ends at x_addr_start. Figure 21 on page 24 shows a sequence of 6 pixels being read out
with R0x3040[14] = 0 and R0x3040[14] = 1.
AR0141CS/D Rev. 6, 4/16 EN 24 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Readout
Figure 21: Effect of Horizontal Mirror on Readout Order
Vertical Flip
When the vert_flip bit (R0x3040[15]) is set in the read_mode register, the order in which
pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends
at y_addr_start. Figure 30 shows a sequence of 6 rows being read out with R0x3040[15] =
0 and R0x3040[15] = 1.
Figure 22: Effect of Vertical Flip on Readout Order
G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0]
LINE_VALID
horiz_mirror = 0
DOUT[11:0]
horiz_mirror = 1
DOUT[11:0]
Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0]
Row6[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row1[11:0]
FRAME_VALID
vert_flip = 0
DOUT[11:0]
vert_flip = 1
DOUT[11:0] Row2[11:0]
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AR0141CS: 1/4-Inch Digital Image Sensor
Subsampling
Subsampling
The AR0141CS supports subsampling. Subsampling allows the sensor to read out a
smaller set of active pixels by either skipping, binning, or summing pixels within the
readout window.
Figure 23: Horizontal Binning in the AR0141CS Sensor
Horizontal binning is achieved either in the pixel readout or the digital readout. The
sensor will sample the combined 2x adjacent pixels within the same color plane.
Figure 24: Vertical Row Binning in the AR0141CS Sensor
Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x
rows within the same color plane.
Pixel skipping can be configured up to 2x in both the x-direction and y-direction. Skip-
ping pixels in the x-direction will not reduce the row time. Skipping pixels in the y-direc-
tion will reduce the number of rows from the sensor effectively reducing the frame time.
Skipping will introduce image artifacts from aliasing.
The sensor increments its x and y address based on the x_odd_inc and y_odd_inc value.
The value indicates the addresses that are skipped after each pair of pixels or rows has
been read.
Table 10: Available Skip and Bin Modes in the AR0141CS Sensor
Subsampling Method Horizontal Vertical
Skipping 2x 2x
Binning 2x 2x
lsb
lsb
lsb
lsb
-
lsb
lsb
e-
e-
e-
e-
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AR0141CS: 1/4-Inch Digital Image Sensor
Subsampling
The sensor will increment x and y addresses in multiples of 2. This indicates that a
GreenR and Red pixel pair will be read together. As well, that the sensor will read a Gr-R
row first followed by a B-Gb row.
(EQ 4)
(EQ 5)
A value of 1 is used for x_odd_inc and y_odd_inc when no pixel subsampling is indicated.
In this case, the sensor is incrementing x and y addresses by 1 + 1 so that it reads consec-
utive pixel and row pairs. To implement a 2x skip in the x direction, the x_odd_inc is set
to 3 so that the x address increment is 1+3, meaning that sensor will skip every other Gr-
R pair.
Note: In skip2 the window size has to be a multiple of 4.
Table 11: Configuration for Horizontal Subsampling
x_odd_inc Restrictions
No subsampling x_odd_inc = 1
skip = (1+1)*0.5 = 1x
The horizontal FOV must be programmed to
meet the following rule:
Skip 2x x_odd_inc = 3
skip = (1+3)*0.5 = 2x
Analog Bin 2x x_odd_inc = 3
skip = (1+3)*0.5 =2x
col_sf_bin_en = 1
Digital Bin 2x x_odd_inc = 3
skip = (1+3)*0.5 =2x
col_bin =1
Table 12: Configuration for Vertical Subsampling
y_odd_inc Restrictions:
No subsampling y_odd_inc = 1
skip = (1+1)*0.5 = 1x
row_bin = 0
The vertical FOV must be programmed to meet
the following rule:
Skip 2x y_odd_inc = 3
skip = (1+3)*0.5 =2x
row_bin = 0
Analog Bin 2x y_odd_inc = 3
skip = (1+3)*0.5 =2x
row_bin = 1
x subsampling factor 1 x_odd_inc+
2
-----------------------------------
=
y subsampling factor 1 y_odd_inc+
2
-----------------------------------
=
x_addr_end x_addr_start–1+
x_odd_inc 1+2
------------------------------------------------------------------------- e v e n n u m b e r=
y_addr_end y_addr_start–1+
y_odd_inc 1+2
------------------------------------------------------------------------- e v e n n u m b e r=
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Frame Rate
Sensor Frame Rate
The time required to read out an image frame (TFRAME) can be derived from the number
of clocks required to output each image and the pixel clock.
The frame-rate is the inverse of the frame period.
fps=1/TFRAME (EQ 6)
The number of clocks can be simplified further into the following parameters:
• The number of clocks required for each sensor row (line_length_pck)
This parameter also determines the sensor row period when referenced to the sensor
readout clock. (TROW = line_length_pck x 1/CLK_PIX)
• The number of row periods per frame (frame_length_lines)
• An extra delay between frames used to achieve a specific output frame period
(extra_delay)
TFRAME=1/(CLK_PIX) ×[frame_length_lines × line_length_pck + extra_delay] (EQ 7)
Figure 25: Frame Period Measured in Clocks
frame_length_lines = active rows + VB
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Row Period (TROW)
line_length_pck will determine the number of clock periods per row and the row period
(TROW) when combined with the sensor readout clock. line_length_pck includes both
the active pixels and the horizontal blanking time per row. The sensor utilizes two
readout paths, as seen in Figure 1 on page 4, allowing the sensor to output two pixels
during each pixel clock.
Row Periods Per Frame
frame_length_lines determines the number of row periods (TROW) per frame. This
includes both the active and blanking rows. The minimum vertical blanking value is
defined by the number of OB rows read per frame, two embedded data rows, and two
blank rows.
(EQ 8)
The sensor is configured to output frame information in two embedded data rows by
setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead output
two blank rows. The data configured in the two embedded rows is defined in two
embedded rows of data at the top of the frame by setting R0x3064[7] and two rows of
embedded statistics at the end of the frame by setting R0x3064[7] for exposure calcula-
tions. See the section on Embedded Data and Statistics.
The locations of the OB rows, embedded rows, and blank rows within the frame readout
are identified in Figure 26: “Slave Mode Active State and Vertical Blanking,” on page 29.
Slave Mode
The slave mode feature of the AR0141CS supports triggering the start of a frame readout
from a VD signal that is supplied from an external device. The slave mode signal allows
for precise control of frame rate and register change updates. The VD signal is an edge
triggered input to the trigger pin and must be at least 3 PIXCLK cycles wide.
Table 13: Minimum Vertical Blanking Configuration
R0x3180[7:4] OB Rows min_vertical_blanking1
0x8 (Default) 8 OB Rows 8 OB + 8 = 16
0x4 4 OB Rows 4 OB + 8 = 12
0x2 2 OB Rows 2 OB + 8 = 10
Minimum frame_length_lines y_addr_end y_addr_start–1+
y_odd_inc 1+2
--------------------------------------------------------------------------- min_vertical_blanking+=
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 26: Slave Mode Active State and Vertical Blanking
If the slave mode is disabled, the new frame will begin after the extra delay period is
finished.
The slave mode will react to the rising edge of the input VD signal if it is in an active state.
When the VD signal is received, the sensor will begin the frame readout and the slave
mode will remain inactive for the period of one frame time plus 16 clock periods
(TFRAME + (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state
and will respond to the VD signal.
Start of frame N
End of frame N
Start of frame N + 1
Time
Frame Valid
OB Rows (2, 4, or 8 rows)
Embedded Data Row (2 rows)
Active Data Rows
Blank Rows or Embedded stats (2 rows)
Extra Vertical Blanking
(frame_length_lines - min_frame_length_lines)
VD Signal
Slave Mode Active State
The period between the
rising edge of the VD signal
and the slave mode ready
state is TFRAME + 16 clocks.
Extra Delay (clocks)
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 27: Slave Mode Example with Equal Integration and Frame Readout Periods
The integration of the last row is started before the end of the programmed integration for the first row.
The row shutter and read operations will stop when the slave mode becomes active and
is waiting for the VD signal. The following should be considered when configuring the
sensor to use the slave mode:
1. The frame period (TFRAME) should be configured to be less than the period of the
input VD signal. The sensor will disregard the input VD signal if it appears before the
frame readout is finished.
2. If the sensor integration time is configured to be less than the frame period, then the
sensor will not have reset all of the sensor rows before it begins waiting for the input
VD signal. This error can be minimized by configuring the frame period to be as close
as possible to the desired frame rate (period between VD signals).
Inactive Active
Row 0
Row N
Inactive Active
Rising
Edge
Rising
Edge
Row Readout
Programmed Integration
Integration due to
Slave Mode Delay
Slave Mode
Trigger
Rising edge of VD
signal triggers the start
of the frame readout.
Row Reset
(start of integration)
Frame
Valid
VD Signal
Rising
Edge
The Slave Mode will become
“Active” after the last row period.
Both the row reset and row read
operations will wait until the rising
edge of the VD signal..
Row reset and read
operations begin
after the rising edge
of the VD signal.
AR0141CS/D Rev. 6, 4/16 EN 31 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 28: Slave Mode Example Where the Integration Period is Half of the Frame Readout Period
The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration
caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of
16.6ms while the integration time is configured to 8.33ms.
When the slave mode becomes active, the sensor will pause both row read and row reset
operations. (Note: The row integration period is defined as the period from row reset to
row read.) The frame-time should therefore be configured so that the slave mode “wait
period” is as short as possible. In the case where the sensor integration time is shorter
than the frame time, the “wait period” will only increase the integration of the rows that
have been reset following the last VD pulse.
The period between slave mode pulses must also be greater than the frame period. If the
rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be
ignored and will wait until the next VD pulse has arrived.
To enter slave mode:
1. While in soft-standby, set R0x30CE[4] = 1 to enter slave mode.
2. Enable the input pins (TRIGGER) by setting R0x301A[8] = 1.
3. Enable streaming by setting R0x301A[2] = 1.
4. Apply sync-pulses to the TRIGGER input.
Inactive Active
Row 0
Row N
Inactive Active
Rising
Edge
Rising
Edge
Row Readout
Programmed Integration
Integration due to
Slave Mode Delay
Slave Mode
Trigger
Row Reset
(start of integration)
Frame
Valid
VD Signal
Rising
Edge
Reset operation is
held during slave
mode “Active” state.
Row reset and read
operations begin after
the rising edge of the
Vd signal.
8.33 ms 8.33 ms
AR0141CS/D Rev. 6, 4/16 EN 32 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Frame Readout
Frame Readout
The sensor readout begins with vertical blanking rows followed by the active rows. The
frame readout period can be defined by the number of row periods within a frame
(frame_length_lines) and the row period (line_length_pck/clk_pix). The sensor will read
the first vertical blanking row at the beginning of the frame period and the last active row
at the end of the row period.
Figure 29: Example of the Sensor Output of a 1280 x 720 Frame at 60 fps
The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor.
The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol.
Figure 29 aligns the frame integration and readout operation to the sensor output. It also
shows the sensor output using the HiSPi Streaming-SP protocol. Different sensor proto-
cols will list different SYNC codes.
Active Rows
Vertical Blanking
Time
1/60s
End of Frame
Readout
End of Frame
Readout
Start of Vertical Blanking
Start of Frame
Start of Active Row
End of Line
Serial SYNC Codes
End of Frame
Row Reset Row ReadRow Reset Row Read
Frame Valid
Line Valid
1/60s
Row Reset Row ReadRow Reset Row Read
1280 x 720 1280 x 720
HB (370 Pixels/Column) HB (370 Pixels/Column)
VB
(30 Rows)
VB
(30 Rows)
AR0141CS/D Rev. 6, 4/16 EN 33 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Frame Readout
Figure 30 illustrates how the sensor active readout time can be minimized while
reducing the frame rate. 750 VB rows were added to the output frame to reduce the
1280 x 720 frame rate from 60 fps to 30 fps without increasing the delay between the
readout of the first and last active row.
Figure 30: Example of the Sensor Output of a 1280 x720 Frame at 30 fps
The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor.
The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol.
Table 14: Serial SYNC Codes Included with Each Protocol Included with the AR0141CS Sensor
Interface/Protocol Start of Vertical
Blanking Row (SOV) Start of Frame
(SOF) Start of Active Line
(SOL) End of Line
(EOL) End of Frame
(EOF)
Parallel Parallel interface uses FRAME VALID (FV) and LINE VALID (LV) outputs to denote start and end of line and
frame.
HiSPi Streaming-S Required Unsupported Required Unsupported Unsupported
HiSPi Streaming-SP Required Required Required Unsupported Unsupported
HiSPi Packetized SP Unsupported Required Required Required Required
Serial SYNC Codes
VB
(780 Rows)
HB (370 Pixels ) HB (370 P ixels )
Frame Valid
Line Valid
1/30s 1/30s
Active Rows
Vertical Blanking
Time End of Frame
Readout
Start of Vertical Blanking
Start of Frame
Start of Active Row
End of Line
End of Frame
Row Reset Row Read
Row Reset Row Read
1280 x 720 1280 x 720
Row Reset Row Read
Row Reset Row Read
End of Frame
Readout
VB
(780 Rows)
AR0141CS/D Rev. 6, 4/16 EN 34 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Changing Sensor Modes
Register Changes
All register writes are delayed by one frame. A register that is written to during the
readout of frame n will not be updated to the new value until the readout of frame n+2.
This includes writes to the sensor gain and integration registers.
Real-Time Context Switching
In the AR0141CS, the user may switch between two full register sets A and B by writing to
a context switch change bit in R0x30B0[13]. When the context switch is configured to
context A the sensor will reference the context A registers. If the context switch is
changed from A to B during the readout of frame n, the sensor will then reference the
context B coarse_integration_time registers in frame n+1 and all other context B registers
at the beginning of reading frame n+2. The sensor will show the same behavior when
changing from context B to context A.
Table 15: List of Configurable Registers for Context A and Context B
Context A Context B
Register Description Address Register Description Address
coarse_integration_time 0x3012 coarse_integration_time_cb 0x3016
line_length_pck 0x300C line_length_pck_cb 0x303E
frame_length_lines 0x300A frame_length_lines_cb 0x30AA
row_bin 0x3040[12] row_bin_cb 0x3040[10]
col_bin 0x3040[13] col_bin_cb 0x3040[11]
fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8]
coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12]
x_addr_start 0x3004 x_addr_start_cb 0x308A
y_addr_start 0x3002 y_addr_start_cb 0x308C
x_addr_end 0x3008 x_addr_end_cb 0x308E
y_addr_end 0x3006 y_addr_end_cb 0x3090
y_odd_inc 0x30A6 y_odd_inc_cb 0x30A8
x_odd_inc 0x30A2 x_odd_inc_cb 0x30AE
green1_gain 0x3056 green1_gain_cb 0x30BC
blue_gain 0x3058 blue_gain_cb 0x30BE
red_gain 0x305A red_gain_cb 0x30C0
green2_gain 0x305C green2_gain_cb 0x30C2
global_gain 0x305E global_gain_cb 0x30C4
AR0141CS/D Rev. 6, 4/16 EN 35 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Figure 31: Example of Changing the Sensor from Context A to Context B
Compression
The AR0141CS can optionally compress 12-bit data to 10-bit using A-law compression.
The compression is applied after the data pedestal has been added to the data. See “Data
Pedestals” on page 19.
The A-law compression is disabled by default and can be enabled by setting R0x31D0
from “0” to “1” and 0x31AC needs to be set to 0x0C0A.
Table 16: A-Law Compression Table for 12-10 bits
Input Range
Input Values Compressed Codeword
11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g
128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g
256 to 511 0 0 0 1 a b c d e f g X 0 1 0 a b c d e f g
512 to 1023 0 0 1 a b c d e f g X X 0 1 1 a b c d e f g
1024 to 2047 0 1 a b c d e f g h X X 1 0 a b c d e f g h
2048 to 4095 1 a b c d e f g h X X X 1 1 a b c d e f g h
Active Rows
Vertical Blanking
Time
1/60s 1/60s
Start of Vertical Blanking
Start of Frame
Start of Active Row
End of Frame
Serial SYNC Codes
c
End of Frame
Readout
End of Frame
Readout
End of Frame
Readout
1/30s
1280 x720
Frame N+1
1280 x 720
Frame N
VB
(30 R ows)
HB (370 Pixels/C olum n)
VB
(30 R ows)
HB (370 Pixels/Colum n)
1280 x 720
Frame N+2
VB
(780 Rows)
HB (370 Pixels/Colum n)
Write context A to B
during readout of Frame N
Integration time of context
B mode implemented
during readout of frame
N+1
Context B mode is
implemented in frame N+2
AR0141CS/D Rev. 6, 4/16 EN 36 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Temperature Sensor
The AR0141CS sensor has a built-in temperature sensor, accessible through registers,
that is capable of measuring die junction temperature.
The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1.
After this, the temperature sensor output value can be read from R0x30B2[9:0].
The value read out from the temperature sensor register is an ADC output value that
needs to be converted downstream to a final temperature value in degrees Celsius. Since
the PTAT device characteristic response is quite linear in the temperature range of oper-
ation required, a simple linear function in the format of the equation below can be used
to convert the ADC output value to the final temperature in degrees Celsius.
(EQ 9)
For this conversion, a minimum of two known points are needed to construct the line
formula by identifying the slope and y-intercept “T0”. These calibration values can be
read from registers R0x30C6 and R0x30C8, which correspond to value read at 105°C and
55°C respectively. Once read, the slope and y-intercept values can be calculated and
used in Equation 9.
For more information on the temperature sensor registers, refer to the AR0141CS
Register Reference.
Temperature slope R0x30B2 9:0T+
0
=
AR0141CS/D Rev. 6, 4/16 EN 37 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Embedded Data and Statistics
The AR0141CS has the capability to output image data and statistics embedded within
the frame timing. There are two types of information embedded within the frame
readout.
• Embedded Data:
If enabled, these are displayed on the two rows immediately before the first active
pixel row is displayed.
•Embedded Statistics:
If enabled, these are displayed on the two rows immediately after the last active pixel
row is displayed.
Figure 32: Frame Format with Embedded Data Lines Enabled
Embedded Data
The embedded data contains the configuration of the image being displayed. This
includes all register settings used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1: Registers R0x3000 to R0x312F
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
Note: All undefined registers will have a value of 0.
In parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register
data will be transferred over 2 pixels where the register data will be broken up into 8 MSB
and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel
word. For example, if a register value of 0x1234 is to be transmitted, it will be transmitted
over two, 12-bit pixels as follows: 0x120, 0x340.
Embedded Statistics
The embedded statistics contain frame identifiers and histogram information of the
image in the frame. This can be used by downstream auto-exposure algorithm blocks to
make decisions about exposure adjustment.
Image
Register Data
Status & Statistics Data
HBlank
VBlank
AR0141CS/D Rev. 6, 4/16 EN 38 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for
digital code values 0 to 28, 120 evenly spaced bins for values 28 to 212, 60 evenly spaced
bins for values 212 to 216. It is recommended that auto exposure algorithms be developed
using the histogram statistics on line 1.
The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signi-
fies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel.
Figure 33 summarizes how the embedded statistics transmission looks like. It should be
noted that data, as shown in Figure 33, is aligned to the MSB of each word:
Figure 33: Format of Embedded Statistics Output within a Frame
The statistics embedded in these rows are as follows:
Line 1:
• 0x0B0 - identifier
• Register 0x303A - frame_count
• Register 0x31D2 - frame ID
• Histogram data - histogram bins 0-243
Line 2:
• 0x0B0 (TAG)
•Mean
• Histogram Begin
•Histogram End
•Low End Histogram Mean
• Percentage of Pixels Below Low End Mean
• Normal Absolute Deviation
{2'b00,frame
_count MSB}
{2'b00,frame
_count LSB}
{2'b00,frame
_ID MSB}
{2'b00,frame
_ID LSB}
histogram
bin0 [19:10]
histogram
bin0 [9:0]
histogram
bin1 [19:0]
histogram
bin1 [9:0]
# words =
10'h1EC
data_format_
code = 8'h0B
histogram
bin243 [19:0]
histogram
bin243 [9:0]
# words =
10'h00C
data_format_
code = 8'h0B
mean
[19:10]
mean
[9:0]
histBegin
[19:10]
histBegin
[9:0]
histEnd
[19:10]
histEnd
[9:0]
lowEndMean
[19:10]
lowEndMean
[9:0]
perc_lowEnd
[19:10]
perc_lowEnd
[9:0]
norm_abs_
dev [19:10]
norm_abs_
dev [9:0]
8'h07 8'h07
8'h07
stats line 1
stats line 2
AR0141CS/D Rev. 6, 4/16 EN 39 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Test Patterns
The AR0141CS has the capability of injecting a number of test patterns into the top of
the datapath to debug the digital logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns
are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can
be enabled at a given point in time by setting the Test_Pattern_Mode register according
to Table 17. When test patterns are enabled the active area will receive the value speci-
fied by the selected test pattern and the dark pixels will receive the value in Test_Pat-
tern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for
blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. The noise pedestal offset at
register 0x30FE impacts on the test pattern output, so the noise_pedestal needs to be set
as 0x0000 for normal test pattern output.
Solid Color
When the color field mode is selected, the value for each pixel is determined by its color.
Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value
in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue.
Vertical Color Bars
When the vertical color bars mode is selected, a typical color bar pattern will be sent
through the digital pipeline.
Walking 1s
When the walking 1s mode is selected, a walking 1s pattern will be sent through the
digital pipeline. The first value in each row is 1.
Table 17: Test Pattern Modes
Test_Pattern_Mode Test Pattern Output
0 No test pattern (normal operation)
1 Solid color test pattern
2 100% Vertical Color Bars test pattern
3 Fade-to-Gray Vertical Color Bars test pattern
256 Walking 1s test pattern (12-bit)
AR0141CS/D Rev. 6, 4/16 EN 40 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the AR0141CS.The interface protocol uses a master/slave model in which a
master controls one or more slave devices. The sensor acts as a slave device. The master
generates a clock (SCLK) that is an input to the sensor and is used to synchronize trans-
fers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or
master device can drive SDATA LOW—the interface protocol determines which device is
allowed to drive SDATA at any given time.
The protocols described in the two-wire serial interface specification allow the slave
device to drive SCLKLOW; the AR0141CS uses SCLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
AR0141CS/D Rev. 6, 4/16 EN 41 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the AR0141CS are 0x20 (write address) and 0x21 (read
address) in accordance with the specification. Alternate slave addresses of0x30 (write
address) and0x31 (read address) can be selected by enabling and asserting the SADDR
input.
An alternate slave address can also be programmed through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-
cates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowl-
edge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
the WRITE should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a WRITE request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, 8 bits at a time. The master generates an acknowledge bit
after each 8-bit transfer. The slave’s internal register address is automatically incre-
mented after every 8 bits are transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
AR0141CS/D Rev. 6, 4/16 EN 42 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Single READ from Random Location
This sequence (Figure 34) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit read slave address/data direction byte and clocks out
one byte of register data. The master terminates the READ by generating a no-acknowl-
edge bit followed by a stop condition. Figure 34 shows how the internal register address
maintained by the AR0141CS is loaded and incremented as the sequence proceeds.
Figure 34: Single READ from Random Location
Single READ from Current Location
This sequence (Figure 35) performs a read using the current value of the AR0141CS
internal register address. The master terminates the READ by generating a no-acknowl-
edge bit followed by a stop condition. The figure shows two independent READ
sequences.
Figure 35: Single READ from Current Location
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
slave to master
master to slave
Slave Address 0
S A Reg Address[15:8] A Reg Address[7:0] Slave Address AA 1Sr Read Data P
Previous Reg Address, N Reg Address, M M+1
A
Slave Address 1S A Read Data Slave Address A1SP Read Data P
Previous Reg Address, N Reg Address, N+1 N+2
AA
AR0141CS/D Rev. 6, 4/16 EN 43 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start from Random Location
This sequence (Figure 36) starts in the same way as the single READ from random loca-
tion (Figure 34). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 36: Sequential READ, Start from Random Location
Sequential READ, Start from Current Location
This sequence (Figure 37) starts in the same way as the single READ from current loca-
tion (Figure 35). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 37: Sequential READ, Start from Current Location
Single WRITE to Random Location
This sequence (Figure 38) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 38: Single WRITE to Random Location
Slave Address 0
S Sr
AReg Address[15:8]
Read Data Read Data
AReg Address[7:0] ARead DataSlave Address
Previous Reg Address, N Reg Address, M
M+1 M+2
M+1
M+3
A1
Read Data Read Data
M+L-2 M+L-1 M+L
AP
A
AAA
Read Data Read Data
Previous Reg Address, N N+1 N+2 N+L-1 N+L
Read DataSlave Address A1 Read Data A PS A A A
Slave Address 0
SAReg Address[15:8] AReg Address[7:0] AP
Previous Reg Address, N Reg Address, M M+
1
A
A
Write Data
AR0141CS/D Rev. 6, 4/16 EN 44 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 39) starts in the same way as the single WRITE to random location
(Figure 38). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 39: Sequential WRITE, Start at Random Location
Slave Address 0
SAReg Address[15:8]
A
AReg Address[7:0] A
Previous Reg Address, N Reg Address, M
M+1 M+2
M+1
M+3
A
AA
M+L-2 M+L-1 M+L
A
AP
Write Data
Write Data Write Data Write DataWrite Data
AR0141CS/D Rev. 6, 4/16 EN 45 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Spectral Characteristics
Figure 40 specifies the quantum efficiency of the RGB Bayer sensor.
Figure 40: Quantum Efficiency - Color Sensor
AR0141CS/D Rev. 6, 4/16 EN 46 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 41 specifies the quantum efficiency of the monochrome sensor.
Figure 41: Quantum Efficiency - Monochrome Sensor
AR0141CS/D Rev. 6, 4/16 EN 47 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 42: RGB-NIR Quantum Efficiency
0
10
20
30
40
50
60
70
350 450 550 650 750 850 950 1050 1150
Quantum Efficiency (%)
Wavelength (nm)
Blue
Green
NIR
Red
AR0141CS/D Rev. 6, 4/16 EN 48 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 43: Chief Ray Angle - 21deg
Image Height CRA
(%) (mm) (deg)
00 0
5 0.113 1.01
10 0.226 2.03
15 0.340 3.07
20 0.453 4.11
25 0.566 5.17
30 0.679 6.23
35 0.792 7.30
40 0.906 8.38
45 1.019 9.46
50 1.132 10.54
55 1.245 11.63
60 1.358 12.73
65 1.472 13.82
70 1.585 14.92
75 1.698 16.01
80 1.811 17.10
85 1.925 18.19
90 2.038 19.28
95 2.151 20.36
100 2.264 21.43
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
0 102030405060708090100
110
CRA (deg)
Image Height (%)
AR0141 Mono CRA Characteristic
AR0141CS/D Rev. 6, 4/16 EN 49 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Electrical Specifications
Unless otherwise stated, the following specifications apply under the following condi-
tions:
VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;
VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +85°C; output load = 10pF;
frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 44 and Table 18.
Figure 44: Two-Wire Serial Bus Timing Parameters
Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
Table 18: Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Parameter Symbol
Standard Mode Fast Mode
UnitMin Max Min Max
SCLK Clock Frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition
After this period, the first clock pulse is
generated
tHD;STA 4.0 - 0.6 - s
LOW period of the SCLK clock tLOW 4.7 - 1.3 - s
HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - s
Set-up time for a repeated START
condition
tSU;STA 4.7 - 0.6 - S
Data hold time tHD;DAT 043.455060.95s
Data set-up time tSU;DAT 250 - 1006-ns
Rise time of both SDATA and SCLK signals tr- 1000 20 + 0.1Cb7300 ns
Fall time of both SDATA and SCLK signals tf- 300 20 + 0.1Cb7300 ns
Set-up time for STOP condition tSU;STO 4.0 - 0.6 - s
Bus free time between a STOP and START
condition
tBUF 4.7 - 1.3 - s
Capacitive load for each bus line Cb- 400 - 400 pF
SSr
tSU;STO
tSU;STA
tHD;STA tHIGH
tLOW tSU;DAT
tHD;DAT
tf
S
DATA
S
CLK
PS
tBUF
tr
tf
trtHD;STA
AR0141CS/D Rev. 6, 4/16 EN 50 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0141CS launches pixel data, FV, and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of
PIXCLK.
See Figure 45 for I/O timing diagram.
Figure 45: I/O Timing Diagram
Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF
SDATA max load capacitance CLOAD_SD -30-30pF
SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 k
Table 18: Two-Wire Serial Bus Characteristics (continued)
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Parameter Symbol
Standard Mode Fast Mode
UnitMin Max Min Max
Data[11:0]
LINE_VALID/
PIXCLK
EXTCLK
tR
tEXTCLK
tF
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
tPLH
tPFH
tPFL
tPLL
tPD
Pxl_0 Pxl _1 Pxl _2 Pxl_n
90%
10%
tRP tFP
90%
10%
FRAME_VALID
AR0141CS/D Rev. 6, 4/16 EN 51 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: Slew rate setting = 2 for PIXCLK
Slew rate setting = 2 for parallel ports
Table 19: I/O Timing Characteristics (2.8V VDD_IO)
Conditions: fPIXCLK=37.125 MHz (720P30fps; VDD_IO = 2.8V
Symbol Definition Condition Min Typ Max Unit
fEXTCLK1 Input clock frequency PLL enabled 6 – 50 MHz
tEXTCLK1 Input clock period PLL enabled 20 – 166 ns
tRInput clock rise time – 3 – ns
tFInput clock fall time – 3 – ns
tRR PIXCLK rise time PCLK slew rate setting= 2 2.0 3.5 6.4 ns
tFP PIXCLK fall time PCLK slew rate setting= 2 1.9 3.3 6.2 ns
Clock duty cycle 45 50 55 %
tJITTER2 Input clock jitter at 27 MHz – – 600 ps
fPIXCLK PIXCLK frequency default PLL configuration 6 37.125 74.25 MHz
tPD PIXCLK to Data[11:0] PCLK slew rate setting=2
parallel slew rate setting= 4
-2.0 – 5.9 ns
tPFH PIXCLK to FV high PCLK slew rate setting=2
parallel slew rate setting=2
-0.9 – 4.4 ns
tPLH PIXCLK to LV high PCLK slew rate setting=2
parallel slew rate setting=2
-0.8 – 4.6 ns
tPFL PIXCLK to FV low PCLK slew rate setting=2
parallel slew rate setting=2
-1.5 – 3.1 ns
tPLL PIXCLK to FV low PCLK slew rate setting=2
parallel slew rate setting=2
-1.5 – 3.3 ns
CLOAD Output load capacitance – 30 – pF
CIN Input pin capacitance – 2.5 – pF
AR0141CS/D Rev. 6, 4/16 EN 52 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: Slew rate setting = 2 for PIXCLK
Slew rate setting = 2 for parallel ports
Note: 30pf loads at nominal voltages.
Table 20: I/O Timing Characteristics (1.8V VDD_IO)
Conditions: fPIXCLK = 37.125 MHz(720P30fps;) VDD_IO = 1.8V
Symbol Definition C Condition Min Typ Max Unit
fEXTCLK1 Input clock frequency PLL enabled 6 – 50 MHz
tEXTCLK1 Input clock period PLL enabled 20 – 166.6666667 ns
tRInput clock rise time – 3 – ns
tFInput clock fall time – 3 – ns
tRR PIXCLK rise time PCLK slew rate setting=2 3.2 5.6 9.5 ns
tFP PIXCLK fall time PCLK slew rate setting=2 2.9 5.0 8.8 ns
Clock duty cycle 45 50 55 %
tJITTER2 Input clock jitter at 27 MHz – – 600 ps
fPIXCLK PIXCLK frequency Default PLL configuration 6 37.125 74.25 MHz
tPD PIXCLK to Data[11:0] PCLK slew rate setting=2
Parallel slew rate setting=2
-2.2 – 5.9 ns
tPFH PIXCLK to FV high PCLK slew rate setting=2
Parallel slew rate setting=2
-0.9 – 4.5 ns
tPLH PIXCLK to LV high PCLK slew rate setting=2
Parallel slew rate setting=2
-0.9 – 4.6 ns
tPFL PIXCLK to FV low PCLK slew rate setting=2
Parallel slew rate setting=2
-1.7 – 3.1 ns
tPLL PIXCLK to FV low PCLK slew rate setting=2
Parallel slew rate setting=2
-1.6 – 3.4 ns
CLOAD Output load capacitance – 30 – pF
CIN Input pin capacitance – 2.5 – pF
Table 21: I/O Rise Slew Rate (2.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 0.83 1.38 2.1 V/ns
6 Default 0.71 1.2 1.84 V/ns
5 Default 0.64 1.07 1.65 V/ns
4 Default 0.56 0.94 1.44 V/ns
3 Default 0.47 0.79 1.21 V/ns
2 Default 0.39 0.64 0.98 V/ns
1 Default 0.29 0.48 0.74 V/ns
0 Default 0.2 0.32 0.49 V/ns
AR0141CS/D Rev. 6, 4/16 EN 53 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: 30pf loads at nominal voltages.
Note: 30pf loads at nominal voltages.
Note: 30pf loads at nominal voltages.
Table 22: I/O Fall Slew Rate (2.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 0.76 1.25 1.85 V/ns
6 Default 0.67 1.12 1.68 V/ns
5 Default 0.61 1.04 1.56 V/ns
4 Default 0.55 0.93 1.41 V/ns
3 Default 0.48 0.81 1.23 V/ns
2 Default 0.4 0.67 1.03 V/ns
1 Default 0.31 0.52 0.79 V/ns
0 Default 0.21 0.35 0.54 V/ns
Table 23: I/O Rise Slew Rate (1.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 0.32 0.51 0.85 V/ns
6 Default 0.28 0.44 0.75 V/ns
5 Default 0.25 0.4 0.68 V/ns
4 Default 0.23 0.36 0.6 V/ns
3 Default 0.2 0.31 0.51 V/ns
2 Default 0.17 0.26 0.41 V/ns
1 Default 0.13 0.2 0.32 V/ns
0 Default 0.09 0.13 0.21 V/ns
Table 24: I/O Fall Slew Rate (1.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13]) Conditions Min Typ Max Units
7 Default 0.32 0.53 0.87 V/ns
6 Default 0.28 0.47 0.77 V/ns
5 Default 0.26 0.43 0.71 V/ns
4 Default 0.24 0.39 0.64 V/ns
3 Default 0.21 0.34 0.56 V/ns
2 Default 0.18 0.29 0.47 V/ns
1 Default 0.14 0.22 0.36 V/ns
0 Default 0.1 0.16 0.25 V/ns
AR0141CS/D Rev. 6, 4/16 EN 54 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
DC Electrical Characteristics
The DC electrical characteristics are shown in the tables below.
Caution Stresses greater than those listed in Table 26 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other con-
ditions above those indicated in the operational sections of this specification is not implied.
Note: Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 25: DC Electrical Characteristics
Symbol Definition Condition Min Typ Max Unit
VDD Core digital voltage 1.7 1.8 1.95 V
VDD_IO I/O digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 V
VAA Analog voltage 2.5 2.8 3.1 V
VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V
VDD_PLL PLL supply voltage 2.5 2.8 3.1 V
VDD_SLVS HiSPi supply voltage 0.3 0.4 0.6 V
VIH Input HIGH voltage VDD_IO*0.7 – – V
VIL Input LOW voltage – – VDD_IO*0.3 V
IIN Input leakage current No pull-up resistor; VIN = VDD_IO or
DGND
20 – – A
VOH Output HIGH voltage VDD_IO-0.3 – – V
VOL Output LOW voltage – – 0.4 V
IOH Output HIGH current At specified VOH -22 – – mA
IOL Output LOW current At specified VOL ––22mA
Table 26: Absolute Maximum Ratings
Symbol Definition Condition Min Max Unit
VDD_MAX Core digital voltage –0.3 2.4 V
VDD_IO_MAX I/O digital voltage –0.3 4 V
VAA_MAX Analog voltage –0.3 4 V
VAA_PIX Pixel supply voltage –0.3 4 V
VDD_PLL PLL supply voltage –0.3 4 V
VDD_SLVS_MAX HiSPi I/O digital voltage –0.3 2.4 V
tST Storage temperature –40 150 °C
AR0141CS/D Rev. 6, 4/16 EN 55 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_PLL = 2.8V
VDD = VDD_IO = 1.8V; CLOAD = 68pF
PLL Enabled and PIXCLK = 74.25 MHz
1x analog gain, 0.36 ms integration time, 60 fps, dark conditions
TJ = 25°C
Note: VAA = VAA_PIX = VDD_PLL = 2.8V
VDD = VDD_IO = 1.8V
VDD_SLVS=1.8V for HiVCM and =0.4V for SLVS
PLL Enabled and PIXCLK = 74.25 MHz
1x analog gain, 0.36 ms integration time, 60 fps, dark conditions
TJ = 25°C
Notes: 1. Analog = VAA + VAA_PIX + VDD_PLL
2. Digital = VDD_IO + VDD_SLVS
Table 27: Operating Current Consumption in Parallel Output and Linear Mode
Definition Condition Symbol Min Typ Max Unit
Digital operating current Streaming,1280x720 60 fps IDD1 – 137 160 mA
I/O digital operating current Streaming,1280x720 60 fps IDD_IO – 15 25 mA
Analog operating current Streaming,1280x720 60 fps IAA –2030mA
Pixel supply current Streaming,1280x720 60 fps IAA_PIX – 1.5 3 mA
PLL supply current Streaming,1280x720 60 fps IDD_PLL – 4 8 mA
Table 28: Operating Currents in HiSPi Output and Linear Mode
Definition Condition Symbol Min Typ Max Unit
Digital Operating Current Streaming,1280x720 60 fps IDD –147 170 mA
Analog operating current Streaming,1280x720 60 fps IAA –20 30 mA
Pixel Supply Current Streaming,1280x720 60 fps IAA_PIX – 1.5 3 mA
PLL Supply Current Streaming,1280x720 60 fps IDD_PLL – 5 9 mA
SLVS Supply Current Streaming,1280x720 60 fps IDD_SLVS – 8 15 mA
HiVCM Supply Current Streaming,1280x720 60 fps IDD –22 25 mA
Table 29: Standby Current Consumption
Definition Condition Symbol Min Typ Max Unit
Soft standby (clock off) Analog, 2.8V - – 0 0.1 mA
Digital, 1.8V - – 0.1 0.25 mA
Soft standby (clock on) Analog, 2.8V - – 0.01 0.2 mA
Digital, 1.8V - – 26 30 mA
AR0141CS/D Rev. 6, 4/16 EN 56 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
HiSPi Electrical Specifications
Note: Refer to “High-Speed Serial Pixel Interface Physical Layer Specification v2.00.00” for
further explanation of the HiSPi transmitter specification. The electrical specifica-
tions below supersede those given in the HiSPi Physical Layer Specification.
Notes: 1. Temperature of 25°C
2. Up to 600 Mbps
Table 30: SLVS Power Supply and Operating Temperature
Parameter Symbol Min Typ Max Unit
SLVS Current Consumption1, 2 IDD_TX 18 mA
HiSPi PHY Current Consumption1,2 IDD_HiSPi 45 mA
Operating temperature3TA-30 70 °C
Table 31: SLVS Electrical DC Specification
Parameter Symbol Min Typ Max Unit
SLVS DC mean common mode voltage VCM 0.45*VDD_TX 0.5*VDD_TX 0.55*VDD_TX V
SLVS DC mean differential output voltage |VOD|0.36*VDD_TX 0.5*VDD_TX 0.64*VDD_TX V
Change in VCM between logic 1 and 0 VCM 25 mV
Change in |VOD| between logic 1 and 0 |VOD|25mV
VOD noise margin NM ±30 %
Difference in VCM between any two channels |VCM|50mV
Difference in VOD between any two channels |VOD|100mV
Common-mode AC Voltage (pk) without VCM cap
termination
VCM_AC 50 mV
Common-mode AC Voltage (pk) with VCM cap
termination
VCM_AC 30 mV
Maximum overshoot peak |VOD| VOD_AC 1.3*|VOD|V
Maximum overshoot Vdiff pk-pk Vdiff_pkpk 2.6*VOD V
Single-ended output impedance RO35 50 70
Output Impedance Mismatch RO20 %
AR0141CS/D Rev. 6, 4/16 EN 57 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Notes: 1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from the 0V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any
edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point. Note that differential
skew also is related to the VCM_AC spec, which also must not be exceeded.
Figure 46: Differential Output Voltage for Clock or Data Pairs
Table 32: SLVS Electrical Timing Specification
Parameter Symbol Min Max Unit Notes
Data Rate 1/UI 280 600 Mbps 1
Bitrate Period tPW 1.43 3.57 ns 1
Max setup time from transmitter tPRE 0.3 UI 1, 2
Max hold time from transmitter tPOST 0.3 UI 1, 2
Eye Width tEYE 0.6 UI 1, 2
Data Total Jitter (pk-pk) @1e-9 tTOTALJIT 0.2 UI 1, 2
Clock Period Jitter (RMS) tCKJIT 50 ps 2
Clock Cycle-to-Cycle Jitter (RMS) tCYCJIT 100 ps 2
Rise time (20% - 80%) tR150ps 0.25 UI 3
Fall time (20% - 80%) tF150ps 0.25 UI 3
Clock duty cycle DCYC 45 55 % 2
Mean Clock to Data Skew tCHSKEW -0.1 0.1 UI 1, 4
PHY-to-PHY Skew tPHYSKEW 2.1 UI 1, 5
Mean differential skew tDIFFSKEW -100 100 ps 6
0V Diff)
VDIFFmax
VDIFFmin
Output Signal is 'Cp - Cn' or 'Dp - Dn'
AR0141CS/D Rev. 6, 4/16 EN 58 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Figure 47: Eye Diagram for Clock and Data Signals
Figure 48: HiSPi Skew Between Data Signals Within the PHY
Table 33: Channel, PHY, and Intra-PHY Skew
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data Rate =480 Mbps; DLL set to 0
Data Lane Skew in Reference to Clock tCHSKEW1PHY -150 ps
CLKJITTER
T ri gger/ R efe rence
VdiffMax
Vdiff
UI/ 2 UI/ 2
Vdiff
TxPre TxPost
CLOCK MASK
DATA MASK
RISE
FALL
20%
80%
tCHSKEW1PHY
AR0141CS/D Rev. 6, 4/16 EN 59 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0141CS.
Note: The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0141CS.
Power-Up Sequence
The recommended power-up sequence for the AR0141CS is shown in Figure 49. The
available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 100s, turn on VAA and VAA_PIX power supply.
3. After 100s, turn on VDD_IO power supply.
4. After 100s, turn on VDD power supply.
5. After 100s, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable EXTCLK.
7. Assert RESET_BAR for at least 1ms. The parallel interface will be tri-stated during this
time.
8. Wait 1800 EXTCLKs for internal initialization into software standby.
9. Initiate load of OTPM data by setting R0x304A=0x0010.
10. Wait for 185135 EXTCLKs for a full OTPM loading.
11. Configure PLL, output, and image settings to desired values.
12. Wait 1ms for the PLL to lock.
13. Set streaming mode (R0x301A[2] = 1).
Table 34: Clock DLL Steps
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data DLL set to 0
Clock DLL Step 1 2 3 4 5 Step
Delay at 660 Mbps 0.25 0.375 0.5 0.625 0.75 UI
Eye_opening at 660 Mbps 0.85 0.78 0.71 0.71 0.69 UI
Table 35: Data DLL Steps
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Clock DLL set to 0
Data DLL Step 1 2 4 6 Step
Delay at 660 Mbps 0.25 0.375 0.625 0.875 UI
Eye opening at 660 Mbps 0.79 0.84 0.71 0.61 UI
AR0141CS/D Rev. 6, 4/16 EN 60 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Figure 49: Power Up
Notes: 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered
before or at least at the same time as the others. If the case happens that VDD_PLL is powered after
other supplies then sensor may have functionality issues and will experience high current draw on
this supply.
Table 36: Power-Up Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD_PLL to VAA/VAA_PIX3t0 0 100 – s
VAA/VAA_PIX to VDD_IO t1 0 100 – s
VDD_IO to VDD t2 0 100 – s
VDD to VDD_SLVS t3 0 100 – s
Xtal settle time tx – 301–ms
Hard Reset t4 12–– ms
Internal Initialization t5 1800 – – EXTCLK
OTPM loading t6 185135 – – EXTCLK
PLL Lock Time t7 1 – – ms
V
DD
_PLL (2.8)
V
AA
_PIX
V
AA
(2.8)
t0
V
DD
_IO(1.8/2.8)
t1
V
DD
(1.8)
V
DD
_SLV S(0.4)
t2
t3
EXTCLK
RESET_BAR t4
tx
Hard
reset
Internal
initialization
Software
Standby
R0x304 A
=0x0010 OTPM
loading
Initialization
Setting
loading
Streaming
PLL
Lock
t5 t6 t7
AR0141CS/D Rev. 6, 4/16 EN 61 ©Semiconductor Components Industries, LLC, 2016
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Power-Down Sequence
The recommended power-down sequence for the AR0141CS is shown in Figure 50. The available power supplies
(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below.
1. Disable streaming if output is active by setting standby R0x301a[2] = 0
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
3. Turn off VDD_SLVS.
4. Turn off VDD.
5. Turn off VDD_IO
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
Figure 50: Power Down
VDD_IO (1.8/2.8)
t4
t 0
t1
t3
t2
EXTCLK
VDD_SLVS (0.4)
VDD (1.8)
VAA_PIX
VAA (2.8)
VDD_PLL (2.8)
Power Down until next Power up cycle
AR0141CS/D Rev. 6, 4/16 EN 62 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Note: t4 is required between power down and next power up time; all decoupling caps from regulators
must be completely discharged.
Table 37: Power-Down Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD_SLVS to VDD t0 0 – – s
VDD to VDD_IO t1 0 – – s
VDD_IO to VAA/VAA_PIX t2 0 – – s
VAA/VAA_PIX to VDD_PLL t3 0 – – s
PwrDn until Next PwrUp Time t4 100 – – ms
AR0141CS/D Rev. 6, 4/16 EN 63 ©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Package Drawings
Package Drawings
Figure 51: 63-Ball iBGA Package (Case 503AH)
Notes: 1. Dimensions are in mm. Dimensions in () are for reference only.
2. Encapsulant: Epoxy.
3. Substrate material: Epoxy laminate 0.25 thickness. Double AR glass.
4. LID MATERIAL: BOROSILICATE GLASS 0.4±0.4MM thickness
Refractive Index at 20C = 1.5255 @ 546 nm and 1.5231 @ 588 nm.
Double Side AR Coating: 530-570nm R<1%; 420-700nm R<2%.
5. Image sensor die: 0.2 thickness.
6. Solder ball material: SAC 305 (95% Sn, 3% Ag, 0.5% Cu).
Dimensions apply to solder balls post reflow.
Pre-reflow ball is
0.5 on a
0.4 SMD ball pad.
IBGA63 9x9
CASE 503AH
ISSUE O
DATE 30 DEC 201
4
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AR0141CS: 1/4-Inch Digital Image Sensor
Package Drawings
AR0141CS/D Rev. 6, 4/16 EN 64 ©Semiconductor Components Industries, LLC, 2016 .
A-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
7. Maximum rotation of optical area relative to package edges: 0.75°.
Maximum tilt of optical area relative to substrate plane D: 25 microns.
Maximum tilt of cover glass relative to optical area plane E: 5 microns.