CYBLE-212019-00 - CYPRESS SEMICONDUCTOR

CYBLE-212019-00

EZ-BLE™ Creator Module

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-09764 Rev. *H Revised March 8, 2018

EZ-BLE™ Creator Module

General Description

The CYBLE-212019-00 is a Bluetooth Low Energy (BLE)

wireless module solution. The CYBLE-212019-00 is a turnkey

solution and includes onboard crystal oscillators, trace antenna,

passive components, and the Cypress PSoC 4 BLE. Refer to the

PSoC 4 BLE datasheet for additional details on the capabilities

of the PSoC 4 BLE device used on this module.

The CYBLE-212019-00 supports a number of peripheral

functions (ADC, timers, counters, PWM) and serial

communication protocols (I2C, UART, SPI) through its

programmable architecture. The CYBLE-212019-00 includes a

royalty-free BLE stack compatible with Bluetooth 4.1 and

provides up to 23 GPIOs in a 14.52 × 19.20 × 2.00 mm package.

The CYBLE-212019-00 is fully certified and qualified and is an

ideal fit for cost sensitive applications. The CYBLE-212019-00 is

drop-in compatible with the CYBLE-012011-00 EZ-BLE Creator

Module.

Module Description

■Module size: 14.52 mm × 19.20 mm × 2.00 mm (with shield)

■Castelated solder pad connections for ease-of-use

■256-KB flash memory, 32-KB SRAM memory

■Up to 23 GPIOs configurable as open drain high/low,

pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output

■Bluetooth 4.1 single-mode module

❐QDID: 81503

❐Declaration ID: D030315

■Certified to FCC, ISED, MIC, KC, and CE regulations

■Industrial temperature range: –40 °C to +85 °C

■32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit

multiply, operating at up to 48 MHz

■Watchdog timer with dedicated internal low-speed oscillator

(ILO)

■Two-pin SWD for programming

Power Consumption

■TX output power: –18 dbm to +3 dbm

■Received signal strength indicator (RSSI) with 1-dB resolution

■TX current consumption of 15.6 mA (radio only, 0 dbm)

■RX current consumption of 16.4 mA (radio only)

■Low power mode support

❐Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on

❐Hibernate: 150 nA with SRAM retention

❐Stop: 60 nA with GPIO (P2.2) or XRES wakeup

Functional Capabilities

■Up to 22 capacitive sensors for buttons or sliders with

best-in-class signal-to-noise ration (SNR) and liquid tolerance

■12-bit, 1-Msps SAR ADC with internal reference,

sample-and-hold (S/H), and channel sequencer

■Two serial communication blocks (SCBs) supporting I2C

(master/slave), SPI (master/slave), or UART

■Four dedicated 16-bit timer, counter, or PWM blocks

(TCPWMs)

■LCD drive supported on all GPIOs (common or segment)

■Programmable low voltage detect (LVD) from 1.8 V to 4.5 V

■I2S master interface

■Bluetooth Low Energy protocol stack supporting generic

access profile (GAP) Central, Peripheral, Observer, or

Broadcaster roles

■Switches between Central and Peripheral roles on-the-go

■Standard Bluetooth Low Energy profiles and services for

interoperability

■Custom profile and service for specific use cases

Benefits

The CYBLE-212019-00 module is provided as a turnkey

solution, including all necessary hardware required to use BLE

communication standards.

■Proven hardware design ready to use

■Cost optimized for applications without space constraint

■Reprogrammable architecture

■Fully certified module eliminates the time needed for design,

development and certification processes

■Bluetooth SIG qualified with QDID and Declaration ID

■Flexible communication protocol support

■PSoC Creator™ provides an easy-to-use integrated design

environment (IDE) to configure, develop, program, and test a

BLE application

Document Number: 002-09764 Rev. *H Page 2 of 39

CYBLE-212019-00

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to

quickly and effectively integrate the module into your design.

■Overview: EZ-BLE Module Portfolio, Module Roadmap

■PSoC 4 BLE Silicon Datasheet

■Application notes: Cypress offers a number of BLE application

notes covering a broad range of topics, from basic to advanced

level. Recommended application notes for getting started with

EZ-BLE modules are:

❐AN96841 - Getting Started with EZ-BLE Module

❐AN91267 - Getting Started with PSoC® 4 BLE

❐AN97060 - PSoC® 4 BLE and PRoC™ BLE - Over-The-Air

(OTA) Device Firmware Upgrade (DFU) Guide

❐AN91162 - Creating a BLE Custom Profile

❐AN91184 - PSoC 4 BLE - Designing BLE Applications

❐AN92584 - Designing for Low Power and Estimating Battery

Life for BLE Applications

❐AN85951 - PSoC® 4 CapSense® Design Guide

❐AN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator

Selection and Tuning Techniques

❐AN91445 - Antenna Design and RF Layout Guidelines

■Technical Reference Manual (TRM):

❐PRoC® BLE Technical Reference Manual

■Knowledge Base Articles

❐KBA10896 - Pin Mapping Differences Between the

EZ-BLE™ Creator Evaluation Board

(CYBLE-212019-EVAL) and the BLE Pioneer Kit

(CY8CKIT-042-BLE) - KBA10896

❐KBA210638 - RF Regulatory Certifications for

CYBLE-012011-00 and CYBLE-212019-00 EZ-BLE™

Creator Modules - KBA210638

❐KBA97095 - EZ-BLE™ Module Placement

❐KBA213976 - FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules

■Development Kits:

❐CYBLE-212019-EVAL, CYBLE-212019-00 Evaluation Board

❐CY8CKIT-042-BLE, Bluetooth® Low Energy (BLE) Pioneer

Kit

❐CY8CKIT-002, PSoC® MiniProg3 Program and Debug Kit

■Test and Debug Tools:

❐CYSmart, Bluetooth® LE Test and Debug Tool (Windows)

❐CYSmart Mobile, Bluetooth® LE Test and Debug Tool

(Android/iOS Mobile App)

Two Easy-To-Use Design Environments to Get You Started Quickly

PSoC® Creator™ Integrated Design Environment (IDE)

PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and

debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, and EZ-BLE module systems with no code size limitations. PSoC peripherals

are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC

Components™.

PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and

configure to suit a broad array of application requirements.

Blutooth Low Energy Component

The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you

quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and

provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)

hardware via the stack.

EZ-Serial™ BLE Firmware Platform

The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed

in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control

signals through the module’s GPIOs, making it easy to add BLE functionality quickly to existing designs.

Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for

User Manuals and instructions for getting started as well as detailed reference materials.

EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you

can download each EZ-BLE module’s firmware images on the EZ-Serial webpage.

Technical Support

■Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.

■Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE forum.

■Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-09764 Rev. *H Page 3 of 39

CYBLE-212019-00

Contents

Overview ............................................................................ 4

Module Description ......................................................4

Pad Connection Interface ................................................ 6

Recommended Host PCB Layout ................................... 7

Digital and Analog Capabilities

and Connections .............................................................. 9

Power Supply Connections

and Recommended External Components ..................10

Connection Options ...................................................10

External Component Recommendation ....................10

Critical Components List ...........................................13

Antenna Design .........................................................13

Electrical Specification .................................................. 14

GPIO .........................................................................16

XRES .........................................................................17

Digital Peripherals ..................................................... 20

Serial Communication ...............................................22

Memory .....................................................................23

System Resources .................................................... 23

Environmental Specifications ....................................... 29

Environmental Compliance .......................................29

RF Certification ..........................................................29

Safety Certification .................................................... 29

Environmental Conditions ......................................... 29

ESD and EMI Protection ........................................... 29

Regulatory Information .................................................. 30

FCC ........................................................................... 30

ISED .......................................................................... 31

European R&TTE Declaration of Conformity ............31

MIC Japan ................................................................. 32

KC Korea ................................................................... 32

Packaging ........................................................................ 33

Ordering Information ...................................................... 35

Part Numbering Convention ......................................35

Acronyms ........................................................................ 36

Document Conventions ................................................. 36

Units of Measure ....................................................... 36

Document History Page ................................................. 37

Sales, Solutions, and Legal Information ...................... 39

Worldwide Sales and Design Support ....................... 39

Products .................................................................... 39

PSoC® Solutions ...................................................... 39

Cypress Developer Community ................................. 39

Technical Support ..................................................... 39

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CYBLE-212019-00

Overview

Module Description

The CYBLE-212019-00 module is a complete module designed to be soldered to the applications main board.

Module Dimensions and Drawing

Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE

module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs

should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-212019-00.

Dimension Item Specification

Module dimensions Length (X) 14.52 ± 0.15 mm

Width (Y) 19.20 ± 0.15 mm

Antenna location dimensions Length (X) 11.00 ± 0.15 mm

Width (Y) 5.00 ± 0.15 mm

PCB thickness Height (H) 0.80 ± 0.10 mm

Shield height Height (H) 1.20 ± 0.10 mm

Maximum component height Height (H) 1.20-mm typical (shield)

Total module thickness (bottom of module to highest component) Height (H) 2.00-mm typical

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CYBLE-212019-00

Figure 1. Module Mechanical Drawing

Top View (View from Top)

Bottom View (Seen from Bottom)

Side View

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on

recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Tabl e 3.

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CYBLE-212019-00

Pad Connection Interface

As shown in the bottom view of Figure 1 on page 5, the CYBLE-212019-00 connects to the host board via solder pads on the backside

of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-212019-00 module.

Figure 2. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner.

This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement

best practices.

2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional

keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The

recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).

Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-212019-00 Antenna

Table 2. Solder Pad Connection Description

Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch

SP 31 Solder Pads 1.02 mm 0.71 mm 1.27 mm

Host PCB Keep Out Area Around Trace Antenna

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CYBLE-212019-00

Recommended Host PCB Layout

Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBLE-212019-00. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad

on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using

either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 4. Host Layout Pattern for CYBLE-212019-00 Figure 5. Module Pad Location from Origin

Top View (Seen on Host PCB)

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CYBLE-212019-00

Table 3 provides the center location for each solder pad on the CYBLE-212019-00. All dimensions are referenced to the center of the

solder pad. Refer to Figure 6 for the location of each module solder pad.

Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location

Solder Pad

(Center of Pad)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

1 (0.39, 4.88) (15.35, 192.13)

2 (0.39, 6.15) (15.35, 242.13)

3 (0.39, 7.42) (15.35, 292.13)

4 (0.39, 8.69) (15.35, 342.13)

5 (0.39, 9.96) (15.35, 392.13)

6 (0.39, 11.23) (15.35, 442.13)

7 (0.39, 12.50) (15.35, 492.13)

8 (0.39, 13.77) (15.35, 542.13)

9 (0.39, 15.04) (15.35, 592.13)

10 (0.39, 16.31) (15.35, 642.13)

11 (0.39, 17.58) (15.35, 692.13)

12 (2.04, 18.82) (80.31, 740.94)

13 (3.31, 18.82) (130.31, 740.94)

14 (4.58, 18.82) (180.31, 740.94)

15 (5.85, 18.82) (230.31, 740.94)

16 (7.12, 18.82) (280.31, 740.94)

17 (8.39, 18.82) (330.31, 740.94)

18 (9.66, 18.82) (380.31, 740.94)

19 (10.93, 18.82) (430.31, 740.94)

20 (12.20, 18.82) (480.31, 740.94)

21 (13.47, 18.82) (530.31, 740.94)

22 (14.14, 16.31) (556.69, 642.12)

23 (14.14, 15.04) (556.69, 592.12)

24 (14.14, 13.77) (556.69, 542.12)

25 (14.14, 12.50) (556.69, 492.12)

26 (14.14, 11.23) (556.69, 442.12)

27 (14.14, 9.96) (556.69, 392.12)

28 (14.14, 8.69) (556.69, 342.12)

29 (14.14, 7.42) (556.69, 292.12)

30 (14.14, 6.15) (556.69, 242.12)

31 (14.14, 4.88) (556.69, 192.12)

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CYBLE-212019-00

Digital and Analog Capabilities and Connections

Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on

CYBLE-212019-00, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each

connection is configurable for a single option shown with a ✓.

Table 4. Solder Pad Connection Definitions

Solder Pad

Number

Device

Port Pin UART SPI I2CTCPWM[2,3] Cap-

Sense

WCO

Out

ECO

Out LCD SWD GPIO

1 XRES External Reset Hardware Connection Input

2P4.0

[4] ✓(SCB1_RTS) ✓(SCB1_MOSI) ✓(TCPWM0_P) ✓(CMOD)✓✓

3P3.7✓(SCB1_CTS) ✓(TCPWM) ✓(Sensor) ✓✓ ✓

4P3.6✓(SCB1_RTS) ✓(TCPWM) ✓(Sensor) ✓✓

5P3.5✓(SCB1_TX) ✓(SCB1_SCL) ✓(TCPWM) ✓(Sensor) ✓✓

6P3.4✓(SCB1_RX) ✓(SCB1_SDA) ✓(TCPWM) ✓(Sensor) ✓✓

7P3.3✓(SCB0_CTS) ✓(TCPWM) ✓(Sensor) ✓✓

8P3.2✓(SCB0_RTS) ✓(TCPWM) ✓(Sensor) ✓✓

9P2.6 ✓(TCPWM) ✓(Sensor) ✓✓

10 VREF Reference Voltage Input (Optional)

11 P2.4 ✓(TCPWM) ✓(Sensor) ✓✓

12 P2.3 ✓(TCPWM) ✓(Sensor) ✓✓ ✓

13 P2.2 ✓(SCB0_SS3) ✓(TCPWM) ✓(Sensor) ✓✓

14 P2.0 ✓(SCB0_SS1) ✓(TCPWM) ✓(Sensor) ✓✓

15 VDD Digital Power Supply Input (1.8 to 5.5V)

16 P1.7 ✓(SCB0_CTS) ✓(SCB0_SCLK ✓(TCPWM) ✓(Sensor) ✓✓

17 P1.6 ✓(SCB0_RTS)✓(SCB0_SS0) ✓(TCPWM) ✓(Sensor) ✓✓

18 P1.5 ✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL) ✓(TCPWM) ✓(Sensor) ✓✓

19 P1.4 ✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM) ✓(Sensor) ✓✓

20 P1.0 ✓(TCPWM) ✓(Sensor) ✓✓

21 P0.4 ✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM) ✓(Sensor) ✓✓ ✓

22 P0.5 ✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL) ✓(TCPWM) ✓(Sensor) ✓✓

23 P0.7 ✓(SCB0_CTS) ✓(SCB0_SCLK ✓(TCPWM) ✓(Sensor) ✓✓(SWDCLK) ✓

24 P0.6 ✓(SCB0_RTS) ✓(SCB0_SS0) ✓(TCPWM) ✓(Sensor) ✓✓(SWDIO) ✓

25 GND[5] Ground Connection

26 GND[5] Ground Connection

27 GND[5] Ground Connection

28 GND[5] Ground Connection

29 VDDR Radio Power Supply (1.9V to 5.5V)

30 P5.0✓(SCB1_RX) ✓(SCB1_SS0) ✓(SCB1_SDA) ✓(TCPWM3_P) ✓(Sensor) ✓✓

31 P5.1 ✓(SCB1_TX) ✓(SCB1_SCLK ✓(SCB1_SCL) ✓(TCPWM3_N) ✓(Sensor) ✓✓ ✓

Notes

2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.

3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive

or negative polarity. TCPWM connections on ports 4 and 5 are direct and can only be used with the specified TCPWM block and polarity specified above.

4. When using the capacitive sensing functionality, Pad 2 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this

capacitor is 2.2 nF and should be placed as close to the module as possible.

5. The main board needs to connect all GND connections (Pad 25/26/27/28) on the module to the common ground of the system.

6. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator.

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CYBLE-212019-00

Power Supply Connections and Recommended External Components

Power Connections

The CYBLE-212019-00 contains two power supply connections,

VDD and VDDR. The VDD connection supplies power for both

digital and analog device operation. The VDDR connection

supplies power for the device radio.

VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts

a supply range of 1.9 V to 5.5 V. These specifications can be

found in Table 9. The maximum power supply ripple for both

power connections on the module is 100 mV, as shown in

Table 7.

The power supply ramp rate of VDD must be equal to or greater

than that of VDDR.

Connection Options

Two connection options are available for any application:

1. Single supply: Connect VDD and VDDR to the same supply.

2. Independent supply: Power VDD and VDDR separately.

External Component Recommendation

In either connection scenario, it is recommended to place an

external ferrite bead between the supply and the module

connection. The ferrite bead should be positioned as close as

possible to the module pin connection.

Figure 7 details the recommended host schematic options for a

single supply scenario. The use of one or two ferrite beads will

depend on the specific application and configuration of the

CYBLE-212019-00.

Figure 8 details the recommended host schematic for an

independent supply scenario.

The recommended ferrite bead value is 330 , 100 MHz. (Murata

BLM21PG331SN1D).

Figure 7. Recommended Host Schematic Options for a Single Supply Option

Two Ferrite Bead Option (Seen from Bottom)

Single Ferrite Bead Option (Seen from Bottom)

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CYBLE-212019-00

Figure 8. Recommended Host Schematic for an Independent Supply Option

Two Ferrite Bead Option (Seen from Bottom)

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CYBLE-212019-00

The CYBLE-212019-00 schematic is shown in Figure 9.

Figure 9. CYBLE-212019-00 Schematic Diagram

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CYBLE-212019-00

Critical Components List

Table 5 details the critical components used in the CYBLE-212019-00 module.

Table 5. Critical Component List

Antenna Design

Table 6 details trace antenna used in the CYBLE-212019-00 module. For more information, see Table 8.

Table 6. Trace Antenna Specifications

Component Reference Designator Description

Silicon U1 56-pin QFN PSoC 4 BLE

Crystal Y1 24.000 MHz, 12PF

Crystal Y2 32.768 kHz, 12.5PF

Item Description

Frequency Range 2400–2500 MHz

Peak Gain 0.5-dBi typical

Average Gain –0.5-dBi typical

Return Loss 10-dB minimum

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CYBLE-212019-00

Electrical Specification

Table 7 details the absolute maximum electrical characteristics for the Cypress BLE module.

Table 7. CYBLE-212019-00 Absolute Maximum Ratings

Table 8 details the RF characteristics for the Cypress BLE module.

Table 8. CYBLE-212019-00 RF Performance Characteristics

Table 9 through Ta ble 4 8 list the module level electrical characteristics for the CYBLE-212019-00. All specifications are valid for –40 °C

 TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

Parameter Description Min Typ Max Units Details/Conditions

VDDD_ABS Analog, digital, or radio supply relative to VSS

(VSSD = VSSA)–0.5 – 6 V Absolute maximum

VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximum

VDD_RIPPLE Maximum power supply ripple for VDD and VDDR

input voltage – – 100 mV

3.0-V supply

Ripple frequency of 100 kHz

to 750 kHz

VGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximum

IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximum

IGPIO_injection GPIO injection current: Maximum for VIH > VDD

and minimum for VIL < VSS –0.5 – 0.5 mA Absolute maximum current

injected per pin

LU Pin current for latch up –200 200 mA –

Parameter Description Min Typ Max Units Details/Conditions

RFO RF output power on ANT –18 0 3

dBm

Configurable via register

settings

RXSRF receive sensitivity on ANT – –87 – Guaranteed by design

simulation

FRModule frequency range 2400 – 2480 MHz –

GPPeak gain – 0.5 – dBi –

GAvg Average gain – –0.5 – –

RL Return loss – –10.5 – dB –

Table 9. CYBLE-212019-00 DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VDD1 Power supply input voltage 1.8 – 5.5

With regulator enabled

VDD2 Power supply input voltage unregulated 1.71 1.8 1.89 Internally unregulated

supply

VDDR1 Radio supply voltage (radio on) 1.9 – 5.5 –

VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 –

Active Mode, VDD = 1.71 V to 5.5 V

IDD3 Execute from flash; CPU at 3 MHz – 1.7 –

T = 25 °C,

VDD = 3.3 V

IDD4 Execute from flash; CPU at 3 MHz – – – T = –40 °C to 85 °C

IDD5 Execute from flash; CPU at 6 MHz – 2.5 – T = 25 °C,

VDD = 3.3 V

IDD6 Execute from flash; CPU at 6 MHz – – – T = –40 °C to 85 °C

IDD7 Execute from flash; CPU at 12 MHz – 4 – T = 25 °C,

VDD = 3.3 V

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CYBLE-212019-00

IDD8 Execute from flash; CPU at 12 MHz – – –

T = –40 °C to 85 °C

IDD9 Execute from flash; CPU at 24 MHz – 7.1 – T = 25 °C,

VDD = 3.3 V

IDD10 Execute from flash; CPU at 24 MHz – – – T = –40 °C to 85 °C

IDD11 Execute from flash; CPU at 48 MHz – 13.4 – T = 25 °C,

VDD = 3.3 V

IDD12 Execute from flash; CPU at 48 MHz – – – T = –40 °C to 85 °C

Sleep Mode, VDD = 1.8 V to 5.5 V

IDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V,

SYSCLK = 3 MHz

Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V

IDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V,

SYSCLK = 3 MHz

Deep-Sleep Mode, VDD = 1.8 V to 3.6 V

IDD15 WDT with WCO on – 1.5 –

A

T = 25 °C,

VDD = 3.3 V

IDD16 WDT with WCO on – – – T = –40 °C to 85 °C

IDD17 WDT with WCO on – – – T = 25 °C,

VDD = 5 V

IDD18 WDT with WCO on – – – T = –40 °C to 85 °C

Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed)

IDD19 WDT with WCO on – – – AT = 25 °C

IDD20 WDT with WCO on – – – T = –40 °C to 85 °C

Hibernate Mode, VDD = 1.8 V to 3.6 V

IDD27 GPIO and reset active – 150 – nA

T = 25 °C,

VDD = 3.3 V

IDD28 GPIO and reset active – – – T = –40 °C to 85 °C

Hibernate Mode, VDD = 3.6 V to 5.5 V

IDD29 GPIO and reset active – – – nA

T = 25 °C,

VDD = 5 V

IDD30 GPIO and reset active – – – T = –40 °C to 85 °C

Stop Mode, VDD = 1.8 V to 3.6 V

IDD33 Stop-mode current (VDD)–20–

T = 25 °C,

VDD = 3.3 V

IDD34 Stop-mode current (VDDR)–40–-

T = 25 °C,

VDDR = 3.3 V

IDD35 Stop-mode current (VDD) – – – T = –40 °C to 85 °C

IDD36 Stop-mode current (VDDR)–––

T = –40 °C to 85 °C,

VDDR = 1.9 V to 3.6 V

Stop Mode, VDD = 3.6 V to 5.5 V

IDD37 Stop-mode current (VDD)–––

T = 25 °C,

VDD = 5 V

IDD38 Stop-mode current (VDDR)–––

T = 25 °C,

VDDR = 5 V

IDD39 Stop-mode current (VDD) – – – T = –40 °C to 85 °C

IDD40 Stop-mode current (VDDR) – – – T = –40 °C to 85 °C

Table 9. CYBLE-212019-00 DC Specifications (continued)

Parameter Description Min Typ Max Units Details/Conditions

Document Number: 002-09764 Rev. *H Page 16 of 39

CYBLE-212019-00

GPIO

Table 10. AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

FCPU CPU frequency DC –48 MHz 1.71 V VDD 5.5 V

TSLEEP Wakeup from Sleep mode – 0 –

s

Guaranteed by characterization

TDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 24-MHz IMO. Guaranteed by

characterization

THIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization

TSTOP Wakeup from Stop mode – – 2 XRES wakeup

Table 11. GPIO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VIH[7]

Input voltage HIGH threshold 0.7 × VDD – –

CMOS input

LVTTL input, VDD < 2.7 V 0.7 × VDD – – –

LVTTL input, VDD  2.7 V 2.0 – – –

VIL

Input voltage LOW threshold – – 0.3 × VDD CMOS input

LVTTL input, VDD < 2.7 V – – 0.3 × VDD –

LVTTL input, VDD  2.7 V – – 0.8 –

VOH

Output voltage HIGH level VDD –0.6 – – IOH = 4 mA at 3.3-V VDD

Output voltage HIGH level VDD –0.5 – – IOH = 1 mA at 1.8-V VDD

VOL

Output voltage LOW level – – 0.6 IOL = 8 mA at 3.3-V VDD

Output voltage LOW level – – 0.6 IOL = 4 mA at 1.8-V VDD

Output voltage LOW level – – 0.4 IOL = 3 mA at 3.3-V VDD

RPULLUP Pull-up resistor 3.5 5.6 8.5 k–

RPULLDOWN Pull-down resistor 3.5 5.6 8.5 –

IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V

IIL_CTBM Input leakage on CTBm input pins – – 4 –

CIN Input capacitance – – 7 pF –

VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V

VHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –

IDIODE Current through protection diode to

VDD/VSS – – 100 A–

ITOT_GPIO Maximum total source or sink chip

current – – 200 mA –

Note

7. VIH must not exceed VDD + 0.2 V.

Document Number: 002-09764 Rev. *H Page 17 of 39

CYBLE-212019-00

XRES

Table 12. GPIO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TRISEF Rise time in Fast-Strong mode 2 – 12

3.3-V VDDD, CLOAD = 25 pF

TFALLF Fall time in Fast-Strong mode 2 – 12 3.3-V VDDD, CLOAD = 25 pF

TRISES Rise time in Slow-Strong mode 10 –60 3.3-V VDDD, CLOAD = 25 pF

TFALLS Fall time in Slow-Strong mode 10 –60 3.3-V VDDD, CLOAD = 25 pF

FGPIOUT1 GPIO FOUT

; 3.3 V  VDD 5.5 V

Fast-Strong mode – – 33

MHz

90/10%, 25-pF load, 60/40 duty cycle

FGPIOUT2 GPIO FOUT

; 1.7 VVDD 3.3 V

Fast-Strong mode – – 16.7 90/10%, 25-pF load, 60/40 duty cycle

FGPIOUT3 GPIO FOUT

; 3.3 V VDD 5.5 V

Slow-Strong mode – – 7 90/10%, 25-pF load, 60/40 duty cycle

FGPIOUT4 GPIO FOUT

; 1.7 V VDD 3.3 V

Slow-Strong mode – – 3.5 90/10%, 25-pF load, 60/40 duty cycle

FGPIOIN GPIO input operating frequency

1.71 V VDD 5.5 V – – 48 90/10% VIO

Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)

Parameter Description Min Typ Max Units Details/Conditions

IIL Input leakage (absolute value).

VIH > VDD ––10A25°C, V

DD = 0 V, VIH = 3.0 V

VOL Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V

Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)

Parameter Description Min Typ Max Units Details/Conditions

TRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12

25-pF load, 10%–90%, VDD = 3.3 V

TFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 25-pF load, 10%–90%, VDD = 3.3 V

TRISESS Output rise time in Slow-Strong mode 10 – 60 25-pF load, 10%-90%, VDD = 3.3 V

TFALLSS Output fall time in Slow-Strong mode 10 – 60 25-pF load, 10%-90%, VDD = 3.3 V

FGPIOUT1 GPIO FOUT

; 3.3 V VDD 5.5 V

Fast-Strong mode – – 24 MHz 90/10%, 25-pF load, 60/40 duty cycle

FGPIOUT2 GPIO FOUT

; 1.71 V VDD 3.3 V

Fast-Strong mode – – 16 MHz 90/10%, 25-pF load, 60/40 duty cycle

Table 15. XRES DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VIH Input voltage HIGH threshold 0.7 × VDDD ––VCMOS input

VIL Input voltage LOW threshold – – 0.3 × VDDD CMOS input

RPULLUP Pull-up resistor 3.5 5.6 8.5 k–

CIN Input capacitance – 3 – pF –

VHYSXRES Input voltage hysteresis – 100 – mV –

IDIODE Current through protection diode to

VDD/VSS – – 100 A–

Table 16. XRES AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TRESETWIDTH Reset pulse width 1 – – s–

Document Number: 002-09764 Rev. *H Page 18 of 39

CYBLE-212019-00

Temperatu r e Sensor

SAR ADC

Table 17. Temperature Sensor Specifications

Parameter Description Min Typ Max Units Details/Conditions

TSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 °C to +85 °C

Table 18. SAR ADC DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

A_RES Resolution – – 12 bits –

A_CHNIS_S Number of channels - single-ended – – 8 8 full-speed[8]

A-CHNKS_D Number of channels - differential – – 4 Diff inputs use

neighboring I/O[8]

A-MONO Monotonicity – – – Yes

A_GAINERR Gain error – – ±0.1 % With external

reference

A_OFFSET Input offset voltage – – 2 mV Measured with 1-V

VREF

A_ISAR Current consumption – – 1 mA –

A_VINS Input voltage range - single-ended VSS –V

DDA V–

A_VIND Input voltage range - differential VSS – VDDA –

A_INRES Input resistance – – 2.2 k–

A_INCAP Input capacitance – – 10 pF –

VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg

(1.024 V)

Note

8. A maximum of eight single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If the

AMUX Buses are being used for other functions, then the maximum number of single-ended ADC channels is six. Similarly, if the AMUX Buses are being used for

other functionality, then the maximum number of differential ADC channels is three.

Table 19. SAR ADC AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

A_PSRR Power-supply rejection ratio 70 – – dB

Measured at 1-V

reference

A_CMRR Common-mode rejection ratio 66 – – –

A_SAMP Sample rate – – 1 Msps –

Fsarintref SAR operating speed without external ref.

bypass – – 100 Ksps 12-bit resolution

A_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHz

A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz –

A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,

1 Msps –1.7 – 2

LSB

VREF = 1 V to VDD

A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V,

1 Msps –1.5 – 1.7 VREF = 1.71 V to VDD

A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V,

500 ksps –1.5 – 1.7 VREF = 1 V to VDD

A_dnl Differential nonlinearity. VDD = 1.71 V to

5.5 V, 1 Msps –1 – 2.2 VREF = 1 V to VDD

A_DNL Differential nonlinearity. VDD = 1.71 V to

3.6 V, 1 Msps –1 – 2 VREF = 1.71 V to VDD

Document Number: 002-09764 Rev. *H Page 19 of 39

CYBLE-212019-00

CSD

A_DNL Differential nonlinearity. VDD = 1.71 V to

5.5 V, 500 ksps –1 – 2.2 LSB VREF = 1 V to VDD

A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz

Table 19. SAR ADC AC Specifications (continued)

Parameter Description Min Typ Max Units Details/Conditions

CSD Block Specifications

Parameter Description Min Typ Max Units Details/Conditions

VCSD Voltage range of operation 1.71 – 5.5 V –

IDAC1 DNL for 8-bit resolution –1 – 1

LSB

–

IDAC1 INL for 8-bit resolution –3 – 3 –

IDAC2 DNL for 7-bit resolution –1 – 1 –

IDAC2 INL for 7-bit resolution –3 – 3 –

SNR Ratio of counts of finger to noise 5 – – Ratio

Capacitance range of

9 pF to 35 pF, 0.1-pF

sensitivity. Radio is not

operating during the

scan

IDAC1_CRT1 Output current of IDAC1 (8 bits) in High

range –612 –

A

–

IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low

range –306 – –

IDAC2_CRT1 Output current of IDAC2 (7 bits) in High

range –305 – –

IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low

range –153 – –

Document Number: 002-09764 Rev. *H Page 20 of 39

CYBLE-212019-00

Digital Peripherals

Timer

Counter

Table 20. Timer DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ITIM1 Block current consumption at 3 MHz – – 42

A

16-bit timer

ITIM2 Block current consumption at 12 MHz – – 130 16-bit timer

ITIM3 Block current consumption at 48 MHz – – 535 16-bit timer

Table 21. Timer AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TTIMFREQ Operating frequency FCLK –48MHz

–

TCAPWINT Capture pulse width (internal) 2 × TCLK ––

–

TCAPWEXT Capture pulse width (external) 2 × TCLK –– –

TTIMRES Timer resolution TCLK –– –

TTENWIDINT Enable pulse width (internal) 2 × TCLK –– –

TTENWIDEXT Enable pulse width (external) 2 × TCLK –– –

TTIMRESWINT Reset pulse width (internal) 2 × TCLK –– –

TTIMRESEXT Reset pulse width (external) 2 × TCLK –– –

Table 22. Counter DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ICTR1 Block current consumption at 3 MHz – – 42

A 16-bit counterICTR2 Block current consumption at 12 MHz – – 130

ICTR3 Block current consumption at 48 MHz – – 535

Table 23. Counter AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TCTRFREQ Operating frequency FCLK –48MHz–

TCTRPWINT Capture pulse width (internal) 2 × TCLK ––

–

TCTRPWEXT Capture pulse width (external) 2 × TCLK –– –

TCTRES Counter Resolution TCLK –– –

TCENWIDINT Enable pulse width (internal) 2 × TCLK –– –

TCENWIDEXT Enable pulse width (external) 2 × TCLK –– –

TCTRRESWINT Reset pulse width (internal) 2 × TCLK –– –

TCTRRESWEXT Reset pulse width (external) 2 × TCLK –– –

Document Number: 002-09764 Rev. *H Page 21 of 39

CYBLE-212019-00

Pulse Width Modulation (PWM)

LCD Direct Drive

Table 24. PWM DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IPWM1 Block current consumption at 3 MHz – – 42

A 16-bit PWMIPWM2 Block current consumption at 12 MHz – – 130

IPWM3 Block current consumption at 48 MHz – – 535

Table 25. PWM AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TPWMFREQ Operating frequency FCLK –48MHz–

TPWMPWINT Pulse width (internal) 2 × TCLK ––

–

TPWMEXT Pulse width (external) 2 × TCLK –– –

TPWMKILLINT Kill pulse width (internal) 2 × TCLK –– –

TPWMKILLEXT Kill pulse width (external) 2 × TCLK –– –

TPWMEINT Enable pulse width (internal) 2 × TCLK –– –

TPWMENEXT Enable pulse width (external) 2 × TCLK –– –

TPWMRESWINT Reset pulse width (internal) 2 × TCLK –– –

TPWMRESWEXT Reset pulse width (external) 2 × TCLK –– –

Table 26. LCD Direct Drive DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ILCDLOW Operating current in low-power mode – 17.5 – A16 × 4 small segment

display at 50 Hz

CLCDCAP LCD capacitance per segment/common

driver – 500 5000 pF –

LCDOFFSET Long-term segment offset – 20 – mV –

ILCDOP1 LCD system operating current, VBIAS = 5 V – 2 –

32 × 4 segments. 50 Hz at

25 °C

ILCDOP2 LCD system operating current, VBIAS = 3.3 V – 2 – 32 × 4 segments

50 Hz at 25 °C

Table 27. LCD Direct Drive AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

FLCD LCD frame rate 10 50 150 Hz –

Document Number: 002-09764 Rev. *H Page 22 of 39

CYBLE-212019-00

Serial Communication

Table 28. Fixed I2C DC Specifications

Table 30. Fixed UART DC Specifications

Table 31. Fixed UART AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

II2C1 Block current consumption at 100 kHz – – 50

A

–

II2C2 Block current consumption at 400 kHz – – 155 –

II2C3 Block current consumption at 1 Mbps – – 390 –

II2C4 I2C enabled in Deep-Sleep mode – – 1.4 –

Table 29. Fixed I2C AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

FI2C1 Bit rate – – 400 kHz –

Parameter Description Min Typ Max Units Details/Conditions

IUART1 Block current consumption at 100 kbps – – 55 A–

IUART2 Block current consumption at 1000 kbps – – 312 –

Parameter Description Min Typ Max Units Details/Conditions

FUART Bit rate – – 1 Mbps –

Table 32. Fixed SPI DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

ISPI1 Block current consumption at 1 Mbps – – 360

A

–

ISPI2 Block current consumption at 4 Mbps – – 560 –

ISPI3 Block current consumption at 8 Mbps – – 600 –

Table 33. Fixed SPI AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

FSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz –

Table 34. Fixed SPI Master Mode AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TDMO MOSI valid after SCLK driving edge – – 18

–

TDSI MISO valid before SCLK capturing edge

Full clock, late MISO sampling used 20 – – Full clock, late MISO sampling

THMO Previous MOSI data hold time 0 – – Referred to Slave capturing edge

Table 35. Fixed SPI Slave Mode AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TDMI MOSI valid before SCLK capturing edge 40 – –

–

TDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU –

TDSO_ext MISO Valid after SCLK driving edge in

external clock mode. VDD < 3.0 V –– 50 –

THSO Previous MISO data hold time 0 – – –

TSSELSCK SSEL valid to first SCK valid edge 100 – – –

Document Number: 002-09764 Rev. *H Page 23 of 39

CYBLE-212019-00

Memory

System Resources

Power-on-Reset (POR)

Table 36. Flash DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VPE Erase and program voltage 1.71 – 5.5 V –

TWS48 Number of Wait states at 32–48 MHz 2 – –

CPU execution from flashTWS32 Number of Wait states at 16–32 MHz 1 – –

TWS16 Number of Wait states for 0–16 MHz 0 – –

Table 37. Flash AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TROWWRITE[9] Row (block) write time (erase and program) – – 20

Row (block) = 256 bytes

TROWERASE[9] Row erase time – – 13 –

TROWPROGRAM[9] Row program time after erase – – 7 –

TBULKERASE[9] Bulk erase time (256 KB) – – 35 –

TDEVPROG[9] Total device program time – – 25 seconds –

FEND Flash endurance 100 K – – cycles –

FRET Flash retention. TA  55 °C, 100 K P/E cycles 20 – – years –

FRET2 Flash retention. TA  85 °C, 10 K P/E cycles 10 – – –

Table 38. POR DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VRISEIPOR Rising trip voltage 0.80 – 1.45 V–

VFALLIPOR Falling trip voltage 0.75 – 1.40 –

VIPORHYST Hysteresis 15 – 200 mV –

Table 39. POR AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TPPOR_TR Precision power-on reset (PPOR) response

time in Active and Sleep modes ––1

s–

Table 40. Brown-Out Detect

Parameter Description Min Typ Max Units Details/Conditions

VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V–

VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – –

Table 41. Hibernate Reset

Parameter Description Min Typ Max Units Details/Conditions

VHBRTRIP BOD trip voltage in Hibernate 1.1 – – V –

Note

9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have

completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make

certain that these are not inadvertently activated.

Document Number: 002-09764 Rev. *H Page 24 of 39

CYBLE-212019-00

Voltage Monitors (LVD)

SWD Interface

Table 42. Voltage Monitor DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79

–

VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 –

VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 –

VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 –

VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 –

VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 –

VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 –

VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 –

VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 –

VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 –

VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 –

VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 –

VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 –

VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 –

VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 –

VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 –

LVI_IDD Block current – – 100 A–

Table 43. Voltage Monitor AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TMONTRIP Voltage monitor trip time – – 1 s–

Table 44. SWD Interface Specifications

Parameter Description Min Typ Max Units Details/Conditions

F_SWDCLK1 3.3 V  VDD  5.5 V – – 14 MHz SWDCLK 1/3 CPU clock frequency

F_SWDCLK2 1.71 V  VDD  3.3 V – – 7

T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – –

–

T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – –

T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T –

T_SWDO_HOLD T = 1/f SWDCLK 1 – – –

Document Number: 002-09764 Rev. *H Page 25 of 39

CYBLE-212019-00

Internal Main Oscillator

Internal Low-Speed Oscillator

Table 49. Recommended ECO Trim Value

BLE Subsystem

Table 45. IMO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IIMO1 IMO operating current at 48 MHz – – 1000

A

–

IIMO2 IMO operating current at 24 MHz – – 325 –

IIMO3 IMO operating current at 12 MHz – – 225 –

IIMO4 IMO operating current at 6 MHz – – 180 –

IIMO5 IMO operating current at 3 MHz – – 150 –

Table 46. IMO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

FIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration

FIMOTOL3 IMO startup time – 12 – s–

Table 47. ILO DC Specifications

Parameter Description Min Typ Max Units Details/Conditions

IILO2 ILO operating current at 32 kHz – 0.3 1.05 A–

Table 48. ILO AC Specifications

Parameter Description Min Typ Max Units Details/Conditions

TSTARTILO1 ILO startup time – – 2 ms –

FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz –

Parameter Description Value Details/Conditions

ECOTRIM 24-MHz trim value

(firmware configuration) 0x0000BCBC Recommended trim value that needs to be loaded to register

CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG

Table 50. BLE Subsystem

Parameter Description Min Typ Max Units Details/Conditions

RF Receiver Specification

RXS, IDLE RX sensitivity with idle transmitter – –89 –

dBm

–

RX sensitivity with idle transmitter

excluding Balun loss – –91 – Guaranteed by design

simulation

RXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 RF-PHY Specification

(RCV-LE/CA/01/C)

RXS, HIGHGAIN RX sensitivity in high-gain mode with idle

transmitter – –91 – –

PRXMAX Maximum input power –10 –1 – RF-PHY Specification

(RCV-LE/CA/06/C)

CI1

Cochannel interference,

Wanted signal at –67 dBm and Interferer

at FRX

– 9 21 dB RF-PHY Specification

(RCV-LE/CA/03/C)

Document Number: 002-09764 Rev. *H Page 26 of 39

CYBLE-212019-00

CI2

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±1 MHz

–315

RF-PHY Specification

(RCV-LE/CA/03/C)

CI3

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±2 MHz

– –29 – RF-PHY Specification

(RCV-LE/CA/03/C)

CI4

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±3 MHz

– –39 – RF-PHY Specification

(RCV-LE/CA/03/C)

CI5

Adjacent channel interference

Wanted Signal at –67 dBm and Interferer

at Image frequency (FIMAGE)

– –20 – RF-PHY Specification

(RCV-LE/CA/03/C)

CI3

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at Image frequency (FIMAGE ± 1 MHz)

– –30 – RF-PHY Specification

(RCV-LE/CA/03/C)

OBB1

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 30–2000 MHz

–30 –27 –

dBm

RF-PHY Specification

(RCV-LE/CA/04/C)

OBB2

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 2003–2399 MHz

–35 –27 – RF-PHY Specification

(RCV-LE/CA/04/C)

OBB3

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 2484–2997 MHz

–35 –27 – RF-PHY Specification

(RCV-LE/CA/04/C)

OBB4

Out-of-band blocking,

Wanted signal a –67 dBm and Interferer

at F = 3000–12750 MHz

–30 –27 – RF-PHY Specification

(RCV-LE/CA/04/C)

IMD

Inter modulation performance

Wanted signal at –64 dBm and 1-Mbps

BLE, third, fourth, and fifth offset channel

–50 – – RF-PHY Specification

(RCV-LE/CA/05/C)

RXSE1 Receiver spurious emission

30 MHz to 1.0 GHz –––57

100-kHz measurement

bandwidth

ETSI EN300 328 V1.8.1

RXSE2 Receiver spurious emission

1.0 GHz to 12.75 GHz –––47

1-MHz measurement

bandwidth

ETSI EN300 328 V1.8.1

RF Transmitter Specifications

TXP, ACC RF power accuracy – ±1 – dB –

TXP, RANGE RF power control range – 20 – –

TXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 –

dBm

–

TXP, MAX Output power, maximum power setting

(PA10) –3 – –

TXP, MIN Output power, minimum power setting

(PA1) – –18 – –

F2AVG Average frequency deviation for

10101010 pattern 185 – –

kHz

RF-PHY Specification

(TRM-LE/CA/05/C)

F1AVG Average frequency deviation for

11110000 pattern 225 250 275 RF-PHY Specification

(TRM-LE/CA/05/C)

Table 50. BLE Subsystem (continued)

Parameter Description Min Typ Max Units Details/Conditions

Document Number: 002-09764 Rev. *H Page 27 of 39

CYBLE-212019-00

EO Eye opening = F2AVG/F1AVG 0.8 – – RF-PHY Specification

(TRM-LE/CA/05/C)

FTX, ACC Frequency accuracy –150 – 150

kHz

RF-PHY Specification

(TRM-LE/CA/06/C)

FTX, MAXDR Maximum frequency drift –50 – 50 RF-PHY Specification

(TRM-LE/CA/06/C)

FTX, INITDR Initial frequency drift –20 – 20 RF-PHY Specification

(TRM-LE/CA/06/C)

FTX, DR Maximum drift rate –20 – 20 kHz/

50 s

RF-PHY Specification

(TRM-LE/CA/06/C)

IBSE1 In-band spurious emission at 2-MHz

offset –––20

dBm

RF-PHY Specification

(TRM-LE/CA/03/C)

IBSE2 In-band spurious emission at 3-MHz

offset –––30 RF-PHY Specification

(TRM-LE/CA/03/C)

TXSE1 Transmitter spurious emissions

(average), <1.0 GHz – – –55.5 FCC-15.247

TXSE2 Transmitter spurious emissions

(average), >1.0 GHz – – –41.5 FCC-15.247

RF Current Specifications

IRX Receive current in normal mode – 18.7 –

–

IRX_RF Radio receive current in normal mode – 16.4 – Measured at VDDR

IRX, HIGHGAIN Receive current in high-gain mode – 21.5 – –

ITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – –

ITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – –

ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – Measured at VDDR

ITX_RF, 0dBm Radio TX current at 0 dBm excluding

Balun loss – 14.2 – Guaranteed by design

simulation

ITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – –

ITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – –

ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – –

ITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – –

Iavg_1sec, 0dBm Average current at 1-second BLE

connection interval – 17.1 –

A

TXP: 0 dBm; ±20-ppm

master and slave clock

accuracy.

For empty PDU exchange

Iavg_4sec, 0dBm Average current at 4-second BLE

connection interval –6.1 –

TXP: 0 dBm; ±20-ppm

master and slave clock

accuracy.

For empty PDU exchange

General RF Specifications

FREQ RF operating frequency 2400 – 2482 MHz –

CHBW Channel spacing – 2 – –

DR On-air data rate – 1000 – kbps –

Table 50. BLE Subsystem (continued)

Parameter Description Min Typ Max Units Details/Conditions

Document Number: 002-09764 Rev. *H Page 28 of 39

CYBLE-212019-00

IDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 s–

IDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 –

RSSI Specifications

RSSI, ACC RSSI accuracy – ±5 – dB –

RSSI, RES RSSI resolution – 1 – –

RSSI, PER RSSI sample period – 6 – s–

Table 50. BLE Subsystem (continued)

Parameter Description Min Typ Max Units Details/Conditions

Document Number: 002-09764 Rev. *H Page 29 of 39

CYBLE-212019-00

Environmental Specifications

Environmental Compliance

This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)

directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBLE-212019-00 module will be certified under the following RF certification standards at production release.

■FCC: WAP2011

■CE

■IC: 7922A-2011

■MIC: 203-JN0509

■KC: MSIP-CRM-Cyp-2011

Safety Certification

The CYBLE-212019-00 module complies with the following regulations:

■Underwriters Laboratories, Inc. (UL) - Filing E331901

■CSA

■TUV

Environmental Conditions

Table 51 describes the operating and storage conditions for the Cypress BLE module.

Table 51. Environmental Conditions for CYBLE-212019-00

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI).

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.

Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Description Minimum Specification Maximum Specification

Operating temperature –40 °C 85 °C

Operating humidity (relative, non-condensation) 5% 85%

Thermal ramp rate – 3 °C/minute

Storage temperature –40 °C 85 °C

Storage temperature and humidity – 85 ° C at 85%

ESD: Module integrated into system Components[10] –15 kV Air

2.2 kV Contact

Note

10. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.

Document Number: 002-09764 Rev. *H Page 30 of 39

CYBLE-212019-00

Regulatory Information

FCC

FCC NOTICE:

The device CYBLE-212019-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter

approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device

may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause

undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by

Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment

generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, ê may cause

harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.

If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment

off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■Reorient or relocate the receiving antenna.

■Increase the separation between the equipment and receiver.

■Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

■Consult the dealer or an experienced radio/TV technician for help

LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well

as the FCC Notice above. The FCC identifier is FCC ID: WAP2011.

In any case the end product must be labeled exterior with “Contains FCC ID: WAP2011”.

ANTENNA WARNING:

This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these

fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the

following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

RF EXPOSURE:

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous.

The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas

in Table 6 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal

instructions about the integrated radio module is not allowed.

The radiated output power of CYBLE-212019-00 with the trace antenna is far below the FCC radio frequency exposure limits.

Nevertheless, use CYBLE-212019-00 in such a manner that minimizes the potential for human contact during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with

transmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-09764 Rev. *H Page 31 of 39

CYBLE-212019-00

ISED

Innovation, Science and Economic Development Canada (ISED) Certification

CYBLE-212019-00 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada

(ISED).

License: IC: 7922A-2011

Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antennas listed in Table 6 on page 13, having a maximum gain of 0.5 dBi. Antennas

not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna

impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna

or transmitter.

ISED NOTICE:

The device CYBLE-212019-00 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the

requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This

device may not cause harmful interference, and (2) This device must accept any interference received, including interference that

may cause undesired operation.

ISED RADIATION EXPOSURE STATEMENT FOR CANADA

This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).

Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any

interference, including interference that may cause undesired operation of the device.

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de

licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur

de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le

fonctionnement.

LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as

the ISED Notice above. The IC identifier is 7922A-2011. In any case, the end product must be labeled in its exterior with “Contains

IC: 7922A-2011”

European R&TTE Declaration of Conformity

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-212019-00 complies with the essential requirements and

other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the

Directive 1999/5/EC, the end-customer equipment should be labeled as follows:

All versions of the CYBLE-212019-00 in the specified reference design can be used in the following countries: Austria, Belgium,

Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-

bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: 002-09764 Rev. *H Page 32 of 39

CYBLE-212019-00

MIC Japan

CYBLE-212019-00 is certified as a module with type certification number 203-JN0509. End products that integrate CYBLE-212019-00

do not need additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

KC Korea

CYBLE-212019-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-2011.

Document Number: 002-09764 Rev. *H Page 33 of 39

CYBLE-212019-00

Packaging

The CYBLE-212019-00 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-212019-00.

Figure 10. CYBLE-212019-00 Tape Dimensions

Figure 11 details the orientation of the CYBLE-212019-00 in the tape as well as the direction for unreeling.

Figure 11. Component Orientation in Tape and Unreeling Direction

Table 52. Solder Reflow Peak Temperature

Module Part Number Package Maximum Peak Temperature Maximum Time at Peak

Temperature No. of Cycles

CYBLE-212019-00 31-pad SMT 260 °C 30 seconds 2

Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number Package MSL

CYBLE-212019-00 31-pad SMT MSL 3

Document Number: 002-09764 Rev. *H Page 34 of 39

CYBLE-212019-00

Figure 12 details reel dimensions used for the CYBLE-212019-00.

Figure 12. Reel Dimensions

The CYBLE-212019-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The

center-of-mass for the CYBLE-212019-00 is detailed in Figure 13.

Figure 13. CYBLE-212019-00 Center of Mass (Seen from Top)

Document Number: 002-09764 Rev. *H Page 35 of 39

CYBLE-212019-00

Ordering Information

Table 54 lists the CYBLE-212019-00 part numbers and features.

Table 55 lists the CYBLE-212019-00 reel shipment quantities.

The CYBLE-212019-00 is offered in tape and reel packaging. The CYBLE-212019-00 ships with a maximum of 500 units/reel.

Part Numbering Convention

The part numbers are of the form CYBLE-FATT##-SB where the fields are defined as follows.

For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales

representative. To locate the nearest Cypress office, visit our website.

Table 54. Ordering Information

Part Number

CPU

Speed

(MHz)

Flash

Size

(KB)

CapSense SCB TCPWM

12-Bit

SAR

ADC

I2SLCD Package Packing Certified

CYBLE-212019-00 48 256 Yes 2 4 1 Msps Yes Yes 31-SMT Tape and Reel Yes

Table 55. Tape and Reel Package Quantity and Minimum Order Amount

Description Minimum Reel Quantity Maximum Reel Quantity Comments

Reel Quantity 500 500 Ships in 500 unit reel quantities.

Minimum Order Quantity (MOQ) 500 – –

Order Increment (OI) 500 – –

U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134

U.S. Cypress Headquarter Contact Info (408) 943-2600

Cypress website address http://www.cypress.com

Document Number: 002-09764 Rev. *H Page 36 of 39

CYBLE-212019-00

Acronyms Document Conventions

Units of Measure

Table 56. Acronyms Used in this Document

Acronym Description

BLE Bluetooth Low Energy

Bluetooth

SIG Bluetooth Special Interest Group

CE European Conformity

CSA Canadian Standards Association

EMI electromagnetic interference

ESD electrostatic discharge

FCC Federal Communications Commission

GPIO general-purpose input/output

IC Industry Canada

IDE integrated design environment

KC Korea Certification

MIC Ministry of Internal Affairs and Communications

(Japan)

PCB printed circuit board

RX receive

QDID qualification design ID

SMT

surface-mount technology; a method for producing

electronic circuitry in which the components are

placed directly onto the surface of PCBs

TCPWM timer, counter, pulse width modulator (PWM)

TUV Germany: Technischer Überwachungs-Verein

(Technical Inspection Association)

TX transmit

Table 57. Units of Measure

Symbol Unit of Measure

°C degree Celsius

kV kilovolt

mA milliamperes

mm millimeters

mV millivolt

A microamperes

m micrometers

MHz megahertz

GHz gigahertz

Vvolt

Document Number: 002-09764 Rev. *H Page 37 of 39

CYBLE-212019-00

Document History Page

Document Title: CYBLE-212019-00, EZ-BLE™ Creator Module

Document Number: 002-09764

Revision ECN Orig. of

Change

Submission

Date Description of Change

** 5086199 DSO 01/14/2016 Preliminary datasheet for CYBLE-212019-00 module.

*A 5148398 DSO 02/22/2016

Update More Information section to add KBA210638 (Certification Test Reports)

to reference list.

Update More Information section to add KBA10896 to reference list.

Updated orientation of module drawings in Figure 1, Figure 2, Figure 3, Figure 4,

Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, and Figure 13 to match orien-

tation in PSoC Creator.

Update Table 4 to add additional information with respect to the functional capabil-

ities for each solder pad.

*B 5137880 MINS 04/20/2016

Updated Document Title to read as “CYBLE-212019-00, EZ-BLE™ Creator

Module”.

Updated to new template.

*C 5418947 DSO 08/30/2016

Changed status from Preliminary to Final.

Updated General Description:

Updated Module Description:

Added Bluetooth Declaration ID and QDID under “Bluetooth 4.1 single-mode

module”.

Updated Power Consumption:

Replaced “Stop: 60 nA with XRES wakeup” with “Stop: 60 nA with GPIO (P2.2) or

XRES wakeup” under “Low power mode support”.

Updated More Information:

Added additional Knowledge Base Article references.

Updated Electrical Specification:

Updated System Resources:

Updated Internal Low-Speed Oscillator:

Updated Table 49 (Updated details in “Value” column corresponding to ECOTRIM

parameter).

Updated Ordering Information:

No change in part numbers.

Added Ta bl e 55 (To specify minimum and maximum reel quantities ship for orders

of the CYBLE-212019-00 module).

Updated to new template.

*D 5529621 DSO 11/15/2016

Updated More Information:

Added EZ-Serial™ BLE Firmware Platform section.

Updated Overview:

Updated Figure 1 to specify that Bottom View is “Seen from Bottom”.

Updated Recommended Host PCB Layout:

Updated Figure 4, Figure 5, and Figure 6 captions to specify that these as “Seen

on Host PCB”.

Updated Power Supply Connections and Recommended External Components:

Updated Figure 7 and Figure 8 to specify that these are “Seen from Bottom”.

Updated Digital and Analog Capabilities and Connections:

Updated Tab le 4:

Updated TCPWM column to add TCPWM capability on Port 2 pins.

Added Footnote 3.

*E 5553544 DSO 12/14/2016

Updated Electrical Specification:

Updated SAR ADC:

Updated Tab le 18 to add Note 8 to specify under what conditions the maximum

number of ADC channels can be achieved.

*F 5731446 GNKK 05/09/2017 Updated the Cypress logo.

*G 6002363 DSO 12/22/2017 Updated reel dimensions in Figure 10 and Figure 12.

Document Number: 002-09764 Rev. *H Page 38 of 39

CYBLE-212019-00

*H 5996958 DSO 03/08/2018

Updated document title.

Updated “PRoC™” references to “Creator”.

Updated “PRoC BLE” references to “PSoC 4 BLE”.

Updated Module Description, More Information, Environmental Specifications,

Regulatory Information, and Part Numbering Convention.

Updated Figure 6.

Removed CYBLE-212023-10 part number.

Updated Sales page.

Document History Page

Document Title: CYBLE-212019-00, EZ-BLE™ Creator Module

Document Number: 002-09764

Document Number: 002-09764 Rev. *H Revised March 8, 2018 Page 39 of 39

CYBLE-212019-00

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

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