BQ27541DRZRG1 - TEXAS INSTRUMENTS

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1. General description

The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin

compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7A.

The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and

3-state outputs. The shift registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP).

The data in each register is transferred to the storage register on a positive-going

transition of the storage register clo ck input (STCP). If both clocks are connected together,

the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.

It is also provided with asynchronou s reset (acti ve LOW) for all 8 shif t register st ages. The

storage register has 8 parallel 3-state bus driver outputs. Data in the storage register

appears at the output whenever the output enable input (OE) is LOW.

2. Features and benefits

Balanced propagation delays

All inputs have Schmitt-trigger action

Inputs accept voltages higher tha n V CC

Input levels:

The 74VHC595 operates with CMOS input level

The 74VHCT595 operates with TTL input level

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD2 2-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Multiple package options

Specified from 40 C t o +85 C and from 40 C to +125 C

3. Applications

Serial-to-parallel data conversion

Remote control holding register

74VHC595; 74VHCT595

8-bit serial-in/serial-out or parallel-out shift register with

output latches

Rev. 2 — 4 July 2012 Product data sheet

Product data sheet Rev. 2 — 4 July 2012 2 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

4. Ordering information

5. Functional diagram

Table 1. Ordering information

Type number Package

Temperatu re range Name Description Version

74VHC595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body

width 3.9 mm SOT109-1

74VHCT595D

74VHC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

74VHCT595PW

74VHC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads;

16 terminals; body 2.5 3.5 0.85 mm

SOT763-1

74VHCT595BQ

Fig 1. Functional di agram

mna554

3-STATE OUTPUTS

8-BIT STORAGE REGISTER

8-STAGE SHIFT REGISTER

Q0Q1Q2Q3Q4Q5Q6Q7

Q7S

151234567

SHCP

STCP

Fig 2. Logic symbol Fig 3. IEC logic symbol

OEMR

1310

11 12

mna552

Q7S

STCP

SHCP

mna553

1D 2D

C1/

13 EN3

SRG8

Product data sheet Rev. 2 — 4 July 2012 3 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Fig 4. Logic diagram

STAGE 0 STAGES 1 TO 6 STAGE 7

FF0

LATCH

FF7

LATCH

mna555

Q1Q2Q3Q4Q5Q6Q7

Q7S

STCP

SHCP

Product data sheet Rev. 2 — 4 July 2012 4 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

6. Pinning information

6.1 Pinning

6.2 Pin description

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16

74VHC595

74VHCT595

Q1 V

Q2 Q0

Q3 DS

Q4 OE

Q5 STCP

Q6 SHCP

Q7 MR

GND Q7S

001aak048

001aak049

74VHC595

74VHCT595

Q7 MR

Q6 SHCP

Q5 STCP

Q4 OE

Q3 DS

Q2 Q0

GND

Q7S

VCC

Transparent top view

710

611

512

413

314

215

terminal 1

index area

GND(1)

Table 2. Pin description

Symbol Pin Description

Q1 1 parallel data output 1

Q2 2 parallel data output 2

Q3 3 parallel data output 3

Q4 4 parallel data output 4

Q5 5 parallel data output 5

Q6 6 parallel data output 6

Q7 7 parallel data output 7

GND 8 ground (0 V)

Q7S 9 serial data output

MR 10 master reset (active LOW)

SHCP 11 shift register clock input

STCP 12 storage register clock input

OE 13 output enable input (active LOW)

DS 14 serial data input

Q0 15 parallel data output 0

VCC 16 supply voltage

Product data sheet Rev. 2 — 4 July 2012 5 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

7. Functional description

[1] H = HIGH voltage state;

L = LOW voltage state;

= LOW-to-HIGH transition;

X = don’t care;

NC = no change;

Z = high-impedance OFF-state.

Table 3. Function table[1]

Control Input Output Function

SHCP STCP OE MR DS Q7S Qn

X X L L X L NC a LOW-level on MR only affects the shift registers

XL L X L L empty shift register loaded into storage register

X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state

X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

XL H X NC QnS contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

L H X Q6S QnS conten ts of shif t re gi ster shif te d th ro ug h ; pre v i o us contents of the

shift register is transferred to the storage register and the parallel

output stages

Fig 7. Timing diagram

STCP

Q7S

Z-state

Product data sheet Rev. 2 — 4 July 2012 6 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.

For TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.

For DHVQFN16 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7.0 V

VIinput voltage 0.5 +7.0 V

IIK input clamping current VI<0.5 V [1] 20 - mA

IOK output clamping current VO<0.5 V or VO>V

CC +0.5V [1] 20 +20 mA

IOoutput current VO=0.5 V to (VCC +0.5V) 25 +25 mA

ICC supply current - +75 mA

IGND ground current 75 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb =40 C to +125 C[2] - 500 mW

Product data sheet Rev. 2 — 4 July 2012 7 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

9. Recommended operating conditions

10. Static characteristics

Table 5. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

74VHC595

VCC supply voltage 2.0 5.0 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage 0 - VCC V

Tamb ambient temperature 40 +25 +125 C

t/V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V

VCC = 4.5 V to 5.5 V - - 20 ns/V

74VHCT595

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage 0 - VCC V

Tamb ambient temperature 40 +25 +125 C

t/V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74VHC595

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V

VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V

VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V

VIL LOW-level

input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V

VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V

VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V

VOH HIGH-level

output voltage VI= VIH or VIL

IO= 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO= 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

IO= 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO= 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V

IO= 8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V

VOL LOW-level

output voltage VI= VIH or VIL

IO= 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

Product data sheet Rev. 2 — 4 July 2012 8 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

IIinput leakage

current VI= 5.5 Vor GND;

VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A

IOZ OFF-state

output current VI=V

IH or VIL;

VO=V

CC or GND; VCC =5.5V --0.25 - 2.5 - 10 A

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC =5.5V --4.0 - 40 - 80A

CIinput

capacitance - 3 10 - 10 - 10 pF

74VHCT595

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO= 50 A 4.4 4.5 - 4.4 - 4.4 - V

IO= 8.0 mA 3.94 - - 3.80 - 3.70 - V

VOL LOW-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO= 50 A - 0 0.1 - 0.1 - 0.1 V

IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current VI= 5.5 Vor GND;

VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A

IOZ OFF-state

output current VI=V

IH or VIL;

VO=V

CC or GND per input pin;

other inputs at VCC or GND;

IO=0 A; V

CC =5.5V

--0.25 - 2.5 - 10 A

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC =5.5V --4.0 - 40 - 80A

ICC additional

supply current per input pin; VI=V

CC 2.1 V;

other inputs at VCC or GND;

IO=0 A; V

CC = 4.5 V to 5.5 V

- - 1.35 - 1.5 - 1.5 mA

CIinput

capacitance - 3 10 - 10 - 10 pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 2 — 4 July 2012 9 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

11. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max Min Max

74VHC595

tpd propagation

delay SHCP to Q7S; see Figure 8 [2]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.7 13.0 1.0 15.0 1.0 16.5 ns

CL= 50 pF - 7.7 16.5 1.0 18.5 1.0 20.1 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 4.0 8.2 1.0 9.4 1.0 10.5 ns

CL= 50 pF - 5.4 10.0 1.0 11.4 1.0 12.5 ns

STCP to Qn; see Figure 9 [2]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.9 11.9 1.0 13.5 1.0 15.0 ns

CL= 50 pF - 7.7 15.4 1.0 17.0 1.0 18.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 4.2 7.4 1.0 8.5 1.0 9.5 ns

CL= 50 pF - 5.5 9.0 1.0 10.5 1.0 11.5 ns

MR to Q7S; see Figure 11 [3]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.9 12.8 1.0 13.7 1.0 15.0 ns

CL= 50 pF - 7.4 16.3 1.0 17.2 1.0 18.7 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 4.4 8.0 1.0 9.1 1.0 10.0 ns

CL= 50 pF - 5.6 10.0 1.0 11.1 1.0 12.0 ns

ten enable time OE to Qn; see Figure 12 [4]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.6 11.5 1.0 13.5 1.0 15.0 ns

CL= 50 pF - 7.4 15.0 1.0 17.0 1.0 18.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns

CL= 50 pF - 5.3 10.6 1.0 12.0 1.0 13.0 ns

tdis disable time OE to Qn; see Figure 12 [5]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.4 11.0 1.0 13.0 1.0 14.5 ns

CL= 50 pF - 8.7 15.7 1.0 16.2 1.0 17.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 3.8 8.0 1.0 9.5 1.0 10.5 ns

CL= 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns

Product data sheet Rev. 2 — 4 July 2012 10 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

fmax maximum

frequency SHCP or STCP;

see Figure 8 and 9

VCC = 3.0 V to 3.6 V 80 125 - 60 - 40 - MHz

VCC = 4.5 V to 5. 5 V 130 170 - 11 0 - 90 - MHz

tWpulse width SHCP HIGH or LOW;

see Figure 8

VCC = 3.0 V to 3. 6 V 5.0 - - 5.0 - 5.0 - ns

VCC = 4.5 V to 5. 5 V 5.0 - - 5.0 - 5.0 - ns

STCP HIGH or LOW;

see Figure 9

VCC = 3.0 V to 3. 6 V 5.0 - - 5.0 - 5.0 - ns

VCC = 4.5 V to 5. 5 V 5.0 - - 5.0 - 5.0 - ns

MR LOW; see Figure 11

VCC = 3.0 V to 3. 6 V 5.0 - - 5.0 - 5.0 - ns

VCC = 4.5 V to 5. 5 V 5.0 - - 5.0 - 5.0 - ns

tsu set-up time DS to SHCP; see Figure 9

VCC = 3.0 V to 3. 6 V 3.5 - - 3.5 - 3.5 - ns

VCC = 4.5 V to 5. 5 V 3.0 - - 3.0 - 3.0 - ns

SHCP to STCP;

see Figure 10

VCC = 3.0 V to 3. 6 V 8.5 - - 8.5 - 8.5 - ns

VCC = 4.5 V to 5. 5 V 5.0 - - 5.0 - 5.0 - ns

thhold time DS to SHCP; see Figure 10

VCC = 3.0 V to 3. 6 V 1.5 - - 1.5 - 1.5 - ns

VCC = 4.5 V to 5. 5 V 2.0 - - 2.0 - 2.0 - ns

trec recovery

time MR to SHCP; see Figure 11

VCC = 3.0 V to 3. 6 V 3.0 - - 3.0 - 3.0 - ns

VCC = 4.5 V to 5. 5 V 2.5 - - 2.5 - 2.5 - ns

CPD power

dissipation

capacitance

fi = 1 MHz; VI=GNDtoV

CC [6]

[7] -180- - - - - pF

74VHCT595; VCC = 4.5 V to 5.5 V

tpd propagation

delay SHCP to Q7S; see Figure 8 [2]

CL= 15 pF - 3.8 8.2 1.0 9.0 1.0 10.0 ns

CL= 50 pF - 5.2 10.0 1.0 11.0 1.0 12.0 ns

STCP to Qn; see Figure 9 [2]

CL= 15 pF - 4.0 7.4 1.0 8.5 1.0 9.5 ns

CL= 50 pF - 5.3 9.0 1.0 10.5 1.0 11.5 ns

MR to Q7S; see Figure 11 [3]

CL= 15 pF - 4.6 8.2 1.0 9.5 1.0 10.5 ns

CL= 50 pF - 5.8 10.5 1.0 11.5 1.0 12.5 ns

Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max Min Max

Product data sheet Rev. 2 — 4 July 2012 11 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

[1] Typical values are measured at nominal supply voltage.

[2] tpd is the same as tPHL and tPLH.

[3] tpd is the same as tPHL only.

[4] ten is the same as tPZL and tPZH.

[5] tdis is the same as tPLZ and tPHZ.

[6] CPD is used to determine the dynamic power dissipation (PDin W).

PD=C

PD VCC2fi+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

(CLVCC2fo) = sum of outputs;

CL= output load capacitance in pF;

VCC = supply voltage in V.

[7] All 9 outputs switching.

ten enable time OE to Qn; see Figure 12 [4]

CL= 15 pF - 4.8 9.0 1.0 11.0 1.0 12.0 ns

CL= 50 pF - 6.2 11.6 1.0 13.0 1.0 14.5 ns

tdis disable time OE to Qn; see Figure 12 [5]

CL= 15 pF - 3.6 6.9 1.0 8.0 1.0 9.0 ns

CL= 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns

fmax maximum

frequency SHCP and STCP;

see Figure 8 and 9130 170 - 110 - 90 - MHz

tWpulse width SHCP HIGH or LOW;

see Figure 8 5.0 - - 5.0 - 5.0 - ns

STCP HIGH or LOW;

see Figure 9 5.0 - - 5.0 - 5.0 - ns

MR LOW; see Figure 11 5.0 - - 5.0 - 5.0 - ns

tsu set-up time DS to SHCP; see Figure 9 3.0 - - 3.0 - 3.0 - ns

SHCP to STCP;

see Figure 10 5.0 - - 5.0 - 5.0 - ns

thhold time DS to SHCP; see Figure 10 2.0 - - 2.0 - 2.0 - ns

trec recovery

time MR to SHCP; see Figure 11 3.0 - - 3.0 - 3.0 - ns

CPD power

dissipation

capacitance

fi = 1 MHz; VI=GNDtoV

CC [6]

[7] -190- - - - - pF

Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max Min Max

Product data sheet Rev. 2 — 4 July 2012 12 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

12. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. Shift clock pulse, maximum frequency and input to output propagation delays

mna557

SHCP input

Q7S output

tPLH tPHL

1/fmax

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 9. Storage clock to output propagation delays

mna558

STCP input

Qn output

tPLH tPHL

tsu 1/fmax

VOH

GND

VOL

SHCP input

GND

Product data sheet Rev. 2 — 4 July 2012 13 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 10. Data set-u p an d hold times

mna560

GND

Q7S output

SHCP input

DS input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 11. Master reset to output propagation delays

mna561

MR input

SHCP input

Q7S output

PHL

rec

GND

Product data sheet Rev. 2 — 4 July 2012 14 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 12. Enable and disable times

mna450

tPLZ

tPHZ

outputs

disabled outputs

enabled

VOH − 0.3 V

VOL + 0.3 V

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VCC

VOL

VOH

GND

tPZL

tPZH

Table 8. Measurement points

Type Input Output

VMVM

74VHC595 0.5VCC 0.5VCC

74VHCT595 1.5 V 0.5VCC

Product data sheet Rev. 2 — 4 July 2012 15 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Test data is given in Table 9.

Definitions for test circuit:

CL = load capacitance including jig and probe capacitance.

RL = load resistance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

S1 = test selection switch.

Fig 13. Load circuitry for switc hin g time s

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

VIVO

RLS1

open

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

74VHC595 VCC 3.0ns 15pF, 50pF 1kopen GND VCC

74VHCT595 3.0 V 3.0ns 15pF, 50pF 1kopen GND VCC

Product data sheet Rev. 2 — 4 July 2012 16 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

13. Package outline

Fig 14. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 2 — 4 July 2012 17 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Fig 15. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 2 — 4 July 2012 18 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Fig 16. Package outline SOT763-1 (DHVQFN16)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4 1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

15 10

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 2 — 4 July 2012 19 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

14. Abbreviations

15. Revision history

Table 10. Abbreviations

Acronym Description

CDM Charged Device Mo del

CMOS Complementary Metal-Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74VHC_VHCT595 v.2 20120704 Product data sheet - 74VHC_VHCT595 v.1

Modifications: •Added GND in the pin configuration drawing DHVQFN16 (errata)

74VHC_VHCT595 v.1 20090811 Product data sheet - -

Product data sheet Rev. 2 — 4 July 2012 20 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 4 July 2012 21 of 22

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74VHC595; 74VHCT595

8-bit serial-in/serial-o ut or paralle l-out shift register with output latches

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 July 2012

Document identifier: 74V HC_VHCT595

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 7

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 Contact information. . . . . . . . . . . . . . . . . . . . . 21

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22