LTC2754
1
2754f
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Quad 12-/16-Bit
SoftSpan IOUT DACs
The LTC
®
2754 is a family of quad 12- and 16-bit multiplying
serial-input, current-output digital-to-analog converters.
They operate from a single 3V to 5V supply and are guar-
anteed monotonic over temperature. The LTC2754A-16
provides full 16-bit performance (±1LSB INL and DNL,
max) over temperature without any adjustments. These
SoftSpan™ DACs offer six output ranges (up to ±10V) that
can be programmed through the 3-wire SPI serial interface,
or pinstrapped for operation in a single range.
The content of any on-chip register (including DAC out-
put-range settings) can be verifi ed in just one instruction
cycle; and if you change any register, that register will be
automatically read back during the next instruction cycle.
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to 0V regardless of output range.
Quad 16-Bit VOUT DAC with Software-Selectable Ranges
n Program or Pin-Strap Six Output Ranges
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
n Maximum 16-Bit INL Error: ±1 LSB over
Temperature
n Guaranteed Monotonic over Temperature
n Low Glitch Impulse 0.26nV•s (3V), 1.25nV•s (5V)
n Serial Readback of All On-Chip Registers
n Low 1A Maximum Supply Current
n 2.7V to 5.5V Single-Supply Operation
n 16-Bit Settling Time: 2µs
n Voltage-Controlled Offset and Gain Trims
n Clear and Power-On-Reset to 0V Regardless of
Output Range
n 52-Pin 7mm × 8mm QFN Package
■ High Resolution Offset and Gain Adjustment
■ Process Control and Industrial Automation
■ Automatic Test Equipment
■ Data Acquisition Systems
LTC2754-16
–
+
+
–
DAC D
DAC A
VREFA
VDD
VOUTA
VOUTD
RINA
REFA
VREFD
REFD
ROFSA
GND
M-SPAN
ROFSD
RCOMD
GEADJD RCOMA
RIND
VOSADJA
VOSADJD
IOUT2A
IOUT1A
IOUT1D
IOUT2D
RFBA
RFBD
GEADJA
–
+
SPI with READBACK
+
–
–
+
+
–
DAC C
DAC B
VREFB
VOUTB
VOUTC
RINB
REFB
VREFC
REFC
ROFSB
ROFSC
RCOMC
GEADJC RCOMB
RINC
VOSADJB
VOSADJC
ALL AMPLIFIERS 1/2 LT1469
IOUT2B
IOUT1B
IOUT1C
IOUT2C
RFBB
RFBC
GEADJB
–
+
+
–
2754 TA01
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178.
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2754 G01
–0.6
0.6
0.8
0.2
49152 65535
VDD = 5V
VREF = 5V
±10V RANGE
LTC2754-16 Integral
Nonlinearity (INL)
LTC2754
2
2754f
1615 17 18 19
TOP VIEW
53
UKG PACKAGE
52-LEAD (7mm s 8mm) PLASTIC QFN
20 21 22 23 24 25 26
5152 50 49 48 47 46 45 44 43 42 41
33
34
35
36
37
38
39
40
8
7
6
5
4
3
2
1GEADJA
RINA
IOUT2A
GND
CS/LD
SDI
SCK
SRO
SROGND
VDD
GND
IOUT2D
RIND
GEADJD
GEADJB
RINB
IOUT2B
GND
LDAC
S2
S1
S0
M-SPAN
RFLAG
CLR
IOUT2C
RINC
GEADJC
RCOMA
REFA
ROFSA
RFBA
IOUT1A
VOSADJA
VOSADJB
IOUT1B
RFBB
ROFSB
REFB
RCOMB
RCOMD
REFD
ROFSD
RFBD
IOUT1D
VOSADJD
VOSADJC
IOUT1C
RFBC
ROFSC
REFC
RCOMC
32
31
30
29
28
27
9
10
11
12
13
14
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ABSOLUTE MAXIMUM RATINGS
IOUT1X, IOUT2X to GND ............................................±0.3V
RINX, RCOMX, REFX, RFBX, ROFSX, VOSADJX,
GEADJX to GND ........................................................±18V
VDD to GND .................................................. –0.3V to 7V
Digital Inputs and
Outputs to GND ................ –0.3V to VDD+0.3V (max 7V)
Operating Temperature Range
LTC2754C ................................................ 0°C to 70°C
LTC2754I..............................................–40°C to 85°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range ...................–65°C to 150°C
(Notes 1, 2)
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2754CUKG-12#PBF LTC2754CUKG-12#TRPBF LTC2754UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2754IUKG-12#PBF LTC2754IUKG-12#TRPBF LTC2754UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
LTC2754BCUKG-16#PBF LTC2754BCUKG-16#TRPBF LTC2754UKG-16 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2754BIUKG-16#PBF LTC2754BIUKG-16#TRPBF LTC2754UKG-16 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
LTC2754ACUKG-16#PBF LTC2754ACUKG-16#TRPBF LTC2754UKG-16 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2754AIUKG-16#PBF LTC2754AIUKG-16#TRPBF LTC2754UKG-16 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2754
3
2754f
ELECTRICAL CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes the
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS
LTC2754-12 LTC2754B-16 LTC2754A-16
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Static Performance
Resolution ●12 16 16 Bits
Monotonicity ●12 16 16 Bits
DNL Differential
Nonlinearity
●±1 ±1 ±0.2 ±1 LSB
INL Integral Nonlinearity ●±1 ±2 ±0.4 ±1 LSB
GE Gain Error All Output Ranges ●±0.5 ±2 ±20 ±2 ±12 LSB
Gain Error Temp-
erature Coeffi cient
∆Gain/∆Temp ±1 ±1 ±1 ppm/°C
BZE Bipolar Zero Error All Bipolar Ranges ●±0.2 ±1 ±12 ±1 ±8 LSB
Bipolar Zero Temp-
erature Coeffi cient
±0.5 ±0.5 ±0.5 ppm/°C
PSR Power Supply
Rejection
VDD = 5V, ±10%
VDD = 3V, ±10%
●
●
±0.025
±0.06
±0.4
±1
±0.03
±0.1
±0.2
±0.5
LSB/V
LSB/V
ILKG IOUT1 Leakage Current TA = 25°C
TMIN to TMAX ●
±0.05 ±2
±5
±0.05 ±2
±5
±0.05 ±2
±5
nA
nA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Pins
Reference Inverting Resistors (Note 4) ●16 20 k
RREF DAC Input Resistance ●810 k
RFB Feedback Resistors (Note 3) ●810 k
ROFS Bipolar Offset Resistors (Note 3) ●16 20 k
RVOSADJ Offset Adjust Resistors ●1024 1280 k
RGEADJ Gain Adjust Resistors ●2048 2560 k
CIOUT1 Output Capacitance Full-Scale
Zero-Scale
75
45
pF
Dynamic Performance
Output Settling Time 0V to 10V Range, 10V Step. To ±0.0015% FS
(Note 5)
2s
Glitch Impulse VDD = 5V (Note 6)
VDD = 3V (Note 6)
1.25
0.26
nV•s
nV•s
Digital-to-Analog Glitch Impulse (Note 7) 2 nV•s
Reference Multiplying BW 0V to 5V Range, VREF = 3VRMS,
Code = Full Scale, –3dB BW
2 MHz
Multiplying Feedthrough Error 0V to 5V Range, VREF = ±10V, 10kHz
Sine Wave
0.5 mV
Analog Crosstalk (Note 8) –109 dB
THD Total Harmonic Distortion (Note 9) Multiplying –110 dB
Output Noise Voltage Density (Note 10) at IOUT1 13 nV/√Hz
VDD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C.
LTC2754
4
2754f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VDD Supply Voltage ●2.7 5.5 V
IDD Supply Current, VDD Digital Inputs = 0V or VDD ●0.5 1 A
Digital Inputs
VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
●
●
2.4
2
V
V
VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
●
●
0.8
0.6
V
V
Hysteresis Voltage 0.1 V
IIN Digital Input Current VIN = GND to VDD ●±1 µA
CIN Digital Input Capacitance VIN = 0V (Note 11) ●6pF
Digital Outputs
VOH IOH = 200µA 2.7V ≤ VDD ≤ 5.5V ●VDD – 0.4 V
VOL IOL = 200µA 2.7V ≤ VDD ≤ 5.5V ●0.4 V
TIMING CHARACTERISTICS
The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 4.5V to 5.5V
t1SDI Valid to SCK Set-Up ●7ns
t2SDI Valid to SCK Hold ●7ns
t3SCK High Time ●11 ns
t4SCK Low Time ●11 ns
t5CS/LD Pulse Width ●9ns
t6LSB SCK High to CS/LD High ●4ns
t7CS/LD Low to SCK Positive Edge ●4ns
t8CS/LD High to SCK Positive Edge ●4ns
t9SRO Propagation Delay CLOAD = 10pF ●18 ns
t10 CLR Pulse Width Low ●36 ns
t11 LDAC Pulse Width Low ●15 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 11) ●50 ns
t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 11) ●40 ns
SCK Frequency 50% Duty Cycle (Note 12) ●40 MHz
VDD = 2.7V to 3.3V
t1SDI Valid to SCK Set-Up ●9ns
t2SDI Valid to SCK Hold (Note 11) ●9ns
t3SCK High Time CL = 10pF ●15 ns
t4SCK Low Time ●15 ns
t5CS/LD Pulse Width ●12 ns
t6LSB SCK High to CS/LD High ●5ns
ELECTRICAL CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes the
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
LTC2754
5
2754f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t7CS/LD Low to SCK Positive Edge ●5ns
t8CS/LD High to SCK Positive Edge ●5ns
t9SRO Propagation Delay CLOAD = 10pF ●26 ns
t10 CLR Pulse Width Low ●60 ns
t11 LDAC Pulse Width Low ●20 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 11) ●70 ns
t13 CS/LD High to RFLAG high CLOAD = 10pF (Note 11) ●60 ns
SCK Frequency 50% Duty Cycle (Note 12) ●25 MHz
TIMING CHARACTERISTICS
The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specifi ed pins is constant for
all output ranges if the IOUT1X and IOUT2X pins are held at ground.
Note 4: Input resistors measured from RINX to RCOMX; feedback resistors
measured from RCOMX to REFX.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7s can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifi er: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. Analog Crosstalk is defi ned as the AC voltage ratio VOUTB/VREFA,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Crosstalk
between other DAC channels is similar or better.
Note 9. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifi er = LT1469.
Note 10. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (), T = temperature (°K), and B =
bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale.
Note 11. Guaranteed by design, not subject to test.
Note 12. When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
fMAX =1
2t
9+tS
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
, where tS is the setup time of the receiving device.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LTC2754-16
TEMPERATURE (°C)
–40
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2754 G03
VDD = 5V
VREF = 5V
±10V RANGE
+INL
–INL
INL vs Temperature
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2754 G01
–0.6
0.6
0.8
0.2
49152 65535
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2754 G02
–0.6
0.6
0.8
0.2
49152 65535
VDD = 5V
VREF = 5V
±10V RANGE
LTC2754
6
2754f
VREF (V)
–10 –8 0
44
–6 2
26810
2754 G08
VDD = 5V
±5V RANGE
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–0.6
0.6
0.8
0.2 +DNL
–DNL
+DNL
–DNL
TEMPERATURE (°C)
–40
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2754 G04
VDD = 5V
VREF = 5V
±10V RANGE
+DNL
–DNL
VREF (V)
–10 –8 0
44
–6 2
26810
2754 G07
VDD = 5V
±5V RANGE
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–0.6
0.6
0.8
0.2 +INL
–INL
+INL
–INL
DNL vs Temperature Bipolar Zero vs Temperature Gain Error vs Temperature
INL vs VREF DNL vs VREF
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LTC2754-16
VDD (V)
2.5
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
34
3.5 4.5
–0.6
0.6
0.8
0.2
55.5
2754 G09
+INL
–INL
INL vs VDD
Multiplying Frequency Response
vs Digital Code
FREQUENCY (Hz)
100
–120
ATTENUATION (dB)
–100
–80
–60
–40
–20
0
1k 10k 100k 1M
2754 G10
10M
ALL BITS OFF
D8
D4
D2
D0
D7
D1
D3
D9
D6
D5
D15
D14
D12
D10
D13
D11
ALL BITS ON
UNIPOLAR 5V OUTPUT RANGE
LT1469 OUTPUT AMPLIFIER
CFEEDBACK = 8.2pF
TEMPERATURE (°C)
–40
BZE (LSB)
–2
0
2
20 60
2754 G05
–4
–6
–8 –20 0 40
4
6
8
80
VDD = 5V
VREF = 5V
±10V RANGE
±0.5ppm/°C (TYP)
TEMPERATURE (°C)
–40
GE (LSB)
–4
0
4
20 60
2754 G06
–8
–12
–16 –20 0 40
8
12
16
80
VDD = 5V
VREF = 5V
±10V RANGE
±1ppm/°C (TYP)
LTC2754
7
2754f
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
LTC2754-12
TA = 25°C, unless otherwise noted.
VDD (V)
2.5
0.5
LOGIC THRESHOLD (V)
0.75
1
1.25
1.5
2
33.5 4 4.5 5 5.5
1.75
2754 G14
RISING
FALLING
Logic Threshold
vs Supply Voltage
Supply Current
vs Logic Input Voltage
LTC2754
Supply Current
vs Clock Frequency
Midscale Glitch Settling 0V to 10V
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
2754 G11
–0.6
0.6
0.8
0.2
3072 4095
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
2754 G12
–0.6
0.6
0.8
0.2
3072 4095
VDD = 5V
VREF = 5V
±10V RANGE
DIGITAL INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3
4
5
4
2754 G13
2
1
01235
VDD = 5V
CLR,LDAC, SDI, SCK,
CS/LD TIED TOGETHER
VDD = 3V
SCK FREQUENCY (Hz)
1
0.0001
SUPPLY CURRENT (mA)
0.001
0.01
0.1
1
10
100
VDD = 5V
100 10k 1M 100M
2754 G15
VDD = 3V
Midscale Glitch
CS/LD
2V/DIV
VOUT
5mV/DIV
500ns/DIVVDD = 3V
VREF = 5V
5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 27pF
2754 G16
0.26nV•s TYP
CS/LD
5V/DIV
VOUT
5mV/DIV
500ns/DIVVDD = 5V
VREF = 5V
5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 27pF
2754 G17
1.25nV•s TYP
500ns/DIV
CS/LD
5V/DIV
GATED
SETTLING
WAVEFORM
250µV/DIV
2754 G17
USING LT1469 AMP
CFEEDBACK = 12pF
0V TO 10V STEP
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER
LTC2754
8
2754f
PIN FUNCTIONS
GEADJA (Pin1): Gain Adjust Pin for DAC A. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRINA (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RINA (Pin 2): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected internally
from RINA to RCOMA. For normal operation tie RINA to the
external reference voltage VREFA (see Typical Applications).
Any or all of these precision-matched resistor sets (Each
set comprising RINX, RCOMX and REFX) may be used to
invert one or more positive reference voltages to the nega-
tive voltages needed by the DACs. Typically 5V; accepts
up to ±15V.
IOUT2A (Pin 3): DAC A Current Output Complement. Tie
IOUT2A to ground.
GND (Pin 4): Ground; provides shielding for IOUT2A. Tie
to ground.
CS/LD (Pin 5): Synchronous Chip Select and Load Pin.
SDI (Pin 6): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK) when CS/LD is low.
SCK (Pin 7): Serial Clock.
SRO (Pin 8): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clocking
out after the last address bit A0 is clocked in. SRO is an
active output only when the chip is selected (i.e., when
CS/LD is low). Otherwise SRO presents a high-impedance
output in order to allow other parts to control the bus.
SROGND (Pin 9): Ground pin for SRO. Tie to ground.
VDD (Pin 10): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V. By-
pass with a 0.1F low-ESR ceramic capacitor to ground.
GND (Pin 11): Ground. Tie to ground.
IOUT2D (Pin 12): DAC D Current Output Complement. Tie
IOUT2D to ground.
RIND (Pin 13): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected inter-
nally from RIND to RCOMD. For normal operation tie RIND
to the external reference voltage VREFD (see Typical
Applications). Any or all of these precision-matched resis-
tor sets (Each set comprising RINX, RCOMX and REFX) may
be used to invert one or more positive reference voltages
to the negative voltages needed by the DACs. Typically
5V; accepts up to ±15V.
GEADJD (Pin 14): Gain Adjust Pin for DAC D. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRIND (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RCOMD (Pin 15): Center Tap Point for Reference Amplifi er
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RIND to RCOMD and from
RCOMD to REFD, respectively (see Block Diagram). For
normal operation tie RCOMD to the negative input of external
reference inverting amplifi er (see Typical Applications).
REFD (Pin 16): Inverted Reference Voltage for DAC D, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFD to RCOMD.
For normal operation tie this pin to the output of reference
inverting amplifi er (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RIND and RCOMD fl oating).
ROFSD (Pin 17): Bipolar Offset Network for DAC D. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RIND (Pin 13). The
impedance looking into this pin is 20k to ground.
RFBD (Pin 18): DAC D Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifi er
for DAC D (see Typical Applications). The DAC output
current from IOUT1D fl ows through the feedback resistor
to the RFBD pin. The impedance looking into this pin is
10k to ground.
IOUT1D (Pin 19): DAC D Current Output. This pin is a
virtual ground when the DAC is operating and should
reside at 0V. For normal operation tie to the negative
input of the I/V converter amplifi er for DAC D (see Typi-
cal Applications).
LTC2754
9
2754f
PIN FUNCTIONS
VOSADJD (Pin 20): DAC D Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJD produces ∆VOS =
-512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RIND). Tie to ground if not used.
VOSADJC (Pin 21): DAC C Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJC produces ∆VOS =
-512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINC). Tie to ground if not used.
IOUT1C (Pin 22): DAC C Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifi er for DAC C (see Typical Applications).
RFBC (Pin 23): DAC C Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifi er
for DAC C (see Typical Applications). The DAC output
current from IOUT1D fl ows through the feedback resistor
to the RFBC pin. The impedance looking into this pin is
10k to ground.
ROFSC (Pin 24): Bipolar Offset Network for DAC C. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RINC (Pin 28). The
impedance looking into this pin is 20k to ground.
REFC (Pin 25): Inverted Reference Voltage for DAC C, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFC to RCOMC.
For normal operation tie this pin to the output of reference
inverting amplifi er (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RINC and RCOMC fl oating).
RCOMC (Pin 26): Center Tap Point for Reference Amplifi er
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RINC to RCOMC and from
RCOMC to REFC, respectively (see Block Diagram). For
normal operation tie RCOMC to the negative input of external
reference inverting amplifi er (see Typical Applications).
GEADJC (Pin 27): Gain Adjust Pin for DAC C. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRINC (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RINC (Pin 28): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected internally
from RINC to RCOMC. For normal operation tie RINC to the
external reference voltage VREFC (see Typical Applica-
tions). Any or all of these precision-matched resistor
sets (Each set comprising RINX, RCOMX and REFX) may be
used to invert one or more positive reference voltages to
the negative voltages needed by the DACs. Typically 5V;
accepts up to ±15V.
IOUT2C (Pin 29): DAC C Current Output Complement. Tie
IOUT2C to ground.
CLR (Pin 30): Asynchronous Clear Pin. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
RFLAG (Pin 31): Reset Flag Pin. An active low output is
asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
M-SPAN (Pin 32): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S2, S1 and S0 (Pins 33, 34
and 35) to confi gure all DACs for operation in a single,
fi xed output range.
To confi gure the part for manual-span use, tie M-SPAN
directly to VDD. The active output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To confi gure the part for SoftSpan use, tie M-SPAN di-
rectly to GND. The output ranges are then individually and
dynamically controllable through the SPI port; and pins
S2, S1 and S0 have no effect.
See ‘Manual Span Confi guration’ in the Operation sec-
tion. M-SPAN must be connected either directly to
GND (SoftSpan confi guration) or to VDD (manual-span
confi guration).
LTC2754
10
2754f
S0 (Pin 33): Span Bit 0. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single fi xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
S1 (Pin 34): Span Bit 1. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single fi xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
S2 (Pin 35): Span Bit 2. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single fi xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
LDAC (Pin 36): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
GND (Pin 37): Ground; provides shielding for IOUT2B. Tie
to ground.
IOUT2B (Pin 38): DAC B Current Output Complement. Tie
IOUT2B to ground.
RINB (Pin 39): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected internally
from RINB to RCOMB. For normal operation tie RINB to the
external reference voltage VREFB (see Typical Applica-
tions). Any or all of these precision-matched resistor sets
(Each set comprising RINX, RCOMX and REFX) may be
used to invert one or more positive reference voltages to
the negative voltages needed by the DACs. Typically 5V;
accepts up to ±15V.
GEADJB (Pin 40): Gain Adjust Pin for DAC B. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRINB (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RCOMB (Pin 41): Center Tap Point for Reference Amplifi er
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RINB to RCOMB and from
RCOMB to REFB, respectively (see Block Diagram). For
normal operation tie RCOMB to the negative input of external
reference inverting amplifi er (see Typical Applications).
REFB (Pin 42): Inverted Reference Voltage for DAC B, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFB to RCOMB.
For normal operation tie this pin to the output of reference
inverting amplifi er (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RINB and RCOMB fl oating).
ROFSB (Pin 43): Bipolar Offset Network for DAC B. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RINB (Pin 39). The
impedance looking into this pin is 20k to ground.
RFBB (Pin 44): DAC B Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifi er
for DAC B (see Typical Applications). The DAC output
current from IOUT1B fl ows through the feedback resistor
to the RFBB pin. The impedance looking into this pin is
10k to ground.
IOUT1B (Pin 45): DAC B Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifi er for DAC B (see Typical Applications).
VOSADJB (Pin 46): DAC B Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset-voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJB produces ∆VOS =
–512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINB). Tie to ground if not used.
VOSADJA (Pin 47): DAC A Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset-voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJA produces ∆VOS =
–512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINA). Tie to ground if not used.
IOUT1A (Pin 48): DAC A Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifi er for DAC A (see Typical Applications).
RFBA (Pin 49): DAC A Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifi er
for DAC A (see Typical Applications). The DAC output
current from IOUT1A fl ows through the feedback resistor
to the RFBA pin. The impedance looking into this pin is
10k to ground.
PIN FUNCTIONS
LTC2754
11
2754f
BLOCK DIAGRAM
DAC B
16-BIT WITH
SPAN SELECT
16
3
DATA REGISTERS
SPAN REGISTERS
INPUT REG
16
3
DATA REGISTERS
INPUT REG
SPAN REGISTERS
DAC REG
DAC REG
39
40
41
42
43
44
45
38
46
21
29
22
23
24
ROFSB
REFB
RINB
RINC
SROGNDSROSCKSDIS0S1S2M-SPAN CS/LD LDACCLRRFLAG
GEADJB
RCOMB
IOUT1B
IOUT2B
VOSADJB
VOSADJC
GEADJC
RFBB
IOUT1C
RFBC
ROFSC
RCOMC
REFC
IOUT2C
DAC C
16-BIT WITH
SPAN SELECT
25
26
27
28
36765303133343532
16
3
DATA REGISTERS
SPAN REGISTERS
DAC REG
DAC REG
INPUT REG
16
3
DATA REGISTERS
INPUT REG
SPAN REGISTERS
DAC REG
DAC REG
2
1
52
51
50
49
48
3
47
20
12
19
18
17
ROFSA
REFA
RINA
RIND
GEADJA
RCOMA
IOUT1A
IOUT2A
VOSADJA
VOSADJD
GEADJD
RFBA
IOUT1D
RFBD
ROFSD
RCOMD
REFD
IOUT2D
16
15
14
13
DAC A
16-BIT WITH
SPAN SELECT
DAC D
16-BIT WITH
SPAN SELECT
POWER-ON
RESET
9
GND
4, 11, 37
8
VDD
10
INPUT REG
INPUT REG
INPUT REG
INPUT REG
DAC REG
DAC REG
DAC B
16-BIT WITH
SPAN SELECT
CONTROL AND READBACK LOGIC
2754 BD
LTC2754-16
2.56M 2.56M
2.56M 2.56M
20k
20k
20k
20k
20k
20k
20k
20k
ROFSA (Pin 50): Bipolar Offset Network for DAC A. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RINA (Pin 2). The
impedance looking into this pin is 20k to ground.
REFA (Pin 51): Inverted Reference Voltage for DAC A, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFA to RCOMA.
For normal operation tie this pin to the output of reference
inverting amplifi er (see Typical Applications). Typically – 5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RINA and RCOMA fl oating).
RCOMA (Pin 52): Center Tap Point for Reference Amplifi er
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RINA to RCOMA and from
RCOMA to REFA, respectively (see Block Diagram). For
normal operation tie RCOMA to the negative input of external
reference inverting amplifi er (see Typical Applications).
Exposed Pad (Pin 53): Ground. The Exposed Pad must
be soldered to the PCB.
PIN FUNCTIONS
LTC2754
12
2754f
TIMING DIAGRAMS
Output Ranges
The LTC2754 is a quad, current-output, serial-input preci-
sion multiplying DAC with selectable output ranges. Ranges
can either be programmed in software for maximum
fl exibility—each of the four DACs can be programmed
to any one of six output ranges—or hardwired through
pin-strapping. Two unipolar ranges are available (0V to 5V
and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V
and –2.5V to 7.5V). These ranges are obtained when an
external precision 5V reference is used. When a reference
voltage of 2V is used, the ranges become: 0V to 2V, 0V to
4V, ±1V, ±2V, ±4V and –1V to 3V. The output ranges are
linearly scaled for other reference voltages.
Manual Span Confi guration
Multiple output ranges are not needed in some applica-
tions. To confi gure the LTC2754 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to VDD. The active output range for all four
DACs is then set via hardware pin strapping of pins S2,
S1 and S0 (rather than through the SPI port); and Write
and Update commands have no effect on the active output
span. See Figure 1 and Table 3.
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
Figure 1. Using M-SPAN to Confi gure the LTC2754
for Single-Span Operation (±10V Range Shown).
LTC2754-16
M-SPAN
S2
S1
S0
2754 F01
CS/LD SDI SCK
VDD
VDD
DAC A ±10V
±10V
±10V
±10V
DAC B
DAC C
DAC D
–
+
–
+
–
+
–
+
SDI
SRO Hi-Z
CS/LD
SCK
LSB 2754 TD
LSB
t2
t9
t8
t5t7
1 2 31 32
t6
t1
LDAC
t3t4
t11
OPERATION
LTC2754
13
2754f
Input and DAC Registers
The LTC2754 has 5 internal registers for each DAC, a total
of 20 registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers—one set for the
code data, and one for the output range of the DAC—plus
one readback register. Double buffering provides the ca-
pability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Note that updates always include both Data and Span
registers; but the values held in the DAC registers will
only change if the associated Input register values have
previously been changed via a Write operation.
Serial Interface
When the CS/LD pin is taken low, the data on the SDI
pin is loaded into the shift register on the rising edge of
the clock (SCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2754 is a 4-bit command
word (C3 C2 C1 C0), followed by a 4-bit address word
(A3 A2 A1 A0) and 16 data (span or code) bits, MSB fi rst.
Figure 2 shows the SDI input word syntax to use when
writing code or span. If a 32-bit input sequence is used,
the fi rst eight bits must be zeros, followed by the same
sequence as for a 24-bit wide input. Figure 3 shows the
input and readback sequences for both 24-bit and 32-bit
operations.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output.The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. SRO outputs a logic low until the readback
OPERATION
data begins. For a 24-bit input sequence, the 16 readback
bits are shifted out on the falling edges of clocks 8-23,
suitable for shifting into a microprocessor on the rising
edges of clocks 9-24. For a 32-bit sequence, the bits are
shifted out on clocks 16-31; see Figure 3b.
When CS/LD is high, the SRO pin presents a high impedance
(three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
The codes for the command word (C3-C0) are defi ned in
Table 1; Table 2 defi nes the codes for the address word
(A3-A0).
Readback
In addition to the Input and DAC registers, each DAC has
one Readback register associated with it. When a Read
command is issued to a DAC, the contents of one of its
four buffers (Input and DAC registers for each of Span
and Code) is copied into its Readback register and seri-
ally shifted out through the SRO pin. Figure 3 shows the
loading and readback sequences.
In the data fi eld (D15-D0) of any non-read instruction cycle,
SRO shifts out the contents of the buffer that was specifi ed
in the preceding command. This “rolling readback” default
mode of operation can dramatically reduce the number
of instruction cycles needed, since any command can be
verifi ed during succeeding commands with no additional
overhead. See Figure 4. Table 1 shows the storage location
(‘readback pointer’) of the data which will be output from
SRO during the next instruction.
For Read commands, the data is shifted out during the Read
instruction itself (on the 16 falling SCK edges immediately
after the last address bit is shifted in on SDI). When checking
the span of a DAC using SRO, the span bits are the last
four bits shifted out, corresponding to their sequence and
positions when writing a span. See Figure 3.
LTC2754
14
2754f
OPERATION
Table 1. Command Codes
CODE
COMMAND
READBACK POINTER–
CURRENT INPUT WORD W0
READBACK POINTER–
NEXT INPUT WORD W+1
C3 C2 C1 C0
0010 Write Span DAC n Set by Previous Command Input Span Register DAC n
0011 Write Code DAC n Set by Previous Command Input Code Register DAC n
0100 Update DAC n Set by Previous Command DAC Span Register DAC n
0101 Update All DACs Set by Previous Command DAC Code Register DAC A
0110 Write Span DAC n
Update DAC n
Set by Previous Command DAC Span Register DAC n
0111 Write Code DAC n
Update DAC n
Set by Previous Command DAC Code Register DAC n
1000 Write Span DAC n
Update All DACs
Set by Previous Command DAC Span Register DAC n
1001 Write Code DAC n
Update All DACs
Set by Previous Command DAC Code Register DAC n
1010 Read Input Span Register DAC n Input Span Register DAC n
1011 Read Input Code Register DAC n Input Code Register DAC n
1100 Read DAC Span Register DAC n DAC Span Register DAC n
1101 Read DAC Code Register DAC n DAC Code Register DAC n
1111 No Operation Set by Previous Command DAC Code Register DAC n
– System Clear – DAC Span Register DAC A
– Initial Power-Up or Power Interupt – DAC Span Register DAC A
Codes not shown are reserved–do not use
Table 2. Address Codes
A3 A2 A1 A0 n
000
×
DAC A
001
×
DAC B
010
×
DAC C
011
×
DAC D
111
×
All DACs (Note 1)
Codes not shown are reserved–do not use.
×
= Don’t Care.
Note 1. If readback is taken using the All DACs address, the LTC2754
defaults to DAC A.
Table 3. Span Codes
S3 S2 S1 S0 SPAN
×
0 0 0 Unipolar 0V to 5V
×
0 0 1 Unipolar 0V to 10V
×
0 1 0 Bipolar –5V to 5V
×
0 1 1 Bipolar –10V to 10V
×
1 0 0 Bipolar –2.5V to 2.5V
×
1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use.
×
= Don’t Care.
LTC2754
15
2754f
Readback in M-Span Confi guration
If the part is in M-Span confi guration and a DAC Span
register is specifi ed for readback, then the data shifted out
of SRO will refl ect the actual active span. The hardware-
confi gured output range is therefore software detectable
and available for use in programming.
Examples
1. Using a 24-bit instruction, load DAC A with the unipolar
range of 0V to 10V, output at zero volts and all other DACs
with the bipolar range of ±10V, outputs at zero volts. Note
all DAC outputs should change at the same time.
a) CS/LD↓
Clock SDI = 0010 1111 0000 0000 0000 0011
b) CS/LD↑
Input register- Range of all DACs set to bipolar
±10V.
c) CS/LD↓
Clock SDI = 0010 0000 0000 0000 0000 0001
d) CS/LD↑
Input register- Range of DAC A set to unipolar 0V
to 10V.
e) CS/LD↓
Clock SDI = 0011 1111 1000 0000 0000 0000
f) CS/LD↑
Input register- Code of all DACs set to midscale.
g) CS/LD↓
Clock SDI = 0011 0000 0000 0000 0000 0000
h) CS/LD↑
Input register- Code of DAC A set to zero code.
i) CS/LD↓
Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX
j) CS/LD↑
Update all DACs for both Code and Range.
k) Alternatively steps i and j could be replaced with
LDAC .
2. Using a 32-bit load sequence, load DAC C with bipolar
±2.5V and its output at zero volts. Use readback to check
Input register contents before updating the DAC output
(i.e., before copying Input register contents into DAC
register).
a) CS/LD↓ (Note that after power-on, the code in
Input register is zero)
Clock SDI = 0000 0000 0011 0100 1000 0000
0000 0000
b) CS/LD↑
Input register- Code of DAC C set to midscale
setting.
c) CS/LD↓
Clock SDI = 0000 0000 0010 0100 0000 0000
0000 0100
Data out on SRO = 1000 0000 0000 0000 Verifi es
that Input register- Code DAC C is at midscale
setting.
d) CS/LD↑
Input register- Range of DAC C set to Bipolar
±2.5V range.
e) CS/LD↓
Clock SDI = 0000 0000 1010 0100 xxxx xxxx
xxxx xxxx
Data Out on SRO = 0000 0000 0000 0100
Verifi es that Input register- range of DAC C set to
Bipolar ±2.5V Range.
CS/LD↑
f) CS/LD↓
Clock SDI = 0000 0000 0100 0100 xxxx xxxx
xxxx xxxx
g) CS/LD↑
Update DAC C for both Code and Range
h) Alternatively steps f and g could be replaced with
LDAC .
OPERATION
LTC2754
16
2754f
OPERATION
System Offset and Reference Adjustments
The LTC2754 has individual offset- and gain- adjust pins
(VOSADJX and GEADJX, respectively) for each of its four
DACs.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2754, which is so low as to be
dominated by external output amplifi er errors even when
using the most precise op amps.
The offset adjust pins VOSADJX can be used to null
unipolar offset or bipolar zero error. The offset-voltage
delta is inverted and attenuated such that a 5V control
voltage applied to VOSADJX produces ∆VOS = –512 LSB
(LTC2754-16) in any output range (assumes a 5V refer-
ence voltage at RINX).
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
∆VOS = –(1/128)VOSADJX [0V to 5V, ±2.5V spans]
∆VOS = –(1/64)VOSADJX [0V to 10V, ±5V, –2.5V to 7.5V
spans]
∆VOS = –(1/32)VOSADJX [±10V span]
The gain error adjust pins GEADJX can be used to null
gain error or to compensate for reference errors. Nominal
adjustment range is ±512 LSB (LTC2754-16) for a volt-
age input range of ±VRINX (i.e., ±5V for a 5V reference
input). The gain-error delta is non-inverting for positive
reference voltages.
Note that these pins compensate the gain by altering the
inverted reference voltage VREFX. In voltage terms, the VREFX
delta is inverted and attenuated by a factor of 128.
∆VREFX = –(1/128)GEADJX
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the performance of which the part is capable.
The VOSADJX pins have an input impedance of 1.28M.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling
performance of the LTC2754. They should be shorted to
GND if not used.
The GEADJX pins have an input impedance of 2.56M, and
are intended for use with fi xed reference voltages only.
They should be shorted to GND if not used. If the reference
inverting resistors are not used for that channel, then
GEADJX, RCOMX and RINX should all be shorted to REFX.
Power-On Reset and Clear
When power is fi rst applied to the LTC2754, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is confi gured for manual span operation, all four
DACs will be set into the pin-strapped range at the fi rst
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a fl ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
LTC2754
17
2754f
OPERATION
C2 C1 C0 A3 A2 A1 A0 D15
MSB
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LSB
C3
LTC2754-16
(WRITE CODE)
CONTROL WORD ADDRESS WORD 16-BIT CODE
SDI C2 C1 C0 A3 A2 A1 A0 D11
MSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
LSB
C3
LTC2754-12
(WRITE CODE)
CONTROL WORD ADDRESS WORD 12-BIT CODE 4 ZEROS
C2C1C0A3A2A1A00000 0000 0000S3S2S1S0C3
LTC2754-16
LTC2754-12
(WRITE SPAN)
CONTROL WORD ADDRESS WORD 12 ZEROS SPAN
2754 F02
Figure 2. Serial Input Write Sequence
LTC2754
18
2754f
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C300000000
CS/LD
SCK
SDI
CONTROL WORD ADDRESS WORD DAC CODE OR DAC SPAN
32-BIT DATA STREAM
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0000000000
SRO
t2
t3t4
t1
t9
D15
17
SCK
SDI
SRO D14D15
18
D14
8 ZEROS
Hi-Z
Hi-Z
READBACK CODE
2754 F04
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0000000000
SRO
READBACK SPAN
SPAN
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
CS/LD
SCK
SDI
SRO Hi-Z
Hi-Z
CONTROL WORD
READBACK CODE
0000000000000000000S3S2S1S00
SRO
READBACK SPAN
ADDRESS WORD DAC CODE OR DAC SPAN
24-BIT DATA STREAM
2754 F03
SPAN
Figure 3a. 24-Bit Instruction Sequence
Figure 3b. 32-Bit Instruction Sequence
OPERATION
LTC2754
19
2754f
OPERATION
SDI
SRO ...
WRITE DATA
DAC A
READ
INPUT DATA
REGISTER DAC A
WRITE DATA
DAC B
READ
INPUT DATA
REGISTER DAC B
WRITE DATA
DAC C
READ
INPUT DATA
REGISTER DAC C
WRITE DATA
DAC D
READ
INPUT DATA
REGISTER DAC D
UPDATE
ALL DACs
READ
DAC DATA
REGISTER DAC A
...
2754 F04
Figure 4. Rolling Readback
LTC2754
20
2754f
APPLICATIONS INFORMATION
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC2754-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 4 and 5 contain equations for evaluating the effects
of op amp parameters on the LTC2754’s accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipolar
gain error. Tables 4 and 5 can also be used to determine
the effects of op amp parameters on the LTC2754-12.
However, the results obtained from Tables 4 and 5 are
in 16-bit LSBs. Divide these results by 16 to obtain the
correct LSB sizing.
Table 6 contains a partial list of LTC precision op amps
recommended for use with the LTC2754. The easy-to-use
design equations simplify the selection of op amps to meet
Table 4. Coeffi cients for the Equations in Table 5
OUTPUT RANGE A1 A2 A3 A4 A5
5V 1.1 2 1 1
10V 2.2 3 0.5 1.5
±5V 2 2 1 1 1.5
±10V 4 4 0.83 1 2.5
±2.5V 1 1 1.4 1 1
–2.5V to 7.5V 1.9 3 0.7 0.5 1.5
A3 • VOS1 • 19.8 •
IB1 • 0.13 •
0
A4 • VOS2 • 13.1 •
A4 • IB2 • 0.13 •
A4 •
()
5V
VREF
()
5V
VREF
()
16.5k
AVOL1
OP AMP
VOS1 (mV)
IB1 (nA)
AVOL1 (V/V)
VOS2 (mV)
IB2 (mV)
AVOL2 (V/V)
VOS1 • 3.2 •
IB1 • 0.0003 •
A1 •
0
0
0
INL (LSB)
()
5V
VREF
()
5V
VREF
()
1.5k
AVOL1
()
66k
AVOL2
()
131k
AVOL1
()
131k
AVOL1
()
131k
AVOL2
()
131k
AVOL2
VOS1 • 0.82 •
IB1 • 0.00008 •
A2 •
0
0
0
DNL (LSB)
()
5V
VREF
()
5V
VREF
A3 • VOS1 • 13.2 •
IB1 • 0.13 •
0
0
0
0
UNIPOLAR
OFFSET (LSB)
()
5V
VREF
()
5V
VREF
()
5V
VREF
VOS1 • 13.2 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
BIPOLAR GAIN
ERROR (LSB)
()
5V
VREF
()
5V
VREF
()
()
()
5V
VREF
()
5V
VREF
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
()
5V
VREF
()
5V
VREF
()
5V
VREF
()
5V
VREF
()
5V
VREF
VOS1 • 13.2 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
Table 6. Partial List of LTC Precision Amplifi ers Recommended for Use with the LTC2754 with Relevant Specifi cations
AMPLIFIER
AMPLIFIER SPECIFICATIONS
VOS
μV
IB
nA
AVOL
V/mV
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/μs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with LTC2755
μs
POWER
DISSIPATION
mW
LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp
LTC2754
21
2754f
APPLICATIONS INFORMATION
the system’s specifi ed error budget. Select the amplifi er
from Table 6 and insert the specifi ed op amp parameters
in Table 5. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.
Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on INL and DNL. For
example, for the LTC2754-16 with a 5V reference in 5V
unipolar mode, a 250µV op amp offset will cause a 3.3LSB
zero-scale error and a 3.3LSB gain error; but only 0.8LSB
of INL degradation and 0.2LSB of DNL degradation.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, con-
sult an op amp’s data sheet to fi nd the worst-case VOS
and IB over temperature. Then, plug these numbers into
the VOS and IB equations from Table 5 and calculate the
temperature-induced effects.
For applications where fast settling time is important, Ap-
plication Note 74, “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time,” offers a thorough discus-
sion of 16-bit DAC settling time and op amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifi er
for use with the LTC2754 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2754
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
There are three primary error sources to consider
when selecting a precision voltage reference for 16-bit
applications: output voltage initial tolerance, output voltage
temperature coeffi cient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
A reference’s output voltage temperature coeffi cient af-
fects not only the full-scale error, but can also affect the
circuit’s apparent INL and DNL performance. If a refer-
ence is chosen with a loose output voltage temperature
coeffi cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient conditions.
Minimizing the error due to reference temperature coef-
fi cient can be achieved by choosing a precision reference
with a low output voltage temperature coeffi cient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2754 with Relevant Specifi cations
REFERENCE
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% 5ppm/°C 12µVP-P
LT1236A-5,
LT1236A-10
±0.05% 5ppm/°C 3µVP-P
LT1460A-5,
LT1460A-10
±0.075% 10ppm/°C 20µVP-P
LT1790A-2.5 ±0.05% 10ppm/°C 12µVP-P
LTC6652A-2.048 ±0.05% 5ppm/°C 2.1ppmP-P
LTC6652A-2.5 2.1ppmP-P
LTC6652A-3 2.1ppmP-P
LTC6652A-3.3 2.2ppmP-P
LTC6652A-4.096 2.3ppmP-P
LTC6652A-5 2.8ppmP-P
LTC2754
22
2754f
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise fl oor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practi-
cal for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, fi ltering the output of the reference
may be required to minimize output noise.
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. IOUT2X must be tied
to the star ground with as low a resistance as possible.
APPLICATIONS INFORMATION
When it is not possible to locate star ground close to
IOUT2, a low resistance trace should be used to route this
pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code-dependent current
fl owing to ground. When the resistance of this circuit
board trace becomes greater than 1, a force/sense am-
plifi er confi guration should be used to drive this pin (see
Figure 5). This preserves the excellent accuracy (1LSB
INL and DNL) of the LTC2754-16.
Layout
Figures 6, 7, 8, and 9 show the layout for the LTC2754
evaluation board, DC1546. This shows how to route the
digital signals around the device without interfering with
the reference and output op amps. Complete demo board
documentation is available in the DC1546 “Quick Start
Guide.”
LTC2754
23
2754f
Figure 5. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifi er.
APPLICATIONS INFORMATION
–
+
–
+
1/2 LT1469
1/2 LT1469
DAC A
LTC2754-16
VREF
5V
2
1
3
48
49
50
2
1
52
1
51
IOUT1A
15pF
IOUT2A
RFBA
VOSADJA
REFA
RCOMA
RINA
ROFSA
VOUTA
3
47
–
+
6
1
23
IOUT2
2
3
*SCHOTTKY BARRIER DIODE
ZETEX*
BAT54S
LT1001
2754 F05
1000pF
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
1
23
3, 12, 29, 38
–
+
LT1468
3
ZETEX
BAT54S
2
200
2007
IOUT2
150pF
3
2
DAC B
DAC C
DAC D
–
+
–
+
–
+
GEADJA
LTC2754
24
2754f
APPLICATIONS INFORMATION
Figure 6. LTC2754 Evaluation Board DC1546. Layer 1, Top Layer (Component Side)
Figure 7. LTC2754 Evaluation Board DC1546. Layer 2, GND Plane
2754 F07
2754 F06
LTC2754
25
2754f
Figure 8. LTC2754 Evaluation Board DC1546. Layer 3, Power Traces
Figure 9. LTC2754 Evaluation Board DC1546. Layer 4, Bottom Layer (Solder Side)
APPLICATIONS INFORMATION
2754 F08
2754 F09
LTC2754
26
2754f
TYPICAL APPLICATION
Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply
TO LT1991
TO LT1991
GEADJA GEADJB GEADJC GEADJD GND
1
GND GND GND SROGND
RINA
2
RFBA
49
ROFSA
REFA
5051
REFB
42
RCOMA
52
RFBB
44
ROFSB
43
RINC RIND RFBC ROFSD RFBD
VOSADJD
IOUT2D
RCOMC RCOMD ROFSC
REFC REFD
40
450k
V+
V–
OUT 6
7
5
4
LT1991
REF
4µF
27
TO LT1991s
14 4 11 37 53 28
5V
26 13 15 25 24 23 16 17 18
20
12
27pF
LT1469
TO LT1991
V+
V–
IOUT1D 19
9
+
–
150pF
150pF
IOUT2C 29
VOSADJC 21
27pF
LT1469
1
8
2
3
6
5
4
VOUTA
2754 TA02
VOUTC
VOUTB
VOUTD
LT1469
V+
V–
+
–
87
2
3
4
LT1469
V+
V–
+
–
+
–
8
2
3
4
4
87
2
3
4
87
6
5
4
87
V+
V–
IOUT1C 22
+
–
IOUT2B 38
VOSADJB 46
27pF
V+
V–
IOUT1B 45
+
–
IOUT2A 3
VOSADJA 47
27pF
V+
V–
IOUT1A
RFLAG
CLR 48
+
–
150pF
V–
V+
+
–
81
2
3
4
V+
V–
+
–
87
6
5
4
150pF
RRCOMB
LTC2754
41
RINB
39
VDD
SDI
CS/LD
5V
10
30
31
5
6
SCK
7
SRO
2
3
4
5
12
13
14
15
7
8
9
10
6
8
M-SPAN
32
S2
35
S1
34
S0
33
LDAC
36
10k
LT1236-5
IN OUT
TRIM
GND
4
62
V+
510µF
0.1µF
T0
ADDITIONAL
OFFSET ADJUST
CIRCUITS
T0
ADDITIONAL
GAIN ADJUST
CIRCUITS
0.1µF
10k
CS1
SDI
SCK
SDO
CS2
0.1µF10µF
10k10k
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
CS/LD
SCK
SDI
CLR
LDAC
VCC
REF
LTC2636
16
GND
111
5V
4µF
450k
450k
150k
50k
M9
M3
M1
50k
450k
150k
P1
P3
P9
8
9
10
1
2
3
450k
V+
V–
OUT 6
7
5
4
LT1991
REF
4µF
+
–
4µF
450k
450k
150k
50k
M9
M3
M1
50k
450k
150k
P1
P3
P9
8
9
10
1
2
3
LTC2754
27
2754f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.00 p 0.10
(2 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45oC
CHAMFER
0.40 p 0.10
5251
1
2
BOTTOM VIEW—EXPOSED PAD
TOP VIEW
SIDE VIEW
6.50 REF
(2 SIDES)
8.00 p 0.10
(2 SIDES)
5.50 REF
(2 SIDES)
0.75 p 0.05
0.75 p 0.05
R = 0.115
TYP
R = 0.10
TYP 0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
6.45 p0.10
5.41 p0.10
0.00 – 0.05
(UKG52) QFN REV Ø 0306
5.50 REF
(2 SIDES)
5.41 p0.05
6.45 p0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
6.10 p0.05
7.50 p0.05
6.50 REF
(2 SIDES) 7.10 p0.05 8.50 p0.05
0.25 p0.05
0.50 BSC
PACKAGE OUTLINE
PACKAGE DESCRIPTION
LTC2754
28
2754f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
LT 0609 • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1469 Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate
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