fax id: 7050 CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 16-Bit Latch Features * Low power, pin-compatible replacement for LCX, LPT, LVC, LVCH & LVT families * 5V tolerant inputs and outputs* * 6 mA & 24 mA balanced drive outputs * Power-off disable outputs permits live insertion * Edge-rate control circuitry for reduced noise * FCT-C speed at 4.2 ns * Latch-up performance exceeds JEDEC standard no. 17 * Typical output skew < 250 ps * Industrial temperature range of -40C to +85C * TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) * Typical Volp (ground bounce) performance exceeds Mil Std 883D * VCC = 2.7V to 3.6V * ESD (HBM) > 2000V CY74FCT163H373 * Bus hold on data inputs * Eliminates the need for external pull-up or pull-down resistors * *Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels CY74FCT163LD2373 * Lite DriveTM option for low noise applications * 6 mA balanced drive outputs * FCT-A speed at 5.2 ns * VCC = 3.0V to 3.6V * ESD (HBM) > 1100V Functional Description These devices are 16-bit, D-type latches, designed for use in bus applications requiring high speed and low power. They can either be used as two independent 8-bit latches, or as a single 16-bit latch by connecting the Output Enable (OE) and Latch (LE) inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce. Flow-through pinout and small shrink packaging aid in simplifying board layout. The CY74FCT163H373 and CY74FCT163LDH373 have "bus hold" on the data inputs, which retain the input's last state whenever the source driving the input goes to high impedance. This eliminates the need for pullup/down resistors and prevents floating inputs. The CY74FCT163373 and the CY74FCT163LD373 are designed with inputs and outputs capable of being driven by 5.0 V buses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power off disable feature enabling them to be used in applications requiring live insertion. Logic Block Diagrams CY74FCT163373, CY74FCT163H373, CY74FCT163LD373, CY74FCT163LDH373 1OE 1 LE 1D 1 D 1O1 C TO 7 OTHER CHANNELS 2 OE 2 LE 2D 1 D 2 O1 C TO 7 OTHER CHANNELS Pin Configuration SSOP/TSSOP Top View 1 OE 1 48 1 LE 1 O1 2 47 1 D1 1 O2 3 46 1 D2 GND 4 45 GND 1 O3 5 44 1 D3 1 O4 6 43 1 D4 VCC 1 O5 7 42 8 41 VCC 1 D5 1 O6 9 40 1 D6 GND 10 39 GND 1 O7 11 38 1 D7 1 O8 37 36 1 D8 2 O1 12 13 2 O2 14 35 2 D2 GND 15 34 GND 2 O3 16 33 2 D3 2 O4 17 32 2 D4 VCC 2 O5 18 31 19 30 VCC 2 D5 2 D1 2 O6 20 29 2 D6 GND 21 28 GND 2 O7 22 27 2 D7 2 O8 23 26 2 D8 2 OE 24 25 2 LE Lite Drive is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 March 19, 1997 - Revised April 20, 1998 CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Maximum Ratings[3, 4] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description [1] D Data Inputs LE Latch Enable Inputs (Active HIGH) OE Output Enable Inputs (Active LOW) Ambient Temperature with Power Applied.................................................. -55C to +125C O Three-State Outputs Supply Voltage Range ......................................0.5V to +4.6V Storage Temperature...................................... -55C to +125C DC Input Voltage ................................................. -0.5V to +7.0V Function Table[2] DC Output Voltage .............................................. -0.5V to +7.0V Inputs DC Output Current (Maximum Sink Current/Pin) ........................... -60 to +120 mA Outputs D LE OE O H H L H L H L L X L L Q0 X X H Z Power Dissipation .......................................................... 1.0W Operating Range Range Industrial Ambient Temperature VCC -40C to +85C 2.7V to3.6V Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage All Inputs VIL Input LOW Voltage VH Input Hysteresis[6] VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA IIH Input HIGH Current IIL Min. Typ.[5] 2.0 Max. Unit 5.5 V 0.8 100 -0.7 V mV -1.2 V VCC=Max., VI=5.5 1 A Input LOW Current VCC=Max., VI=GND 1 A IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V 1 A IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND 1 A IOS Short Circuit Current[7] VCC=Max., VOUT=GND -240 mA IOFF Power-Off Disable VCC=0V, VOUT4.5V 100 A ICC Quiescent Power Supply Current VIN0.2V, VIN>VCC-0.2V VCC=Max. 0.1 10 A ICC Quiescent Power Supply Current (TTL inputs HIGH) VIN=VCC-0.6V[8] VCC=Max. 2.0 30 A -60 -135 Note: 1. On the CY74FCT163H373 & CY74FCT163LDH373 these pins have "bus hold. 2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. Z = High Impedance. Q0=Previous state of flip-flop. 3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 5. Typical values are at VCC=3.3V, TA = +25C ambient. 6. This parameter is guaranteed but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 8. Per TTL driven input; all other inputs at VCC or GND. 2 CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage VIL Input LOW Voltage VH Input Hysteresis[6] VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA IIH Input HIGH Current VCC=Max., VI=VCC IIL Input LOW Current IBBH IBBL All Inputs Min. Typ.[5] 2.0 Max. Unit VCC V 0.8 100 [9] Bus Hold Sustain Current on Bus Hold Input VCC=Min. -0.7 V mV - 1.2 V 100 A 100 A VI=2.0V -50 A VI=0.8V +50 A 500 A VCC=Max., VOUT=VCC 1 A High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND 1 A IOS Short Circuit Current[7] VCC=Max., VOUT=GND -240 mA IOFF Power-Off Disable VCC=0V, VOUT4.5V 100 A ICC Quiescent Power Supply Current VIN0.2V, VIN>VCC-0.2V VCC=Max. +40 A ICC Quiescent Power supply Current (TTL inputs HIGH) VIN=VCC-0.6V[8] VCC=Max. +350 A IBHHO IBHLO Bus Hold Overdrive Current on Bus Hold Input IOZH High Impedance Output Current (Three-State Output pins) IOZL [9] VCC=Max., VI=1.5V -60 -135 Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description [7] Test Conditions Min. IODL Output LOW Dynamic Current VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 IODH Output HIGH Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V -45 VOH Output HIGH Voltage VCC=Min., IOH= -0.1 mA VOL Output LOW Voltage Typ.[5] - Max. Unit 180 mA -180 mA VCC-0.2 V VCC=Min., IOH= -8 mA 2.4[10] 3.0 VCC=3.0V, IOH= -24 mA 2.0 3.0 VCC=Min., IOL= 0.1mA V V 0.2 VCC=Min., IOL= 24 mA 0.3 V 0.55 Electrical Characteristics For Lite Drive Devices Over the Operating Range VCC=3.0V to 3.6V Parameter Description Test Conditions Max. Unit Output LOW Dynamic Current VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 15.0 45 mA IODH Output HIGH Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V -15.0 -45 mA VOH Output HIGH Voltage VCC=3.0 V, IOH= -6 mA VOL Output LOW Voltage VCC=3.0 V, IOL= 6 mA Notes: 9. Pins with bus hold are described in Pin Description. 10. VOH=VCC-0.6 V at rated current. 3 Min. Typ.[5] IODL [7] 2.4 3.0 V 0.55 V CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Capacitance[6](TA = +25C, f = 1.0 MHz) Parameter Description Test Conditions Typ.[5] Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Power Supply Characteristics Parameter Description Test Conditions Typ.[5] Max. Unit ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, VIN=GND Outputs Open, OE=GND 50 75 A/MHz IC Total Power Supply Current[12] VCC=Max., f1=10 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, One VIN=GND Bit Toggling, OE=GND VIN=VCC-0.6V or VIN=GND 0.5 0.8 mA 0.5 0.8 mA VCC=Max., f1=2.5 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, Six- VIN=GND teen Bits Toggling, OE=GND VIN=VCC-0.6V or VIN=GND 2.0 3.0[13] mA 2.0 3.3[13] mA Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15] CY74FCT163373A CY74FCT163H373A CY74FCT163373C CY74FCT163H373C Description Min. Max. Min. Max. Unit Fig. No.[16] tPLH tPHL Propagation Delay D to Q Output 1.5 4.8 1.5 4.1 ns 1, 3 tPLH tPHL Propagation Delay LE to Q Output 2.0 8.0 2.0 5.5 ns 1, 5 tPZH tPZL Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSU Input Setup time 2.0 - 2.0 - ns 1, 4 tH Input Hold time 1.5 - 1.5 - ns 1, 4 0.5 ns -- Parameter tSK(O) Output Skew [17] 0.5 Notes: 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + I INPUTS + I DYNAMIC 12. IC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 14. Minimum limits are guaranteed but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See "Parameter Measurement Information" in the General Information section. 17. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4 CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V [14,15] CY74FCT163LD373[18] CY74FCT163LDH373 Parameter Description Min. CY74FCT163LD373A[18] CY74FCT163LDH373A Max. Min. Max. Unit Fig. No.[16] 1.5 4.8 ns 1, 3 8.0 ns 1. 3 tPLH tPHL Propagation Delay Clock to Q Output 8 tPLH tPHL Propagation Delay LE to Q Output 13 tPZH tPZL Output Enable Time 12 1.5 6.2 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 7.5 1.5 5.6 ns 1, 7, 8 tSU Input Setup time 2.0 - 2.0 ns 1, 4 tH Input Hold time 1.5 - 1.5 ns 1, 4 ns -- tSK(O) Output Skew [17] 0.5 0.5 Note: 18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF. Ordering Information CY74FCT163373 Speed (ns) 4.2 5.2 Ordering Code Package Name Package Type CY74FCT163373CPAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163373CPVC O48 48-Lead (300-Mil) SSOP CY74FCT163373APAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163373APVC O48 48-Lead (300-Mil) SSOP Operating Range Industrial Industrial Ordering Information CY74FCT163H373 Speed (ns) 4.2 5.2 Ordering Code Package Name Package Type CY74FCT163H373CPAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163H373CPVC O48 48-Lead (300-Mil) SSOP CY74FCT163H373APAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163H373APVC O48 48-Lead (300-Mil) SSOP Operating Range Industrial Industrial Ordering Information CY74FCT163LD373 Speed (ns) 5.2 8.0 Ordering Code Package Name Package Type CY74FCT163LD373APAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163LD373APVC O48 48-Lead (300-Mil) SSOP CY74FCT163LD373PAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163LD373PVC O48 48-Lead (300-Mil) SSOP 5 Operating Range Industrial Industrial CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Ordering Information CY74FCT163LDH373 Speed (ns) Ordering Code Package Name Package Type 5.2 CY74FCT163LDH373APAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163LDH373APVC O48 48-Lead (300-Mil) SSOP 8.0 CY74FCT163LDH373PAC Z48 48-Lead (240-Mil) TSSOP CY74FCT163LDH373PVC O48 48-Lead (300-Mil) SSOP Document #: 38-00580-A Package Diagrams 48-Lead Shrunk Small Outline Package O48 6 Operating Range Industrial Industrial : CY74FCT163373 CY74FCT163H373 CY74FCT163LD373 CY74FCT163LDH373 Package Diagrams (continued) 48-Lead Thin Shrunk Small Outline Package Z48 (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.