CY74FCT163LD373APAC - Cypress Semiconductor

16-Bit Latc h

ax id: 7050

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

March 19

1997 - Revised April 20

1998

Features

• Low power, pin-compat ible replacement for LCX, LPT,

LVC, LVCH & LVT famil ies

• 5V toler ant inputs and outpu ts*

• 6 mA & 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control cir cuitry for red uced noise

• FCT-C speed at 4.2 ns

• Latc h-up perf orman ce exce eds JEDEC standard no. 17

• Typical output skew < 250 ps

• Industrial tem perature range of –40°C to +85°C

• TSSOP (19.6 -mil pit ch) or SSOP (25- mil pitc h)

• Typical Volp (ground bounce) performance exceeds Mil

Std 883D

•V

CC = 2.7V to 3.6V

• ESD (HBM) > 2000V

CY74FCT163H373

• Bus hold on data inputs

• Eliminates the need for external pull-up or pul l- down

resistors

• *Dev ices with bus hol d are not rec ommended for trans-

lating rail-to-rail CMOS signal s to 3.3V logi c levels

CY74FCT163LD2373

• Lite Drive™ option for low noise applications

• 6 mA balanced drive outputs

• FCT-A speed at 5.2 ns

•V

CC = 3.0V to 3.6V

• ESD (HBM) > 1100V

Functional Descripti on

These devices are 16-bit, D-type latches, designed for use in

bus applications requiring high speed and low power. They can

eithe r be used as two independe nt 8-bi t lat ches, or as a si ngle

16-bit latch by connecting the Output Enable (OE ) and Latch

(LE) inputs. The outputs are 24-mA balanced output drivers

with current limiting resistors to reduce the need for external

terminating resistors and provide for minimal undershoot and

reduced g round bounce. Flow-throug h pino ut and small shrink

packaging aid in simplifying board layout.

The CY74FCT163H373 and CY74FCT163LDH373 have “bus

hold” on the data inputs, which retain the input’s last state

whenever the source driving the input goes to high impedance.

This eliminates the need for pullup/down resistors and pre-

vents float ing inputs .

The CY74FCT163373 and the CY74FCT163LD373 are

designed with inputs and outputs capable of being driven by

5.0 V buses, allowing them to be used in mixed voltage

systems as translators. The outputs are also designed with a

power off disable feature enabling them to be used in

appli cations requiring live insertion.

Lite Drive is a tradem ark of Cypress Semiconductor Corporation.

Logic Block Diagrams CY74FCT163373, CY74FCT163H373, Pin Configuration

1OE

1LE

1D11O1

TO 7 OTHERCHANNELS

2OE

2LE

2D12O1

GND

1OE

SSOP/TSSOP

Top View

1O1

1O2

1O3

1O4

1D1

1D2

1D3

1D4

1LE

GND

VCC

1O7

1O8

1O5

1O6

1D5

1D6

1D7

1D8

VCC

GND

2O3

2O4

2O1

2O2

2D1

2D2

2D3

2D4

GND

VCC

2O7

2O8

2O5

2O6

2D5

2D6

2D7

2D8

VCC

GND

2OE 2LE

TO 7 OTHERCHANNELS

CY74FCT163LD373, CY74FCT163LDH373

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user

guidelines, not tested.)

Storage Temperature...................................... −55°C to +125°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage Range......................................0.5V to +4.6V

DC Input Vo ltage.................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current /Pi n)...........................−60 to +120 mA

Power Dissipation.......................................................... 1.0W

Pin Description

Name Description

DData Input s[1]

LE Latch Enable Input s (Active HIGH)

OE Output Enable Inputs (Active LOW)

OThree-State Outputs

Function Table[2]

Inputs Outputs

DLE OE O

H H L H

L H L L

X L L Q0

X X H Z

Operating Range

Range Ambient

Temperature VCC

Industrial −40°C to +85°C 2.7V to3.6V

Electric al Characteristics for Non Bus Hold Devices Over the Operating Range V CC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Vo ltage All In p ut s 2.0 5.5 V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

IIH Input HIGH Current VCC=Max., VI=5.5 ±1µA

IIL Input LOW Current VCC=Max., VI=GND ±1µA

IOZH High Impedance Output Cur rent

(Three-State Output pins) VCC=Max., VOUT=5.5V ±1µA

IOZL High Impedance Output Cur rent

(Three-State Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Cir cuit Curren t[7] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power-Off Disabl e VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN≤0.2V,

VIN>VCC–0.2V VCC=Max. 0.1 10 µA

∆ICC Quiescent Power Supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. 2.0 30 µA

Note:

1. On the CY74FCT163H373 & CY74FCT163LDH373 these pins have “bus hold.

2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop.

3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature

range.

4. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5. Typical values are at VCC=3.3V, TA = +25°C ambient.

6. This parameter is guaranteed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferabl e in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, IOS tests should be performed last.

8. Per TTL driven input; all other inputs at VCC or GND.

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Vo ltage All In puts 2.0 VCC V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 – 1.2 V

IIH Input HIGH Current VCC=Max., VI=VCC ±100 µA

IIL Input LOW Current ±100 µA

IBBH

IBBL Bus Hold Sustain Curr ent on Bus Hold Input [9] VCC=Min. VI=2.0V –50 µA

VI=0.8V +50 µA

IBHHO

IBHLO Bus Hold Overdriv e Current on Bus Hold Input[9] VCC=Max., VI=1.5V ±500 µA

IOZH High Impedance Output Cur rent

(Three-State Output pins) VCC=Max., VOUT=VCC ±1µA

IOZL High Impedance Output Cur rent

(Three-State Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Cir cuit Curren t[7] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power-Off Disabl e VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN≤0.2V,

VIN>VCC–0.2V VCC=Max. +40 µA

∆ICC Quiesce nt Power supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. +350 µA

Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V 45 180 mA

IODH Output HIGH Dynamic Curren t[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V –45 ––180 mA

VOH Output HIGH Voltage VCC=M i n ., I OH= –0.1 mA VCC–0.2 V

VCC=Mi n ., IOH= –8 mA 2.4[10] 3.0 V

VCC=3.0V, IOH= –24 mA 2.0 3.0 V

VOL Output LOW Voltage VCC=Mi n ., IOL= 0.1mA 0.2 V

VCC=Mi n ., IOL= 24 mA 0.3 0.55

Electrical Characteristics For Lite Drive Devices Over the Op erating Range VCC=3.0V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V 15.0 45 mA

IODH Output HIGH Dynamic Curren t[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V –15.0 –45 mA

VOH Output HIGH Voltage VCC=3.0 V, IOH= –6 mA 2.4 3.0 V

VOL Output LOW Voltage VCC=3.0 V, IOL= 6 mA 0.55 V

Notes:

9. Pins with bus hold are described in Pin Description.

10. VOH=VCC–0.6 V at rated current.

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Capacitance[6](TA = +25°C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.[5] Max. Unit

CIN Input Capacitanc e VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT = 0V 5.5 8.0 pF

Pow er Supply Characteri stic s

Parameter Description Test Conditi ons Typ.[5] Max. Unit

ICCD Dyna mic Power Supply

Current[11] VCC=Max., O ne Input Toggling,

50% Duty Cycle,

Outputs Open, OE=GND

VIN=VCC or

VIN=GND 50 75 µA/MHz

ICTotal Pow e r S u p ply

Current[12] VCC=Max., f1=10 MHz, 50%

Duty Cycle, Out puts Ope n, One

Bit Toggling, OE=GND

VIN=VCC or

VIN=GND 0.5 0.8 mA

VIN=VCC–0 .6V or

VIN=GND 0.5 0.8 mA

VCC=Max., f1=2.5 MHz, 50%

Duty Cycle, Outputs Open, Six-

teen Bits Toggling, OE=GND

VIN=VCC or

VIN=GND 2.0 3.0[13] mA

VIN=VCC–0 .6V or

VIN=GND 2.0 3.3[13] mA

Swi tch i ng C h ara cter i sti cs Over the Operating Range VCC=3.0V to 3.6V[14,15]

Parameter Description

CY74FCT163373A

CY74FCT163H373A CY74FCT163373C

CY74FCT163H373C

Min. Max. Min. Max. Unit Fig. No.[16]

tPLH

tPHL Propagation Delay D to Q

Output 1.5 4.8 1.5 4.1 ns 1, 3

tPLH

tPHL Propagat ion De la y L E t o Q

Output 2.0 8.0 2.0 5.5 ns 1, 5

tPZH

tPZL Output Enabl e Time 1.5 6.2 1.5 5.8 ns 1, 7, 8

tPHZ

tPLZ Output Disabl e T i m e 1.5 5.6 1.5 5.2 ns 1, 7, 8

tSU Input Se tup time 2.0 -2.0 -ns 1, 4

tHInput Ho ld time 1.5 -1.5 -ns 1, 4

tSK(O) Output Skew[17] 0.5 0.5 ns —

Notes:

11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

12. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input lev e ls

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

14. Minimum limits are guaranteed but not tested on Propagation Delays.

15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.

16. See “Parameter Measurement Information” in the General Information section.

17. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Swi tch i ng C h ara cter i sti cs Over the Operating Range VCC=3.0V to 3.6V [14,15]

Parameter Description

CY74FCT163LD373[18]

CY74FCT163LDH373 CY74FCT163LD373A[18]

CY74FCT163LDH373A

Min. Max. Min. Max. Unit Fig. No. [16]

tPLH

tPHL Propagation Delay Clock to

Q Output 81.54.8ns 1, 3

tPLH

tPHL Propagat ion De la y L E t o Q

Output 13 8.0 ns 1. 3

tPZH

tPZL Output Enable Time 12 1.5 6.2 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time 7.5 1.5 5.6 ns 1, 7, 8

tSU Input Setup time 2.0 - 2.0 ns 1, 4

tHInput Ho ld time 1. 5 - 1.5 ns 1, 4

tSK(O) Output Skew[17] 0.5 0.5 ns —

Note:

18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF.

Ordering Information CY74FCT163373

Speed

(ns) Ordering Code Package

Name Package Ty pe Operating

Range

4.2 CY74FCT163373CPAC Z48 48-Lead (240-Mi l) TSSOP Industrial

CY74FCT163373CPVC O48 48-Lead (300-Mil) SSOP

5.2 CY74FCT163373APA C Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163373APVC O48 48-Lead (300-Mi l) SSOP

Ordering Information CY74FCT163H373

Speed

(ns) Ordering Code Package

Name P ac kage Type Operating

Range

4.2 CY74FCT163H373CPAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163H373CPVC O48 48-Lead (300-Mil) SSOP

5.2 CY74FCT163H373APA C Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163H373APVC O48 48-Lead (300-Mil) SSOP

Ordering Information CY74FCT163LD373

Speed

(ns) Ordering Code Package

Name Package Ty pe Operating

Range

5.2 CY74FCT16 3LD373APAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163LD373APVC O48 48-Lead (30 0-Mi l) SSOP

8.0 CY74FCT16 3LD373PAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163LD373PVC O48 48-Lead (300-Mil ) SSOP

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

Document #: 38-00580-A

Ordering Information CY74FCT163LDH373

Speed

(ns) Ordering Code Package

Name Package Ty pe Operating

Range

5.2 CY74FCT16 3LDH373APAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163LDH373APVC O48 48-Lead (30 0-Mi l) SSOP

8.0 CY74FCT16 3LDH373PAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163LDH373PVC O48 48-Lead (300-Mil ) SSOP

Package Di ag ra ms

48-Lead Shrunk Small Outline Package O48

CY74FCT163373

CY74FCT163H373

CY74FCT163LD373

CY74FCT163LDH373

of any circui try other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any l icense under patent or other rights. Cypress Semi conductor does not author ize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag ra ms (continued)

48-Lead Thin Shrunk Small Outline PackageZ48