DC894C-C - Linear Technology

LT3825

3825fe

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Isolated No-Opto

Synchronous Flyback Controller

with Wide Input Supply Range

n Isolated Medium Power (10W to 60W) Supplies

n Isolated Telecom, Medical Converters

n Instrumentation Power Supplies

n Isolated Power over Ethernet Supplies

48V to 3.3V at 12A Isolated Supply

Efficiency

n Senses Output Voltage Directly from Primary Side

Winding—No Opto-Isolator Required

n Synchronous Driver for High Efficiency

n Input Voltage Limited Only by External

Power Components

n Accurate Output Regulation without User Trims

n Switching Frequency from 50kHz to 250kHz

n Synchronizable

n Load Compensation

n Programmable Undervoltage Lockout

n Available in a Thermally Enhanced 16-Lead

TSSOP Package

The LT

3825 is an isolated switching regulator controller

designed for medium power flyback topologies. A typical

application is 10W to 60W with input voltage limited only

by external power path components. A third transformer

winding provides output voltage feedback.

The LT3825 is a current mode controller that regulates

output voltage based on sensing secondary voltage via a

transformer winding during flyback. This allows for tight

output regulation without the use of an opto-isolator,

improving dynamic response and reliability. Synchronous

rectification increases converter efficiency and improves

output cross regulation in multiple output converters.

The LT3825 operates in forced continuous conduction

mode which improves cross regulation in multiple winding

applications. Switching frequency is user programmable

and can be externally synchronized. The part also has load

compensation, undervoltage lockout and soft-start circuity.

LOAD CURRENT (A)

EFFICIENCY (%)

379

3825 TA01b

611 12

458 10

36VIN 48VIN

72VIN

Regulation

LOAD CURRENT (A)

3.13

OUTPUT (V)

3.18

3.28

3.33

3.38

3.43

379

3825 TA01c

3.23

611 12

458 10

36VIN

48VIN

72VIN

100k12k

3.01k

28.7k

402k

20Ω

47Ω

47k 20Ω

•

100pF 470µF

×4

VOUT+

3.3V

12A

VIN+

36V TO 72V

0.02Ω

47µF

15k

2.1k 150k 0.22µF

100k

10k

15Ω

330Ω

47pF

2.2µF

0.1µF

10nF

2.2nF

0.1µF

3825 TA01a

1µF

×2

tON SYNC

PGDLY

UVLO

SENSE–

SENSE+

RCMP ENDLY OSC

LT3825

GND SFST

•

VCC SG

CCMP

L, LT , LT C , LT M , Burst Mode, SwitcherCAD, Linear Technology and the Linear logo are registered

trademarks and No RSENSE, ThinSOT are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents, including

6948466, 5841643.

LT3825

3525fe

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

VCC to GND

Low Impedance Source ........................ –0.3V to 18V

Current Fed

(VCC Has Internal 19.5V Clamp) ...........30mA Into VCC

UVLO, SYNC Pin Voltage ........................... –0.3V to VCC

SENSE–, SENSE+ Pin Voltage ......................–0.5V, +0.5V

FB Pin Current ........................................................±2mA

VC Pin Current ....................................................... ±1mA

Operating Junction Temperature Range

(Notes 2, 3, 4) ........................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Note 1)

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.5V, VSENSE– = 0V; RCMP = 1k,

RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified (Note 3).

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

VCC

tON

ENDLY

SYNC

SFST

OSC

PGDLY

RCMP

CCMP

SENSE+

SENSE–

UVLO

GND

TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

VCC Turn-On Voltage l14.0 15.3 16.0 V

VCC Turn-Off Voltage l8 9.7 11 V

VCC Hysteresis VCC(ON) – VCC(OFF) l4.0 5.6 6.5 V

VCC Shunt Clamp VUVLO = 0V, IVCC = 15mA l19.5 20.5 V

VCC Supply Current (Note 5) (ICC) VC = Open l4 6.4 10 mA

VCC Start-Up Current VCC = 10V l180 400 µA

Feedback Amplifier

Feedback Regulation Voltage (VFB)l1.220 1.237 1.251 V

Feedback Pin Input Bias Current RCMP Open 200 nA

Feedback Amplifier Transconductance ∆IC = ±10µA l700 1000 1400 µmho

Feedback Amplifier Source or Sink Current l25 55 90 µA

Feedback Amplifier Clamp Voltage VFB = 0.9V

VFB = 1.4V

2.56 V

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3825EFE#PBF LT3825EFE#TRPBF 3825EFE 16-Lead Plastic 4.4mm TSSOP –40°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3825EFE LT3825EFE#TR 3825EFE 16-Lead Plastic 4.4mm TSSOP –40°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LT3825

3825fe

PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Voltage Line Regulation 12V ≤ VCC ≤ 18V l0.005 0.02 %/V

Feedback Amplifier Voltage Gain VC = 1.2V to 1.7V 1400 V/V

Soft-Start Charging Current VSFST = 1.5V 16 20 25 µA

Soft-Start Discharge Current VSFST = 1.5V, VUVLO = 0V 0.8 1.3 mA

Control Pin Threshold (VC) Duty Cycle = Min 1.0 V

Gate Outputs

PG, SG Output High Level l6.6 7.4 8.0 V

PG, SG Output Low Level l0.01 0.05 V

PG, SG Output Shutdown Strength VUVLO = 0V; IPG, ISG = 20mA l1.6 2.3 V

PG Rise Time CPG = 1nF 11 ns

SG Rise Time CSG = 1nF 15 ns

PG, SG Fall Time CPG, CSG = 1nF 10 ns

Current Amplifier

Switch Current Limit at Maximum VCVSENSE+ l88 98 110 mV

∆VSENSE/∆VC0.07 V/V

Sense Voltage Overcurrent Fault Voltage VSENSE+l206 230 mV

Timing

Switching Frequency (fOSC) COSC = 100pF l84 100 110 kHz

Oscillator Capacitor Value (COSC) (Note 6) 33 200 pF

Minimum Switch On-Time (tON(MIN)) 200 ns

Flyback Enable Delay Time (tED) 265 ns

PG Turn-On Delay Time (tPGDLY) 200 ns

Maximum Switch Duty Cycle l85 88 %

SYNC Pin Threshold l1.53 2.1 V

SYNC Pin Input Resistance 40 kΩ

Load Compensation

Load Comp to VSENSE Offset Voltage VRCMP with VSENSE+ = 0V 1 mV

Feedback Pin Load Compensation Current VSENSE+ = 20mV, VFB = 1.230V 20 µA

UVLO Function

UVLO Pin Threshold (VUVLO)l1.215 1.240 1.265 V

UVLO Pin Bias Current VUVLO = 1.2V

VUVLO = 1.3V

–0.25

–4.50

–3.4

±0.25

–2.50

µA

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.5V, VSENSE– = 0V; RCMP = 1k,

RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified (Note 3).

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: The LT3825 is tested under pulsed load conditions, such that TJ

≈

TA.

The LT3825E is guaranteed to meet performance specifications from 0°C to

125°C. Specifications over the –40°C to 125°C operating junction temperature

range are assured by design, characterization and correlation with statistical

process controls. Note that the maximum ambient temperature consistent

with these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and other

environmental factors.

Note 4: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formula:

TJ = TA + (PD • 40°C/W)

Note 5: Supply current does not include gate charge current to the

MOSFETs. See Applications Information.

Note 6: Component value range guaranteed by design.

LT3825

3525fe

TYPICAL PERFORMANCE CHARACTERISTICS

VCC(0N) and VCC(OFF)

vs Temperature

VCC Start-Up Current

vs Temperature VCC Current vs Temperature

SENSE Voltage vs Temperature

SENSE Fault Voltage

vs Temperature

Oscillator Frequency

vs Temperature

VFB vs Temperature

Feedback Pin Input Bias

vs Temperature VFB Reset vs Temperature

TEMPERATURE (°C)

–50

VCC (V)

3825 G01

–25 0 50

75 100 125

VCC(ON)

VCC(OFF)

TEMPERATURE (°C)

–50

IVCC (µA)

200

250

300

25 75

3825 G02

150

100

–25 0 50 100 125

TEMPERATURE (°C)

–50

25 75

3825 G03

–25 0 50 100 125

IVCC (mA)

DYNAMIC CURRENT CPG = 1nF,

CSG = 1nF, fOSC = 100kHz

STATIC PART CURRENT

VCC = 14V

TEMPERATURE (°C)

–50

SENSE VOLTAGE (mV)

100

110

104

050 75

3825 G04

106

108

102

–25 25 100 125

FB = 1.1V

SENSE = VSENSE+

WITH VSENSE– = 0V

TEMPERATURE (°C)

–50

SENSE VOLTAGE (mV)

215

3825 G05

200

190

–25 0 50

185

180

220

210

205

195

75 100 125

SENSE = VSENSE+

WITH VSENSE– = 0V

TEMPERATURE (°C)

–50

fOSC (kHz)

100

110

104

050 75

3825 G06

106

108

102

–25 25 100 125

COSC = 100pF

TEMPERATURE (°C)

–50

1.230

VFB (V)

1.231

1.233

1.234

1.235

1.240

1.237

050 75

3825 G07

1.232

1.238

1.239

1.236

–25 25 100 125

TEMPERATURE (°C)

–50

FEEDBACK PIN INPUT BIAS (nA)

200

250

300

25 75

3825 G08

150

100

–25 0 50 100 125

RCMP OPEN

TEMPERATURE (°C)

–50

VFB RESET (V)

1.03

3825 G09

1.00

0.98

–25 0 50

0.97

0.96

1.04

1.02

1.01

0.99

75 100 125

LT3825

3825fe

TYPICAL PERFORMANCE CHARACTERISTICS

Feedback Amplifier Output

Current vs VFB

Feedback Amplifier Source and

Sink Current vs Temperature

Feedback Amplifier gm

vs Temperature

Feedback Amplifier Voltage Gain

vs Temperature UVLO vs Temperature IUVLO Hysteresis vs Temperature

Soft-Start Charge Current

vs Temperature

PG, SG Rise and Fall Times

vs Load Capacitance

VCC Clamp Voltage

vs Temperature

VFB (V)

0.9

–70

IVC (µA)

–50

–30

–10

11.1 1.4

1.2 1.3 1.5

3825 G10

125°C

25°C

–40°C

TEMPERATURE (°C)

–50

IVC (µA)

25 75

3825 G11

–25 0 50 100 125

SOURCE CURRENT

VFB = 1.1V

SINK

CURRENT

VFB = 1.4V

TEMPERATURE (°C)

–50

900

gm (µmho)

950

1000

1050

1100

–25 0 25 50

3825 G12

75 100 125

TEMPERATURE (°C)

–50

AV (V/V)

1550

3825 G13

1400

1300

–25 0 50

1250

1200

1150

1100

1600

1650

1700

1500

1450

1350

75 100 125

TEMPERATURE (°C)

–50

UVLO (V)

1.240

1.245

1.250

25 75

3825 G14

1.235

1.230

–25 0 50 100 125

1.225

1.220

TEMPERATURE (°C)

–50

3.4

3.5

3.7

25 75

3825 G15

3.3

3.2

–25 0 50 100 125

3.1

3.0

3.6

IUVLO (µA)

TEMPERATURE (°C)

–50

SFST CHARGE CURRENT (µA)

3825 G16

–25 0 50

75 100 125

CAPACITANCE (nF)

TIME (ns)

3825 G17

2 4 6 1071 3 5 9

TA = 25°C

FALL TIME

RISE TIME

TEMPERATURE (°C)

–50 –25

19.0

VCC (V)

20.0

21.5

050 75

3825 G18

19.5

21.0

20.5

25 100 125

ICC = 10mA

LT3825

3525fe

PIN FUNCTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum PG On-Time

vs Temperature PG Delay Time vs Temperature Enable Delay Time vs Temperature

TEMPERATURE (°C)

–50

tON(MIN) (ns)

330

3825 G19

300

280

–25 0 50

270

260

340

320

310

290

75 100 125

RtON(MIN) = 158k

TEMPERATURE (°C)

–50

tPGDLY (ns)

150

200

250

050 75

3825 G20

100

–25 25 100 125

300

RPGDLY = 16.9k

RPGDLY = 27.4k

TEMPERATURE (°C)

–50

tED (ns)

280

300

320

25 75

3825 G21

260

240

–25 0 50 100 125

220

200

RENDLY = 90k

SG (Pin 1): Synchronous Gate Drive Output. This pin pro-

vides an output signal for a secondary-side synchronous

switch. Large dynamic currents may flow during voltage

transitions. See the Applications Information for details.

VCC (Pin 2): Supply Voltage Pin. Bypass this pin to

ground with a 4.7µF capacitor or more. This pin has a

19.5V clamp to ground. VCC has an undervoltage lockout

function that turns the part on when VCC is approximately

15.3V and off at 9.7V. In a conventional “trickle-charge”

bootstrapped configuration, the VCC supply current

increases significantly during turn-on causing a benign

relaxation oscillation action on the VCC pin if the part does

not start normally.

tON (Pin 3): Pin for external programming resistor to set

the minimum time that the primary switch is on for each

cycle. Minimum turn-on facilitates the isolated feedback

method. See Applications Information for details.

ENDLY (Pin 4): Pin for external programming resistor to

set enable delay time. The enable delay time disables the

feedback amplifier for a fixed time after the turn-off of the

primary-side MOSFET. This allows the leakage inductance

voltage spike to be ignored for flyback voltage sensing.

See Applications Information for details.

SYNC (Pin 5): Pin for synchronizing the internal oscilla-

tor with an external clock. The positive edge on a pulse

causes the oscillator to discharge causing PG to go low

(off) and SG high (on). The sync threshold is typically

1.53V. See Applications Information for details. Tie to

ground if unused.

SFST (Pin 6): This pin, in conjunction with a capacitor to

ground, controls the ramp-up of peak primary current as

sensed through the sense resistor. This is used to control

converter inrush current at start-up. The VC pin voltage

cannot exceed the SFST pin voltage, so as SFST increases,

the maximum voltage on VC increases commensurately,

allowing higher peak currents. Total VC ramp time is ap-

proximately 70ms per µF of capacitance. Leave pin open

if not using the soft-start function.

OSC (Pin 7): This pin in conjunction with an external

capacitor defines the controller oscillator frequency. The

frequency is approximately 100kHz • 100/COSC(pF).

FB (Pin 8): Pin for the feedback node for the power supply

feedback amplifier. Feedback is usually sensed via a third

winding and enabled during the flyback period. This pin

also sinks additional current to compensate for load cur-

rent variation as set by the RCMP pin. Keep the Thevenin

equivalent resistance of the feedback divider at roughly 3k.

LT3825

3825fe

VC (Pin 9): Pin used for frequency compensation for

the switcher control loop. It is the output of the feed-

back amplifier and the input to the current comparator.

Switcher frequency compensation components are

normally placed on this pin to ground. The voltage on

this pin is proportional to the peak primary switch cur-

rent. The feedback amplifier output is enabled during the

synchronous switch-on time.

UVLO (Pin 10): A resistive divider from VIN to this pin sets

an undervoltage lockout based upon VIN level (not VCC).

When the UVLO pin is below its threshold, the gate drives

are disabled, but the part draws its normal quiescent current

from VCC. The VCC undervoltage lockout supersedes this

function so VCC must be great enough to start the part.

The bias current on this pin has hysteresis such that the

bias current is sourced when the UVLO threshold is ex-

ceeded. This introduces a hysteresis at the pin equivalent

to the bias current change times the impedance of the

upper divider resistor. The user can control the amount

of hysteresis by adjusting the impedance of the divider.

See the Applications Information for details. Tie the UVLO

pin to VCC if you are not using this function.

SENSE– (Pin 11), SENSE+ (Pin 12): These pins are used

to measure primary-side switch current through an ex-

ternal sense resistor. Peak primary-side current is used

in the converter control loop. Make Kelvin connections

to the sense resistor to reduce noise problems. SENSE–

connects to the ground side. At maximum current (VC at

its maximum voltage) it has a 98mV threshold. The signal

is blanked (ignored) during the minimum turn-on time.

CCMP (Pin 13): Pin for external filter capacitor for the

optional load compensation function. Load compensation

reduces the effects of parasitic resistances in the feedback

sensing path. A 0.1µF ceramic capacitor suffices for most

applications. Short this pin to GND in less demanding ap-

plications that don’t require load compensation.

RCMP (Pin 14): Pin for optional external load compensation

resistor. Use of this pin allows for nominal compensation

of parasitic resistances in the feedback sensing path. In

less demanding applications, this resistor is not needed

and this pin can be left open. See Applications Informa-

tion for details.

PGDLY (Pin 15): Pin for external programming resistor to

set delay from synchronous gate turn-off to primary gate

turn-on. See Applications Information for details.

PG (Pin 16): Gate Drive Pin for the Primary-Side MOS-

FET Switch. Large dynamic currents flow during voltage

transitions. See the Applications Information for details.

GND (Exposed Pad Pin 17): This is the ground connec-

tion for both signal ground and gate driver grounds. This

GND must be connected to the PCB ground plane. Careful

attention must be paid to ground layout. See Applications

Information for details.

PIN FUNCTIONS

LT3825

3525fe

BLOCK DIAGRAM

SENSE–

SENSE+

CCMP

VCC

TO FB

PGATE

SGATE

CURRENT

SENSE AMP

RCMPF

50k

LOAD

COMPENSATION

–

VCC

15.3V

VCC UVLO

UVLO

IUVLO

OSC

tON

PGDLY

ENDLY

SYNC

1.237V

REFERENCE

(VFB)

INTERNAL

REGULATOR

UVLO

COLLAPSE DETECT

ERROR AMP

CLAMPS

0.7

1.3

19.5V

–

SFST

TSD

CURRENT TRIP

SLOPE COMPENSATION

CURRENT

COMPARATOR OVERCURRENT

FAULT

LOGIC

BLOCK

–

RCMP

GATE DRIVE

PG 16

SG 1

GND 17

OSCILLATOR SET ENABLE

VCC

GATE DRIVE

LT3825

3825fe

FLYBACK FEEDBACK AMPLIFIER

–

VFB

1.237V

ENABLE

COLLAPSE

DETECT

LT3825 FEEDBACK AMP

–

VIN

PRIMARY

FLYBACK

SECONDARY

•

VFLBK

CVC

3825 FFA

COUT ISOLATED

OUTPUT

TIMING DIAGRAM

PRIMARY SIDE

MOSFET DRAIN

VOLTAGE

PG VOLTAGE

SG VOLTAGE

VIN

tON(MIN) ENABLE

DELAY

MIN ENABLE

FEEDBACK

AMPLIFIER

ENABLED

PG DELAY

3825 TD

VFLBK 0.8 • VFLBK

LT3825

3525fe

OPERATION

The LT3825 is a current mode switcher controller IC de-

signed specifically for use in an isolated flyback topology

employing synchronous rectification. The LT3825 opera-

tion is similar to traditional current mode switchers. The

major difference is that output voltage feedback is derived

via sensing the output voltage through the transformer. This

precludes the need of an opto-isolator in isolated designs

greatly improving dynamic response and reliability. The

LT3825 has a unique feedback amplifier that samples a

transformer winding voltage during the flyback period and

uses that voltage to control output voltage.

The internal blocks are similar to many current mode

controllers. The differences lie in the flyback feedback

amplifier and load compensation circuitry. The logic block

also contains circuitry to control the special dynamic

requirements of flyback control.

For more information on the basics of current mode

switcher/controllers and isolated flyback converters see

Application Note 19.

Feedback Amplifier—Pseudo DC Theory

For the following discussion refer to the simplified Fly-

back Feedback Amplifier diagram. When the primary-side

MOSFET switch MP turns off, its drain voltage rises above

the VIN rail. Flyback occurs when the primary MOSFET is

off and the synchronous secondary MOSFET is on. Dur-

ing flyback the voltage on nondriven transformer pins is

determined by the secondary voltage. The amplitude of

this flyback pulse as seen on the third winding is given as:

VFLBK =VOUT +ISEC •ESR +RDS(ON)

( )

RDS(ON) = on-resistance of the synchronous MOSFET MS

ISEC = transformer secondary current

ESR = impedance of secondary circuit capacitor, winding

and traces

NSF = transformer effective secondary-to-feedback winding

turns ratio (i.e., NS/NFLBK)

The flyback voltage is scaled by an external resistive divider

R1/R2 and presented at the FB pin. The feedback amplifier

compares the voltage to the internal bandgap reference.

The feedback amp is actually a transconductance ampli-

fier whose output is connected to VC only during a period

in the flyback time. An external capacitor on the VC pin

integrates the net feedback amp current to provide the

control voltage to set the current mode trip point.

The regulation voltage at the FB pin is nearly equal to the

bandgap reference VFB because of the high gain in the

overall loop. The relationship between VFLBK and VFB is

expressed as:

VFLBK =

R1+R2

R2 •VFB

Combining this with the previous VFLBK expression yields

an expression for VOUT in terms of the internal reference,

programming resistors and secondary resistances:

VOUT =R1+R2

•V

FB •NSF











– ISEC •ESR +RDS(ON)

( )

The effect of nonzero secondary output impedance is dis-

cussed in further detail; see Load Compensation Theory.

The practical aspects of applying this equation for VOUT

are found in the Applications Information.

Feedback Amplifier Dynamic Theory

So far, this has been a pseudo-DC treatment of flyback

feedback amplifier operation. But the flyback signal is a

pulse, not a DC level. Provision must be made to enable

the flyback amplifier only when the flyback pulse is present.

This is accomplished by the “Enable” line in the diagram.

Timing signals are then required to enable and disable the

flyback amplifier. There are several timing signals which

are required for proper LT3825 operation. Please refer to

the Timing Diagram.

Minimum Output Switch On-Time (tON(MIN))

The LT3825 affects output voltage regulation via flyback

pulse action. If the output switch is not turned on, there

is no flyback pulse and output voltage information is

not available. This causes irregular loop response and

start-up/latch-up problems. The solution is to require the

primary switch to be on for an absolute minimum time

per each oscillator cycle. If the output load is less than

LT3825

3825fe

OPERATION

that developed under these conditions, forced continuous

operation normally occurs. See Applications Information

for further details.

Enable Delay (ENDLY)

The flyback pulse appears when the primary-side switch

shuts off. However, it takes a finite time until the trans-

former primary-side voltage waveform represents the

output voltage. This is partly due to rise time on the

primary-side MOSFET drain node but, more importantly,

is due to transformer leakage inductance. The latter causes

a voltage spike on the primary side, not directly related

to output voltage. Some time is also required for internal

settling of the feedback amplifier circuitry. In order to

maintain immunity to these phenomena, a fixed delay is

introduced between the switch turn-off command and the

enabling of the feedback amplifier. This is termed “enable

delay.” In certain cases where the leakage spike is not

sufficiently settled by the end of the enable delay period,

regulation error may result. See Applications Information

for further details.

Collapse Detect

Once the feedback amplifier is enabled, some mechanism

is then required to disable it. This is accomplished by a

collapse detect comparator, which compares the flyback

voltage (FB referred) to a fixed reference, nominally 80%

of VFB. When the flyback waveform drops below this level,

the feedback amplifier is disabled.

Minimum Enable Time

The feedback amplifier, once enabled, stays enabled for

a fixed minimum time period termed “minimum enable

time.” This prevents lockup, especially when the output

voltage is abnormally low; e.g., during start-up. The mini-

mum enable time period ensures that the VC node is able

to “pump up” and increase the current mode trip point to

the level where the collapse detect system exhibits proper

operation. This time is set internally.

Effects of Variable Enable Period

The feedback amplifier is enabled during only a portion of

the cycle time. This can vary from the fixed minimum enable

time described to a maximum of roughly the “off” switch

time minus the enable delay time. Certain parameters of

feedback amp behavior are directly affected by the variable

enable period. These include effective transconductance

and VC node slew rate.

Load Compensation Theory

The LT3825 uses the flyback pulse to obtain information

about the isolated output voltage. An error source is

caused by transformer secondary current flow through

the synchronous MOSFET RDS(ON) and real life nonzero

impedances of the transformer secondary and output

capacitor. This was represented previously by the expres-

sion “ISEC • (ESR + RDS(ON)).” However, it is generally

more useful to convert this expression to effective output

impedance. Because the secondary current only flows

during the off portion of the duty cycle (DC), the effective

output impedance equals the lumped secondary imped-

ance divided by OFF time DC.

Since the OFF time duty cycle is equal to 1 – DC then:

RS(OUT) =

ESR +R

DS(ON)

1– DC

where:

RS(OUT) = effective supply output impedance

DC = duty cycle

RDS(ON) and ESR are as defined previously

This impedance error may be judged acceptable in less

critical applications, or if the output load current remains

relatively constant. In these cases the external FB resistive

divider is adjusted to compensate for nominal expected

error. In more demanding applications, output impedance

error is minimized by the use of the load compensation

function.

Figure 1 shows the Block Diagram of the load compensation

function. Switch current is converted to a voltage by the

external sense resistor, averaged and lowpass filtered by

the internal 50k resistor RCMPF and the external capacitor

on CCMP

. This voltage is impressed across the external

RCMP resistor by op amp A1 and transistor Q3 producing a

current at the collector of Q3 that is subtracted from the

LT3825

3525fe

OPERATION

node. This effectively increases the voltage required at the

top of the R1/R2 feedback divider to achieve equilibrium.

The average primary-side switch current increases to main-

tain output voltage regulation as output loading increases.

The increase in average current increases the RCMP resistor

current which affects a corresponding increase in sensed

output voltage, compensating for the IR drops.

Assuming a relatively fixed power supply efficiency, Eff,

power balance gives:

POUT = Eff • PIN

VOUT • IOUT = Eff • VIN • IIN

•

RCMPF

50k

VIN

VFLBK

R2 LOAD

COMP I

R1 FB

VFB

Q1 Q2

RCMP CCMP RSENSE

SENSE+

3825 F01

–

14 13

Figure 1. Load Compensation Diagram

Average primary-side current is expressed in terms of

output current as follows:

IIN =K1 •IOUT

where :

K1 =VOUT

•Eff

So the effective change in VOUT target is:

∆VOUT =K1•∆IOUT •RSENSE

RCMP

•R1•NSF

thus :

∆VOUT

∆IOUT

=K1•RSENSE

RCMP

•R1•NSF

where:

K1 = dimensionless variable related to VIN, VOUT and

efficiency as explained above

RSENSE = external sense resistor

Nominal output impedance cancellation is obtained by

equating this expression with RS(OUT):

K1•RSENSE

RCMP

•R1•NSF =

ESR +R

DS(ON)

1– DC

Solving for RCMP gives:

RCMP =K1•RSENSE •1– DC

( )

ESR +RDS(ON)

•R1•NSF

The practical aspects of applying this equation to determine

an appropriate value for the RCMP resistor are found in the

Applications Information.

LT3825

3825fe

APPLICATIONS INFORMATION

Transformer Design

Transformer design/specification is the most critical part

of a successful application of the LT3825. The following

sections provide basic information about designing the

transformer and potential trade-offs.

If you need help, the LT C Applications group is available

to assist in the choice and/or design of the transformer.

Turns Ratios

The design of the transformer starts with determining duty

cycle (DC). DC impacts the current and voltage stress on

the power switches, input and output capacitor RMS cur-

rents and transformer utilization (size vs power).

The ideal turns ratio is:

NIDEAL =

OUT

•

1– DC

Avoid extreme duty cycles as they, in general, increase

current stresses. A reasonable target for duty cycle is 50%

at nominal input voltage.

For instance, if we wanted a 48V to 5V converter at 50%

DC then:

NIDEAL =

•

1– 0.5

0.5

9.6

In general, better performance is obtained with a lower

turns ratio. A DC of 45.5% yields a 1:8 ratio.

Note the use of the external feedback resistive divider

ratio to set output voltage provides the user additional

freedom in selecting a suitable transformer turns ratio.

Turns ratios that are the simple ratios of small integers;

e.g., 1:1, 2:1, 3:2 help facilitate transformer construction

and improve performance.

When building a supply with multiple outputs derived

through a multiple winding transformer, lower duty cycle

can improve cross regulation by keeping the synchronous

rectifier on longer, and thus, keep secondary windings

coupled longer.

For a multiple output transformer, the turns ratio between

output windings is critical and affects the accuracy of the

voltages. The ratio between two output voltages is set with

the formula VOUT2 = VOUT1 • N21 where N21 is the turns

ratio between the two windings. Also keep the secondary

MOSFET RDS(ON) small to improve cross regulation.

The feedback winding usually provides both the feedback

voltage and power for the LT3825. So set the turns ratio

between the output and feedback winding to provide a

rectified voltage that under worst-case conditions is greater

than the 11V maximum VCC turn-off voltage.

NSF >VOUT

11+V

For our example: NSF >5

11+0.7 =1

2.34

We will choose 1

Leakage Inductance

Transformer leakage inductance (on either the primary or

secondary) causes a spike after the primary-side switch

turn-off. This is increasingly prominent at higher load

currents, where more stored energy is dissipated. Higher

flyback voltage may break down the MOSFET switch if it

has too low a BVDSS rating.

One solution to reducing this spike is to use a snubber

circuit to suppress the voltage excursion. However, sup-

pressing the voltage extends the flyback pulse width. If

the flyback pulse extends beyond the enable delay time,

output voltage regulation is affected. The feedback system

has a deliberately limited input range, roughly ±50mV re-

ferred to the FB node. This rejects higher voltage leakage

spikes because once a leakage spike is several volts in

amplitude, a further increase in amplitude has little effect

on the feedback system.

Therefore, it is advisable to arrange the snubber circuit to

clamp at as high a voltage as possible, observing MOSFET

breakdown, such that leakage spike duration is as short as

possible. Application Note 19 provides a good reference

on snubber design.

LT3825

3525fe

As a rough guide, leakage inductance of several percent

(of mutual inductance) or less may require a snubber, but

exhibit little to no regulation error due to leakage spike

behavior. Inductances from several percent up to perhaps

ten percent cause increasing regulation error.

Avoid double digit percentage leakage inductances as

there is a potential for abrupt loss of control at high load

current. This curious condition potentially occurs when the

leakage spike becomes such a large portion of the flyback

waveform that the processing circuitry is fooled into think-

ing that the leakage spike itself is the real flyback signal!

It then reverts to a potentially stable state whereby the

top of the leakage spike is the control point, and the

trailing edge of the leakage spike triggers the collapse

detect circuitry. This typically reduces the output voltage

abruptly to a fraction, roughly one-third to two-thirds of

its correct value.

Once load current is reduced sufficiently, the system snaps

back to normal operation. When using transformers with

considerable leakage inductance, exercise this worst-case

check for potential bistability:

1. Operate the prototype supply at maximum expected

load current.

2. Temporarily short circuit the output.

3. Observe that normal operation is restored.

If the output voltage is found to hang up at an abnormally

low value, the system has a problem. This is usually evident

by simultaneously viewing the primary-side MOSFET drain

voltage to observe firsthand the leakage spike behavior.

A final note—the susceptibility of the system to bistable

behavior is somewhat a function of the load current/volt-

age characteristics. A load with resistive—i.e., I = V/R

behavior—is the most apt to be bistable. Capacitive loads

that exhibit I = V2/R behavior are less susceptible.

Secondary Leakage Inductance

Leakage inductance on the secondary forms an inductive

divider on the transformer secondary, reducing the size

of the feedback flyback pulse. This increases the output

voltage target by a similar percentage.

Note that unlike leakage spike behavior, this phenomenon

is independent of load. Since the secondary leakage in-

ductance is a constant percentage of mutual inductance

(within manufacturing variations), the solution is to adjust

the feedback resistive divider ratio to compensate.

Winding Resistance Effects

Primary or secondary winding resistance acts to reduce

overall efficiency (POUT/PIN). Secondary winding resistance

increases effective output impedance degrading load

regulation. Load compensation can mitigate this to some

extent but a good design keeps parasitic resistances low.

Bifilar Winding

A bifilar or similar winding is a good way to minimize

troublesome leakage inductances. Bifilar windings also

improve coupling coefficients and thus improve cross

regulation in multiple winding transformers. However,

tight coupling usually increases primary-to-secondary

capacitance and limits the primary-to-secondary break-

down voltage, so it isn’t always practical.

Primary Inductance

The transformer primary inductance, LP

, is selected based

on the peak-to-peak ripple current ratio (X) in the trans-

former relative to its maximum value. As a general rule,

keep X in the range of 20% to 40% ripple current (i.e., X

= 0.2 to 0.4). Higher values of ripple will increase conduc-

tion losses, while lower values will require larger cores.

APPLICATIONS INFORMATION

LT3825

3825fe

Ripple current and percentage ripple is largest at minimum

duty cycle; in other words, at the highest input voltage.

LP is calculated from:

LP=V

IN(MAX) •DCMIN

( )

fOSC •XMAX •PIN

IN(MAX) •DCMIN

( )

2•Eff

OSC •XMAX •P

OUT

where:

fOSC is the oscillator frequency

DCMIN is the DC at maximum input voltage

XMAX is ripple current ratio at maximum input voltage

For a 48V (VIN = 36V to 72V) to 5V/8A converter with 90%

efficiency, POUT = 40W and PIN = 44.44W. Using X = 0.4

and fOSC = 200kHz:

DCMIN =1

1+N•V

IN(MAX)

VOUT

1+1

•72

=35.7%

LP=72V •0.357

( )

200kHz •0.4 •44.44W

=186µH

Optimization might show that a more efficient solution

is obtained at higher peak current but lower inductance

and the associated winding series resistance. A simple

spreadsheet program is useful for looking at trade-offs.

Transformer Core Selection

Once LP is known, the type of transformer is selected.

High efficiency converters use ferrite cores to minimize

core loss. Actual core loss is independent of core size for

a fixed inductance, but decreases as inductance increases.

Since increased inductance is accomplished through more

turns of wire, copper losses increase. Thus transformer

design balances core and copper losses. Remember that

increased winding resistance will degrade cross regulation

and increase the amount of load compensation required.

The main design goals for core selection are reducing

copper losses and preventing saturation. Ferrite core

material saturates hard, rapidly reducing inductance

when the peak design current is exceeded. This results

in an abrupt increase in inductor ripple current and, con-

sequently, output voltage ripple. Do not allow the core

to saturate! The maximum peak primary current occurs

at minimum VIN:

IPK =PIN

VIN(MIN) •DCMAX

•1+XMIN













now :

DCMAX =1

1+N•V

IN(MIN)

VOUT

1+1

•36

=52.6%

XMIN =VIN(MIN) •DCMAX

( )

OSC •LP•P

=36 •52.6%

( )

200kHz •186µH•44.44

0.202

Using the example numbers leads to:

IPK =44.44W

36 •0.526

•1+0.202











=2.58A

Multiple Outputs

One advantage that the flyback topology offers is that ad-

ditional output voltages can be obtained simply by adding

windings. Designing a transformer for such a situation is

beyond the scope of this document. For multiple windings,

realize that the flyback winding signal is a combination of

activity on all the secondary windings. Thus load regulation

is affected by each windings load. Take care to minimize

cross regulation effects.

APPLICATIONS INFORMATION

LT3825

3525fe

Setting Feedback Resistive Divider

The expression for VOUT developed in the Operation sec-

tion is rearranged to yield the following expression for the

feedback resistors:

R1=R2 VOUT +ISEC •ESR +RDS(ON)

( )







FB •NSF

– 1













Continuing the example, if ESR + RDS(ON) = 8mΩ, R2 =

3.32k, then:

R1=3.4k 5+8•0.008

1.232 •1/ 3 – 1











=37.6k

choose 37.4k.

It is recommended that the Thevenin impedance of the

resistive divider (R1||R2) is roughly 3k for bias current

cancellation and other reasons.

Current Sense Resistor Considerations

The external current sense resistor is used to control peak

primary switch current, which controls a number of key

converter characteristics including maximum power and

external component ratings. Use a noninductive current

sense resistor (no wire-wound resistors). Mounting the

resistor directly above an unbroken ground plane con-

nected with wide and short traces keeps stray resistance

and inductance low.

The dual sense pins allow for a fully Kelvined connection.

Make sure that SENSE+ and SENSE– are isolated and con-

nect close to the sense resistor to preserve this.

Peak current occurs at 98mV of sense voltage VSENSE. So

the nominal sense resistor is VSENSE/IPK. For example, a

peak switch current of 10A requires a nominal sense resistor

of 0.010Ω. Note that the instantaneous peak power in the

sense resistor is 1W, and that it is rated accordingly. The

use of parallel resistors can help achieve low resistance,

low parasitic inductance and increased power capability.

Size RSENSE using worst-case conditions, minimum LP

VSENSE and maximum VIN. Continuing the example, let us

assume that our worst-case conditions yield an IPK 40%

above nominal so IPK = 3.64A . If there is a 10% tolerance

on RSENSE and minimum VSENSE = 80mV, then RSENSE •

110% = 80mV/3.64A and nominal RSENSE = 20mΩ. Round

to the nearest available lower value.

Selecting the Load Compensation Resistor

The expression for RCMP was derived in the Operation

section as:

RCMP =K1•RSENSE •1– DC

( )

ESR +RDS(ON)

•R1 • NSF =RS(OUT)

Continuing the example:

K1=VOUT

IN •Eff









=5

48 •90% =0.116

If ESR +RDS(ON) =8mΩ

RCMP =0.116 •20mΩ•1– 0.455

( )

8mΩ•37.4kΩ

1.96k

This value for RCMP is a good starting point, but empiri-

cal methods are required for producing the best results.

This is because several of the required input variables are

difficult to estimate precisely. For instance, the ESR term

above includes that of the transformer secondary, but its

effective ESR value depends on high frequency behavior,

not simply DC winding resistance. Similarly, K1 appears

as a simple ratio of VIN to VOUT times (differential) ef-

ficiency, but theoretically estimating efficiency is not a

simple calculation.

The suggested empirical method is as follows:

1. Build a prototype of the desired supply including the

actual secondary components.

2. Temporarily ground the CCMP pin to disable the load

compensation function. Measure output voltage while

sweeping output current over the expected range.

Approximate the voltage variation as a straight line,

∆VOUT/∆IOUT = RS(OUT).

3. Calculate a value for the K1 constant based on VIN, VOUT

and the measured efficiency.

APPLICATIONS INFORMATION

LT3825

3825fe

4. Compute:

RCMP =K1•

SENSE

RS(OUT)

•R1•NSF

5. Verify this result by connecting a resistor of this value

from the RCMP pin to ground.

6. Disconnect the ground short to CCMP and connect a 0.1µF

filter capacitor to ground. Measure the output imped-

ance RS(OUT) = ∆VOUT/∆IOUT with the new compensation

in place. RS(OUT) should have decreased significantly.

Fine tuning is accomplished experimentally by slightly

altering RCMP

. A revised estimate for RCMP is:

′

RCMP =RCMP •1+RS(OUT)CMP

RS(OUT)













where R′CMP is the new value for the load compensation

resistor, RS(OUT)CMP is the output impedance with RCMP

in place and RS(OUT) is the output impedance with no

load compensation (from step 2).

Setting Frequency

The switching frequency of the LT3825 is set by an

external capacitor connected between the OSC pin and

ground. Recommended values are between 200pF and

33pF, yielding switching frequencies between 50kHz and

250kHz. Figure 2 shows the nominal relationship between

external capacitance and switching frequency. Place the

capacitor as close as possible to the IC and minimize OSC

trace length and area to minimize stray capacitance and

potential noise pickup.

You can synchronize the oscillator frequency to an external

frequency. This is done with a signal on the SYNC pin.

Set the LT3825 frequency 10% slower than the desired

external frequency using the OSC pin capacitor, then use

a pulse on the SYNC pin of amplitude greater than 2V

and with the desired frequency. The rising edge of the

SYNC signal initiates an OSC capacitor discharge forcing

primary MOSFET off (PG voltage goes low). If the oscilla-

tor frequency is much different from the sync frequency,

problems may occur with slope compensation and system

stability. Keep the sync pulse width greater than 500ns.

Selecting Timing Resistors

There are three internal “one-shot” times that are pro-

grammed by external application resistors: minimum

on-time, enable delay time and primary MOSFET turn-on

delay. These are all part of the isolated flyback control

technique, and their functions are previously outlined in

the Theory of Operation section.

The following information should help in selecting and/or

optimizing these timing values.

Minimum On-Time (tON(MIN))

Minimum on-time is the programmable period during which

current limit is blanked (ignored) after the turn on of the

primary-side switch. This improves regulator performance

by eliminating false tripping on the leading edge spike in

the switch, especially at light loads. This spike is due to

both the gate/source charging current and the discharge

of drain capacitance. The isolated flyback sensing requires

a pulse to sense the output. Minimum on-time ensures

that there is always a signal to close the loop.

The LT3825 does not employ cycle skipping at light loads.

Therefore, minimum on-time along with synchronous

rectification sets the switch over to forced continuous

mode operation.

APPLICATIONS INFORMATION

COSC (pF)

fOSC (kHz)

100

200

300

100 200

3825 F02

Figure 2. fOSC vs OSC Capacitor Values

LT3825

3525fe

The tON(MIN) resistor is set with the following equation:

RtON(MIN) (kΩ)=tON(MIN)(ns) – 104

1.063

Keep RtON(MIN) greater than 70k. A good starting value

is 160k.

Enable Delay Time (ENDLY)

Enable delay time provides a programmable delay between

turn-off of the primary gate drive node and the subsequent

enabling of the feedback amplifier. As discussed earlier, this

delay allows the feedback amplifier to ignore the leakage

inductance voltage spike on the primary side.

The worst-case leakage spike pulse width is at maximum

load conditions. So set the enable delay time at these

conditions.

While the typical applications for this part use forced

continuous operation, it is conceivable that a secondary-

side controller might cause discontinuous operation at

light loads. Under such conditions the amount of energy

stored in the transformer is small. The flyback waveform

becomes “lazy” and some time elapses before it indicates

the actual secondary output voltage. The enable delay time

should be made long enough to ignore the “irrelevant”

portion of the flyback waveform at light load.

Even though the LT3825 has a robust gate drive, the gate

transition time slows with very large MOSFETs. Increase

delay time as required when using such MOSFETs.

The enable delay resistor is set with the following

equation:

RENDLY (kΩ)=tENDLY (ns) – 30

2.616

Keep RENDLY greater than 40k. A good starting point is 56k.

Primary Gate Delay Time (PGDLY)

Primary gate delay is the programmable time from the

turn-off of the synchronous MOSFET to the turn-on of

the primary-side MOSFET. Correct setting eliminates

overlap between the primary-side switch and secondary-

side synchronous switch(es) and the subsequent current

spike in the transformer. This spike will cause additional

component stress and a loss in regulator efficiency.

The primary gate delay resistor is set with the following

equation:

RPGDLY (kΩ)=

PGDLY

(ns)+47

9.01

A good starting point is 27k.

Soft-Start Functions

The LT3825 contains an optional soft-start function that

is enabled by connecting an external capacitor between

the SFST pin and ground. Internal circuitry prevents the

control voltage at the VC pin from exceeding that on the

SFST pin. There is an initial pull-up circuit to quickly bring

the SFST voltage to approximately 0.8V. From there it

charges to approximately 2.8V with a 20µA current source.

The SFST node is discharged to 0.8V when a fault occurs.

A fault is VCC too low (undervoltage lockout), current sense

voltage greater than 200mV or the IC’s thermal (over tem-

perature) shutdown is tripped. When SFST discharges, the

VC node voltage is also pulled low to below the minimum

current voltage. Once discharged and the fault removed,

the SFST recharges up again.

In this manner, switch currents are reduced and the stresses

in the converter are reduced during fault conditions.

The time it takes to fully charge soft-start is:

tSS =CSFST •1.4V

20µA=70ms •CSFST (µF)

UVLO Pin Function

The UVLO pin provides a user programming undervoltage

lockout. This is typically used to provide undervoltage

lockout based on VIN. The gate drivers are disabled when

UVLO is below the 1.24V UVLO threshold. An external

resistive divider between the input supply and ground is

used to set the turn-on voltage.

APPLICATIONS INFORMATION

LT3825

3825fe

The bias current on this pin depends on the pin volt-

age and UVLO state. The change provides the user with

adjustable UVLO hysteresis. When the pin rises above

the UVLO threshold a small current is sourced out of the

pin, increasing the voltage on the pin. As the pin voltage

drops below this threshold, the current is stopped, further

dropping the voltage on UVLO. In this manner, hysteresis

is produced.

Referring to Figure 3, the voltage hysteresis at VIN is

equal to the change in bias current times RA. The design

procedure is to select the desired VIN referred voltage

hysteresis, VUVHYS. Then:

RA=

UVHYS

UVLO

where:

IUVLO = IUVLOL – IUVLOH is approximately 3.4µA

RB is then selected with the desired turn-on voltage:

RB=RA

VIN(ON)

VUVLO

– 1











If we wanted a VIN-referred trip point of 36V, with 1.8V

(5%) of hysteresis (on at 36V, off at 34.2V):

RA=1.8V

3.4µA=529k, use 523k

RB=523k

36V

1.23V – 1











=18.5k, use 18.7k

Even with good board layout, board noise may cause

problems with UVLO. You can filter the divider but keep

large capacitance off the UVLO node because it will slow

the hysteresis produced from the change in bias current.

Figure 3c shows an alternate method of filtering by split-

ting the RA resistor with the capacitor. The split should

put more of the resistance on the UVLO side.

Converter Start-Up

The standard topology for the LT3825 utilizes a third

transformer winding on the primary side that provides both

feedback information and local VCC power for the LT3825

(see Figure 4). This power “bootstrapping” improves

converter efficiency but is not inherently self-starting.

Start-up is affected with an external “trickle-charge” resis-

tor and the LT3825’s internal VCC undervoltage lockout

circuit. The VCC undervoltage lockout has wide hysteresis

to facilitate start-up.

In operation, the “trickle charge” resistor, RTR, is con-

nected to VIN and supplies a small current, typically on the

order of 1mA to charge CTR. Initially the LT3825 is off and

draws only its start-up current. When CTR reaches the VCC

turn-on threshold voltage the LT3825 turns on abruptly

and draws its normal supply current.

APPLICATIONS INFORMATION

VIN

LT3825

(3a) UV Turning ON

UVLO

IUVLO

VIN

LT3825

(3b) UV Turning OFF (3c) UV Filtering

UVLO UVLO

VIN

RA2

RA1

CUVLO

3825 F03

IUVLO

Figure 3

IVCC

3825 F04

RTR

CTR

VIN

IVCC

VVCC

VON THRESHOLD

VPG

VCC

LT3825 PG

GND

•

Figure 4. Typical Power Bootstrapping

LT3825

3525fe

Switching action commences and the converter begins to

deliver power to the output. Initially the output voltage is low

and the flyback voltage is also low, so CTR supplies most

of the LT3825 current (only a fraction comes from RTR.)

VCC voltage continues to drop until after some time, typi-

cally tens of milliseconds, the output voltage approaches

its desired value. The flyback winding then provides the

LT3825 supply current and the VCC voltage stabilizes.

If CTR is undersized, VCC reaches the VCC turn-off threshold

before stabilization and the LT3825 turns off. The VCC

node then begins to charge back up via RTR to the turn-

on threshold, where the part again turns on. Depending

upon the circuit, this may result in either several on-off

cycles before proper operation is reached, or permanent

relaxation oscillation at the VCC node.

RTR is selected to yield a worst-case minimum charging

current greater than the maximum rated LT3825 start-up

current, and a worst-case maximum charging current less

than the minimum rated LT3825 supply current.

RTR(MAX) <VIN(MIN) – VCC(ON _ MAX)

ICC(ST _ MAX)

and

RTR(MIN) >VIN(MAX) – VCC(ON _ MIN)

ICC(MIN)

Make CTR large enough to avoid the relaxation oscillatory

behavior described above. This is complicated to deter-

mine theoretically as it depends on the particulars of the

secondary circuit and load behavior. Empirical testing is

recommended. Note that the use of the optional soft-start

function lengthens the power-up timing and requires a

correspondingly larger value for CTR.

If you have an available input voltage within the VCC

range, the internal wide hysteresis range UVLO function

becomes counterproductive. In such cases it is better to

operate the LT3825 directly from the available supply. In

this case, use the LT3837 which is identical to the LT3825

except that it lacks the internal VCC undervoltage lockout

function. It is designed to operate directly from supplies

in the range of 4.5V to 19V. See the LT3837 data sheet

for further information.

The LT3825 has an internal clamp on VCC of approximately

19.5V. This provides some protection for the part in the

event that the switcher is off (UVLO low) and the VCC node

is pulled high. If RTR is sized correctly the part should

never attain this clamp voltage.

Control Loop Compensation

Loop frequency compensation is performed by connecting

a capacitor network from the output of the feedback ampli-

fier (VC pin) to ground as shown in Figure 5. Because of

the sampling behavior of the feedback amplifier, compen-

sation is different from traditional current mode switcher

controllers. Normally only CVC is required. RVC can be

used to add a “zero” but the phase margin improvement

traditionally offered by this extra resistor is usually already

accomplished by the nonzero secondary circuit impedance.

CVC2 can be used to add an additional high frequency pole

and is usually sized at 0.1 times CVC.

In further contrast to traditional current mode switchers,

VC pin ripple is generally not an issue with the LT3825.

The dynamic nature of the clamped feedback amplifier

forms an effective track/hold type response, whereby the

VC voltage changes during the flyback pulse, but is then

“held” during the subsequent “switch-on” portion of the

next cycle. This action naturally holds the VC voltage stable

APPLICATIONS INFORMATION

RVC

CVC

3825 F05

CVC2

Figure 5. VC Compensation Network

LT3825

3825fe

during the current comparator sense action (current mode

switching).

AN19 provides a method for empirically tweaking frequency

compensation. Basically it involves introducing a load

current step and monitoring the response.

Slope Compensation

This part incorporates current slope compensation. Slope

compensation is required to ensure current loop stability

when the DC is greater than 50%. In some switcher con-

trollers, slope compensation reduces the maximum peak

current at higher duty cycles. The LT3825 eliminates this

problem by having circuitry that compensates for the slope

compensation so that maximum current sense voltage is

constant across all duty cycles.

Minimum Load Considerations

At light loads, the LT3825 derived regulator goes into

forced continuous conduction mode. The primary-side

switch always turns on for a short time as set by the

tON(MIN) resistor. If this produces more power than the

load requires, power will flow back into the primary during

the “off” period when the synchronization switch is on.

This does not produce any inherently adverse problems,

though light load efficiency is reduced.

Maximum Load Considerations

The current mode control uses the VC node voltage and

amplified sense resistor voltage as inputs to the current

comparator. When the amplified sense voltage exceeds

the VC node voltage, the primary-side switch is turned off.

In normal use, the peak switch current increases while

FB is below the internal reference. This continues until

VC reaches its 2.56V clamp. At clamp, the primary-side

MOSFET will turn off at the rated 98mV VSENSE level. This

repeats on the next cycle.

It is possible for the peak primary switch currents as

referred across RSENSE to exceed the max 98mV rating

because of the minimum switch-on time blanking. If the

voltage on VSENSE exceeds 206mV after the minimum

turn-on time, the SFST capacitor is discharged, causing

the discharge of the VC capacitor. This then reduces the

peak current on the next cycle and will reduce overall

stress in the primary switch.

Short-Circuit Conditions

Loss of current limit is possible under certain conditions

such as an output short circuit. If the duty cycle exhib-

ited by the minimum on time is greater than the ratio of

secondary winding voltage (referred-to-primary) divided

by input voltage, then peak current is not controlled at

the nominal value. It ratchets up cycle-by-cycle to some

higher level. Expressed mathematically, the requirement

to maintain short-circuit control is:

DCMIN =tON(MIN) •fOSC <ISC •RSEC +RDS(ON)

( )

VIN •NSP

where:

tON(MIN) = primary-side switch minimum on-time

ISC = short-circuit output current

NSP = secondary-to-primary turns ratio (NSEC/NPRI)

Other variables as previously defined

Trouble is typically encountered only in applications with a

relatively high product of input voltage times secondary-

to-primary turns ratio and/or a relatively long minimum

switch on time. Additionally, several real world effects such

as transformer leakage inductance, AC winding losses, and

output switch voltage drop combine to make this simple

theoretical calculation a conservative estimate. Prudent

design evaluates the switcher for short-circuit protection

and adds any additional circuitry to prevent destruction.

APPLICATIONS INFORMATION

LT3825

3525fe

Output Voltage Error Sources

The LT3825’s feedback sensing introduces additional

sources of errors. The following is a summary list.

The internal bandgap voltage reference sets the reference

voltage for the feedback amplifier. The specifications detail

its variation.

The external feedback resistive divider ratio proportional

directly affects regulated voltage. Use 1% components.

Leakage inductance on the transformer secondary reduces

the effective secondary-to-feedback winding turns ratio

(NS/NF) from its ideal value. This increases the output

voltage target by a similar percentage. Since secondary

leakage inductance is constant from part to part (with a

tolerance) adjust the feedback resistor ratio to compensate.

The transformer secondary current flows through the

impedances of the winding resistance, synchronous MOS-

FET RDS(ON) and output capacitor ESR. The DC equivalent

current for these errors is higher than the load current

because conduction occurs only during the converter’s

“off” time. So divide the load current by (1 – DC).

If the output load current is relatively constant, the feedback

resistive divider is used to compensate for these losses.

Otherwise, use the LT3825 load compensation circuitry

(see Load Compensation).

If multiple output windings are used, the flyback winding

will have a signal that represents an amalgamation of all

these windings impedances. Take care that you examine

worst-case loading conditions when tweaking the voltages.

Power MOSFET Selection

The power MOSFETs are selected primarily on the criteria of

on- resistance, RDS(ON), input capacitance, drain-to-source

breakdown voltage (BVDSS), maximum gate voltage (VGS)

and maximum drain current (ID(MAX)).

For the primary-side power MOSFET, the peak current is:

IPK(PRI) =PIN

VIN(MIN) •DCMAX

•1+XMIN













where XMIN is peak-to-peak current ratio as defined earlier.

For each secondary-side power MOSFET, the peak cur-

rent is:

IPK(SEC) =IOUT

1– DCMAX

•1+XMIN













Select a primary-side power MOSFET with a BVDSS greater

than:

BVDSS ≥IPK

LLKG

+VIN(MAX) +VOUT(MAX)

NSP

where NSP reflects the turns ratio of that secondary-

to-primary winding. LLKG is the primary-side leakage

inductance and CP is the primary-side capacitance (mostly

from the COSS of the primary-side power MOSFET). A

snubber may be added to reduce the leakage inductance

as discussed earlier.

For each secondary-side power MOSFET, the BVDSS should

be greater than:

BVDSS ≥ VOUT + VIN(MAX) • NSP

Choose the primary-side MOSFET RDS(ON) at the nominal

gate drive voltage (7.5V). The secondary side MOSFET gate

drive voltage depends on the gate drive method.

Primary-side power MOSFET RMS current is given by:

IRMS(PRI) =

IN(MIN) DCMAX

For each secondary-side power MOSFET RMS current is

given by:

IRMS(SEC) =

OUT

1– DCMAX

Calculate MOSFET power dissipation next. Because the

primary-side power MOSFET operates at high VDS, a transi-

tion power loss term is included for accuracy. CMILLER is

the most critical parameter in determining the transition

loss, but is not directly specified on the data sheets.

APPLICATIONS INFORMATION

LT3825

3825fe

CMILLER is calculated from the gate charge curve included

on most MOSFET data sheets (Figure 6).

The flat portion of the curve is the result of the Miller

(gate-to-drain) capacitance as the drain voltage drops.

The Miller capacitance is computed as:

CMILLER =

– Q

The curve is done for a given VDS. The Miller capacitance

for different VDS voltages are estimated by multiplying the

computed CMILLER by the ratio of the application VDS to

the curve specified VDS.

APPLICATIONS INFORMATION

VGS

a b

3825 F06

MILLER EFFECT

GATE CHARGE (QG)

Figure 6. Gate Charge Curve

With CMILLER determined, calculate the primary-side power

MOSFET power dissipation:

PDPRI =IRMS(PRI)2•RDS(ON) 1+ δ

( )

IN(MAX) •PIN(MAX)

DCMIN

•RDR •CMILLER

VGATE(MAX) – VTH

•fOSC

where:

RDR is the gate driver resistance (≈10Ω)

VTH is the MOSFET gate threshold voltage

fOSC is the operating frequency

VGATE(MAX) = 7.5V for this part

(1 + δ) is generally given for a MOSFET in the form of a

normalized RDS(ON) vs temperature curve. If you don’t have

a curve, use δ = 0.005/°C • ∆T for low voltage MOSFETs.

The secondary-side power MOSFETs typically operate

at substantially lower VDS, so you can neglect transition

losses. The dissipation is calculated using:

PD(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ)

With power dissipation known, the MOSFETs’ junction

temperatures are obtained from the equation:

TJ = TA + PD • θJA

where TA is the ambient temperature and θJA is the MOSFET

junction-to-ambient thermal resistance.

Once you have TJ, iterate your calculations recomputing

δ and power dissipations until convergence.

Gate Drive Node Consideration

The PG and SG gate drivers are strong drives to minimize

gate drive rise and fall times. This improves efficiency

but the high frequency components of these signals can

cause problems. Keep the traces short and wide to reduce

parasitic inductance.

The parasitic inductance creates an LC tank with the

MOSFET gate capacitance. In less than ideal layouts, a

series resistance of 5Ω or more may help to dampen the

ringing at the expense of slightly slower rise and fall times

and efficiency.

The LT3825 gate drives will clamp the max gate voltage

to roughly 7.4V, so you can safely use MOSFETs with max

VGS of 10V or larger.

Synchronous Gate Drive

There are several different ways to drive the synchronous

gate MOSFET. Full converter isolation requires the synchro-

nous gate drive to be isolated. This is usually accomplished

by way of a pulse transformer. Usually the pulse driver is

used to drive a buffer on the secondary as shown in the

application on the front page of this data sheet.

However, other schemes are possible. There are gate

drivers and secondary side synchronous controllers avail-

able that provide the buffer function as well as additional

features.

LT3825

3525fe

APPLICATIONS INFORMATION

Capacitor Selection

In a flyback converter, the input and output current flows

in pulses, placing severe demands on the input and output

filter capacitors. The input and output filter capacitors are

selected based on RMS current ratings and ripple voltage.

Select an input capacitor with a ripple current rating

greater than:

IRMS =PIN

VIN(MIN)

1– DCMAX

DCMAX

Continuing the example:

IRMS =44.4W

36V

1– 52.6%

52.6% =1.17A

Keep input capacitor series resistance (ESR) and induc-

tance (ESL) small, as they affect electromagnetic interfer-

ence suppression. In some instances, high ESR can also

produce stability problems because flyback converters

exhibit a negative input resistance characteristic. Refer

to Application Note 19 for more information.

The output capacitor is sized to handle the ripple cur-

rent and to ensure acceptable output voltage ripple.

The output capacitor should have an RMS current

rating greater than:

IRMS =IOUT

DCMAX

1– DCMAX

Continuing the example:

IRMS =8A 52.6%

1– 52.6% =8.43A

This is calculated for each output in a multiple winding

application.

ESR and ESL along with bulk capacitance directly affect

the output voltage ripple. The waveforms for a typical

flyback converter are illustrated in Figure 7.

The maximum acceptable ripple voltage (expressed as a

percentage of the output voltage) is used to establish a

starting point for the capacitor values. For the purpose

of simplicity we will choose 2% for the maximum output

ripple, divided equally between the ESR step and the

charging/discharging ∆V. This percentage ripple changes,

depending on the requirements of the application. You can

modify the equations below.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor is determined by:

ESRCOUT ≤1% •VOUT •1– DCMAX

( )

IOUT

OUTPUT VOLTAGE

RIPPLE WAVEFORM

SECONDARY

CURRENT

PRIMARY

CURRENT

IPRI

∆VCOUT

3825 F07

RINGING

DUE TO ESL

IPRI

∆VESR

Figure 7. Typical Flyback Converter Waveforms

LT3825

3825fe

APPLICATIONS INFORMATION

The other 1% is due to the bulk C component, so use:

COUT ≥IOUT

1% •VOUT •fOSC

In many applications the output capacitor is created from

multiple capacitors to achieve desired voltage ripple, reli-

ability and cost goals. For example, a low ESR ceramic

capacitor can minimize the ESR step, while an electrolytic

capacitor satisfies the required bulk C.

Continuing our example, the output capacitor needs:

ESRCOUT ≤1% •5V •1– 49%

( )

8A =3mΩ

COUT ≥8A

1% •5•200kHz

=800µF

These electrical characteristics require paralleling several

low ESR capacitors possibly of mixed type.

Most capacitor ripple current ratings are based on 2000

hour life. This makes it advisable to derate the capacitor

or to choose a capacitor rated at a higher temperature

than required.

One way to reduce cost and improve output ripple is to use

a simple LC filter. Figure 8 shows an example of the filter.

The design of the filter is beyond the scope of this data

sheet. However, as a starting point, use these general

guide lines. Start with a COUT 1/4 the size of the nonfilter

solution. Make C1 1/4 of COUT to make the second filter

pole independent of COUT

. C1 may be best implemented

with multiple ceramic capacitors. Make L1 smaller than

the output inductance of the transformer. In general, a

0.1µH filter inductor is sufficient. Add a small ceramic

capacitor (COUT2) for high frequency noise on VOUT. For

those interested in more details refer to “Second-Stage

LC Filter Design,” Ridley, Switching Power Magazine, July

2000, p8-10.

Circuit simulation is a way to optimize output capacitance

and filters, just make sure to include the component parasit-

ics. LT C SwitcherCAD is a terrific free circuit simulation

tool that is available at www.linear.com. Final optimization

of output ripple must be done on a dedicated PC board.

Parasitic inductance due to poor layout can significantly

impact ripple. Refer to the PC Board Layout section for

more details.

IC Thermal Considerations

Take care to ensure that the LT3825 junction temperature

does not exceed 125°C. Power is computed from the aver-

age supply current, the sum of quiescent supply current

(ICC in the specifications) plus gate drive currents.

The primary gate drive current is computed as:

fOSC • QG

where QG is the total gate charge at max VGS (obtained from

the gate charge curve) and f is the switching frequency.

Since the synchronous driver is usually driving a capaci-

tive load, the synchronous gate drive power dissipation is:

fOSC • CS • VSGMAX

where CS is the SG capacitive load and VSGMAX is the SG

pin max voltage.

The total IC dissipation is computed as:

PD(TOTAL) = VCC • (ICC + fOSC • (QGPRI + CS • VSGMAX))

VCC is the worst-case LT3825 supply voltage.

Junction temperature is computed as:

TJ = TA + PD • θJA

where:

TA is the ambient temperature

θJA is the FE16 package junction-to-ambient thermal

impedance (40°C/W).

RLOAD

COUT2

1µF

VOUT

COUT

470µF

47µF

×3

FROM

SECONDARY

WINDING

0.1µH

3825 F08

Figure 8

LT3825

3525fe

PC Board Layout Considerations

In order to minimize switching noise and improve output

load regulation, connect the GND pin of the LT3825 directly

to the ground terminal of the VCC decoupling capacitor,

the bottom terminal of the current sense resistor, the

ground terminal of the input capacitor, and the ground

plane (multiple vias). Place the VCC capacitor immediately

adjacent to the VCC and GND pins on the IC package. This

capacitor carries high di/dt MOSFET gate drive currents.

Use a low ESR ceramic capacitor.

Take care in PCB layout to keep the traces that conduct high

switching currents short, wide and with minimal overall

loop area. These are typically the traces associated with

the switches. This reduces the parasitic inductance and

also minimizes magnetic field radiation. Figure 9 outlines

the critical paths.

Keep electric field radiation low by minimizing the length

and area of traces (keep stray capacitances low). The drain

of the primary-side MOSFET is the worst offender in this

category. Always use a ground plane under the switcher

circuitry to prevent coupling between PCB planes.

Check that the maximum BVDSS ratings of the MOSFETs

are not exceeded due to inductive ringing. This is done by

viewing the MOSFET node voltages with an oscilloscope. If

it is breaking down either choose a higher voltage device,

add a snubber or specify an avalanche-rated MOSFET.

Place the small-signal components away from high fre-

quency switching nodes. This allows the use of a pseudo-

Kelvin connection for the signal ground, where high di/dt

gate driver currents flow out of the IC ground pin in one

direction (to the bottom plate of the VCC decoupling capaci-

tor) and small-signal currents flow in the other direction.

Keep the trace from the feedback divider tap to the FB pin

short to preclude inadvertent pickup.

For applications with multiple switching power converters

connected to the same input supply, make sure that the

input filter capacitor for the LT3825 is not shared with

other converters. AC input current from another converter

could cause substantial input voltage ripple and this could

interfere with the LT3825 operation. A few inches of PC

trace or wire (L @ 100nH) between the CIN of the LT3825

and the actual source VIN is sufficient to prevent current

sharing problems.

APPLICATIONS INFORMATION

CVIN

GATE

TURN-ON

GATE

TURN-ON

RSENSE

• •

CVCC

VCC

GND

LT3825

VCC

VIN

GND

LT3825

GATE

TURN-OFF

GATE

TURN-OFF

COUT

3825 F09

OUT

•

Figure 9. High Current Paths

LT3825

3825fe

TYPICAL APPLICATIONS

48V to 5V at 8A Isolated Supply

100k12k

•

VOUT+

VIN+

36V TO 72V

0.03Ω

Si4490DY

P6SMB100A

MBRS1100

15k

ALL CAPACITORS 25V UNLESS OTHERWISE NOTED

T1: EDFD25-3F3 GAP FOR LP = 200µH (i.e., AL = 200nH/T2)

3.01k

20Ω

47µF

20V

47k

1/4W

0.1µF

29.4k

402k

BAS21

2.1k

1% 100k

100k

680pF

10k

15Ω

B0540W

47Ω

470µF

6TPE470MI

×4

FMMT718 FMMT618

10Ω

1/4W

PA0184

1 4

BAT54

330Ω

47pF

2.2µF

100V

0.1µF

0.22µF

10nF

2.2nF

0.1µF

1µF

0.1µF

2.2nF

250V

Si7336ADP

×2

1nF

3825 TA02a

tON SYNC

PGDLY

UVLO SENSE–

SENSE+

RCMP ENDLY OSC

LT3825

GND SFST

VCC SG

CCMP

PINS 1 TO 3, 32T OF 2 × 32AWG

PINS 4 TO 5, 11T OF 1 × 32AWG

PINS 1 TO 3, 32T OF 2 × 32AWG

PINS 10, 11, 12 TO PINS 7, 8, 9, 4T OF 5 MIL COPPER FOIL

PINS 1 TO 3, 32T OF 2 × 32AWG

2 MIL

POLYESTER

FILM

Efficiency vs Load Current

LOAD CURRENT (A)

EFFICIENCY (%)

3825 TA02b

2 3 5

678

36VIN

72VIN

48VIN

Output Regulation vs Load Current

LOAD CURRENT (A)

4.75

OUTPUT (V)

4.80

4.90

4.95

5.00

5.25

5.10

356

3825 TA02c

4.85

5.15

5.20

5.05

2478

36VIN

72VIN

48VIN

LT3825

3525fe

TYPICAL APPLICATIONS

48V to 3.3V at 6A Isolated Supply

Efficiency vs Load Current Output Regulation vs Load Current

100k15k

•

VOUT+

3.3V

VIN+

36V TO 72V

0.04Ω

Si4490DY

Si7892DP

15k

3.01k

20Ω

47µF

20V

47k

1/4W

0.1µF

26.1k

402k

BAS21

866Ω

1% 62k

10k

680pF

10k

15Ω

B0540W 47Ω

150µF

6TPB150ML

×3

PA0184

1 4

BAT54

330Ω

47pF

0.82µF

100V

0.1µF

0.22µF

3.3nF

2.2nF

0.1µF

1µF

0.1µF

PULSE PB2134

2.2nF

250V

3825 TA03a

tON SYNC

PGDLY

UVLO SENSE–

SENSE+

RCMP ENDLY OSC

LT3825

GND SFST

VCC SG

CCMP

FMMT718

FMMT618

LOAD CURRENT (A)

EFFICIENCY (%)

3825 TA03b

80 2346

36VIN

72VIN

48VIN

LOAD CURRENT (A)

3.38

3.43

3825 TA03c

3.33

3.28

2 3 4 6

3.23

3.18

3.13

OUTPUT (V)

36VIN

72VIN 48VIN

LT3825

3825fe

TYPICAL APPLICATIONS

48V to 3.3V at 12A Isolated Supply

Efficiency vs Load Current Output Regulation vs Load Current

100k12k

3.01k

28.7k

402k

20Ω 47Ω

47k

1/4W

BAS21

20Ω

•

100pF

250V 2.2nF

250V

C1 TO C4

47µF ×3

470µF

0.1µH VOUT+

3.3V

12A

VIN+

36V TO 72V T1

0.02Ω

1/2W

47µF Si4490DY

15k

750Ω 150k 10k

C1 TO C4: TDK C3225X5R0J476M

C5: SANYO 6TPD470M

L1: VISHAY IHLP2525CZERR10M

Q1: ZETEX FMMT618

Q2: ZETEX FMMT718

T1: PULSE PA1477NL

10k BAT54

B0540W

15Ω

PA0184

330Ω

47pF

2.2µF

100V

0.1µF

0.01µF

1nF

10nF

2.2nF

0.1µF

3825 TA04a

1µF

tON SYNC

PGDLY

UVLO

SENSE–

SENSE+

RCMP ENDLY OSC

LT3825

GND SFST

VCC SG

CCMP

Si7336ADP

•

LOAD CURRENT (A)

EFFICIENCY (%)

379

3825 TA04b

611 12

458 10

36VIN

72VIN

48VIN

LOAD CURRENT (A)

3.13

OUTPUT (V)

3.23

3.33

3.43

3.18

3.28

3.38

4 6 8 10

3825 TA04c

122

36VIN

72VIN

48VIN

LT3825

3525fe

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE16 (BC) TSSOP REV J 1012

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

1 3 4 5678

DETAIL B IS THE PART OF

THE LEAD FRAME FEATURE

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

4.90 – 5.10*

(.193 – .201)

16 1514 13 12 11

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC

2.94

(.116)

0.48

(.019)

REF

0.51

(.020)

REF

0.195 – 0.30

(.0077 – .0118)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

2.94

(.116)

3.58

(.141)

3.58

(.141)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev J)

Exposed Pad Variation BC

DETAIL B

LT3825

3825fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

B 12/09 Change to Absolute Maximum Ratings

Change to Electrical Characteristics

Change to Pin Functions

Change to Block Diagram

Change to Flyback Feedback Amplifier

Text Change to Applications Information

Change to Typical Application

Change to Related Parts

2, 3

C 01/10 Change TA = 25°C to TJ = 25°C

Addition to Note 3

2, 3

D 11/12 Changed Typical Application schematic's circuit rating 1

Temperature grade clarification in Note 3 3

E 12/12 Updated G21 graph

Updated package

(Revision history begins at Rev B)

LT3825

3525fe

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2007

LT 1212 REV E • PRINTED IN USA

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