CS43L43
DS479PP1 25
6.0 APPLICATIONS
6.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS43L43 requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance. Figure 5 shows the recommended power
arrangement with VA, VA_HP and VL connected
to clean supplies. Decoupling capacitors should be
located as c lose to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.
6.2 Clock Modes
The CS43L43 operates in one of two clocking
modes. Base Rate Mode supports input sample
rates up to 50 kHz while High Rate Mode supports
input sample rates up to 100 kHz, see Table 10 and
11. All clock modes use 64x oversampling.
6.3 De-Emphasis
The CS43L43 includes on-chip digital de-empha-
sis. Figure 27 shows the de-emphasis curve for Fs
equal to 44.1 kHz. The frequency response of the
de-emphasis curve will scale proportionally with
changes in sample rate, Fs.
The de-emphasis feature is included to accommo-
date older audio recordings that utilize pre-empha-
sis equalization as a means of noise reduction.
6.4 Recommended Power-up Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and
VQ_HP will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ_HP low and will initiate the
Stand-Alone power-up sequence. The control port
will be acces sible at thi s time. If Control Po rt oper-
ation is desired, write the CP_EN bit prior to the
completion of the Stand-Alone power-up se-
quence, approximately 1024 LRCK cycles. Writ-
ing this bit will halt the Stand-Alone power-up
sequence and initialize the control port to its default
settings. The desired register settings can be loaded
while keeping the PDN bit set to 1.
3. If Control Port Mode is selected via the CP_EN
bit, set t he PDN bit to 0 which wi ll initiate the po w-
er-up sequence, which requires approximately
50 µS when the POR bit is set to 0. If the POR bit
is set to 1, see Section 6.5 for total power-up tim-
ing.
6.5 Popguard® Transient Control
The CS43L43 uses Popguard® technology to mini-
mize the effects of output transients during pow-
er-up and power-down. This technique minimizes
the audio transients commonly produced by sin-
gle-ended, single-supply converters whe n it is im-
plemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is initially powered-up, the audio
outputs, HP_A and HP_B, are clamped to GND.
Following a delay of approximately 1000 sample
periods, each output begins to ramp toward the qui-
escent voltage. Approximately 10,000 left/right
clock cycles later, the outputs reach VQ_HP and au-
dio output begins . This gradual voltage rampi ng al-
lows time for the external DC-blocking capacitor to
charge to the quiescent voltage, minimizing the
power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output
buffers are disconnected from HP_A and HP_B. In
their place, a soft-start current sink is substituted
which allows the DC-blocking capacito rs to slowly
discharge. Once this charge i s dissipated, the pow-
er to the device may be turned off and the system is
ready for the next power-on.