Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Features
l16-Pin TSSOP package
l1.8 to 3.3 Volt supply
l24-Bit conversion / 96 kHz sample rate
l94 dB dynamic range at 3 V supply
l-85 dB THD+N at 1.8 V supply
lLow power consumption
lDigital volume co ntrol
96 dB attenuation, 1 dB step size
lDigital bass and treble boost
Selectable cor ner frequencies
Up to 12 dB boost in 1 dB increments
lPeak signal limiting to prevent clipping
lDe-emphasis for 32 kHz, 44.1 kHz, and
48 kHz
lHeadphone amplifier
up to 25 mWrms power output into 16 load*
25 dB analog attenuation and mute
Zero crossing cl ick free level transitions
lATAPI mixing functio ns
* 1 kHz sine wave at 3.3V supply
Description
The CS43L43 is a complete stereo digital-to-analog out-
put syst em i nc lud in g in ter pol ation, 1-bit D/A c onv ers ion ,
analog filtering, volume control, and a headphone ampli-
fier, in a 16-pin TSSOP package.
The CS43L43 is based on delta-sigma modulation,
where the modulator output controls the reference volt-
age input to an ultra-linear analog low-pass filter. This
arch itec ture al lows inf inite adjustm ent of the samp le rate
between 2 kHz and 100 kHz simply by changing the
maste r cl oc k fre que nc y.
The CS43L43 contains on-chip digital bass and treble
boost, peak signal limiting and de-emphasis. The
CS43L43 o perates from a +1 .8 V to +3.3 V supply and
consumes only 16 mW of power with a 1.8 V supply.
These featu res are idea l for porta ble CD, MP3 and M D
players and other portable playback systems that require
extremely low power consumption.
ORDERING INFORMATION
CS43L43-KZ -10 to 70 °C 16-pin TSSOP
CDB43L43 Evaluation Board
SCLK/DEM
SDATA
DIF1/SDA
MCLK
VA_HP
HP_A
SERIAL
PORT
DE-
CONTROL PORT
∆Σ
DAC
RST
LRCK
DIF0/SCL
VA
VL
DIGITAL
VOLUME
CONTROL
∆Σ
DAC
DIGITAL
FILTERS
ANALOG
FILTER
ANALOG
FILTER
GND FILT+ REF_GND
ANALOG
VOLUME
CONTROL HEAD-
PHONE
AMPLIFIER
ANALOG
VOLUME
CONTROL
HP_B
EMPHASIS
VQ_HP
BASS/TREBLE
BOOST
LIMITING
CS43L43
Low Voltage, Stereo DAC with Headphone Amp
FEB 00
DS479PP1
CS43L43
2DS479PP1
TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................4
ANALOG CHARACTERISTICS..........................................................................4
POWER AND THERMAL CHARACTERIS TICS ................ ....... .........................6
DIGITAL CHARACTERISTICS...........................................................................7
ABSOLUTE MAXIMUM RATINGS.....................................................................7
RECOMMENDED OPERATING CONDITIONS.................................................7
SWITCHING CHAR ACTERISTICS........... ...... ...... ....... ...... ....... ...... ....... ...... ......8
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE 10
2.0 TYPICAL CONNECTION DIAGRAM ...............................................................11
3.0 REGISTER QUICK REFERENCE .....................................................................12
4.0 REGISTER DESCRIPTION ...............................................................................13
4.1 Power and Muting Control (address 01h).................................................13
4.2 Channel A Analog Attenuation Control (address 02h) (VOLA).................15
4.3 Channel B Analog Attenuation Control (address 03h) (VOLB).................15
4.4 Channel A Digital Volume Control (address 04h) (DVOLA) ......................15
4.5 Channel B Digital Volume Control (address 05h) (DVOLb).......................15
4.6 Tone Control (address 06h).......................................................................16
4.7 Mode Control (address 07h)......................................................................17
4.8 Limiter Attack Rate (address 08h) (ARATE)..............................................18
4.9 Limiter Release Rate (address 09h) (RRATE) ......................................19
4.10 Volume and Mixing Control (address 0Ah)..............................................19
4.11 Mode Control 2 (address 0Bh).................................................................21
5.0 PIN DESCRIPTION ............................................................................................22
6.0 APPLICATIONS .................................................................................................25
6.1 Grounding and Power Supply Decoupling ................................................25
6.2 Clock Modes .............................................................................................25
6.3 De-Emphasis ............................................................................................25
6.4 Recommended Power-up Sequence ........................................................25
6.5 Popguard® Transient Control ...................................................................25
7.0 CONTROL PORT INTERFACE .........................................................................26
7.1 Memory Address Pointer (MAP).................................................................27
8.0 PARAMETER DEFINITIONS .............................................................................35
Total Harmonic Distortion + Noise (THD+N) ....................................................35
Dynamic Range................................................................................................35
Contacting Cirrus Logi c Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I
2
C is a reg is tered trademark of Philips Semiconductors.
PopGuard is a trademark , Crystal is a registered trademark of Cirrus Logic, Inc.
Preliminary product inf o rmation descri bes pr oduct s whi ch are in prod uct i on, but for whic h ful l characterizat i on da t a is not yet availab le . Ad vance p roduct infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained i n this docum ent is accurate and reli able. However , the i nfor mation is sub ject to change with out no tice and i s provi ded AS IS without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of pa tent s o r ot h er ri ghts
of third parties. Thi s document i s the propert y of Cirru s Logic, I nc. and implie s no licen se under patent s, copy rights, trademarks, or trade secre ts. No part of
this publicati o n may be copied, reproduced, stored in a retr i eval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) wi t hou t the prior written consen t of Ci rrus Lo gi c, Inc. I tems from any Cirrus Logi c websi te or disk may be printed f or use by t he user . However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS43L43
DS479PP1 3
Interchannel Isolation .......................................................................................35
Interchannel Gain Mismatch.............................................................................35
Gain Error.........................................................................................................35
Gain Drift ..........................................................................................................35
9.0 REFERENCES ...................................................................................................35
10.0 PACKAGE DIMENSIONS ...............................................................................36
LIST OF FIGURES
Figure 1. External Serial Mode Input Timing .....................................................................9
Figure 2. Internal Ser ial Mod e Input Timing ................... ...... .................... ...... ....... ...... ......9
Figure 3. Internal Ser ial Clo ck Genera tio n ........ ....... ................... ...... ....... ...... ....... ...... ......9
Figure 4. Control Port Timing - Two-Wire Mode ..............................................................10
Figure 5. Typical Conn ec tio n Diagram ........ ...... ....... ...... ...... ....... ...... .................... ...... ....11
Figure 6. Control Port Timing, Two-Wire Mode ...............................................................27
Figure 7. Base-Rate Stopband Rejection ........................................................................28
Figure 8. Base-Rate Transition Band ..............................................................................28
Figure 9. Base-Rate Transition Band (Detail) ..................................................................28
Figure 10. Base-Rate Passband Ripple ..........................................................................28
Figure 11. High-Rate Stopband Rejection .......................................................................28
Figure 12. High-Rate Transition Band .............................................................................28
Figure 13. High-Rate Transition Band (Detail) ................................................................29
Figure 14. High-Rate Passband Ripple ...........................................................................29
Figure 15. Output Test Load ............................................................................................29
Figure 16. CS43L43 Control Port Mode - Serial Audio Format 0 (I2S) ............................ 30
Figure 17. CS43L43 Control Port Mode - Serial Audio Format 1 (I2S) ............................ 30
Figure 18. CS43L43 Control Port Mode - Serial Audio Format 2 ....................................30
Figure 19. CS43L43 Control Port Mode - Serial Audio Format 3 ....................................31
Figure 20. CS43L43 Control Port Mode - Serial Audio Format 4 ....................................31
Figure 21. CS43L43 Control Port Mode - Serial Audio Format 5 ....................................31
Figure 22. CS43L43 Control Port Mode - Serial Audio Format 6 ....................................32
Figure 23. CS43L43 Stand-Alone Mode - Serial Audio Format 0 (I2S) ...........................32
Figure 24. CS43L43 Stand-Alone Mode - Serial Audio Format 1 ....................................32
Figure 25. CS43L43 Stand-Alone Mode - Serial Audio Format 2 ....................................33
Figure 26. CS43L43 Stand-Alone Mode - Serial Audio Format 3 ....................................33
Figure 27. De-Emphasis Curve .......................................................................................34
Figure 28. ATAPI Block Diagram .....................................................................................34
LIST OF TABLES
Table 1. Example Analog Volume Settings .....................................................................15
Table 2. Example Digital Volume Settings ......................................................................15
Table 3. Example Bass Boost Settings ...........................................................................16
Table 4. Example Treble Boost Settings .........................................................................16
Table 5. Example Limiter Attack Rate Settings ...............................................................18
Table 6. Example Limiter Release Rate Settings ............................................................19
Table 7. ATAPI Decode ...................................................................................................20
Table 8. Digital Interface Format .....................................................................................21
Table 9. Stand Alone De-Emphasis Control ....................................................................23
Table 10. HRM Common Clock Frequencies ..................................................................23
Table 11. BRM Common Clock Frequencies ..................................................................23
Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) ......................23
CS43L43
4DS479PP1
1.0 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 °C; GND = 0 V; Logic "1" = VL = 1.8 V; Logic "0" =
GND = 0 V; Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to
20 kHz, unless otherwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz; Fs for High-Rate Mode =
96 kHz, SCLK = 6.144 MHz. Test load RL=16, CL = 10 pF (See Figure 15))
Notes: 1. One-half LSB of triangular PDF dither is added to data.
Parameter
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Headph one Output Dynamic Performance for VA = VA_HP = 1.8 V
Dynami c Rang e (Note 1)
18 to 24-Bit unweight ed
A-Weighted
16-Bit unweighted
A-Weighted
TBD
TBD
-
-
88
91
86
89
-
-
-
-
TBD
TBD
-
-
89
92
87
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-82
-68
-28
-80
-66
-26
TBD
-
-
-
-
-
-
-
-
-
-
-
-85
-69
-29
-83
-67
-27
TBD
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 66 - - 66 - dB
Headph one Output Dynamic Performance for VA = VA_HP = 3.0 V
Dynami c Rang e. (Note 1)
18 to 24-Bit. unweight ed
A-Weighted
16-Bit. unweighted
A-Weighted
TBD
TBD
-
-
91
93
89
91
-
-
-
-
TBD
TBD
-
-
92
94
90
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise. (Note 1)
18 to 24-Bit. 0 dB
-20 dB
-60 dB
16-Bit. 0 dB
-20 dB
-60 dB
THD+N -
-
-
-
-
-
-76
-71
-31
-78
-69
-29
TBD
-
-
-
-
-
-
-
-
-
-
-
-73
-72
-32
-78
-70
-30
TBD
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation. (1 kHz) - 66 - - 66 - dB
CS43L43
DS479PP1 5
ANALOG CHARACTERISTICS (Continued)
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-14) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
4. Referenced to a 1 kHz, full-scale sine wave.
5. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
6. De-empha si s is not available in High-Rate Mod e.
Parameters Symbol Min Typ Max Units
Analog Output
Full Scale Headphone Output Voltage TBD 0.55 x VA TBD Vpp
Headphone Output Quiescent Voltage VQ_HP -0.5 x VA_HP- VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Maximum Headphone Output VA=VA_HP=1.8V
AC-Current VA=VA_HP=3.0V IHP -
-31
52 -
-mA
mA
Parameter
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response (Note 2)
Passband (Note 3)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4535
-
.4998
-
0
0
-
-
-
-
.4426
.4984
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz
(Note 4) -.02 - +.08 0 - +0.11 dB
StopBand .5465 - - .577 - - Fs
StopBand Attenuation (Note 5) 50 - - 55 - - dB
Group Delay tgd - 9/Fs - - 4/Fs - s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz -
--
±0.36/Fs -
--
-±1.39/Fs
±0.23/Fs -
-s
s
De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+.2/-.1
+.05/-.14
+0/-.22 (Note 6) dB
dB
dB
CS43L43
6DS479PP1
POWER AND THERMAL CHARACTERISTICS GND = 0 V ( All voltages with respect to
ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)
Notes: 7. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
8. Valid with the recommended capacitor values on FILT+ and VQ_HP as shown in Figure 5. Increasing
the capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor
type, as any leakage current in excess of 1.0 µA will cause degradation in analog performance.
Base-rate Mode
Parameters Symbol Min Typ Max Units
Power Supplies
Power Su pply Cur rent- VA=1.8V
Normal Operation VA_HP=1.8V
VL=1.8V
IA
IA_HP
ID_L
-
-
-
7.3
1.5
4
-
-
-
mA
mA
µA
Power Su pply Cur rent- VA=1.8V
Power Down Mode (Note 7) VA_HP=1.8V
VL=1.8V
IA
IA_HP
ID_L
-
-
-
TBD
TBD
TBD
-
-
-
µA
µA
µA
Power Su pply Cur rent- VA=3.0V
Normal Operation VA_HP=3.0V
VL=3.0V
IA
IA_HP
ID_L
-
-
-
10.5
1.5
9.3
-
-
-
mA
mA
µA
Power Su pply Cur rent- VA=3.0V
Power Down Mode (Note 7) VA_HP=3.0V
VL=3.0V
IA
IA_HP
ID_L
-
-
-
TBD
TBD
TBD
-
-
-
µA
µA
µA
Total Power Dissipation- All Supplies=1.8V
Normal Operation All Supplies=3.0V -
-16
36 TBD
TBD mW
mW
Max Headphone Power Dissipation
With Full-scale Output VA_HP=1.8V
and 16ohm Load VA_HP= 3.0 V -
-TBD
TBD -
-mW
mW
Package Thermal Resistance θJA -75-°C/Watt
Power Supply Rejection Ratio (Note 8) 1 kHz
60 Hz PSRR -
-60
40 -
-dB
dB
CS43L43
DS479PP1 7
DIGITAL CHARACTERISTICS (TA = 25°C; VL = 1.7V - 3.6V; GND = 0 V)
ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; al l vol ta ge s with resp ect to gr ou nd .)
9. To prevent clipping the outputs, VA_HPMIN is limited by the Full-Scale Output Voltage VFS_HP, where
VA_HP must be 200 mV greater than VFS_HP. However, if distortion is not a concern, VA_HP may be
as low as 0.9 V at any time.
Parameters Symbol Min Typ Max Units
High-L ev el Inpu t Vol tage VIH 0.7 x VL - - V
Low-Level Input Voltage VIL - - 0.3 x VL V
Input Leakage Current Iin --±10µA
Input Capacitance - 8 - pF
Parameters Symbol Min Max Units
DC Power Supplies: Positive Analog
Headphone
Digital I/O
VA
VA_HP
VL
-0.3
-0.3
-0.3
4.0
4.0
4.0
V
V
V
Input Current, Any Pin Except Supplies Iin 10mA
Digital Input Voltage VIND -0.3 VL + 0.4 V
Ambient Operating Temperature (power applied) TA-55 125 °C
Storage Temperature Tstg -65 150 °C
Parameters Symbol Min Typ Max Units
Ambient Temperature TA-10 - 70 °C
DC Power Supplies: Positive Analog
Headphone (Note 9)
Digital I/O
VA
VA_HP
VL
1.7
0.9
1.7
-
-
-
3.6
3.6
3.6
V
V
V
CS43L43
8DS479PP1
SWITCHING CHARACTERISTICS (TA = -10 to 70°C; VA = 1.7V - 3.6V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20pF)
Notes: 10. In Internal SCLK Mode, the duty cycle must be 50% +/− 1/2 MCLK Period.
Parameters Symbol Min Typ Max Units
Input Sample Rate Base Rate Mode
High Rate Mode Fs
Fs 2
50 -
-50
100 kHz
kHz
MCLK Pulse Width High MCLK/LRCK = 1024 7 - - ns
MCLK Pulse Width High MCLK/LRCK = 1024 7 - - ns
MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns
MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns
MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns
MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only) 40 50 60 %
SCLK Pulse Width Low tsclkl 20 - - ns
SCLK Pulse Width High tsclkh 20 - - ns
SCLK Period Base Rate Mode tsclkw --ns
High Rate Mode tsclkw --ns
SCLK rising to LRCK edge delay tslrd 20 - - ns
SCLK rising to LRCK edge setup time tslrs 20 - - ns
SDATA valid to SCLK rising setup time tsdlrs 20 - - ns
SCLK rising to SDATA hold time tsdh 20 - - ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) (Note 10) - 50 - %
SCLK Period tsclkw --ns
SCLK rising to LRCK edge tsclkr --µs
SDATA valid to SCLK rising setup time tsdlrs --ns
SCLK rising to SDATA hold time Base Rate Mode tsdh --ns
High Rate Mode tsdh --ns
1
128
()Fs
----------------------
1
64
()Fs
-------------------
1
SCLK
-----------------
tsclkw
2
------------------
1
512
()Fs
---------------------- 10+
1
512
()Fs
----------------------15+
1
384
()Fs
----------------------15+
CS43L43
DS479PP1 9
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 1. External Serial Mode Input Timing Figure 2. Interna l Serial Mode Input Timin g
*The SCLK pulses shown are internal to the CS43L43.
SDATA
*INTERNAL
SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
SDATA
LRCK
MCLK
*
INTERNAL SCLK
1N
2N
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L43.
N equals MCLK divided by SCLK
CS43L43
10 DS479PP1
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE
(TA = 25 °C; VL = 1.7V - 3.6V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 30 pF)
Notes: 11. The Two-Wire Mode is compatible with the I2C protocol.
12. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter Symbol Min Max Unit
Two-Wire Mode (Note 11)
SCL Clock Frequ enc y fscl -100kHz
RST Rising Edge to Start tirs 500 - ns
Bus Free Time Be tween Transmi ssio ns tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Fall ing (Note 12) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL trc -25ns
Fall T ime of SCL tfc -25ns
Rise Time SDA trd -1µs
Fall T ime of SDA tfd -300ns
Setup Time for Stop Condition tsusp 4.7 - µs
Figure 4. Control Port Timing - Two-Wire Mode
tbuf thdst thdst
tlow trc
tfc
thdd
thigh
tsud tsust
tsusp
Stop Start
Start
Stop
Repeated
SDA
SCL
tirs
RST
trd trd
CS43L43
DS479PP1 11
2.0 TYPICAL CONNECTION DIAGRAM
MCLK
LRCK
SCLK/DEM
SDATA
RST
DIF0/SCL
DIF1/SDA
GND
µc/
Digital
Audio
Source
VA VA_HP
HP_A
HP_B
FILT+
CS43L43
1.8 to 3.3 V
Supply
*Ferrite
bead
*1.0 µF 0.1 µF
+0.1 µF *1.0 µF
+
1.0 µF
0.9 to 3.3 V
Supply
*Ferrite
bead
220 µF
220 µF
1.8 to 3.3 V
Supply *1.0 µF 0.1 µF
+VL
*Ferrite
bead
+
+
+
12 13
4
5
1
3
2
10
14
16
6
15 9
8
7
11
1 K
1 K
47 µH
47 µH
*
Optional
Mode
Configuration
+
16
Headphones
1.0 µF
VQ_HP
REF_GND
Figure 5. Typical Connection Diagram
CS43L43
12 DS479PP1
3.0 REGISTER QUICK REFERENCE
Addr Function 7 6 5 4 3 2 1 0
0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
1h Power and Muting
Control AMUTE SZC1 SZC0 POR Reserved Reserved PDN Reserved
default 11010010
2h Channel A Analog
Attenuation Control VOLA7 VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0
default 00000000
3h Channel B Analog
Attenuation Control VOLB7 VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0
default 00000000
4h Channel A Digital
Volume Control DVOLA7 DVOLA6 DVOLA5 DVOLA4 DVOLA3 DVOLA2 DVOLA1 DVOLA0
default 00000000
5h Channel B Digital
Volume Control DVOLB7 DVOLB6 DVOLB5 DVOLB4 DVOLB3 DVOLB2 DVOLB1 DVOLB0
default 00000000
6h Tone Control BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0
default 00000000
7h Mode Control BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP
default 00000000
8h Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
default 00100000
9h Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
default 00010000
Ah Volume and Mixing
Control TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0
default 00001001
Bh Mode Control 2 MCLKDIV Reserved Reserved Reserved Reserved DIF2 DIF1 DIF0
default 00000000
CS43L43
DS479PP1 13
4.0 REGISTER DESCRIPTION
4.1 POWER AND MUTING CONTROL (ADDRESS 01H)
4.1.1 AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-
ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Digital and Analog
10 - Ramped Digital and Analog
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross Digital and Analog
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Digital and Analog
Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock pe-
riods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change
will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channe l.
76543210
AMUTE SZC1 SZC0 POR RESERVED RESERVED PDN RESERVED
11010010
CS43L43
14 DS479PP1
4.1.3 POPGUARD® TRANSIENT CONTROL (POR)
Default - 1
0 - Disabled
1 - Enabled
Function:
The Popguard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the
quiescent voltage during power-on or power-off when this feature is enabled. Please see section 6.5 for
implementation details.
4.1.4 POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state whenever this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to enabled on power-up and
must be disabled before normal operation will begin.
CS43L43
DS479PP1 15
4.2 CHANNEL A ANALOG ATTENUATION CONTROL (ADDRESS 02H) (VOLA)
4.3 CHANNEL B ANALOG ATTENUATION CONTROL (ADDRESS 03H) (VOLB)
Default = 0 dB (No attenuation)
Function:
The Analog Attenuation Control operates independently from the Digital Volume Control. The Analog At-
tenuation Control registers allow the user to attenuate the headphone output signal in 1 dB increments
from 0 to -25 dB, using the analog volume control. Attenuation settings are decoded as shown in Table 1,
using a 2s complement code. The volume changes are implemented as dictated by the Soft and Zero
Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted
as zero.
4.4 CHANNEL A DIGITAL VOLUME CONTROL (ADDRESS 04H) (DVOLA)
4.5 CHANNEL B DIGITAL VOLUME CONTROL (ADDRESS 05H) (DVOLB)
Default = 0 dB (No attenuation)
Function:
The Digital Volume Control allows the user to alter the signal level in 1 dB increments from +18 to -96 dB,
using the Digital Volume Control. Volume settings are decoded as shown in Table 2, using a 2s comple-
ment code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Pow-
er and Muting Control register. All volume settings less than - 96 dB are equivalent to muting the channel
via the ATAPI bits (See Section 4.10.4). NOTES: Setting this register to values greater than +18 dB will
cause distortion in the audio outputs.
76543210
VOLx7 VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0
00000000
Binary Code Decimal Value Volume Setting
00000000 0 0 dB
11110110 -10 -10 dB
11110001 -15 -15 dB
Table 1. Example A n alog Volume Settings
76543210
DVOLx7 DVOLx6 DVOLx5 DVOLx4 DVOLx3 DVOLx2 DVOLx1 DVOLx0
00000000
Binary Code Decimal Value Volume Setting
00001010 12 +12 dB
00000111 7 +7 dB
00000000 0 0 dB
11000100 -60 -60 dB
10100110 -90 -90 dB
Table 2. Example D i gi tal Volume Settings
CS43L43
16 DS479PP1
4.6 TONE CONTROL (ADDRESS 06H)
4.6. 1 BASS B OOST LEVEL (BB)
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.
4.6.2 TREBLE BOO ST LEVEL (TB)
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB. NOTE: Treble Boost is not available in High-Rate Mode.
76543210
BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0
00000000
Binary Code Decimal Value Boost Setting
0000 0 0 dB
0010 2 +2 dB
1010 6 +6 dB
1001 9 +9 dB
1100 12 +12 dB
Table 3. Example Bass Boost Settings
Binary Code Decimal Value Boost Setting
0000 0 0 dB
0010 2 +2 dB
1010 6 +6 dB
1001 9 +9 dB
1100 12 +12 dB
Table 4. Example Treble Boost Settings
CS43L43
DS479PP1 17
4.7 MODE CONTROL (ADDRESS 07H)
4.7. 1 BASS B OOST CORNE R FREQUENCY (BBCF)
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The bass boost corner frequency is user selectable as shown above.
4.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF)
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The treble boost corner frequency is user selectable as shown above. NOTE: Treble Boost is not avail-
able in High-Rate Mode.
4.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the
A Channel Attenuation and Volume Control Bytes and the B Channel Bytes are ignored when this function
is enabled.
4.7.4 DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (See Figure 27) NOTE: De-emphasis is not available in
High-Rate Mode.
76543210
BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP
00000000
CS43L43
18 DS479PP1
4.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When this function is enabled the digital volume control section is bypassed. This disables the digital vol-
ume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog attenuation con-
trol will remain functional.
4.8 LIMITER ATTACK RATE (ADDRESS 08H) (ARATE)
Default = 20h - 1 LRCK’s per 1/8 dB
Function:
The limiter attack rate is user selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}. Where
{value} is the decimal value in the Limiter Attack Rate register and RATE is in LRCKs per 1/8 dB of
change. NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of
the limiter. Use the LIM_EN bit to disable the limiter function (see Section 4.10.3).
76543210
ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
00100000
Binary Code Decimal Value LRCKs per 1/8 dB
00000001 1 32
00010100 20 1.6
00101000 40 0.8
00111100 60 0.53
01011010 90 0.356
Table 5. Example Limiter Attack Rate Settings
CS43L43
DS479PP1 19
4.9 LIMITER RELEASE RATE (ADDRESS 09H) (RRATE)
Default = 10h - 32 LRCKs per 1/8 dB
Function:
The limiter release rate is user selectable. The rate is a function of sampling frequency, Fs, and the value
in Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}. Where {val-
ue} is the decimal value in the Limiter Release Rate register and RATE is in LRCKs per 1/8 dB of change.
NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Section 4.10.3).
4.10 VOLUME AND MIXING CONTROL (ADDRESS 0AH)
4.10.1 TONE CONTROL MODE (TC)
Default = 00
00 - All set tings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to 00. Alternately, one of three pre-defined settings may be used.
4.10.2 TONE CONTROL ENABLE (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
76543210
RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
00010000
Binary Code Decimal Value LRCKs per 1/8 dB
00000001 1 512
00010100 20 25
00101000 40 12
00111100 60 8
01011010 90 5
Table 6. Example Limiter Release Rate Settings
76543210
TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0
00001001
CS43L43
20 DS479PP1
4.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS43L43 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, then the digital attenuation is increased. The attack rate is determined by the Limiter Attack
Rate register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user se-
lected level and then, the Bass Boost is increased back to the user selected level. The release rate is
determined by the Limiter Release Rate register. NOTE: The A=B bit should be set to 1 for optimal limiter
performanc e.
4.10.4 ATAPI CHANNEL MIXIN G AND MUTING (ATAPI)
Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS43L43 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Ta-
ble 7 and Figure 28 for additional information. NOTE: All mixing functions occur prior to the digital volume
control.
ATAPI3 ATAPI2 ATAPI1 ATAPI0 HP_A HP_B
0000 MUTE MUTE
0001 MUTE R
0010 MUTE L
0011 MUTE [(L+R)/2]
0100 R MUTE
0101 R R
0110 R L
0111 R [(L+R)/2]
1000 L MUTE
1001 L R
1010 L L
1011 L [(L+R)/2]
1100 [(L+R)/2] MUTE
1101 [(L+R)/2] R
1110 [(L+R)/2] L
1111 [(L+R)/2] [(L+R)/2]
Table 7. ATAPI Decode
CS43L43
DS479PP1 21
4.11 MODE CONTROL 2 (ADDRESS 0BH)
4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry. NOTE: Internal SCLK is not available when this function is enabled.
4.11.2 DIGITAL INTERFACE FORMAT (DIF)
Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 16-22. NOTE: Internal SCLK is not available
when MCLKDIV is enabled.
76543210
MCLKDIV RESERVED RESERVED RESERVED RESERVED DIF2 DIF1 DIF0
00000000
DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE
000I
2S, up to 24-bit data, 64 x Fs Internal SLCK 0 16
001I
2S, up to 24-bit data, 32 x Fs Internal SLCK 1 17
0 1 0 Left Justified, up to 24-bit data, 2 18
0 1 1 Right Justified, 24-bit data 3 1 9
1 0 0 Right Justified, 20-bit data 4 2 0
1 0 1 Right Justified, 16-bit data 5 2 1
1 1 0 Right Justified, 18-bit data 6 2 2
1 1 1 Identical to Format 1 1 17
Table 8. Digital Interface Format
CS43L43
22 DS479PP1
5.0 PIN DESCRIPTION
LRCK 1 Left/Right Clock (Input) - The Left/Right clock determines which channel is currently being
input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at
the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output
from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period
dif ference. The req uired re lationsh ip between th e Left/Right clo ck, seria l clock a nd serial dat a is
defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins
when in Stand-Alone mode. The options are detailed in Figures 16-26.
SDATA 2 Serial Audio Data (Input) - Twos complement MSB-first serial data is input on this pin. The
data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right
clock. The required relationship between the Left/Right clock, serial clock and serial data is
defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins
when in Stand-Alone mode. The options are detailed in Figures 16-26.
SCLK 3 Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. The
required rel atio ns hip between the L eft/ Ri gh t cl oc k, s eri al c lock and seri al dat a is define d by the
Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in
Stand-Alone mode. The options are detailed in Figures 16-26.
The CS3L43 supports both internal and external serial clock generation modes. The Internal
Serial Clock Mode eliminates possible clock interference from an external SCLK. Use of the
Internal Serial C lock Mode is always pref erre d.
Internal Serial C lock Mode - In the Internal Serial Clock Mode, the serial clock is internally
derived and sync hronous with the ma st er clock an d lef t/right c lock. The SCLK/ LRCK freq uency
ratio is either 32, 48, or 64 depending upon the Mode Control 2 (0Bh) register when in Control
Port Mode or the DIF1-0 pins when in S tand-Alone mode as shown in Figures 16-26. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK.
External Serial Clock Mode - The CS3L43 will enter the External Serial Clock Mode whenever
16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period.
The devic e will rev ert to Internal Seria l Clo ck Mode if no low to hi gh tra ns iti ons are d ete cte d on
the SCLK pin for 2 consecutive periods of LRCK.
Left/Right Clock LRCK RST Reset
Serial Data SDATA DIF1/SDA DIF1/SDA
Serial Clock/ DEM SCLK/DEM HP_B Headphone Output B
Interface Power VL VA_HP Headphone Amp Power
Master Clock MCLK VA Analog Power
DIF0/SCL DIF0/SCL GND Ground
HP Quiescent Voltage VQ_HP HP_A Headphone Output A
Reference Ground REF_GND FILT+ Positive Voltage Reference
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
CS43L43
DS479PP1 23
DEM 3 De-emphasis Control (Input) - When using Internal Serial Clock Mode, Pin 3 is available for
de-emphasis control and selects the 44.1 kHz de-emphasis filter, see Table 9 and Figure 30.
When using External Serial Clock Mode, de-emphasis control is not available.NOTE:
De-emphasis is not available in High-Rate Mode.
VL 4 Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.
MCLK 5 Master Clock (Input) - The master clock frequency must be either 256x, 384x, 512x, 768x or
1024x the inp ut s am pl e rat e in Bas e R a te M od e (BRM ) an d 12 8x , 19 2x, 256x o r 38 4x the inp ut
sample rat e in Hi gh Rate Mo de (HRM ). Note that some mu ltipli catio n factor s req uire set ting the
MCLKDIV bit (see Section 4.11.1). Tables 10 and 11 illustrates several standard audio sample
rates and the required master clock frequencies.
DIF0 and DIF1
(Stand-Alone Mo de) 6 & 15 Digit al In terface Format (Input) - The required relat ionsh ip between the Lef t/Right cl ock, seria l
clock and serial data is defined by the Digital Interface Format and the options are detailed in
Figures 23-26
SCL
(Control Port Mode) 6Serial Control Interface Clock (Input) - Clocks t he s erial c ont rol d at a into or ou t of SDA/C DIN .
External
DEMO DESCRIPTION
0 Disabled
1 44.1 kHz
T able 9. S tand Alone De-Emphasis Control
Sample Rate
(kHz)
MCLK (MHz)
HRM
128x 192x 256x* 384x*
32 4.0960 6.1440 8.1920 12.2880
44.1 5.6448 8.4672 11.2896 16.9344
48 6.1440 9.2160 12.2880 18.4320
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).
Table 10. HRM Common Clock Frequencies
Sample Rate
(kHz)
MCLK ( MHz)
BRM
256x 384x 512x 768x* 1024x*
32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 32.7680 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).
Table 11. BRM Common Clock Frequencies
.
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
00I
2S, up to 24-bit data 0 23
0 1 Left Justified, up to 24-bit data 1 24
1 0 Right Justified, 24-bit Data 2 25
1 1 Right Justified, 16-bit Data 3 26
Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode)
CS43L43
24 DS479PP1
VQ_HP 7 He adp hone Qu ies cent Voltage (Output) - Fil ter c on nec tio n fo r inte rna l he adp hon e am p q uie s-
cent reference voltage. A capacitor must be connected from VQ_HP to analog ground, as
shown in Figure 5. VQ_HP is not intended to supply external current. VQ_HP has a typical
source impedance of 250 k and any current drawn from this pin will alter device performance.
REF_GND 8 Reference Grou nd (Input) - Ground reference for the internal sampling circuits. Must be con-
nected to analog ground.
FILT+ 9 Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. An
external capacitor is required from FILT+ to analog ground, as shown in Figure 5. The recom-
me nded va lue will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz.
FILT+ is not intended to supply external current. FILT+ has a typical source impedance of
250 k and any current drawn from this pin will alter device performance.
HP_A and HP_B 10 & 14 Headp hone O utput s (Output) - The full s cale analo g headphon e output lev el is specifi ed in the
Analog Characteristics specifications table.
GND 11 Ground (Input) - Ground Reference.
VA 12 Analog Power (Input) - Analog power supply. Typically 1 .8 to 3.3 VDC.
VA_HP 13 Headphone Amp Pow er (Input) - Headphon e a mp lif ier pow e r s upp ly. Typically 0. 9 t o 3 .3 VDC.
SDA
(Control Port Mode) 15 Serial Control Dat a I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line.
RST 16 Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings, including the control port, when low. See Recommended Power-up
Sequence on page 25.
CS43L43
DS479PP1 25
6.0 APPLICATIONS
6.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS43L43 requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance. Figure 5 shows the recommended power
arrangement with VA, VA_HP and VL connected
to clean supplies. Decoupling capacitors should be
located as c lose to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.
6.2 Clock Modes
The CS43L43 operates in one of two clocking
modes. Base Rate Mode supports input sample
rates up to 50 kHz while High Rate Mode supports
input sample rates up to 100 kHz, see Table 10 and
11. All clock modes use 64x oversampling.
6.3 De-Emphasis
The CS43L43 includes on-chip digital de-empha-
sis. Figure 27 shows the de-emphasis curve for Fs
equal to 44.1 kHz. The frequency response of the
de-emphasis curve will scale proportionally with
changes in sample rate, Fs.
The de-emphasis feature is included to accommo-
date older audio recordings that utilize pre-empha-
sis equalization as a means of noise reduction.
6.4 Recommended Power-up Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and
VQ_HP will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ_HP low and will initiate the
Stand-Alone power-up sequence. The control port
will be acces sible at thi s time. If Control Po rt oper-
ation is desired, write the CP_EN bit prior to the
completion of the Stand-Alone power-up se-
quence, approximately 1024 LRCK cycles. Writ-
ing this bit will halt the Stand-Alone power-up
sequence and initialize the control port to its default
settings. The desired register settings can be loaded
while keeping the PDN bit set to 1.
3. If Control Port Mode is selected via the CP_EN
bit, set t he PDN bit to 0 which wi ll initiate the po w-
er-up sequence, which requires approximately
50 µS when the POR bit is set to 0. If the POR bit
is set to 1, see Section 6.5 for total power-up tim-
ing.
6.5 Popguard® Transient Control
The CS43L43 uses Popguard® technology to mini-
mize the effects of output transients during pow-
er-up and power-down. This technique minimizes
the audio transients commonly produced by sin-
gle-ended, single-supply converters whe n it is im-
plemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is initially powered-up, the audio
outputs, HP_A and HP_B, are clamped to GND.
Following a delay of approximately 1000 sample
periods, each output begins to ramp toward the qui-
escent voltage. Approximately 10,000 left/right
clock cycles later, the outputs reach VQ_HP and au-
dio output begins . This gradual voltage rampi ng al-
lows time for the external DC-blocking capacitor to
charge to the quiescent voltage, minimizing the
power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output
buffers are disconnected from HP_A and HP_B. In
their place, a soft-start current sink is substituted
which allows the DC-blocking capacito rs to slowly
discharge. Once this charge i s dissipated, the pow-
er to the device may be turned off and the system is
ready for the next power-on.
CS43L43
26 DS479PP1
To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the pow-
er-down state. If full discharge does not occur, a
transient will oc cur when the au dio output s are ini-
tially clamped to GND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance and the
output load. For example, with a 220 µF capacitor
and a 16 ohm load on the headphone outputs, the
minimum power-down time will be approximately
0.4 seconds.
Use of the Mute Control function on the line out-
puts is recommended for designs requiring the ab-
solute minimum in extraneous clicks and pops.
Also, use of the Mute Control function ca n enable
the system designer to achieve idle channel
noise/signal -to -noi se ratios. whic h are onl y limited
by the external mute circuit. See the CDB43L43
datasheet for a suggested mute circuit
7.0 CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
In Control Port Mode, SDA is a bi-directional data
line. Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 4. The 7-bit addr ess fie ld must be
0010000. The eighth bit of the address byte is the
R/W bit (high for a read, low for a write). If the op-
eration is a write, the next byte is the Memory Ad-
dress Pointer, MAP, which selects the register to be
read or written. The MAP is then followed by the
data to be written. If the operation is a read, then
the contents of the register pointed to by the MAP
will be output after the chip address.
The CS43L43 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
The Two-Wire control port mode is compatible
with the I2C protocol.
CS43L43
DS479PP1 27
7.1 MEMORY ADDRESS POINTER (MAP)
7.1.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = 0
0 - Disabled
1 - Enabled
7.1.2 MAP0-3 (MEMORY ADDRESS POINTER)
Default = 0000
76543210
INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0
00000000
SDA
SCL
001000
ADDR
AD0 R/W
Start
ACK DATA
1-8 ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 6. Control Port Timing, Two-Wire Mode
CS43L43
28 DS479PP1
Figure 7. Base-Rate Stopband Rejection Figure 8. Base-Rate Transition Band
Figure 9. Base-Rate Transition Band (Detail) Figure 10. Base-Rate Passband Ripple
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude dB
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude dB
Figure 11. High-Rate Stopband Rejection Figure 12. High-Rate Transition Band
CS43L43
DS479PP1 29
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude dB
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude dB
Figu re 13. High-Rate Tra n sition Band (D etail) Figu re 14. High-Rate Passband Ripple
HP_x
GND
220 µF
Vout
RLCL
+
Figure 15. Output Test Load
CS43L43
30 DS479PP1
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
I2S, Up to 24-Bit data and INT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 16. CS43L43 Control Port Mode - Serial Audio Format 0 (I2S)
Figure 17. CS43L43 Control Port Mode - Serial Audio Format 1 (I2S)
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
I2S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 18. CS43L43 Control Port Mode - Serial Audio Format 2
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
Left Justified, up to 24-Bit data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
CS43L43
DS479PP1 31
Figure 19. CS43L43 Control Port Mode - Serial Audio Format 3
LRCK
SCLK
Left Ch ann el
SDATA 65432107
23 22 21 20 19 18 65432107
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode External SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 20. CS43L43 Control Port Mode - Serial Audio Format 4
LRCK
SCLK
Left Channel Right Channel
SDATA 6543210987
15 14 13 12 11 10
10 6543210987
15 14 13 12 11 10
17 16 17 16
32 clocks
19 18 19 18
Internal SCLK Mode External SCLK Mode
Right Justified, 20-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 20-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 40 Cycles per LRCK Period
Figure 21. CS43L43 Control Port Mode - Serial Audio Format 5
LRCK
SCLK
Left Ch ann el Right Channel
SDATA 6543210987
15 14 13 12 11 10 6543210987
15 14 13 12 11 10
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
CS43L43
32 DS479PP1
Figure 22. CS43L43 Control Port Mode - Serial Audio Format 6
LRCK
SCLK
Left Channel Right Chan ne l
SDATA 6543210987
15 14 13 12 11 10
10 6543210987
15 14 13 12 11 10
17 16 17 16
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 18-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 36 Cycles per LRCK Period
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
I2S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 23. CS43L43 Stand-Alone Mode - Serial Audio Format 0 (I2S)
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figu re 24. CS43L43 Stand-Alone Mode - Serial Audio Format 1
CS43L43
DS479PP1 33
LRCK
SCLK
Left Ch ann el
SDATA 65432107
23 22 21 20 19 18 65432107
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode External SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figu re 25. CS43L43 Stand-Alone Mode - Serial Audio Format 2
LRCK
SCLK
Left Ch ann el Right Channel
SDATA 6543210987
15 14 13 12 11 10 6543210987
15 14 13 12 11 10
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figu re 26. CS43L43 Stand-Alone Mode - Serial Audio Format 3
CS43L43
34 DS479PP1
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 27. De-Emphasis Curve
Σ
HP_A
HP_B
Left Channel
Audio Data
Right Channel
Audio Data
Channel B
Digital
Volume
Control
MUTE
EQ Analog
Volume
Control
Channel A
Digital
Volume
Control MUTE
EQ Analog
Volume
Control
Figure 28. ATAPI Block Diagram
CS43L43
DS479PP1 35
8.0 PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converters
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
9.0 REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Conver ters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4343 Evaluation Board Datasheet
3) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
CS43L43
36 DS479PP1
10.0 PACKAGE DIMENSIONS
Notes: 1. D and E1 are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of b dimension at maximum material condition. Dambar intrusion shall not
reduce dim ens io n b by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.043 -- -- 1.10
A1 0.002 -- 0.006 0.05 -- 0.15
A2 0.033 0.035 0.037 0.85 0.90 0.95
b 0.008 -- 0.012 0.19 -- 0.30 2,3
D -- 0.197 -- -- 5.00 -- 1
E -- 0.252 -- -- 6.40 --
E1 0.169 0.173 0.177 4.30 4.40 4.50 1
e -- 0.026 -- -- 0.65 --
L 0.020 0.024 0.028 0.50 0.60 0.70
0°-- 8°0°-- 8°
JEDEC #: MO-150
16L SSOP PACKAGE DRAWING
E
N
123
e b A1
A2 A
D
SEATING
PLANE
E1
L
SIDE VIEW
END VIEW
TOP VIEW
• Notes •