TDA8793 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Objective speciﬁcation

File under Integrated Circuits, IC02 1998 May 14

INTEGRATED CIRCUITS

TDA8793

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter

1998 May 14 2

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

FEATURES

•8-bit low-power ADC (170 mW typical)

•2.7 to 3.6 V operation

•Sampling rate up to 100 Msps

•Track-and-hold circuit

•CMOS/TTL compatible digital inputs and outputs

•Internal references

•Power-down mode; 5 mW.

APPLICATIONS

•Radio communications

•Digital data storage read channels

•Medical imaging

•Digital instrumentation.

GENERAL DESCRIPTION

The TDA8793 is an 8-bit low-power Analog-to-Digital

Converter (ADC) which includes a track-and-hold circuit

and an internal reference. The device converts an analog

input signal, up to 100 MHz, into 8-bit binary codes at a

maximum sample rate of 100 Msps. All digital inputs and

output are TTL/CMOS compatible.

The power-down mode enables the device power

consumption to be reduced to 5 mW.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCCA analog supply voltage 2.7 3.0 3.6 V

VCCD digital supply voltage 2.7 3.0 3.6 V

VCCO output stages supply voltage 2.7 3.0 3.6 V

ICCA analog supply current −40 −mA

ICCD digital supply current −16 −mA

ICCO output stages supply current −0.1 −mA

INL integral non linearity ramp input;

fCLK = 100 MHz;

VCCA =V

CCD =3V

−±1 tbf LSB

DNL differential non-linearity ramp input;

fCLK = 100 MHz;

VCCA =V

CCD =3V

−±0.75 tbf LSB

fCLK(max) maximum clock input frequency 100 −−MHz

Ptot total power dissipation VCC =3V −tbf −mW

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA8793 LQFP32 plastic low proﬁle quad ﬂat package; 32 leads; body 5 ×5×1.4 mm SOT401-1

1998 May 14 3

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGR016

TRACK-AND-

HOLD ADC LATCHES CMOS

OUTPUTS

VREFOUT = 1.85 V

VSDN = 1.25 V

REFERENCE

INN

REFOUT 2

REFIN

SDN

STDBY

INP

CLK

TEN

DEC

AGND

VCCA

VCCD

VCCO2

VCCO1

CLOCK DRIVER

DGND

OGND1

ODGND2

TDA8793

1998 May 14 4

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected

REFIN 2 reference input for ADC

INN 3 negative input

INP 4 positive input

REFOUT 5 reference for AC coupling

AGND 6 analog ground

VCCA 7 analog supply voltage

STDBY 8 standby mode input; (active HIGH)

DGND 9 digital ground

VCCD 10 digital supply voltage

CLK 11 clock input

TEN 12 track enable input; (active LOW)

n.c. 13 not connected

n.c. 14 not connected

D0 15 data output bit 0 (LSB)

D1 16 data output bit 1

D2 17 data output bit 2

D3 18 data output bit 3

OGND1 19 output ground 1

VCCO1 20 output supply voltage 1

OGND2 21 output ground 2

VCCO2 22 output supply voltage 2

D4 23 data output bit 4

D5 24 data output bit 5

D6 25 data output bit 6

D7 26 data output bit 7 (MSB)

n.c 27 not connected

n.c 28 not connected

n.c 29 not connected

n.c 30 not connected

DEC 31 decoupling

SDN 32 stabilized decoupling node

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8793

MGR017

n.c.

REFOUT

STDBY

VCCA

INN

AGND

DGND

CLK

n.c.

VCCD

D0 D7

n.c.

SDN

n.c.

VCCO2

VCCO1

n.c.

OGND2

DEC

n.c.

D1 D6

OGND1

n.c.

TEN

INP

REFIN

1998 May 14 5

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCCA analog supply voltage −0.3 +7.0 V

VCCD digital supply voltage −0.3 +7.0 V

VCCO output stages supply voltage −0.3 +7.0 V

∆VCC supply voltage differences between:

VCCA and VCCD −1.0 +1.0 V

VCCO and VCCD −1.0 +1.0 V

VCCA and VCCO −1.0 +1.0 V

VINP, INN input voltage range referenced to AGND −0.3 +7.0 V

IOoutput current −10 mA

Tstg storage temperature −55 +150 °C

Tamb operating ambient temperature 0 70 °C

Tjjunction temperature −−°C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 94 °C/W

1998 May 14 6

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

CHARACTERISTICS

VCCA =V

7to V6= 2.7 to 3.6 V; VCCD =V

10 to V9= 2.7 to 3.6 V; VCCO =V

20 (or V22) to V19 (or V21) = 2.7 to 3.6 V;

AGND to DGND and OGND shorted together; VCCA to VCCD =−0.15 to +0.15 V; VCCD to VCCO =−0.15 to +0.15 V;

VCCA to VCCO = −0.15 to +0.15 V; Tamb = 0 to 70 °C; typical values measured at VCCA =V

CCD =V

CCO = 3.0 V and

Tamb =25°C unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VCCA analog supply voltage 2.7 3.0 3.6 V

VCCD digital supply voltage 2.7 3.0 3.6 V

VCCO output stages supply voltage 2.7 3.0 3.6 V

ICCA analog supply current −40 −mA

ICCD digital supply current −16 −mA

ICCO output stages supply current fi= ramp input −0.1 −mA

fi= 50 MHz −tbf −mA

Internal reference (SDN pin); note 1

Vref reference voltage −1.25 −V

Vreg line regulation voltage 2.7 < VCCA < 3.6 V −2−mV

TC temperature coefﬁcient −tbf −ppm/K

ILload current −500 −−µA

Internal reference (pin REFOUT)

Vo(ref) reference voltage −1.85 −V

Vo(reg) line regulation voltage 2.7 < VCCA < 3.6 V −3−mV

TC temperature coefﬁcient −tbf −ppm/K

ILload current −500 −−µA

Clock input (pin CLK); note 2

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2 −VCCD V

IIL LOW-level input current VCLK =0 −2−+2 µA

IIH HIGH-level input current VCLK =V

CCD −−5µA

rclock rise time 0.75 −tbf ns

tfclock fall time 0.75 −tbf ns

Ziinput impedance fCLK = 100 MHz −tbf −kΩ

Ciinput capacitance fCLK = 100 MHz −2−pf

Standby input (pin STDBY); see Table 1

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2 −VCCD V

IIL LOW-level input current VCLK =0 −5−−µA

IH HIGH-level input current VCLK =V

CCD −−5µA

1998 May 14 7

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

Track enable input (pin TEN); see Table 2

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2 −VCCD V

IIL LOW-level input current VCLK =0 −5−−µA

IH HIGH-level input current VCLK =V

CCD −−5µA

Pins INP and INN (analog input voltage referenced to AGND); VREFIN = 1.25 V; see Table 3

Vi(p-p) input voltage range

(peak-to-peak value) Vi=V

INP −VINN;

Tamb =25°C0.95 1 1.05 V

∆TCI input voltage range drift −tbf −ppm/K

Vi(os) input offset voltage output code = 127 tbf tbf tbf mV

Ziinput impedance fCLK = 50 MHz −tbf −kΩ

Ciinput capacitance fCLK = 50 MHz −2−pf

IIL LOW-level input current VINP =V

REFOUT −0.5;

VINP =V

REFOUT + 0.5 −1−−µA

IH HIGH-level input current VINP =V

REFOUT −0.5;

VINP =V

REFOUT + 0.5 −−40 µA

Voltage controlled regulator input pin VREFIN (referenced to AGND); see note 3

Vi(ref) reference voltage tbf 1.25 tbf V

Ii(ref) input current on pin VREFIN −tbf −µA

Outputs; ADC data outputs

VOL LOW-level output voltage IO=1mA −−0.5 V

VOH HIGH-level output voltage IO=−0.4 mA VCC −0.5 −VCCD V

CLoutput load capacitance −−10 pF

δv/δt slew rate 10 to 90%; CL=10pF −tbf −V/ns

Switching characteristics; see note 2 and Table 1

fCLK(min) minimum clock frequency track = LOW −−tbf MHz

track = HIGH −−tbf kHz

fCLK(max) maximum clock frequency 100 −−MHz

tW(CLKH) clock pulse width HIGH 4 −−ns

tW(CLKL) clock pulse width LOW 4 −−ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 May 14 8

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

Notes

1. It is possible to use the reference output voltage (pin SDN) to drive other analog circuits under the limits indicated in

Chapter “Characteristics”.

2. In addition to a good layout of the digital and analog grounds, it is recommended that the rise and fall times of the

clock must be not less than 0.75 ns.

3. It is possible with an external reference connected to REFIN pin to adjust the ADC input range. The input range

variation will be fixed.

4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 k acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = 6.02 ×EB + 1.76 dB.

Analog signal processing; see note 3

INL integral non-linearity ramp input;

fCLK = 100 MHz;

VCCA =V

CCD =3V

−±1 tbf LSB

DNL differential non-linearity ramp input;

fCLK = 100 MHz;

VCCA =V

CCD =3V

−±0.75 tbf LSB

S/N signal-to-noise ratio (full scale) without harmonics;

fi= 50 MHz;

fCLK = 100 MHz

−44.5 −dB

BA(−3dB) −3 dB analog bandwidth −150 −MHz

THD total harmonics distortion fi= 50 MHz; single mode −−55 −dB

fi= 50 MHz;

differential mode −−55 −dB

Hfund(FS) full scale fundamental harmonics fi= 50 MHz;

fCLK = 100 MHz −−0dB

D2(FS) full scale second harmonic distortion

all components fi= 50 MHz;

fCLK = 100 MHz −tbf −dB

HD3(FS) full scale third harmonic distortion all

components fi= 50 MHz;

fCLK = 100 MHz;

single mode

−tbf −dB

fi= 50 MHz;

fCLK = 100 MHz;

differential mode

−tbf −dB

EB effective bits fCLK = 100 MHz; note 4 −−−

= 20 MHz; note 4 −7.2 −bits

fi= 50 MHz; note 4 −7.0 −bits

Data timing; fCLK = 100 MHz; CL= 10 pF; (see Fig.7)

tds sampling delay −−1.5 ns

thoutput hold time 3 −−ns

tdoutput delay time −5 tbf ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 May 14 9

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

Table 1 Standby selection

Table 2 Track-and-hold selection

Table 3 Output coding and input voltage (typical values; referenced to AGND); VREFIN = 1.25 V

STDBY S0 TO D7 ICCA +I

CCD

0 inactive 56 mA

1 active; output logic state LOW 1.5 mA

TEN TRACK-AND-HOLD

0 active

1 inactive; tracking mode

STEP VINP (V) VINN (V) BINARY OUTPUT BITS

D7 D6 D5 D4 D3 D2 D1 D0

Underﬂow <1.6 >2.1 00000000

0 1.6 2.1 00000000

1 ... ... 00000001

... ... ... ... ... ... ... ... ... ... ...

127 1.85 1.85 ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ...

254 ... ... 11111110

255 2.1 1.6 11111111

Overﬂow >2.1 <1.6 11111111

1998 May 14 10

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

APPLICATION INFORMATION

Fig.3 Application diagram for single input mode with internal reference.

handbook, full pagewidth

MGR019

50 Ω50 Ω

231

100 nF

10 nF

220 nF

100 nF

input

REFIN

DEC

32SND

INN

INP

REFOUT

100 nF

TDA8793

Fig.4 Application diagram for single input mode with external reference.

handbook, full pagewidth

MGR020

50 Ω50 Ω

231

100 nF

10 nF

220 nF

100 nF

input

REFIN

DEC

INN

INP

REFOUT

100 nF

EXTERNAL

REFERENCE

1.25 V

TDA8793

1998 May 14 11

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

Fig.5 Application diagram for differential input mode with internal reference.

handbook, full pagewidth

MGR021

50 Ω

231

100 nF

220 nF

100 nF

input 1

input 2

REFIN

DEC

32SND

INN

INP

REFOUT

100 nF

TDA8793

Fig.6 Application diagram for differential input mode using transformer.

handbook, full pagewidth

MGR022

100 Ω100 Ω

231

100 nF

input

REFIN

DEC

1 : 1

SND

INN

INP

REFOUT

100 nF

220 nF

TDA8793

1998 May 14 12

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

Fig.7 Timing diagram.

handbook, full pagewidth

tds

CLK

MGR018

50 %

HIGH

LOW

50 %

HIGH

LOW

sample N sample N + 1 sample N + 2

DATA

D0 to D7

tCPH

tCPL

DATA

N − 1

DATA

N − 2 DATA

N + 1

DATA

1998 May 14 13

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

PACKAGE OUTLINE

0.2

UNIT A

max. A1A2A3bpcE

(1) eH

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 1.60 0.15

0.05 1.5

1.3 0.25 0.27

0.17 0.18

0.12 5.1

4.9 0.5 7.15

6.85 1.0 0.95

0.55 7

0.12 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT401-1 95-12-19

97-08-04

D(1) (1)(1)

5.1

4.9

7.15

6.85

0.95

0.55

vMB

vMA

24 17

detail X

(A )

0 2.5 5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm SOT401-1

pin 1 index

1998 May 14 14

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reﬂow soldering

Reflow soldering techniques are suitable for all LQFP

packages.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 50 and 300 seconds depending on heating

method. Typical reflow peak temperatures range from

215 to 250 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP

packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for LQFP

packages with a pitch (e) larger than 0.5 mm, the

following conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

•The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

1998 May 14 15

Philips Semiconductors Objective speciﬁcation

8-bit, low-power, 3 V, 100 Msps,

analog-to-digital converter TDA8793

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

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Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Printed in The Netherlands 545104/1200/01/pp16 Date of release: 1998 May 14 Document order number: 9397 750 03675