LINEAR TECHNOLOG
Y
LINEAR TECHNOLOG
Y
LINEAR TECHNOLOG
Y
NOVEMBER 1998 VOLUME VIII NUMBER 4
, LTC and LT are registered trademarks of Linear Technology Corporation.
Adaptive Power, Burst Mode, C-Load,
FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, No R
SENSE
, PolyPhase, SwitcherCAD and UltraFast are
trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that
manufacture the products.
World’s Smallest 24-Bit ADC
Packs High Accuracy,
Ease of Use, into SO-8
by Michael K. Mayes
Introduction
Linear Technology enters the delta-
sigma
1, 2
analog-to-digital converter
market with a tiny, high performance,
24-bit ADC, the LTC2400. The
device’s superiority to existing delta-
sigma ADC’s results from the
combination of an accurate analog
modulator with an innovative new
digital architecture. Typically, fine-
line, digitally optimized processes are
required for a delta-sigma ADC’s
on-chip digital filter. The resulting
ICs have high pin counts, large pack-
ages and complex interfaces. The
LTC2400’s breakthrough in digital
filtering allows the use of an analog-
optimized process. The result is the
smallest (SO-8 package), lowest pin
count (8) simplest to use delta-sigma
converter on the market. A highly
accurate on-chip oscillator, using
Linear’s high performance CMOS pro-
cess, sets the digital filter’s notch
frequency, eliminating the need for
an external crystal. Additionally, the
part offers exceptional INL, DNL, noise
and 50Hz/60Hz rejection. The inno-
vation does not end here; this article
will show how performance, ease of
use and functionality make this part
the new state of the art in high reso-
lution delta-sigma ADCs.
Overview
The analog modulator is critical to the
performance of a delta-sigma ADC.
For high DC accuracy, 1st
or 2nd
order modulators provide insufficient
differential nonlinearity (DNL). The
LTC2400 achieves optimum DC per-
formance from a 3rd order delta-sigma
modulator (see Figure 1). Feedfor-
ward compensation and analog
processing within the modulator elimi-
nate instability issues associated with
high order modulators. The 1-bit ADC
and DAC within the modulator guar-
antee monotonicity and exceptional
INL performance of 4ppm.
The output of the delta-sigma
modulator is applied to a decimating
filter. The sinc
4
filter removes the
quantization noise from the modula-
tor output. Additionally, this filter
rejects the fundamental frequency and
its harmonics. This notch frequency
is set by an on-chip oscillator, typi-
cally at line frequency for DC
applications. The combination of a
4th order sinc filter with a precision
thin-film, factory-trimmed oscillator
guarantees at least 120dB rejection
of line frequency ±2%. Several con-
verters on the market use sinc
3
or
sinc
1
filters. Since line frequencies
can vary up to 2% over a 24-hour
period, converters using these lower
order filters cannot achieve 120dB
continued on page 3
Authors can be contacted
at (408) 432-1900
IN THIS ISSUE…
COVER ARTICLE
World’s Smallest 24-Bit ADC Packs
High Accuracy, Ease of Use, into SO-8
..................................................... 1
Michael K. Mayes
Issue Highlights ............................ 2
LTC
®
in the News ........................... 2
DESIGN FEATURES
Wide Input Range,
High Efficiency Step-Down
Switching Regulators .................... 5
Jeff Schenkel
A 4.5ns, 4mA, Single-Supply,
Dual Comparator Optimized for
3V/5V Operation .......................... 10
Joseph G. Petrofsky
250MHz RGB Video Multiplexer in
Space-Saving Package Drives Cables,
Switches Pixels at 100MHz ......... 16
John Wright and Frank Cox
LT
®
1468: An Operational Amplifier
for Fast, 16-Bit Systems .............. 18
George Feliz
LTC1622: Low Input Voltage, Current
Mode PWM Buck Converter .......... 21
San-Hwa Chee
LTC1531 Isolated Comparator .... 24
Wayne Shumaker
DESIGN IDEAS
PolyPhase™ Switching Regulators
Offer High Efficiency in Low Voltage,
High Current Applications .......... 27
Craig Varga
Level Shift Allows CFA Video
Amplifier to Swing to Ground
on a Single Supply ...................... 30
Frank Cox
DESIGN INFORMATION
Component and Measurement
Advances Ensure 16-Bit DAC Settling
Time (Part Two) ........................... 31
Jim Williams
Net1 and Net2 Serial Interface Chip
Set Supports Test Mode ............... 34
David Soo
New Device Cameos ..................... 37
Design Tools ................................ 39
Sales Offices ............................... 40
Linear Technology Magazine • November 1998
2
EDITOR’S PAGE
a
Be a
Linear Insider!
Visit our web site
(www.linear-tech.com/insider)
or use the response card in this issue to
register. We will notify you via email
about new
information on the
web site that matches
your interests
Issue Highlights
Our cover article for this issue in-
troduces Linear Technology’s entry
into the delta-sigma analog-to-digital
converter market: the tiny, high per-
formance, 24-bit LTC2400. The
LTC2400’s superiority to existing
delta-sigma ADC’s results from the
combination of an accurate analog
modulator with an innovative new
digital architecture. The LTC2400’s
breakthrough in digital filtering allows
the use of an analog-optimized pro-
cess. The result is the smallest (SO-8
package), lowest pin count (8) sim-
plest to use delta-sigma converter on
the market.
Our Design Features section debuts
three new power products. The
LT1676 and LT1776 are Linear
Technology’s latest offerings for high
voltage (to 60V) step-down switching
regulator applications. The LT1676/
LT1776 operate in a fixed frequency
mode (100kHz for the LT1676 vs
200kHz for the LT1776) and can be
externally synchronized to a higher
switching frequency. The internal out-
put switch is rated at a nominal peak
current of 700mA, which typically
accommodates DC output currents
of up to 500mA.
The LTC1622
step-down DC/DC
controller is
designed to
harness all the
energy from
lithium-ion
batteries. Its
wide input-voltage
range and
100% duty cycle
allow low dropout for
maximum energy extraction from
the battery. Its low quiescent current
extends battery life. High frequency
operation allows the use of small
inductors, making it ideal for com-
munications products.
In addition, this issue introduces
two new comparators. The LT1720 is
an UltraFast™, low power, single-
supply, dual comparator designed to
operate on a single 3V or 5V supply.
The comparators feature internal hys-
teresis, making them easy to use,
even with slowly moving input signals.
The LT1720 is fabricated in Linear
Technology’s 6GHz complementary
bipolar process, resulting in unprec-
edented speed for its low power
consumption.
The LTC1531 is an isolated, self-
powered comparator that receives
power and communicates through
internal isolation capacitors. The iso-
lation capacitors provide 3000V
RMS
of
isolation between the comparator and
its output. This allows the part to be
used in applications that require high
voltage isolated sensing without the
need for an isolated power source.
In the amplifier arena, we premier
the LT1468, a single op amp optimized
for accuracy and speed in 16-bit sys-
tems. Operating from ±15V supplies,
the LT1468 in a gain of –1 configura-
tion will settle in 900ns to 150µV for
a 10V step. It also features the excel-
lent DC specifications required for
16-bit designs. Two key applications
are current-to-voltage (I/V) conver-
sion following a fast, 16-bit current
output digital-to-analog converter
(DAC) and buffering the input
of an analog-to-digital
converter (ADC).
One of the first
products from LTC’s
new proprietary high
speed bipolar
process is a
250MHz RGB
(red, green, blue)
multiplexer that is
optimized for switching
speed. This new MUX, the
LT1675, is designed for pixel switch-
ing in video graphics and for RGB
routing. It is configured with three
SPDT RGB video switches and three
current feedback amplifiers for direct
driving of cables.
Our two Design Ideas for this issue
are a PolyPhase supply based on two
LTC1430As operating 180° out of
phase, and a current feedback video
LTC in the News…
Linear Technology Corporation
announced its first quarter
financial results on October 13,
1998, reporting net sales of
$116,032,000––an increase of 6%
compared to the same period last
year. The Company’s net income
for the quarter, $44,382,000 or
$0.56 diluted earnings per share,
was up 9% compared to the first
quarter of last year. Linear
Technology also reported that dur-
ing the quarter it purchased back
1,800,000 shares of its common
stock at a cost of approximately
$100,000,000. In discussing the
results, President and CEO Robert
H. Swanson noted that the
Company continued to have out-
standing profitability and Linear
Technology’s return on sales for
the quarter “was both a record for
the Company and the strongest in
the industry.”
Linear Technology’s new delta-
sigma analog-to-digital converter,
the LTC2400 (see page 1), was the
cover story of the September issue
of Electronic Design. The article
detailed the LTC2400’s exceptional
speed, precision and ease-of-use,
and included a range of illustra-
tions highlighting the LTC2400’s
24-bit differential nonlinearity with
no missing codes. The article also
underscored this new part’s
groundbreaking design, allowing
it to be housed in a tiny SO-8
package yet deliver superior per-
formance compared to competing
parts more than twice its size.
amplifier with a level shifter for
ground-referenced signals.
Our Design Information section
features the conclusion of Jim
Williams’s exposition on measuring
16-bit DAC settling time, and also
introduces the LTC1545, a Net1 and
Net2 compliant serial interface chip
that supports the optional Test Mode,
Remote Loopback and Local Loop-
back functions.
We conclude with a septet of New
Device Cameos.
Linear Technology Magazine • November 1998
3
DESIGN FEATURES
rejection, even with exact external
oscillators (refer to Figure 6a).
A simple, SPI-compatible 3-wire
interface outputs data with single-
cycle settling. This simplifies the user
interface by eliminating latency and
redundant data normally associated
with delta-sigma ADCs. As a black
box, the converter resembles tradi-
tional, easy-to-use converters.
Performance
Designed on a 2µ, single-metal, ana-
log CMOS process, the LTC2400 is
implemented with a die size under
10kmil
2
. The key to Linear attaining
the nearly impossible is the highly
efficient sinc
4
filter. Once the tiny
digital circuitry was completed, the
analog circuitry was optimized for
ultrahigh performance.
The result is 24-bit DNL with no
missing codes guaranteed. As shown
in Figure 2, the integral nonlinearity
is a mere ±2ppm or 0.0002%. This
compares favorably with other 24-bit
devices’ INL performance of 15ppm–
30ppm. Transparent to the user, the
converter continuously executes self-
calibration algorithms automatically
adjusting the offset and full-scale.
With an initial accuracy of 1ppm, the
offset drifts less than 0.01ppm/°C
and the full scale drifts less than
0.02ppm/°C (see Figures 3 and 4).
Combining these DC parameters with
RMS noise performance of 0.3ppm
(see Figure 5), the LTC2400 resembles
a 6-digit digital voltmeter on a chip.
The modulator consists of opera-
tional amplifiers and switched
capacitor circuits. Previous delta-
sigma converters place limitations on
these circuits. Since the LTC2400
was designed on an analog process,
these limitations are removed. This
allows a power supply range of 2.7V
to 5.5V and a reference range of from
below 10mV to 90% of V
CC
. At V
CC
=
3V, the power consumption is 750µW;
it falls to 45µW in power-down mode.
In many applications, the input
signal may exceed V
REF
or fall below
ground. Conventional delta-sigma
converters are unable to provide the
user with any indication of these over-
range conditions. The LTC2400 has
on-chip overrange circuitry. It con-
tinues to output 24-bit valid data
over an effective input range of
–12.5% × V
REF
to 112.5% × V
REF
.
One of the main advantages of
delta-sigma converters over SAR or
flash-type architectures is the inher-
ent rejection of line frequency. In order
to achieve good rejection, past delta-
sigma converters required an accurate
external oscillator or crystal with a
precise, uncommon value. The
LTC2400 incorporates an on-chip
oscillator eliminating the need for
∫∫∫
AUTOCALIBRATION
AND
CONTROL
SERIAL
INTERFACE
INTERNAL
OSCILLATOR
DECIMATING
FIR
FILTER
Σ
fO
(INT/EXT)
DOUT
SCLK
CS
ADC
DAC
VREF
VIN
GND
VCC
0.00E+00 4.19E+06 8.39E+06 1.26E+07 1.68E+07
OUTPUT CODE (DECIMAL)
INTEGRAL NONLINEARITY (ppm)
5
4
3
2
1
0
–1
–2
–3
–4
–5
V
CC
= 5V
V
REF
= 2.5V
T
A
= 25°C
f
O
= GND
–40 –15 10 35 60 85
TEMPERATURE (°C)
OFFSET ERROR (ppm)
5
4
3
2
1
0
–1
–2
–3
–4
–5
V
CC
= 5V
V
REF
= 5V
f
O
= GND
–40 –15 10 35 60 85
TEMPERATURE (°C)
FULL-SCALE ERROR (ppm)
5
4
3
2
1
0
–1
–2
–3
–4
–5
V
CC
= 5V
V
REF
= 5V
f
O
= GND
Figure 1. LTC2400 block diagram
Figure 2. LTC2400 integral nonlinearity error Figure 3. Offset drift Figure 4. Full-scale drift
LTC2400, continued from page 1
Linear Technology Magazine • November 1998
4
DESIGN FEATURES
external components. The internal
oscillator is so precise that the ADC
rejects line frequency over a ±2%
range, independent of supply or oper-
ating temperature (see Figure 6a,
where sinc
1
, sinc
2
and sinc
3
filters are
shown for comparison). Line frequen-
cies of 50Hz or 60Hz are selectable by
simply tying the f
O
pin to V
CC
or
ground. Other rejection frequencies
can be obtained by driving the f
O
pin
with an external clock.
The converter is so robust that the
noise performance and line rejection
are insensitive to layout. As shown in
Figure 7, large noise errors applied to
V
CC
, V
REF
or V
IN
(1.25V
P-P
, 60Hz, ±2%)
have no effect on the ADC’s noise and
linearity performance.
Ease of Use
At a glance, the LTC2400 looks more
like an op amp than a delta-sigma
converter. With only eight pins, it’s
–1.2 –1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2
OUTPUT CODE (ppm OF V
REF
)
NUMBER OF OCCURRENCES AT V
IN
= OV
1400
1200
1000
800
600
400
200
0
V
DD
= 5V
V
REF
= 5V
T
A
= 25°C
f
O
= GND
RMS NOISE = 0.3ppm =1.5µV
PEAK-TO-PEAK NOISE = 1.8ppm = 9µV
OFFSET ERROR = 0.28ppm
about as easy to use as a common op
amp (see Figure 8). Superior noise
rejection and internal analog circuitry
enable the use of one supply pin, one
ground pin and a single-ended input.
The internal oscillator eliminates
external crystals/capacitors and
added device pins. The remaining pins
form a standard 3-wire interface, con-
sisting of a three-statable serial data
output (D
OUT
) under the control of a
chip select pin (CS) and a serial data
output clock (SCLK).
Applications currently using tradi-
tional ADCs can easily migrate to the
LTC2400. Single-cycle settling yields
a one-to-one correspondence between
the start of a conversion and the
output word. This allows the user to
place a multiplexer in front of the
ADC without worrying about latency
or data statistically dependent on
previous conversion results.
Functionality
Despite its small size and low pin
count, the LTC2400 provides many
flexible modes of operation. For
example, tying CS low forces a con-
tinuous conversion mode. With CS
tied high, the device enters a 45µW
power-down mode. For applications
requiring ultralow power, a capacitor
can be tied to CS. Under this
0 50 100 150 200 250 300
0
–20
–40
–60
–80
–100
–120
–140
FREQUENCY (Hz)
REJECTION (dB)
SINC
SINC
2
SINC
3
SINC
4
(LTC2400)
–5.8% –3.3% 60 +3.3% +5.8%
0
–20
–40
–60
–80
–100
–120
–140
REJECTION (dB)
FREQUENCY (Hz)
1V
RMS
60Hz
V
IN
V
CC
V
REF
20
10
0
–10
–20
CODE OUT (ppm)
ONE-SHOT OUTPUT CODE
(NO AVERAGING)
INJECTED NOISE
TIME
Figure 5. Noise histogram Figure 6a. Filter response vs filter order
Figure 6b. Filter response at line frequency
Figure 7. Noise injection
continued on page 36
Linear Technology Magazine • November 1998
5
DESIGN FEATURES
Wide Input Range, High Efficiency
Step-Down Switching Regulators
by Jeff Schenkel
Introduction
The LT1676 and LT1776 are Linear
Technology’s latest offerings for high
efficiency step-down switching regu-
lator applications. These two parts
are pin-for-pin compatible and virtu-
ally identical in operation, the only
difference being their internal oscil-
lator frequencies—100kHz for the
LT1676 vs 200kHz for the LT1776.
They operate in a fixed frequency
mode (as opposed to constant off-
time or on-time, for instance) and can
be externally synchronized to a higher
switching frequency.
The internal output switch is rated
at a nominal peak current of 700mA,
which typically accommodates DC
output currents of up to 500mA. The
input voltage range is 7.4V to 60V.
Maintaining acceptable efficiency in
the upper half of this input voltage
range requires very fast output-switch
edge rates. The LT1676/LT1776 con-
tain specialized output circuitry to
deliver this performance. Addition-
ally, they contain circuitry to monitor
output load level and reduce leading-
edge switch rate (turn-on) when the
output load is light. This arrange-
ment helps avoid pulse skipping at
light load, with its consequent sub-
harmonic behavior.
True current mode operation is
supported, with all its well known
advantages for switching regulator
operation. The shutdown pin imple-
ments a pair of functions. Pulling it
down to near ground turns off the
part almost completely and reduces
the quiescent current to a few tens of
microamperes. The second shutdown
pin function acts at a threshold of
roughly 1.25V. Below this level, the
part operates normally, except that
output switching action is inhibited.
This allows the implementation of an
undervoltage lockout function set by,
for instance, an external resistor
divider. The LT1676/LT1776 are avail-
able in both 8-pin SO and PDIP
packages.
Theory of Operation
The LT1676/LT1776 are current
mode switching regulator ICs opti-
mized for high efficiency operation in
high input voltage, low output voltage
buck topologies. The block diagram
in Figure 1 shows an overall view of
the system. Several of the blocks are
straightforward and similar to those
found in traditional designs, includ-
ing the internal bias regulator,
oscillator and feedback amplifier. The
novel portion includes an elaborate
output switch section and a logic
section to provide the control signals
required by the switch section.
The LT1676/LT1776 operate much
the same as traditional current mode
switchers, the major difference being
their specialized output switch
section. Due to space constraints,
this discussion will not reiterate the
basics of current mode switcher/con-
trollers and the step-down topology.
A good source of information on these
topics is Linear Technology Applica-
tion Note 19.
SWDR
SWDR
SWON
SWON
BOOST
1776 BD
BOOST
SWOFF
SWOFF
LOGICOSC
BIAS
V
TH
V
B
V
BG
V
BG
FB
V
C
GND
SYNC
SHDN
V
CC
FB
AMP
BOOST
COMP
g
m
I
I
I I
R1 R
SENSE
I
COMP
Q4
Q3
Q2
Q1
Q5
V
SW
D1
V
IN
5
3
2
1
6
4
8
7
Figure 1. LT1776 block diagram
Linear Technology Magazine • November 1998
6
DESIGN FEATURES
One of the classic problems in
delivering low output voltage from a
high input voltage at good efficiency
is that minimizing AC switching losses
requires very fast voltage (dV/dt) and
current (dI/dt) transitions at the out-
put device. This is in spite of the fact
that in a cost-effective bipolar IC pro-
cess implementation, slow lateral
PNPs must be included in the switch-
ing signal path.
Fast, positive-going slew rate action
is provided by lateral PNP Q3 driving
the Darlington arrangement of Q1
and Q2. The extra β available from Q2
greatly reduces the drive requirements
of Q3. Although desirable for dynamic
reasons, this topology alone will yield
a large DC forward voltage drop. A
second lateral PNP, Q4, acts directly
on the base of Q1 to reduce the volt-
age drop after the slewing phase has
taken place. To achieve the desired
high slew rate, PNPs Q3 and Q4 are
“force-fed” packets of charge via the
current sources controlled by the
BOOST signal.
Please refer to the timing diagram
of Figure 2a. A typical oscillator cycle
is as follows: The logic section first
generates a SWDR signal, which pow-
ers up the current comparator and
allows it time to settle. About 1µs
later, the SWON signal is asserted
and the BOOST signal is pulsed for a
few hundred nanoseconds. After a
short delay, the V
SW
pin slews rapidly
to V
IN
. Later, after the peak switch
current, indicated by the control volt-
age V
C
, has been reached (current
mode control), the SWON and SWDR
signals are turned off and SWOFF is
pulsed for a few hundred nanosec-
onds. The use of an explicit turn-off
device (Q5) improves turn-off response
time and thus aids both controllabil-
ity and efficiency.
The system described previously
handles heavy loads (continuous
mode) at good efficiency, but is actu-
ally counterproductive for light loads.
The method of jamming charge into
the PNP bases makes it difficult to
turn them off rapidly and achieve the
very short switch ON times required
by light loads in discontinuous mode.
Furthermore, the high leading edge
dV/dt rate has a similar adverse effect
on light load controllability.
The solution is to employ a “boost
comparator” whose inputs are the V
C
control voltage and a fixed internal
threshold reference, V
TH
. (Remember
that in a current mode switching
topology, the V
C
voltage determines
the peak switch current.) When the
V
C
signal is above V
TH
, the previously
described “high dV/dt” action is per-
formed. When the V
C
signal is below
V
TH
, the BOOST pulses are absent, as
can be seen in Figure 2b. Now the DC
current activated by the SWON signal
alone drives Q4 and this transistor
drives Q1 by itself. The absence of a
BOOST pulse plus the lack of a sec-
ond NPN driver results in a much
lower slew rate, which aids light load
controllability.
A further aid to overall efficiency is
provided by the specialized bias regu-
lator circuit, which has a pair of
inputs, V
IN
and V
CC
. The V
CC
pin is
normally connected to the switching
supply output. During start-up con-
ditions, the LT1676/LT1776 power
themselves directly from V
IN
. How-
ever, after the switching supply output
voltage reaches about 2.9V, the bias
regulator uses this supply as its input.
Previous generation step-down con-
troller ICs without this provision
typically required hundreds of milli-
watts of quiescent power when
SWOFF
1776 TD01
BOOST
SWON
SWDR
0
V
IN
V
SW
SWOFF
1776 TD02
BOOST
SWON
SWDR
0
V
IN
V
SW
V
IN
V
CC
V
SW
LT1676
FB
V
C
SHDN
SYNC
C1: PANASONIC HFQ
(201) 348-7522
C2: AVX D CASE TPSD107M010R0080
(803) 946-0362
C4, C5: X7R OR COG/NPO
D1: MOTOROLA 100V, 1A, SMD SCHOTTKY
(800) 441-2447
L1: COILCRAFT DO3316P-224
(847) 936-6400
2
C1
39µF
63V
5
4
1676 F04a
3
7
8
1
V
IN
12V TO
48V
6
GND
+
C2
100µF
10V
+
D1
MBRS1100 R1
36.5k
1%
V
OUT
5V
0mA to 500mA
R2
12.1k
1%
R3
22k
5%
L1
220µH
C3
2200pF
X7R C4
100pF
C5
100pF
FOR 3.3V V
OUT
VERSION:
R1: 24.3k, R2: 14.7k
L1: 150µH, DO3316P-154
I
OUT
: 0mA TO 500mA
LOAD CURRENT (mA)
1
60
EFFICIENCY (%)
70
80
90
10 100 1000
1676 F04b
50
40
30
20
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
Figure 2a. Timing diagram: high dV/dt mode Figure 2b. Timing diagram: low dV/dt mode
Figure 3a. Minimum component-count application Figure 3b. Efficiency of Figure 3a’s circuit
Linear Technology Magazine • November 1998
7
DESIGN FEATURES
operating at high input voltages. This
both degraded efficiency and limited
available output current due to inter-
nal heating.
Choosing Between the
LT1676 and LT1776
As previously mentioned, the LT1676
and LT1776 devices are pin-for-pin
compatible and, in fact, nearly iden-
tical. The only real difference is in
their internal oscillator frequencies,
nominally 100kHz for the LT1676
and 200kHz for the LT1776. A user
must decide which version is best
suited for his or her particular appli-
cation. Generally, the LT1776 is
favored, as its higher switching fre-
quency allows for a lower valued and
possibly physically smaller and less
costly inductor. However, the higher
switching frequency of the LT1776
increases AC switching losses,
adversely affecting efficiency and
internal power dissipation. In fact,
certain combinations of high input
voltage and output current may yield
unacceptable internal power dissipa-
tion and consequent thermal rise. In
these cases, the slower switching fre-
quency of the LT1676 may yield
acceptable operation. (A more thor-
ough treatment of input voltage vs
operating frequency considerations
can be found in the LT1776 data
sheet.)
Applications
Minimum Component-
Count Application
Figure 3a shows a basic “minimum
component count” application using
the LT1676. The circuit produces 5.0V
at up to 500mA I
OUT
with input volt-
ages in the range of 12V to 48V. The
typical P
OUT
/P
IN
efficiency is shown in
Figure 3b. No pulse skipping is
observed down to zero external load.
(The several milliamperes drawn by
the V
CC
pin acts as a sufficient pre-
load.) As shown, the SHDN and SYNC
pins are unused, however either (or
both) can be optionally driven by
external signals as desired.
Minimum PC Board
Area Application
The previous application example
used the LT1676 to demonstrate
simultaneously the maximum input
voltage and output current capabil-
ity. As such, the input bypass
capacitor choice was a high frequency
aluminum electrolytic type, rated to
V
IN
V
CC
V
SW
LT1776
FB
V
C
SHDN
SYNC
C1: AVX D CASE 15µF 35V
TPSD156M035R0300
(803) 946-0362
C2: AVX D CASE 100µF 10V
TPSD107M010R0080
C3: 2200pF, X7R
2
C1
15µF
35V
5
4
1776 F07a
3
7
8
1
V
IN
10V–30V
6
GND
+
C2
100µF
10V
+
D1
MBRS-
1100
R1
36.5k
1%
V
OUT
5V
0mA to 400mA
R2
12.1k
1%
R3
22k
5%
L1
68µH
C3
2200pF C4
100pF
C5
100pF
C4, C5: 100pF, X7R OR COG/NPO
D1: MOTOROLA 100V, 1A, SMD SCHOTTKY
MBRS1100
(800) 441-2447
L1: COILCRAFT DO1608C-683
(847) 936-6400
FOR 3.3V V
OUT
VERSION:
I
OUT
: 0mA TO 500mA
L1: 47µH, DO1608C-473
R1: 24.3k, R2: 14.7k
LOAD CURRENT (mA)
1
60
EFFICIENCY (%)
70
80
90
10 100 1000
1776 F07b
50
40
30
20
V
IN
= 10V
V
IN
= 20V
V
IN
= 30V
V
IN
V
IN
12V–48V
V
CC
V
SW
U1
LT1676 FB
V
C
SYNC 2
C1
39µF
63V
NC
Q1
PN2484
Q2
2N2369
5
4
1676 F06
3
7
8
6
1
GND
SHDN
V
+
V
–
IN
–
IN
+
U2
LTC1440
REF
HYST
OUT 4
7
12
3
6
5
8
GND
+
C2
100µF
10V
+
D1
MBRS1100 R1
39k
5%
V
OUT
5V
R2
10k
5%
R6
22k
R7
2.4M
R3
323k
1%
R4
100k
1%
L1
220µH
C3
100pF
R7
10M
C1: PANASONIC HFQ
(201) 348-2552
C2: AVX D CASE
TPSD107M010R0080
(803) 946-0362)
C4, C5: X7R OR COG/NPO
D1: MOTOROLA 100V, 1A,
SMD SCHOTTKY
(800) 441-2447
L1: COILCRAFT DO3316-224
(847) 639-6400
LOAD CURRENT (mA)
1
60
EFFICIENCY (%)
70
80
90
10 100 1000
1676 F07b
50
40
30
20
V
IN
= 12V
V
IN
= 36V
V
IN
= 48V
V
IN
= 24V
Figure 4a. Minimum PC board area application
Figure 4b. Efficiency of Figure 4a’s circuit
Figure 5a. Burst Mode operation configuration Figure 5b. Efficiency of Figure 5a’s circuit
Linear Technology Magazine • November 1998
8
DESIGN FEATURES
63V. Also, the 100kHz switching rate
of the LT1676 requires an inductor of
about 220µH. The DO3316 device
size was chosen to support the output
current requirements. However, both
of these components are physically
large.
The application example in Figure
4a shows a circuit that is much smaller
physically than the previous mini-
mum component count application.
The nominal 200kHz switching
frequency of the LT1776 allows the
use of a physically smaller 68µH
inductor—a Coilcraft DO1608C-683.
This inductor will support output
current to 400mA at 5V. However, the
part is incapable of withstanding an
indefinite short circuit to ground.
(Momentary shorts of a few seconds
or less can still be tolerated.)
Additionally, the bulky aluminum
electrolytic capacitor previously on
V
IN
has been replaced by a compact
35V-rated tantalum type. The result
is a postage-stamp-sized circuit with
efficiency as shown in Figure 4b.
Burst Mode Application
The minimum component count
application demonstrates that power
supply efficiency degrades with lower
output load current. This is not
surprising, as the LT1676 itself rep-
resents a fixed power overhead. A
possible way to improve light load
efficiency is to use Burst Mode™
operation.
Figure 5a shows the LT1676 con-
figured for Burst Mode operation.
Output voltage regulation is now pro-
vided in a “bang-bang” digital manner,
via comparator U2, an LTC1440.
Resistor divider R4/R5 provides a
scaled version of the output voltage,
which is compared against U2’s
internal reference. Intentional hys-
teresis is set by the R6/R7 divider. As
the output voltage falls below the
regulation range, the LT1676 is turned
on. The output voltage rises and, as it
climbs above the regulation range,
the LT1676 is turned off. Efficiency is
maximized as the LT1676 is only pow-
ered up while it is providing heavy
output current. Figure 5b shows that
efficiency is typically maintained at
75% or better down to a load current
of 10mA. Even at a load current of
V
IN
V
CC
V
SW
U1
LT1776
U3
LT1121-5
FB
V
C
SHDN
SYNC
C1: PANASONIC HFQ
(201) 348-7522
C2: AVX TPSD107M010R0080
(803) 946-0362
L1: COILCRAFT DO3316P-104
(847) 639-6400
7
C1
39µF
63V
5
4
1776 TA02
2
3
8
1
V
IN
11V TO 30V
(SEE TEXT)
6
GND
V
CC
IN
+
PROG
U2
LT1620
I
OUT
IN
–
NC
AVG
SENSE
2
5
4
6
3
8
1
7
GND
+
D1
MBRS1100 R1
57.6k
1%
3-CELL
LEAD-ACID
BATTERY
R2
12.1k
1%
R3
22k
R5
3k
R6
12k
L1
100µHR4
0.5Ω
C4
2200pF
C3
100pF
C7
0.1µF
C5
100pF
C6
0.33µF
C2
100µF
10V
C8
1µF
+
+
7.2V
2mA, efficiency is still a respectable
65% to 75% (depending on V
IN
).
Resistor divider R1/R2 is still
present, but does not directly influ-
ence output voltage. It is chosen to
ensure that the LT1676 delivers high
output current throughout the volt-
age regulation range. Its presence is
also required to maintain proper
short-circuit protection. Transistors
Q1 and Q2 and resistor R7 form a
high V
IN
, low quiescent current volt-
age regulator to power U2.
Battery Charger Application
Figure 6a shows the LT1776 con-
figured as a constant-current/
constant-voltage battery charger. An
LT1620 rail-to-rail current sense
amplifier (U2) monitors the differen-
tial voltage across current sense
resistor R4. As this equals and exceeds
the voltage across resistor R5 in the
R5/R6 divider, the LT1620 responds
by sinking current at its I
OUT
pin. This
is connected to the V
C
control node of
the LT1776 and therefore acts to
reduce the amount of power delivered
to the load. The overall constant-
current/constant-voltage behavior
can be seen in Figure 6b.
Target voltage and current limits
are independently programmable. The
output voltage of 7.2V, which corre-
sponds to the charging voltage of a
3-cell lead-acid battery, is set by the
R1/R2 divider and the internal refer-
OUTPUT CURRENT (mA)
0
OUTPUT VOLTAGE (V)
8
7
6
5
4
3
2
1
050 100 150 250200
1776 TA05
Figure 6a. Wide V
IN
range, high efficiency battery charger
Figure 6b. Battery charger output voltage vs
output current for Figure 6a’s circuit
Linear Technology Magazine • November 1998
9
DESIGN FEATURES
ence of the LT1776. Output current,
presently 200mA, is set by current
sense resistor R4 and the R5/R6 di-
vider. (A 16-pin version of the LT1620
that implements end-of-cycle detec-
tion is also available. This is useful for
implementing lead-acid battery “top-
off” charger behavior or the like. See
the LT1620 data sheet for further
information.)
The circuit as shown accommo-
dates an input voltage range of 11V to
30V. The upper input voltage limit of
30V is determined not by the LT1776,
but by the LT1121-5 regulator (U3).
(A regulated 5V is required by the
LT1620.) This regulator was chosen
for its micropower behavior, which
helps maintain good overall efficiency.
However, the basic catalog part is
only rated to 30V. Substitution of the
industry standard LM317, for
example, extends the allowable input
voltage to 40V (or more with the HV
version), but its greater quiescent
current drain degrades efficiency from
that shown.
Dual Output SEPIC Converter
All of the previous applications pro-
vide a single positive output voltage.
Real world situations often require
dual supply voltages. The SEPIC
topology (single-ended primary induc-
tance converter) offers a cost-effective
way to simultaneously generate a
negative voltage with a single piece of
magnetics. The circuit in Figure 7
uses an LT1776 to generate both posi-
tive and negative 5V. The two
inductors shown are actually just two
windings on a standard Coiltronics
inductor. Capacitor C3 creates the
SEPIC topology, which improves regu-
lation and reduces ripple current in
L1.
For the best negative supply volt-
age regulation, this output should
have a preload of at least 1% of the
maximum positive load. Total avail-
able current from both outputs is
limited to 500mA. Maximum negative
supply current is limited by the posi-
tive 5V load. A typical limit is one-half
of the positive current, but a more
exact calculation includes the input
voltage. For this and further details of
this topology, see Linear Technology
Design Note 100.
Positive-to-Negative Converter
The previous example used a dual
inductor to create a pair of output
voltages, one positive and the other
negative. The positive-to-negative con-
verter topology illustrated in Figure 8
generates a single negative output
voltage from a positive input voltage,
using just an ordinary inductor. The
topology is somewhat similar to the
original step-down arrangement, but
the inductor is grounded and the
LT1776 ground is now referred to the
negative output voltage. Note that the
integrated circuit must now be rated
for the worst case sum of the input
voltage plus the absolute value of the
output voltage. The relatively high
input voltage rating of the LT1676/
LT1776 parts along with their good
efficiency under such conditions make
them an excellent choice for imple-
menting this topology. The circuit as
shown converts an input voltage in
the range of 10V to 28V to a –5V
output. Available output current is
300mA at the worst case V
IN
of 10V.
The user should exercise caution
in modifying this circuit for other
applications. The positive-to-negative
topology is not as straightforward as
the step-down topology. It is actually
more like a flyback topology, in that
current is delivered to the output in
+
+
+
+
C1
15µF
35V
C7
100pF
V
CC
V
SW
FB
V
C
2
3
7
8
1
6
SHDN
SYNC
5
4
V
IN
GND
C5
2200pF
X7R
R3
22k
5%
C6
100pF
C3
100µF
10V
C4
100µF
10V
C2
100µF
10V
L1* 100µH
R1
36.5k
1%
R2
12.1k
1%
L1*
100µH
D2
MBR1100
D1
MBR-
1100
V
OUT
–5V
†
V
OUT
5V
†
V
IN
10V–28V
†
TOTAL AVAILABLE CURRENT IS LIMITED TO 500mA (SEE TEXT)
LT1776
AVX D CASE TPSD156M035R0300
(803) 946-0362
AVX D CASE TPSD107M010R0080
X7R OR COG/NPO
MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY
(800) 441-2447
COILTRONICS CTX100-3 SINGLE CORE WITH 2 WINDINGS
(561) 241-7876
C1:
C2, C3, C4:
C6, C7:
D1, D2:
*L1:
+
+
C1
15µF
35V
C5
100pF
V
CC
V
SW
FB
V
C
2
3
7
8
1
6
SHDN
SYNC
5
4
V
IN
GND C3
2200pF
X7R
R3
22k
5%
C4
100pF
C2
100µF
10V
L1 100µHR1
36.5k
1%
R2
12.1k
1%
D1
MBRS1100
V
OUT
–5V
0mA–300mA
V
IN
10V–28V
AVX D CASE TPSD156M035R0300
(803) 946-0362
AVX D CASE TPSD107M010R0080
X7R OR COG/NPO
MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY
(800) 441-2447
COILCRAFT D03316-104
(847) 639-6400
C1:
C2:
C4, C5:
D1:
L1:
LT1776
Figure 7. Dual-output SEPIC converter
Figure 8. Positive-to-negative converter
continued on page 20
Linear Technology Magazine • November 1998
10
DESIGN FEATURES
A 4.5ns, 4mA, Single-Supply,
Dual Comparator Optimized for
3V/5V Operation
Introduction
The LT1720 is an UltraFast™ (4.5ns),
low power (4mA/comparator), single-
supply, dual comparator designed to
operate on a single 3V or 5V supply.
These comparators feature internal
hysteresis, making them easy to use,
even with slowly moving input sig-
nals. The LT1720 is fabricated in
Linear Technology’s 6GHz com-
plementary bipolar process, resulting
in unprecedented speed for its low
power consumption. Table 1 summa-
rizes the LT1720’s performance
specifications.
The LT1720 is offered in SO-8,
with just three pins per comparator
plus power and ground. For a
full-featured, 7ns, single-supply com-
parator with dual complementary
outputs and internal latch, the
LT1394 is available from this same
high speed process.
These fast, small, low power com-
parators are versatile building blocks
for a variety of high speed, single-
supply applications, such as clock
generators, window comparators, tim-
ing skew generators, coincidence
detectors and pulse stretchers.
Circuit Description
The block diagram of one comparator
in the LT1720 is shown in Figure 1.
There are differential inputs (+IN/
–IN), an output (OUT), a single posi-
tive supply (V
CC
) and ground (GND).
The two comparators are completely
independent, sharing only the power
and ground pins. The circuit topology
consists of a differential input stage,
a gain stage with hysteresis and a
complementary common-emitter out-
put stage. All of the internal signal
paths utilize low voltage swings for
high speed at low power.
The input stage topology maximizes
the input dynamic range available
without requiring the power, com-
plexity and die area of two complete
input stages such as are found in rail-
to-rail input comparators. With a 2.7V
supply, the LT1720 still has a
respectable 1.6V of input common
mode range. The differential input
voltage range is rail-to-rail, without
the large input currents found in com-
peting devices. The input stage also
features phase reversal protection to
prevent false outputs when the inputs
are driven below the –100mV com-
mon mode voltage limit.
The internal hysteresis is imp-
lemented by positive, nonlinear
feedback around a second gain stage.
Until this point, the signal path has
been entirely differential. The signal
path is then split into two drive sig-
nals for the upper and lower output
transistors. The output transistors
are connected common emitter for
rail-to-rail output operation. The
by Joseph G. Petrofsky
–
+
–
+
–
+
–
+
+IN
–IN
A
V1
A
V2
NONLINEAR STAGE
OUT
GND
V
CC
Σ
Σ
++
+
+
retemaraPsnoitidnoCeulaV
yaleDnoitagaporPVm02=evirdrevOsn5.4
yaleDnoitagaporPVm5=evirdrevOsn7
tnerruCylppuSV
CC
V5=rotarapmoCrepAm4
egatloVylppuSstimiLegnaRerutarepmeTlluFV6otV7.2
egnaRegatloVtupnIstimiLegnaRerutarepmeTlluFV(otV1.0–
CC
)V2.1–
egatloVtesffOtupnIV
CC
V,V5=
MC
V1=Vm1
siseretsyHderrefeR-tupnIV
CC
V,V5=
MC
V1=Vm5.3
)woL(egatloVtuptuOI
KNIS
Am01=xaMV4.0
)hgiH(egatloVtuptuOI
ECRUOS
Am4=V(
CC
niM)V4.0–
Table 1. Typical LT1720 specifications, TA = 25°C
Figure 1. LT1720 block diagram
Linear Technology Magazine • November 1998
11
DESIGN FEATURES
Schottky clamps limit the output volt-
ages at about 300mV from the rail,
not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail amplifiers
and other products. But the output of
a comparator is digital, and this out-
put stage can drive TTL or CMOS
directly. It can also drive a host of
other loads, as will be demonstrated
in the applications below.
The bias conditions and signal
swings in the output stages are
designed to turn their respective out-
put transistors off faster than on.
This nearly eliminates the surge of
current from V
CC
to ground that occurs
at transitions, keeping the power
consumption low even with high out-
put-toggle frequencies. In fact, the
internal-frequency-dependent cur-
rent drain is the equivalent of putting
just 15pF on the output. The low
surge current also helps keep the
LT1720 well behaved in high speed
applications.
Internal Hysteresis
The LT1720 includes internal hyster-
esis, eliminating the linear region
where high speed comparators are
most temperamental. The input-
output transfer characteristic is
illustrated in Figure 2, which shows
the definitions of V
OS
and V
HYST
based
upon the two measurable trip points.
The 3.5mV (typical) hysteresis band
makes the LT1720 well behaved, even
with slowly moving inputs.
The exact amount of hysteresis will
vary from unit-to-unit; the LT1720
specifications include both upper and
lower limits that are guaranteed over
temperature. The hysteresis will also
vary slightly with changes in supply
voltage and common mode voltage. If
a comparator is used to detect a
threshold crossing in one direction
only, only that trip point is signifi-
cant. Therefore, a stable offset voltage
with an unpredictable level of hyster-
esis, as seen in many competing
comparators, is useless. The LT1720
is many times better than prior com-
parators in this regard. Figure 3 shows
a typical LT1720’s input voltages vs
supply voltages. The V
OS
shift is only
320µV, corresponding to a typical
PSRR of 80dB.
Speed Limits
The LT1720 comparators are intended
for high speed applications, where it
is important to understand a few limi-
tations. These limitations can roughly
be divided into three categories: input
speed limits, output speed limits and
internal speed limits.
There are no significant input speed
limits except the shunt capacitance
of the input nodes. If the 2pF typical
input nodes are driven, the LT1720
will respond.
The output speed is constrained by
the slew currents available from the
output transistors. To maintain low
power quiescent operation, the
LT1720 output transistors are sized
to deliver 25mA–45mA typical slew
currents. This is sufficient to drive
small capacitive loads and logic gate
inputs at extremely high speeds. But
the slew rate will slow dramatically
with heavy capacitive loads. Because
the propagation delay (t
PD
) definition
ends at the time the output voltage is
halfway between the supplies, the
fixed slew current actually makes the
LT1720 faster at 3V than 5V with
20mV of input overdrive.
The internal speed limits manifest
themselves as dispersion. All com-
parators have some degree of
dispersion, defined as a change in
propagation delay vs input overdrive.
The propagation delay of the LT1720
will vary with overdrive, from a typical
of 4.5ns at 20mV overdrive to 7ns at
5mV overdrive (typical). The LT1720’s
primary source of dispersion is the
hysteresis stage. As a change of
polarity arrives at the gain stage, the
positive feedback of the hysteresis
stage subtracts from the overdrive
available. Only when enough time
has elapsed for a signal to propagate
forward through the gain stage, back-
wards through the hysteresis stage
and forward through the gain stage
again, will the output stage receive
the same level of overdrive that it
would have received in the absence of
hysteresis.
With 5mV of overdrive, the LT1720
is faster with a 5V supply than with a
3V supply, the opposite of what is
true with 20mV overdrive. This is due
to the internal speed limit, because
the gain stage is faster at 5V than 3V
due primarily to the reduced junction
capacitances with higher reverse volt-
age bias.
In many applications, as shown in
the following examples, there is plenty
of input overdrive. Even in applica-
V
HYST
(= V
TRIP+
– V
TRIP–
)
V
HYST
/2
V
OL
V
OH
V
TRIP–
V
TRIP+
∆V
IN
= V
IN+
– V
IN–
V
TRIP+
+ V
TRIP–
2
V
OS
=
V
OUT
0
SUPPLY VOLTAGE (V)
2.5
V
OS
AND TRIP VOLTAGE (mV)
3
2
1
0
–1
–2
–3 4.0 5.0
1720 G01
3.0 3.5 4.5 5.5 6.0
V
TRIP+
V
OS
V
TRIP–
T
J
= 25°C
V
CM
= 1V
–
+
1/2 LT1720
V
CC
2.7V–6V
2k
620Ω220Ω
1MHz–10MHz
CRYSTAL (AT-CUT)
1.8k
2k
0.1µF
GROUND
CASE
OUTPUT
Figure 2. Hysteresis I/O characteristics
Figure 3. The LT1720’s hysteresis is
insensitive to supply-voltage variations.
Figure 4. Simple 1MHz–10MHz
crystal oscillator
Linear Technology Magazine • November 1998
12
DESIGN FEATURES
tions providing low levels of over-
drive, the LT1720 is fast enough that
the absolute dispersion of 2.5ns (= 7
– 4.5) is small enough to ignore.
The gain and hysteresis stage of
the LT1720 is simple, short and high
speed to minimize dispersion. This
internal “self-latch” can be usefully
exploited in many applications
because it occurs early in the signal
chain, in a low power, fully differen-
tial stage. It is therefore highly immune
to disturbances from other parts of
the circuit, either in the same com-
parator, on the supply lines or from
the other comparator in the same
package. Once a high speed signal
trips the hysteresis, the output will
respond, after a fixed propagation
delay, without regard to these exter-
nal influences that can cause trouble
in nonhysteretic comparators.
Applications
Crystal Oscillators
Figure 4 shows a simple crystal oscil-
lator using one half of an LT1720. The
2k–620Ω resistor pair set a bias point
at the comparator’s noninverting
input. The 2k–1.8k–0.1µF path sets
the inverting input node at an appro-
priate DC average level based on the
output. The crystal’s path provides
resonant positive feedback and stable
oscillation occurs. Although the
LT1720 will give the correct logic out-
put when one input is outside the
common mode range, additional
delays may occur when it is so oper-
ated, opening the possibility of
spurious operating modes. Therefore,
the DC bias voltages at the inputs are
set near the center of the LT1720’s
common mode range and the 220Ω
resistor attenuates the feedback to
the noninverting input. The circuit
will operate with any AT-cut crystal
from 1MHz to 10MHz over a 2.7V to
6V supply range.
The output duty cycle for the cir-
cuit of Figure 4 is roughly 50% but it
is affected by resistor tolerances and,
to a lesser extent, by comparator off-
sets and timings.
The circuit of Figure 5 creates a
pair of complementary outputs with a
forced 50% duty cycle. Crystals are
narrow-band elements, so the feed-
back to the noninverting input is a
filtered analog version of the square
wave output. Changing the nonin-
verting reference level can therefore
vary the duty cycle. C1 operates as in
the previous example, whereas C2
creates a complementary output by
comparing the same two nodes with
the opposite input polarity. A1 com-
pares band-limited versions of the
outputs and biases C1’s negative in-
put. C1’s only degree of freedom to
respond is variation of pulse width;
hence the outputs are forced to 50%
duty cycle. This circuit works well
because of the two matched delays
and rail-to-rail style outputs.
–
+
–
+
–
+
C1
1/2 LT1720
C2
1/2 LT1720
A1
LT1636
VCC
2.7V–6V
2k
620Ω220Ω
1MHz–10MHz
CRYSTAL (AT-CUT)
100k
100k
2.2k
1.3k
2k
1k
0.1µF
0.1µF
0.1µF
OUTPUT 0
OUTPUT 1
GROUND
CASE
OPTIONAL—
SEE TEXT
–
+
–
+
–
+
C1
1/2 LT1720
C2
1/2 LT1720
A1
LT1636
VCC
2.7V–6V
2k
620Ω220Ω
1MHz–10MHz
CRYSTAL (AT-CUT)
100k
100k
1.8k
2k
1k
0.1µF
0.1µF
0.1µF
OUTPUT
OUTPUT
GROUND
CASE
Figure 5. Crystal oscillator with complementary outputs and 50% duty cycle
Figure 6. Crystal-based nonoverlapping 10MHz clock generator
Linear Technology Magazine • November 1998
13
DESIGN FEATURES
The circuit in Figure 6 shows a
crystal oscillator circuit that gener-
ates two nonoverlapping clocks by
making full use of the two indepen-
dent comparators of the LT1720. C1
oscillates as before, but with a lower
reference level, C2’s output will toggle
at different times. The resistors set
the degree of separation between the
output’s high pulses. With the values
shown, each output has a 44% high
and 56% low duty cycle, sufficient to
allow 2ns between the high pulses
where both are at logic low. Figure 7
shows the two outputs.
The optional A1 feedback network
shown can be used to force identical
output duty. Because the reference
level set for C2 is lower than that set
for C1, the steady state duty cycles
will be 44% rather than 50%. Note,
though, that the addition of this net-
work only adjusts the percentage of
time each output is high to be the
same, which can be important in
switching circuits requiring identical
settling times. It cannot adjust the
relative phases between the two out-
puts to be exactly 180
°
apart because
the signal at the input node driven by
the crystal is not an exact sinusoid.
Timing Skews
For a number of reasons, the LT1720
is an excellent choice for applications
requiring differential timing skew. The
two comparators in a single package
are inherently well matched, with just
300ps ∆t
PD
typical. Monolithic con-
struction keeps the delays well
matched vs supply voltage and tem-
perature. Crosstalk between the
comparators, usually a disadvantage
in monolithic duals, has minimal
effect on the LT1720 timing due to the
internal hysteresis, as discussed
earlier.
The circuits of Figure 8 show basic
building blocks for differential timing
skews. The 2.5k resistance interacts
with the 2pF typical input capaci-
tance to create at least ±4ns delay,
controlled by the potentiometer set-
ting. A differential and a single-ended
version are shown. In the differential
configuration, the output edges can
be smoothly scrolled through ∆t = 0
with negligible interaction.
Fast Waveform Sampler
Figure 9 uses a diode-bridge-type
switch for clean, fast waveform sam-
pling. The diode bridge, because of its
inherent symmetry, provides lower
–
+
–
+
LT1720
DIFFERENTIAL ±4ns
RELATIVE SKEW
CIN
CIN
CIN
CIN
VREF
2.5k
2.5k
INPUT
–
+
–
+
LT1720
0ns–4ns SINGLE-ENDED
DELAY
CIN
CIN
CIN
CIN
VREF
INPUT
AC errors than other semiconductor-
based switching technologies. This
circuit features 20dB of gain, 10MHz
full power bandwidth and 100µV/
°
C
baseline uncertainty. Switching delay
is less than 15ns and the minimum
sampling window width for full power
response is 30ns.
The input waveform is presented
to the diode bridge switch, the output
of which feeds the LT1227 wideband
amplifier. The LT1720 comparators,
triggered by the sample command,
generate phase-opposed outputs.
These signals are level shifted by the
transistors, providing complementary
bipolar drive to switch the bridge. A
skew compensation trim ensures
bridge-drive signal simultaneity
within 1ns. The AC balance corrects
for parasitic capacitive bridge imbal-
ances. A DC balance adjustment trims
bridge offset.
The trim sequence involves ground-
ing the input via 50Ω and applying a
100kHz sample command. The DC
balance is adjusted for minimal bridge
ON vs OFF variation at the output.
The skew compensation and AC bal-
ance adjustments are then optimized
for minimum AC disturbance in the
output. Finally, unground the input
and the circuit is ready for use.
Coincidence Detector
High speed comparators are especially
suited for interfacing pulse-output
transducers, such as particle detec-
tors, to logic circuitry. The matched
Q0
2V/DIV
Q1
2V/DIV
10ns/DIV
Figure 7, Nonoverlapping outputs
of Figure 6’s circuit
Figure 8. Timing-skew generation is easy with the LT1720.
Linear Technology Magazine • November 1998
14
DESIGN FEATURES
delays of a monolithic dual are well
suited for those cases where the coin-
cidence of two pulses needs to be
detected. The circuit of Figure 10 is a
coincidence detector that uses an
LT1720 and discrete components as
a fast AND gate.
The reference level is set to 1V, an
arbitrary threshold. Only when both
input signals exceed this will a coin-
cidence be detected. The Schottky
diodes from the comparator outputs
to the base of the MRF-501 form the
AND gate, while the other two
Schottkys provide for fast turn-off. A
logic AND gate could instead be used,
but would add considerably more
delay than the 300psec contributed
by this discrete stage.
This circuit can detect coincident
pulses as narrow as 2.5ns. For nar-
rower pulses, the output will degrade
gracefully, responding, but with nar-
row pulses that don’t rise all the way
to high before starting to fall. The
decision delay is 4.5ns with input
signals 50mV or more above the ref-
erence level. This circuit creates a
–
+
5V
2.2k2.2k
INPUT
±100mV FULL SCALE
1k LT1227
909Ω
100Ω
OUTPUT
±1V FULL SCALE
5V
AC BALANCE
3pF
3.6k
1.5k
0.1µF
C
IN
C
IN
2k
2k
10pF
SKEW
COMP
2.5k
1.1k
1.1k
1.1k
1.1k
820Ω820Ω
MRF501 MRF501
LM3045
11
96
8
DC BALANCE
500Ω
51Ω51Ω
10 7
680Ω
–5V
13
= 1N5711
= CA3039 DIODE ARRAY
(SUBSTRATE TO –5V)
–
+
1/2 LT1720
–
+
1/2 LT1720
SAMPLE
COMMAND
TTL compatible output but it can
typically drive CMOS as well.
Pulse Stretcher
For detecting short pulses from a
single sensor, a pulse stretcher is
often required. The circuit of Figure
11 acts as a one-shot, stretching the
width of an incoming pulse to a con-
sistent 100ns. Unlike a logic one-shot,
this LT1720-based circuit requires
only 100pV-s of stimulus to trigger.
The circuit works as follows: Com-
parator C1 functions as a threshold
Figure 9. Fast waveform sampler using the LT1720 for timing-skew compensation
Linear Technology Magazine • November 1998
15
DESIGN FEATURES
5V 3.9k
1k
0.1µF
51Ω
51Ω
300Ω
300Ω
5V 5V
4× 1N5711
MRF501
(GROUND
CASE LEAD)
OUTPUT
COINCIDENCE COMPARATORS 300ps AND GATE
1/2 LT1720
–
+
–
+
1/2 LT1720
–
+
–
+
PULSE SOURCE C1
1/2 LT1720
C2
1/2 LT1720
50Ω51Ω
6.8k
1N5711
24Ω
15k
R 1k
2k 2k
2k
C
100pF
0.01µF
OUTPUT
100ns
5V
detector, whereas comparator C2 is
configured as a one-shot. The first
comparator is prebiased with a thresh-
old of 8mV to overcome comparator
and system offsets and establish a
low output in the absence of an input
signal. An input pulse sends the out-
put of C1 high, which in turn latches
C2’s output high. The output of C2 is
fed back to the input of the first
comparator, causing regeneration and
latching both outputs high. Timing
capacitor C now begins charging
through R and, at the end of 100ns,
C2 resets low. The output of C1 also
goes low, latching both outputs low. A
new pulse at the input of C1 can now
restart the process. Timing capacitor
C can be increased without limit for
longer output pulses.
This circuit has an ultimate
sensitivity of better than 14mV with
5ns–10ns input pulses. It can even
detect an avalanche generated test
pulse of just 1ns duration with
sensitivity better than 100mV.
1
It
can detect short events better than
the coincidence detector above
because the one-shot is configured to
catch just 100mV of upward
movement from C1’s V
OL
, whereas
the coincidence detector’s 2.5ns
specification is based on a full, legiti-
mate logic high.
Conclusion
The new LT1720 dual 4.5ns single-
supply comparators feature high
speeds and low power consumption.
They are versatile and easy-to-use
building blocks for a wide variety of
system design challenges.
1
See Linear Technology Application Note 47,
Appendix B. This circuit can detect the output of
the pulse generator described after 40dB of
attenuation.
Figure 10. A 2.5ns coincidence detector
Figure 11. A 1ns pulse stretcher
for
the latest information
on LTC products,
visit
www.linear-tech.com
Authors can be contacted
at (408) 432-1900
Linear Technology Magazine • November 1998
16
DESIGN FEATURES
250MHz RGB Video Multiplexer in
Space-Saving Package Drives
Cables, Switches Pixels at 100MHz
by John Wright and
Frank Cox
Introduction
One of the first products from LTC’s
new proprietary high speed bipolar
process is a 250MHz RGB (red, green,
blue) multiplexer that is optimized for
switching speed and makes excellent
use of the new complementary 6GHz
transistors. This new MUX, the
LT1675, is designed for pixel switch-
ing in video graphics and for RGB
routing. It is configured with three
SPDT (single pole, double throw) RGB
video switches and three current feed-
back amplifiers for direct driving of
cables.
The new RGB MUX is similar to the
LT1203/LT1205 video switches com-
bined with the LT1260 triple CFA, but
with greatly enhanced performance
in far less space. The boost over the
older configuration is a factor of five
in switching speed and a factor of 2.5
in bandwidth, while the PCB foot-
print is reduced by more than five.
This “juiced” performance is accom-
plished with one-third less supply
current than required by the equiva-
lent multichip design.
Dense Process Yields
Big Performance from
Tiny PC Board Space
One advantage of the dense, high
speed bipolar process is that it results
in a reduced die size for the LT1675,
even though it has well over 300
active devices. The benefit to the user
is that the LT1675 comes in a small
16-pin SSOP package, which is the
same size as an SO-8. To enhance the
small PC board theme, the LT1675 is
configured for a fixed gain of two,
eliminating six external gain setting
resistors. The fixed gain of two in the
CFA is ideal for driving double termi-
nated 50Ω or 75Ω cables. Additionally,
stray PCB capacitance on the sensi-
tive feedback node is no longer a
problem. Figure 1 shows a typical
application switching between two
RGB sources and driving 75Ω cables.
In contrast, some competitive solu-
tions are housed in bulky 24-pin,
wide-SO packages and draw signifi-
cantly more supply current.
RED 1
GREEN 1
BLUE 1
RED 2
GREEN 2
BLUE 2
75Ω
75Ω
75Ω
75Ω
CABLE
CABLE
CABLE
V
+
V
–
SELECT RGB1/RGB2
1675 TA01
ENABLE
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
V
OUT RED
75Ω
75Ω
V
OUT GREEN
V
OUT BLUE
+1
+1 +2
+2
+2
+1
+1
+1
+1
CABLE
R2
75Ω
R2
75Ω
1675 F05
750Ω75Ω
750Ω
OFF
750Ω75Ω
750Ω
OFF
750Ω
R1
75Ω
R1
75Ω
750Ω
ON
n
.
.
.
⇒
1575
n – 1
n = NUMBER OF LT1675s
IN PARALLEL
Figure 1. LT1675 typical application: switching between
two RGB sources and driving three cables
Figure 2. Select pin switches inputs
at 100MHz. RED 1 = 0V, RED 2 =
1V, R
L
= 100Ω, 10pF scope probe;
measured between 50Ω back
termination and 50Ω load
Figure 3. Input-referred switching
transient. R
L
= 150Ω, 10pF scope
probe
Figure 4. Each off channel loads the cable termination
with the 1575Ω.
3V
0V
1V
0V
SELECT
LOGIC
PIN 10
RED OUT
PIN 15
2ns/DIV
3V
0V
0V
SELECT
LOGIC
PIN 10
RED OUT
PIN 15
5ns/DIV
50mV
Linear Technology Magazine • November 1998
17
DESIGN FEATURES
The LT1675’s internal switches
change state in less than 1ns but the
output of the MUX switches in 2.5ns.
This increased time is due to the finite
bandwidth of the current feedback
amplifier that drives the cable. To
toggle at 100MHz, as shown in Figure
2, implies a pixel width of 5ns; accom-
plishing this requires a slew rate in
excess of 1000V/µs. In Figure 2, the
Select pin (pin 10) is driven from a
sine wave generator, since only cross-
ings of the logic threshold are required.
The fast current steering break-
before-make SPDT tee switches
minimize switching glitches. The
switching transients of Figure 3,
measured between the 75Ω back ter-
mination and the 75Ω load, show
what the monitor receives. The glitch
is only 50mV
p-p
, the duration is only
5ns and nature of this transient is
small and fast enough to not be visible
even on quality graphics terminals.
Additionally, the break-before-make
SPDT switch is open before the alter-
nate channel is connected, which
means there is no input feedthrough
or crosstalk during switching.
R1
R2
R3
R4
CHIP
SELECT
1675 F06
ENABLE
LT1675 #1
75Ω
A
V
= 2
LT1675 #2
74HC04
ENABLE
75Ω
RED
OUT
A
V
= 2
75Ω
Expanding Inputs Does Not
Increase Power Dissipation
In video routing applications, where
the ultimate in speed is not manda-
tory, as it is in pixel switching, it is
possible to expand the number of
MUX inputs by shorting the LT1675
outputs together and switching with
the ENABLE pins. This technique does
not increase the power dissipation
because LT1675s draw virtually zero
current when disabled. The internal
gain-set resistors have a nominal
value of 750Ω and cause a 1500Ω
shunt across the 75Ω cable termina-
tion. Figure 4 shows schematically
the effect of expanding the number of
inputs. The effect of this loading is to
cause a gain error that can be calcu-
lated by the following formula:
75Ω + 75Ω
1575Ω
n – 1
||
75Ω
1575Ω
n – 1
||
(
(
6dB + 20log dB
GAIN ERROR (dB) =
where n is the total number of
LT1675s.
For example, using ten LT1675s
(20 red, 20 green, 20 blue) the gain
error is only –1.7dB per channel.
Figure 5 shows a 4-input RGB
router. The response from red 1 input
to red output is shown in Figure 6, for
1V
0V
1V
0V
RED 1
INPUT
RED
OUTPUT
5V
0V
0V
CHIP
SELECT
RED
OUTPUT
retemaraPsnoitidnoCseulaVlacipyT
htdiwdnaBBd3–R
L
=510ΩzHM052
ssentalFniaGBd1.0R
L
51=0ΩzHM07
klatssorCzHM01taslennahCevitcAneewteBBd06–
etaRwelSR
L
51=0Ωsµ/V0011
niaGlaitnereffiDR
L
51=0Ω%70.0
esahPlaitnereffiDR
L
51=0Ω˚50.0
emiTtceleSlennahCR
L
51=0ΩV,
NI
V1=sn5.2
emiTelbanER
L
51=0Ωsn01
gniwSegatloVtuptuOR
L
51=0ΩV3±
rorrEniaGR
L
51=0ΩV,
NI
V1±=%4
egatloVtesffOtuptuOVm02
tnerruCylppuSslennahCeerhTllAAm03
delbasiDtnerruCylppuSAµ1
Table 1. LT1675 performance, V
S
= ±5V
Active
a 25MHz square wave with Chip Select
= 0V. In this example, the gain error is
just –0.23dB. The response to tog-
gling between IC1 and IC2 with Chip
Select is shown in Figure 7. In this
case red 1 input is connected to 0V,
and red 3 is connected to an uncor-
related sine wave.
Figure 5. Two LT1675s build a 4-input
RGB router.
Figure 6. Square wave response: chip
select = 0V, IC 2 disabled
Figure 7. Toggling the 4-input router:
Red 1 input = 0V; Red 3 input =
uncorrelated sine wave
continued on page 20
Linear Technology Magazine • November 1998
18
DESIGN FEATURES
LT1468: An Operational Amplifier
for Fast, 16-Bit Systems by George Feliz
Introduction
The LT1468 is a single operational
amplifier that has been optimized for
accuracy and speed in 16-bit sys-
tems. Operating from ±15V supplies,
the LT1468 in a gain of –1 configura-
tion will settle in 900ns to 150µV for
a 10V step. The LT1468 also features
the excellent DC specifications
required for 16-bit designs. Input off-
set voltage is 75µV max, input bias
current is 10nA maximum for the
inverting input and 40nA maximum
for the noninverting input and DC
gain is 1V/µV minimum. The LT1468
specifications are summarized in
Table 1. Two key applications that
illustrate its use are current-to-volt-
age (I/V) conversion following a fast,
16-bit current output digital-to-ana-
log converter (DAC), such as LTC1597
(Figure 1), and buffering the input of
an analog-to-digital converter (ADC),
such as the 333ksps LTC1604 (Fig-
ure 2). Both applications will be
discussed in detail to highlight the
LT1468 design requirements and
trade-offs.
16-Bit DAC
Current-to-Voltage Converter
with 1.7µs Settling Time
The key AC specification of the circuit
of Figure 1 is settling time as it limits
the DAC update rate. The settling
time measurement is an exception-
ally difficult problem that has been
ably addressed by Jim Williams,
beginning in the August 1998 issue
and concluding in this issue of Linear
Technology magazine and, in greater
detail, in Linear Technology Applica-
tion Note 74. Minimizing settling time
is limited by the need to null the DAC
output capacitance, which varies from
70pF to 115pF, depending on code.
This capacitance at the amplifier input
combines with the feedback resistor
to form a zero in the closed-loop fre-
quency response in the vicinity of
200kHz–400kHz. Without a feedback
capacitor, the circuit will oscillate.
The choice of 20pF stabilizes the cir-
cuit by adding a pole at 1.3MHz to
limit the frequency peaking and is
chosen to optimize settling time. The
settling time to 16-bit accuracy is
theoretically bounded by 11.1 time
constants set by the 6kΩ and 20pF.
Figure 1’s circuit settles in 1.7µs to
150µV for a 10V step. This compares
favorably with the 1.33µs theoretical
limit and is the best result obtainable
with a wide variety of LTC and com-
petitive amplifiers. This excellent
settling requires the amplifier to be
free of thermal tails in its settling
behavior.
The LTC1597 current output DAC
is specified with a 10V reference input.
The LSB is 25.4nA, which becomes
153µV after conversion by the
LT1468, and the full-scale output is
1.67mA, which corresponds to 10V
at the amplifier output. The zero-
scale offset contribution of the LT1468
is the input offset voltage and the
inverting input current flowing
through the 6k feedback resistor. This
worst-case total of 135µV is less than
one LSB. At full-scale there is an
insignificant additional 10µV of error
due to the 1V/µV minimum gain of
the amplifier. The low input offset of
the amplifier ensures negligible deg-
radation of the DAC’s outstanding
linearity specifications.
With its low 5nV/√Hz input voltage
noise and 0.6pA/√Hz input current
noise, the LT1468 contributes only
an additional 23% to the DAC output
noise voltage. As with any precision
application, and particularly with wide
bandwidth amplifiers, the noise band-
width should be minimized with an
external filter to maximize resolution.
ADC Buffer
The important amplifier specifications
for an analog-to-digital converter
buffer application (Figure 2) are low
noise and low distortion. The LTC1604
16-bit ADC signal-to-noise ratio (SNR)
–
+
LTC1597
DAC
INPUTS
10V
V
REF
6k
20pF
DAC C
OUT
70pF–115pF
LT1468
–15V
15V
2k
50pF
OPTIONAL NOISE FILTER
V
OUT
16
1LSB = 25.4nA
FULL SCALE = 1.67mA 10V
153µV
Table 1. LT1486 key specifications
egatloVtesffOtupnIxaMVµ57
tnerruCsaiBtupnIgnitrevnIxaMAn01
saiBtupnIgnitrevninoN
tnerruC
xaMAn04
niaGCDniMVµ/V1
RRMCniMBd69
egatloVesioNtupnIzH/Vn5
tnerruCesioNtupnIzH/Ap6.0
htdiwdnaBniaGzHM09
etaRwelSsµ/V22
V10rofDHT
P-P
zHk001,Bd6.59–
,Vµ051otemiTgniltteSCAD petSV01 sµ7.1
A
V
otemiTgniltteS1–= petSV01,Vµ051 sn009
V,tnerruCylppuS
S
V51±=xaMAm2.5
(Figure 1's Circuit)
Figure 1. 16-bit DAC I/V converter with 1.7µs settling time
Linear Technology Magazine • November 1998
19
DESIGN FEATURES
of 90dB implies 56µV
RMS
noise at the
input. The noise for the amplifier,
100Ω/3000pF filter and a high value
10kΩ source is 15µV
RMS
, which
degrades the SNR by only 0.3dB. The
LTC1604 total harmonic distortion
(THD) is a low –94dB at 100kHz. The
buffer/filter combination alone has
2nd and 3rd harmonic distortion bet-
ter than –100dB for a 5V
P-P
, 100kHz
input, so it does not degrade the AC
performance of the ADC.
The buffer also drives the ADC
from a low source impedance. With-
out a buffer, the LTC1604 acquisition
time increases with increasing source
resistance above 1k and therefore the
maximum sampling rate must be
reduced. With the low noise, low dis-
tortion LT1468 buffer, the ADC can
be driven at maximum speed from
higher source resistances without
sacrificing AC performance.
The DC requirements for the ADC
buffer are relatively modest. The
input offset voltage, CMRR (96dB
minimum) and noninverting input
bias current through the source resis-
tance, R
S
, affect the DC accuracy,
but these
errors are an insignificant
fraction of the ADC offset and full-
scale errors.
Circuit Description
A simplified schematic of LT1468 is
shown in Figure 3. The circuit is a
single, folded-cascode gain stage for
fast settling and high bandwidth. The
inputs are PNP transistors Q1 and Q2
with bias current cancellation from
current source I7–Q12 to match Q1
and Q2, and the current mirror com-
posed of Q13, Q14 and Q15. I7 is
trimmed to minimize the inverting
input current (critical for errors in
DAC I/V circuits). The input devices
are protected by 100Ω resistors and
back-to-back diodes D1 and D2. The
collectors of Q1 and Q2 are loaded by
current sources I3 and I4 and the
emitters of cascode transistors Q3
and Q4. I3 and I4 are trimmed to null
the input offset voltage.
The mirror formed by Q5 and Q6
performs differential-to-single ended
conversion into the high gain node at
the collectors of Q4 and Q6. To
increase the gain of this single stage,
–
+
V
IN
R
S
LT1468
15V
–15V
100Ω
3000pF
530kHz NOISE FILTER
LTC1604
16 ADC
OUTPUTS
5V
–5V
I7
50µAI1
100µA
I2
400µAI5
350µA2mA
Q12
Q13
Q3
Q2
Q4
Q5
Q14
Q15
Q1
Q6
C1
4pF
Q7
Q8 Q9
Q11
Q10
D2
D1
100Ω100Ω
I3
150µAI4
150µA
I6
350µA
OUT
+IN –IN
BIAS
C2
10pF
2k 2k 1k
V–
V+
the Q5–Q6 mirror is bootstrapped by
follower Q7 and current source I2 so
that the mirror floats with the output
level. With this scheme, Q6 never
sees a change in base-collector volt-
age and does not degrade the gain
with its output impedance, which is a
factor of 5–10 lower than that of NPNs
Q3 and Q4. By choosing I2 so that Q7
runs at twice the collector current of
Q5–Q6, the base current of Q7 bal-
ances the combined base currents of
Q5 and Q6. A benefit of this balanced
design is low offset voltage drift
(2µV/°C maximum).
The output stage is formed by Q8,
Q9, Q10 and Q11 and current sources
I5 and I6. This stage further buffers
the gain node from the output. The
path from the emitter of Q7 to the
output has symmetrical current gain,
as it contains both an NPN and PNP,
whether sourcing or sinking current.
This balance reduces 2nd harmonic
distortion.
Frequency compensation is set by
capacitor C1 on the gain node for a
90MHz gain bandwidth at 100kHz.
Capacitor C2 rolls off the mirror gain,
which produces a pole-zero pair so
that the open-loop response reaches
unity gain at 25MHz with 42° of phase
margin. C2 is bootstrapped to the
output so that it does not degrade
slew rate. The gain and phase versus
frequency are shown in Figure 4. Slew
rate is set by I1 and C1 and is typi-
cally 22V/µs.
Design Trade-Offs
Previous precision designs had
multiple gain stages and highly bal-
anced configurations. The price paid
by these classic designs is lack of
FREQUENCY (Hz)
GAIN (dB)
10M
1418_02a.EPS
70
60
50
40
30
20
10
0
–1010k 100k 1M 100M
PHASE
GAIN
100
80
60
40
20
0
–20
–40
–60
PHASE (DEGREES)
Figure 2. ADC buffer
Figure 3. LT1468 simplified schematic
Figure 4. LT1468 gain and phase vs frequency
Linear Technology Magazine • November 1998
20
DESIGN FEATURES
bandwidth, slew rate and settling time.
The LT1468 uses a single stage
topology to obtain excellent AC speci-
fications with high bandwidth and
state-of-the-art 16-bit settling. The
demands of precision dictate a fully
balanced design and painstaking care
in the die layout. The AC perfor-
mance is ultimately limited, however,
by the need for high gain and low
input bias current. High gain requires
bootstrapping the current mirror in
the signal path, which degrades phase
margin at high frequency. For this
reason the mirror is compensated to
lower the unity-gain frequency of the
amplifier, which reduces bandwidth
at low closed-loop gains.
To obtain low input bias current,
the choice of operating currents is
limited by the accuracy of the input
bias current cancellation circuitry.
With trimming, up to a 50× reduction
V
S
= ±15V
T
A
= 25°C
f = 10kHz
SOURCE RESISTANCE, R
S
(Ω)
TOTAL NOISE VOLTAGE (nV/√Hz)
100k
1468_05.eps
100 1k 10k
100
10
1
0.1
RESISTOR
NOISE ONLY
TOTAL
NOISE
R
S
–
+
in I
B
can be achieved. This constraint
sets the maximum value of current
source I1, which also places limits on
bandwidth, slew rate, noise voltage
and noise current. The LT1468 total
noise is best with source resistance in
the 1kΩ to 20kΩ region, where any
increase in noise is due to the resistor
(Figure 5).
It should be noted that the input
bias current cancellation current is
not bootstrapped to the input stage to
provide constant I
B
vs input common
mode voltage. The reason is simple:
this circuitry runs at submicroamp
current levels and has no chance of
settling if it is allowed to move with
the inputs. The I
B
is optimized for
inverting configurations with a con-
stant input voltage and provides
excellent settling.
Conclusion
The LT1468 has an unequaled blend
of speed and precision that is ideal for
16-bit applications. Its unique virtues
also provide outstanding performance
in low distortion active filters and
precision instrumentation.
Figure 5. Total noise vs unmatched
source resistance
discrete pulses. The output capacitor
must supply the entire load current
for at least a portion of the switching
cycle, so output capacitor ripple cur-
rent rating and ESR may be an issue.
Maximum available output current
will usually be a strong function of
input voltage. Supporting low V
IN
-to-
V
OUT
ratios may require additional
components for maintaining control-
loop stability. A detailed theoretical
analysis of this topology and its
behavior can be found in Linear Tech-
nology Application Note 44.
Conclusion
The LT1676 and LT1776 provide ex-
cellent efficiency in high input voltage/
low output voltage switching regula-
tor applications. This LT1776’s 8-pin
SO package and 200kHz switching
rate are especially useful in imple-
menting compact power supply
solutions. These devices’ innate abil-
ity to avoid pulse skipping under light
loads, plus the optional sync func-
tion, aid in controlling the frequency
spectrum of switching-generated
noise.
LT1676/LT1776, continued from page 9
Authors can be contacted
at (408) 432-1900
Performance
Table 1 summarizes the major per-
formance specifications of the
LT1675; Figure 8 shows a graph of
crosstalk.
Conclusion
By taking full advantage of LTC’s new
complementary high speed bipolar
process, the LT1675 RGB multiplexer
dramatically raises the level of per-
FREQUENCY (Hz)
CROSSTALK REJECTION (dB)
100M
1418_02a.EPS
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
100k 1M 10M 1G
R
S
= 75Ω
R
L
= 150Ω
GREEN 1 DRIVEN
RED 1 SELECTED
R
S
= 75Ω
R
L
= 150Ω
GREEN 1 DRIVEN
RED 1 SELECTED
formance while saving PC board
space. A channel-to-channel toggle
rate of 100MHz makes the LT1675
perfect for pixel switching and the
simple expansion feature using the
ENABLE pin is ideal for RGB routing.
A fixed gain of two for driving double
terminated cables simplifies PC board
layout and boosts performance. These
high performance multiplexers
complement the large number of video
products offered by LTC.
Figure 8. LT1675 crosstalk rejection vs
frequency
LT1675, continued from page 17
Linear Technology Magazine • November 1998
21
DESIGN FEATURES
LTC1622: Low Input Voltage,
Current Mode PWM Buck Converter
by San-Hwa Chee
Introduction
The push for 2.5V system supplies
continues unabated as manufactur-
ers introduce more parts that operate
at this low voltage. The rewards are
great, especially for battery-powered
equipment, since the lower voltage
reduces power consumption and
thereby extends the time between
battery replacements or recharges.
With a 2.5V system supply, operation
from a single lithium-ion battery
becomes highly attractive, because
its end-of-charge voltage is 2.7V and
it has the most energy per volume
compared to NiCd and NiMH.
The 8-pin LTC1622 step-down DC/
DC controller is designed to help sys-
tem designers harness all of the
available energy from lithium-ion
batteries in several ways. Its wide
operating input-voltage range (2.0V
to an absolute maximum of 10V) and
100% duty cycle allows low dropout
for maximum energy extraction from
the battery. The part’s low quiescent
current, 400µA, with a shutdown cur-
rent of 15µA, extends battery life. Its
user-selectable Burst Mode opera-
tion enhances efficiency at low load
current.
For portable applications where
board space is a premium, the
LTC1622 operates at a constant fre-
quency of 550kHz and can be
synchronized to frequencies of up to
750kHz. High frequency operation
allows the use of small inductors,
making this part ideal for communi-
cations products. The LTC1622 comes
in a tiny 8-lead MSOP package, pro-
viding a complete power solution while
occupying only a small area.
The LTC1622 uses a pulse-width,
current mode architecture, which
provides excellent AC and DC load
and line regulation. Peak inductor
current is set by an external sense
resistor. This allows the design to be
optimized for each application. A soft-
start pin allows the LTC1622 to power
up gently.
A Detailed Look
at the LTC1622
The LTC1622 is a constant-frequency,
pulse-width-modulated, current
mode switching regulator. In normal
operation, the external P-channel
power MOSFET is turned on during
each cycle when the oscillator sets a
latch and turned off when the current
comparator resets the latch. The peak
inductor current at which the current
comparator resets the latch is con-
trolled by the voltage on the I
TH
pin,
which is the output of the error
amplifier, g
m
. An external resistive
divider connected between V
OUT
and
ground allows g
m
to receive an output
feedback voltage, V
FB
. When the load
current increases, it causes a slight
decrease in V
FB
relative to the 0.8V
reference, which, in turn, causes the
I
TH
voltage to increase until the aver-
age inductor current matches the new
load current. (For a more detailed
description, please refer to the
LTC1622 data sheet.)
The value of the R
SENSE
is chosen
based on the required output current.
The LTC1622 current comparator has
a maximum threshold of 100mV/
R
SENSE
. The current-comparator
threshold sets the peak of the induc-
tor current, yielding a maximum
average output current equal to the
peak value minus one-half the peak-
to-peak inductor ripple current. For
applications where the duty cycle is
+
+SENSE–
PDRV
GND
VFB
VIN
ITH
SYNC/MODE
RUN/SS
1
7
6
3
8
2
5
4
C1
10µF
16V R1
10k
C3
220pF
470pF
R2 0.03Ω
Si3443DV
D1
L1 4.7µH
R3
159k
R4
75k
C2
47µF
6V
VOUT
2.5V/1.5A
LTC1622
VIN
2.5V–8.5V
C1: MURATA CERAMIC GRM235Y5V106Z
(814) 236-1431
C2: SANYO POSCAP 6TPA47M
(619) 661-6835
L1: MURATA LQN6C-4R7M04
D1: IR10BQ015
(310) 322-3331
R2: DALE, 0.25W
(605) 665-9301
LOAD CURRENT (A)
60
EFFICIENCY (%)
70
80
90
100
0.001 1.000
50
0.010
40
0.100
V
IN
= 3.3V
V
IN
= 6V
V
IN
= 4.2V
V
IN
= 8.4V
V
OUT
= 2.5V
R
SENSE
= 0.03Ω
LOAD CURRENT (A)
EFFICIENCY (%)
0.001 1.0000.010 0.100
V
IN
= 3.3V
V
IN
= 6V
V
IN
= 4.2V
V
IN
= 8.4V
V
OUT
= 2.5V
R
SENSE
= 0.03Ω
100
90
80
70
60
50
40
Figure 1. LTC1622 typical application: 2.5V/1.5A converter
Figure 2. Efficiency vs load current for Figure
1’s circuit (Burst Mode enabled)
Figure 3. Efficiency vs load current for Figure
1’s circuit (Burst Mode disabled)
Linear Technology Magazine • November 1998
22
DESIGN FEATURES
Figure 4. Transient response with Burst Mode
enabled; load step = 50mA to 1.2A Figure 5. Transient response with Burst Mode
inhibited; load step = 50mA to 1.2A
high (> 80%), the value of the sense
resistor is set to approximately 50mV/
I
OUTMAX
to account for the effect of
slope compensation. Under short-cir-
cuit conditions, the frequency of the
oscillator will be reduced to about
120kHz. This low frequency allows
the inductor current to safely dis-
charge, thereby preventing current
runaway.
The LTC1622 includes protection
against output overvoltage conditions
or transients. An overvoltage com-
parator monitors the output voltage
and forces the external MOSFET off
when the feedback voltage has risen
to 8% above the reference voltage
(0.8V).
Burst Mode Operation
The LTC1622’s Burst Mode operation
is enabled at low load currents simply
by connecting the SYNC/MODE pin
to V
IN
or letting it float. In this mode,
the minimum peak current of the
inductor is set to 0.36V/R
SENSE
even
though the voltage at the I
TH
pin would
indicate a lower value. If the inductor’s
average current is greater than the
load requirement, the voltage at the
I
TH
pin will drop as V
OUT
rises slightly.
When the I
TH
voltage goes below 0.12V,
a sleep signal is generated, turning
off the external MOSFET. The load
current is now supported by the out-
put capacitor. The LTC1622 will
resume normal operation when the
I
TH
voltage goes above 0.22V. For fre-
quency-sensitive applications, Burst
Mode operation is inhibited by con-
necting the SYNC/MODE pin to
ground. In this case, constant-fre-
quency operation will be maintained
at a lower load current together with
lower output ripple. If the load cur-
rent is low enough, cycle skipping will
occur to maintain regulation.
Frequency Synchronization
The LTC1622 can be externally driven
by a clock signal of up to 750kHz.
Synchronization is inhibited when the
feedback voltage is below 0.3V. This
is done to prevent inductor current
build-up under short-circuit condi-
tions. Burst Mode operation is
inhibited when the LTC1622 is driven
by an external clock.
Undervoltage Lockout and
Dropout Operation
An undervoltage lockout circuit is
incorporated into the LTC1622. When
the input voltage drops below 2.0V,
most of the LTC1622 circuitry will be
turned off, reducing the quiescent
current from 400µA to several micro-
amperes and forcing the external
MOSFET off.
The LTC1622 is capable of turning
the external P-channel MOSFET on
continuously (100% duty cycle) when
the input voltage falls to near the
output voltage. In dropout, the out-
put voltage is determined by the input
voltage minus the voltage drop across
the MOSFET, the sense resistor and
the inductor resistance.
RUN/Soft-Start Pin
The RUN/SS pin is a dual-function
pin that provides the soft-start func-
tion and a means to shut down the
LTC1622. An internal current source
charges an external capacitor. When
the voltage on the Run/SS pin reaches
0.65V, the LTC1622 begins operat-
ing. As the voltage on the RUN/SS
continues to increase linearly from
0.65V to 1.8V, the internal current
limit also increases proportionally.
The current limit begins at 0A (at
V
RUN/SS
= 0.65V) and ends at 0.10V/
R
SENSE
(V
RUN/SS
> 1.8V); therefore,
this pin can be used for power supply
sequencing.
2.5V/1.5A
Step-Down Regulator
A typical application circuit using the
LTC1622 is shown in Figure 1. This
circuit supplies a 1.5A load at 2.5V
with an input supply between 2.7V
up to 8.5V. The 0.03Ω sense resistor
is selected to ensure that the circuit is
capable of supplying 1.5A at a low
input voltage. In addition, a sublogic
threshold MOSFET is used, since the
circuit operates at input voltages as
low as 2.7V. The circuit operates at
the internally set frequency of 550kHz.
A 4.7µH inductor is chosen so that
the inductor’s current remains con-
tinuous during burst periods at low
load current. For low output voltage
ripple, a low ESR capacitor (100mΩ)
is used.
OUTPUT VOLTAGE
(AC COUPLED)
0.1V/DIV
0.1ms/DIV
OUTPUT VOLTAGE
(AC COUPLED)
0.1V/DIV
0.1ms/DIV
Linear Technology Magazine • November 1998
23
DESIGN FEATURES
Efficiency Considerations
The efficiency curves for Figure 1’s
circuit are shown in Figures 2 and 3.
Figure 2 shows the efficiency with
Burst Mode enabled, whereas Figure
3 has Burst Mode defeated. Note that,
at low load currents, the efficiency is
higher with Burst Mode operation.
However, constant frequency opera-
tion is still achievable at a lower load
currents with Burst Mode operation
defeated. The kinks in the efficiency
curves indicate the transition out of
Burst Mode operation.
The components of Figure 1 have
been carefully chosen to provide the
amount of output power using a mini-
mum of board space. Efficiency is
also a prime consideration in select-
ing the components, as illustrated in
Figures 2 and 3. Figures 4 and 5 show
the transient response of V
OUT
with a
load step from 50mA to 1.2A. Figure
4 has Burst Mode enabled, while Fig-
ure 5 has it defeated. Note that the
output voltage ripple (in the middle
portion of the photographs) is higher
for Burst Mode operation than with
Burst Mode disabled at 50mA load
current.
Applications that require better
transient response can use the cir-
cuit in Figure 6, whose components
are selected specifically for this
requirement. Figures 7 and 8 show
the response with and without Burst
Mode operation, respectively. Note
that the transient response has been
enhanced significantly. However, this
comes at the expense of slightly
reduced efficiency at low load cur-
rents, as indicated by the efficiency
curves of Figures 9 and 10.
Conclusion
Although the LTC1622 comes in a
tiny 8-pin MSOP, it is packed with
features that are not normally found
in other DC/DC converters. Its ability
to operate from input voltages as low
as 2.0V makes it attractive for single
lithium-ion battery-powered applica-
tions. Features like Burst Mode and
100% duty cycle ensure that energy
from the battery is used efficiently
and charge is extracted down to the
last coulomb. For telecommunications
products, where noise generated by a
switching regulator may spell trouble,
the synchronizable LTC1622 can
operate at a constant frequency, mak-
ing noise a nonissue for system
designers.
Figure 7. Transient response with Burst Mode
enabled; load step = 50mA to 1.2A Figure 8. Transient response with Burst Mode
inhibited; load step = 50mA to 1.2A
+
+SENSE–
PDRV
GND
VFB
VIN
ITH
SYNC/MODE
RUN/SS
1
7
6
3
8
2
5
4
C1
47µF
16V R1
22k
C3
100pF
470pF
R2 0.03Ω
Si3443DV
D1
L1 1.3µH
R3
159k
R4
75k
C2
100µF
6V
VOUT
2.5V/1.5A
LTC1622
VIN
2.5V–8.5V
C1: AVX TPSD476M016R0150
(803) 946-0362
C2: AVX TPSD476M016R0065
L1: MURATA LQN6C-1R5M04
(814) 237-1431
D1: IR10BQ015
(310) 322-3331
R2: DALE, 0.25W
(605) 665-9301
LOAD CURRENT (A)
EFFICIENCY (%)
100
90
80
70
60
50
40
0.001 1.0000.010 0.100
V
IN
= 3.3V
V
IN
= 6V
V
IN
= 8.4V
V
OUT
= 2.5V
R
SENSE
= 0.03Ω
V
IN
= 4.2V
LOAD CURRENT (A)
EFFICIENCY (%)
100
90
80
70
60
50
40
0.001 1.0000.010 0.100
V
IN
= 3.3V
V
IN
= 6V
V
IN
= 8.4V
V
OUT
= 2.5V
R
SENSE
= 0.03Ω
V
IN
= 4.2V
Figure 9. Efficiency vs load current for
Figure 6’s circuit (Burst Mode enabled)
Figure 10. Efficiency vs load current for
Figure 6’s circuit (Burst Mode disabled)
Figure 6. 2.5V/1.5A converter with improved transient response
0.1ms/DIV
OUTPUT VOLTAGE
(AC COUPLED)
0.1V/DIV
OUTPUT VOLTAGE
(AC COUPLED)
0.1V/DIV
0.1ms/DIV
Linear Technology Magazine • November 1998
24
DESIGN FEATURES
LTC1531 Isolated Comparator
Introduction
The LTC1531 is an isolated, self-pow-
ered comparator that receives power
and communicates through internal
isolation capacitors. The internal iso-
lation capacitors provide 3000V
RMS
of isolation between the comparator
and its output. This allows the part to
be used in applications that require
high voltage isolated sensing without
the need to provide an isolated power
source. The isolated side provides a
2.5V pulsed reference output that
can deliver 5mA for 100µs using the
power stored on the isolated external
capacitor. A 4-input, dual-differen-
tial comparator samples at the end of
the reference pulse and transmits the
result back to the nonisolated side.
The nonisolated, powered side latches
the result of the comparator and pro-
vides a zero-cross comparator output
for triggering a triac. Typical applica-
tions include isolated temperature
sensing and control, isolated voltage
monitoring and other sensing appli-
cations riding on top of high common
mode voltages, such as the AC power
line.
Basic Operation
The block diagram in Figure 1 shows
the basic components of the LTC1531.
The nonisolated powered side toggles
between pumping AC voltage through
the capacitive barrier to the isolated
side, where it is rectified and stored
on an external capacitor tied to V
PW
,
and listening for a comparison result.
When the isolated-side V
PW
voltage
reaches 3.3V, the comparison cir-
cuitry is enabled. On the next listen
cycle, the 2.5V V
REG
output pulses on
for 100µs, at the end of which a
comparison is done, with the result
transmitted back to the nonisolated
side. If a valid result is received, the
DATA output is updated and the
VALID output pulses on for 1ms. When
the latched DATA output is high, the
zero-cross comparator output is en-
abled for firing a triac whenever the
zero-cross comparator inputs pass
through 0V.
Figure 2 represents a typical V
PW
start-up sequence, showing V
REG
out-
put pulses after V
PW
reaches 3.3V.
Thereafter, whenever V
PW
reaches
3.3V the comparator samples during
the next listen period in the power/
listen cycle. Figure 2 shows typical
sampling with light loading on V
REG.
Sampling is not uniform but depends
on the combination of V
PW
= 3.3V and
the 800Hz power/listen cycle. The
comparator samples at a typical rate
of 200Hz–300Hz. The actual sam-
pling rate depends on the internal
and external loading on the 2.5V V
REG
output and the charging rate to the
VOLTAGE
PUMP
TRANSMIT
AND
DRIVER
TIMING
POWERED SIDE ISOLATED SIDE
TIMING
DECODE
POWER-ON
RESET
VALID
QD
R
25
V
CC
V
CC
1
DATA 26
ZCDATA
ZERO-CROSS
COMPARATOR
27
GND
ZCPOS ZCNEG SHDN
28 432
LATCH
12
CMPOUT
14
ISOGND
ISOLATION
BARRIER
1531 BD
V2
18
V1
Σ
Σ
13
V
REG
11
V
PW
–
+
–
+
2.5V
REG
3.3V
DET
COMPARE
17
15
V4
16
V3
V
CC
V
CC
TIME (ms)
0
V
PW
(V)
3.3
2.5
1531 F01
100 200 300
NOTES: V
RIPPLE
DEPENDS ON C
VPW
AND I
VPW
+ I
VREG
t
SAMPLE
DEPENDS ON I
VPW
+ I
VREG
t
SAMPLE
V
REF
V
PW
V
CC
= 5V
C
VPW
= 1µF
I
VREG
= 5mA
V
RIPPLE
Figure 1. LTC1531 block diagram
Figure 2. Typical V
PW
power-up and V
REG
samples
by Wayne Shumaker
Linear Technology Magazine • November 1998
25
DESIGN FEATURES
external capacitor on V
PW
. This charg-
ing rate, through the internal isolation
capacitors to V
PW
, can be modeled as
a 100k source resistance and a 5.5V
source with V
CC
= 5V. Figure 4 shows
typical sampling periods for different
load currents and supply voltages.
The sample rate does not depend on
the external storage capacitor, whose
value should be chosen to minimize
ripple on V
PW
for different V
REG
loads.
V
PW
can also be used to power con-
tinuous, low current circuits, such as
the LT1495 op amp or the LTC1540
comparator, provided that such cir-
cuits do not prevent V
PW
from reaching
3.3V.
Isolated Comparator
The LTC1531 isolated switched
capacitor comparator has four inputs
that sum the voltages together to
perform the following comparison:
(V1 + V2)/2 > (V3 + V4)/2
By rearranging the equation, for
example, a dual differential compari-
son can be performed:
(V1 – V4) > (V3 – V2) or (V1 – V3) > (V4
– V2)
The comparator inputs have a rail-
to-rail input range. They sample once
at the end of the 100µs V
REG
pulse.
Their summing nature allows mid-
V
REG
referencing, for example, by
connecting V3 to V
REG
and V4 to
ISOGND, which sums together to pro-
vide 1.25V for the negative comparator
input. In the isolated temperature
control application (Figure 5), the
comparator is used to compare the
voltage across the thermistor to the
voltage across R4, with (V1 – V3) > (V4
– V2).
The isolated comparator has an
isolated output, CMPOUT, which can
be used for hysteresis. This output is
Hi-Z except when V
REG
is on; then the
output is either 2.5V or 0V, depend-
ing on the result of the previous
comparison. This output, in combi-
nation with the comparator, can be
used to create a delta-sigma modula-
tor for transmitting isolated voltage
signals across the isolation barrier,
as in the isolated voltage sense appli-
cation (Figure 6).
Applications
The LTC1531 can be used to isolate
sensors such as in the isolated ther-
mistor temperature controller in
Figure 5. In this circuit, a comparison
is made between the voltages across a
thermistor and a resistor that is driven
by the 2.5V V
REG
output. As the
thermistor resistance rises with tem-
perature, the voltage across the
thermistor increases. When it exceeds
the voltage across R4, the compara-
tor output becomes zero and the triac
control to the heater is turned off.
Hysteresis can be added in the tem-
perature control by using CMPOUT
and R5. A 10° phase-shifted AC line
signal is supplied through R1, R2 and
C1 to the zero-cross comparator for
firing the triac.
In the overtemperature detect
application in Figure 6, an isolated
thermocouple is cold junction com-
pensated with the micropower LT1389
reference and the Yellow Springs ther-
mistor. The micropower LT1495 op
amp provides gain to give an overall
0°C–200°C temperature range,
adjustable by changing the 10M feed-
back resistor. The isolated comparator
is connected to compare at 1.25V or
TIME (ms)
0
V
REG
(V)
2.5
3.3
0
1531 F02
2010 30 40
V
CC
= 5V, C
VPW
= 1µF
I
V
REG
= 100µA
NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE
ON V
PW
> 3.3V AND THE POWER-LISTEN CYCLE
SAMPLING
IVREG (mA)
tSAMPLE (ms)
1531 F03
30
25
20
15
10
5
001234
VCC = 4.5V
VCC = 5.5V
VCC = 5V
5.6V
AC
120V
NEUTRAL
HEATER
25Ω
ISOGND
V1
V2
V3
V4
ISOLATION
BARRIER
1531 TA01
VALID
GND
390Ω
R5
HYSTERESIS
1M
R1/(R1 + R2) = ATTENUATION
R2 • C1 = Tan(θ)/(2π60Hz)
θ = DESIRED PHASE LAG
COMPARISON
V1 – V3 > V4 – V2
R = R
O
• exp (B/T – B/T
O
)
B = 3807
T
O
= 298°K
2.5V
100µF
1µF
LTC1531
R2
47k
R1
680k
150Ω
+
–
THERM
30k
YSI 44008
R4
50k
V
PW
V
CC
SHDN
CMPOUT
V
REG
ZCDATA
ZC
+
ZC
–
DATA
LED
1k
QD
C1
0.01µF
2.5k
5W
+
+
IN4004
TECCOR
Q4008L4
OR EQUIVALENT
2N2222
OR
2N3904
Figure 3. Typical V
REG
and V
PW
with I
V
REG
= 100µA
Figure 4. Typical average t
SAMPLE
vs I
V
REG
Figure 5. Isolated thermistor temperature controller
Linear Technology Magazine • November 1998
26
DESIGN FEATURES
ISOGND
V1
V2
V3
V4
1531 TA08
VALID
GND
ISOLATION
BARRIER
10M
33k
10.2k
1M
2.5V
2.2µFLT1389
LTC1531
+
–
VPW
VCC
VCC
VTRIP
SHDN
CMPOUT
VREG
ZCDATA
ZC+ZC –
DATA QD
+
–
+
–
+
LT1495
1.74M
1.13k
GAIN SET FOR 0°C TO 200°C
UNUSED
OP AMP
10.7k
K
THERM
30k
YSI 44008
–
+
LT1495
COLD JUNCTION COMPENSATES 0°C TO 60°C
OUTPUT, VTRIP = 1 AT ≥100°C
RESPONSE TIME = 10 sec
RESOLUTION = 4mV ≥ 0.5°C
the center of the temperature range.
In this case, V
TRIP
goes high when the
temperature exceeds 100°C.
The LTC1531 can use the high
impedance nature of CMPOUT as a
duty-cycle modulator, as in the iso-
lated voltage sense application in
Figure 7. The duty-cycle output of the
comparator is smoothed with the
LT1490 rail-to-rail op amp to repro-
duce the voltage at V
IN
. The output
time constant, R2 • C2, should
approximately equal the input time
constant, 35 • R1 • C1. The factor of
35 results from CMPOUT being on for
only 100µs at an average sample rate
of 300Hz.
Conclusion
The LTC1531 is a versatile part for
sensing signals that require large iso-
lation voltages. The ability of the
LTC1531 to supply power through
the isolation barrier simplifies appli-
cations; it can be combined with other
micropower circuits in a variety of
isolated signal conditioning and sens-
ing applications.
V
OUT
0V – V
CC
FULL-SCALE
OUTPUT
ISOGND
V1
V2
V3
V4
1531 TA05
VALID
10k
GND R1
1M
ISOLATION
BARRIER RESOLUTION = 4mV
SETTLING TIME CONSTANT = 10 sec
2.5V
2.2µF
0V TO 2.5V
FULL-SCALE
INPUT
C1
0.22µF
V
IN
LTC1531
+
–
V
PW
V
CC
V
CC
V
CC
V
CC
SHDN
CMPOUT
V
REG
ZCDATA
ZC
+
ZC
–
DATA
10k
R3
10M QD
R2
10M
C2, 1µF
+
–
+
LT1490
Figure 6. Overtemperature detect
Figure 7. Isolated voltage detect
for
the latest information
on LTC products,
visit
www.linear-tech.com
Linear Technology Magazine • November 1998
27
DESIGN IDEAS
PolyPhase Switching Regulators
Offer High Efficiency in Low Voltage,
High Current Applications by Craig Varga
Introduction
In recent years, there has been a
tendency in the digital world toward
smaller device geometries and higher
gate counts. This has led to require-
ments for lower voltages and higher
currents for logic supplies. As this
trend continues, to levels under 2V
and over 30A, the conventional buck
regulator approach ceases to be viable.
Switch currents are too high for a
single device to handle, inductor
energy storage exceeds what is avail-
able in surface mount technology and
ripple current requirements on input
capacitors dictate the use of many
capacitors in parallel. Although all
this may seem like enough of a
challenge, the transient response
requirements also become much more
severe. The question that arises is: “is
there a topology that can solve all of
these problems simultaneously? ” The
answer is “PolyPhase™.”
What is PolyPhase, Anyway?
Since it is apparent that multiple
FETs need to be paralleled to handle
the current requirements, the ques-
tion is whether there is a way to drive
them intelligently, rather than by
brute force. The solution is to stagger
the turn-on times so that the dead
bands in the input current waveform
are “filled up,” so to speak. In the
simplest implementation, there are
essentially two independent synchro-
nous buck regulators operating 180°
5
4
6
8
12
AST
AST
–T
+T
RET
RCC
3
1
Q
SYNC1
SYNC2
I
SENSE2
I
SENSE1
I
SENSE1
I
SENSE2
SYNC1
SYNC2
Q
OSC
10
11
13
5V
5V
12V 5V
C23
0.47µF
CHARGE PUMP
OPTIONAL
U4
CD4047
(POWER FROM 5V)
2RX
RST
CX
9
C6, 100pF,
NPO, 5%
R6
3.09k
1%
R3
1k
C22
1µF
10V
C3
22µF
25V
C13
180pF
C21
47µF
10V
C1
1µF
16V
R1
51Ω
R4
1k
C28
0.1µF
+
C7
470µF
6.3V
+
R10
10Ω
R24
39k
+
C35
1µF
10V
C34
1µF
10V
C36
1µF
10V
+V
IN
R13
0.002Ω
TRACE Q1
MMBT3906LT1
D1
BAW56LT1
R12
10k
D4
BAT54 D2
BAT54
D3
BAT54
C18
1000pF
+
R5
9.76k
1% +V
OUT
2.5V/30A
OUTPUT
RTN
+V
IN
INPUT
RTN
7
8
5
6
2
1
4
3
U2
LTC1430ACS8
C14
1500pF
C11
470µF
6.3V
+
R14
10k
R28
1Ω
C25
1µF
16V
C19
6800pF
C5
1µF
10V
PV
CC2
G2
SHDN
COMP
PV
CC1
G1
FB
GND
R22
1Ω
R23
1Ω
5V
12V
CHARGE PUMP
OPTIONAL
R20
1Ω
Q2
Si4410DY
Q3
Si4410DY
L2
0.8µH
ETQP1F0R8LB
Q5
Si4410DY
Q4
Si4410DY
R21
1Ω
C10
470µF
6.3V
C32
470µF
6.3V
+
7
8
5
6
2
1
4
3
U3
LTC1430ACS8
C15
1500pF
C8
470µF
6.3V
C17
1000pF
+
R15
10k
C2
1µF
16V
R29
1Ω
R2
9.76k
1%
C16
180pF
C24
1µF
16V
C20
6800pF
C4
1µF
10V
PV
CC2
G2
SHDN
COMP
PV
CC1
G1
FB
GND
C12
470µF
6.3V
R26
1Ω
R27
1Ω
R19
1Ω
C27, 0.47µF
Q6
Si4410DY
Q7
Si4410DY
L1
0.8µH
ETQP1F0R8LB
Q9
Si4410DY
Q8
Si4410DY
R25
1Ω
R16
10Ω
C9
470µF
6.3V
C33
470µF
6.3V
++
R17
10k, 1%
R11
0.002Ω
TRACE
R18
10k
1%
R7
51k
(4)
C30
0.022µF
12V R32
10Ω
R8
4.3k
C26
22µF
25V
+
C29
1µF
16V
C31
0.022µF
C38
3300pF
C37
3300pF
27
6
××
×
481
3+
–
U1
LT1006
SHARE AMPLIFIER
NOTES:
1. ALL RESISTORS = ±5% UNLESS NOTED OTHERWISE.
2. INPUT/OUTPUT CAPACITORS = KEMET T510 SERIES (408) 986-0424
3. TRACE RESISTORS R11, R13 = 0.1
"
WIDE x 0.675
"
LONG
R9
4.3k
R31
1k
R30
1k
+
CLOCK
Figure 1. 2-phase synchronous buck regulator
Authors can be contacted
at (408) 432-1900
Linear Technology Magazine • November 1998
28
DESIGN IDEAS
out of phase. The net effect of this is
that the input and output ripple cur-
rents of the two channels tend to
cancel during steady-state operation.
This results in significant reductions
in both input and output capacitor
requirements. There is also a fourfold
reduction in the total inductor energy
storage requirement, which means
much smaller inductors and vastly
improved transient dynamics. Dur-
ing a large load step, the two channels
operate at maximum duty factor in an
attempt to maintain the desired out-
put voltage. Both inductor currents
slew rapidly and are now additive,
since they are going in the same direc-
tion. Hence, the slew rate is double
what a single channel could do for
equal inductor values. However, due
to the ripple current cancellation dur-
ing steady-state conditions, the two
inductors can be reduced to approxi-
mately one-half the value that a single
channel design would require for equal
ripple currents. Since during slew
they appear to be operating in paral-
lel, the actual slew rate is four times
that of a single channel design with
equal steady-state output ripple cur-
rent. Both input and output ripple
frequencies are double those of a
single-channel design, further sim-
plifying filtering requirements.
Why Stop at Two?
If two channels are good, aren’t more
channels better? In a word, yes. In
principle, there is no limit to the num-
ber of parallel channels that can be
added. As the number of channels, n,
increases, the ripple frequency
increases to n times the single-chan-
nel frequency. Input and output RMS
ripple currents continue to decrease.
Diminishing returns are reached as n
rises above three. At three stages, the
ripple reductions are very substan-
tial and dynamic performance is
excellent. Adding more channels pro-
duces slight improvements but the
dramatic gains will have been real-
ized by n = 3. The only real penalty is
added complexity.
Another aspect worth considering
is expandability. It is reasonable with
today’s technology to build a single
stage, all surface mount, synchro-
nous buck regulator capable of
approximately 15 amps continuous
output current. At higher current lev-
els, power dissipation in individual
devices becomes difficult to manage.
Gate drive capability of driver ICs is
somewhat limited and is incapable of
driving enough paralleled MOSFETs
to handle larger currents at high fre-
quencies. Inductors capable of greater
energy storage cannot be obtained in
surface mount technology. Therefore,
if currents substantially greater than
15 amps are required, it is a simple
matter of paralleling additional stages
to obtain the higher currents. For 30
amps, use two stages. At 45 amps,
use three stages and so on. As more
stages are added, the ripple currents
are further reduced, so there is no
need to add large quantities of input
or output capacitors to handle the
higher current capability.
The bottom line is that PolyPhase
designs offer a considerable reduc-
tion in the cost and volume of the
power devices at the expense of a little
added complexity in the control
circuitry.
2-Phase Design Example
The circuit shown in Figure 1 is a 2-
phase, voltage mode–control, synchro-
nous buck regulator designed for a
5V input and output voltages below
3.3V. It is intended to power large
memory arrays, ASICs, FPGAs and
the like in server and workstation
applications. The output is capable of
more than 30 amps continuous at
outputs of 2.5V and below, with peak
current capability of greater than 40
amps. The design is entirely surface
mount and the maximum height above
the board is 5.5mm. Overall board
area is only 4.24 in
2
. Efficiency is
excellent, as can be seen in the curve
in Figure 2. Output ripple voltage is
shown in Figure 3. The circuit’s
dynamic response to a 10 amp load
step is shown in Figure 4. The
CURRENT (A)
0
EFFICIENCY (%)
100
95
90
85
80
75
70 510 15 20
DC201 F01b
25 30
V
IN
= 5V
V
OUT
= 2V
V
OUT
= 3.3V
V
OUT
= 2.5V
2µs/DIV
20mV/DIV
V
O
= 2.5V
V
IN
= 5V 10µs/DIV
100mV/DIV
Efficiency of Figure 1’s circuit, V
IN
= 5V
Figure 3. Output ripple with 30A load Figure 4. Transient response with 10A load step (100ns rise time)
∆V = 160mV
Linear Technology Magazine • November 1998
29
DESIGN IDEAS
response is dominated by the output
capacitor’s ESR and shows the out-
put voltage recovered to the original
level in under 10µs. Figures 5 and 6
show how the input and output ripple
currents cancel.
Circuit Operation
The basic design consists of two
LTC1430CS8-based synchronous
buck regulators connected in parallel
and operated 180° out of phase. U4,
the CD4047 oscillator, is used to gen-
erate the required clock signals and
synchronize the two LTC1430s.
Unfortunately, simply connecting two
regulators in parallel is a recipe for
instant disaster. The output voltages
of the two regulators will be slightly
different due to normal component
tolerances. Therefore, the higher out-
put voltage channel will attempt to
supply the full load current, while the
lower voltage output will sink current
from the output in a desperate attempt
to reduce the output voltage to where
it thinks it should be. The result is
like a dog chasing its tail, with large
currents running around in a circle
and going nowhere.
2µs/DIV
A + B
CHANNEL A
CHANNEL B
5A/DIV
I
O
= 25A
2µs/DIV
CHANNEL A
5A/DIV
CHANNEL A + B =
TOTAL INPUT
RIPPLE CURRENT,
UNFILTERED
CHANNEL B
5A/DIV
I
O
= 15A
f = 306kHz
Op amp U1 solves this problem.
Because the two channels are identi-
cal, if the output currents are the
same, the input currents will be also.
Low value sense resistors are included
in the input power path to allow the
circuit to measure input current. U1
then forces the input current of chan-
nel two to match the input current of
channel one by making small adjust-
ments in channel two’s output voltage.
It does this by adding or subtracting
a small amount of current from chan-
nel two’s feedback divider. The two
sense resistors are short lengths of
PCB trace and only need to be ratio-
metrically accurate. Absolute value
of these resistors is not important
(see Linear Technology Application
Note 69, Appendix A, for a discussion
on how to design trace resistors).
The only remaining trick in the
circuit is the role of Q1 and its asso-
ciated circuitry. At start-up, the
LTC1430’s clock frequency is slowed
down to approximately 10kHz until
the output voltage rises to approxi-
mately 50% of the desired level. If,
during this start-up phase, an attempt
is made to synchronize the controller
to a very high frequency, the oscilla-
tor ramp amplitude never rises to a
level sufficiently high to trip the PWM
comparator and enable the FET driv-
ers. Therefore, the output gets stuck
on ground. Q1 fixes this by forcing
the sync signals high during the turn-
on transient. Once the output voltage
nears its final level, the clock signals
are allowed to synchronize the two
PWM controllers.
Conclusion
The design shown combines the per-
formance characteristics that will be
required to power the digital systems
that will emerge over the next several
years. Circuits based on these con-
cepts will be able to efficiently deliver
very high current at low voltage while
relying on surface mount technology
to maintain low profile and minimum
use of real estate. They will also pro-
vide substantially better dynamic
performance than has been available
using more conventional design meth-
odologies and do all of this at a
reasonable cost.
Figure 5. Ripple cancellation—input Figure 6. Ripple cancellation—output
for
the latest information
on LTC products,
visit
www.linear-tech.com
Linear Technology Magazine • November 1998
30
DESIGN IDEAS
Level Shift Allows CFA Video Amplifier
to Swing to Ground on a Single Supply
A current feedback (CFA) video
amplifier can be made to run off a
single supply and still amplify ground-
referenced video with the addition of
a simple and inexpensive level shifter.
The circuit in Figure 1 is an amplifier
and cable driver for a current output
video DAC. The video can be compos-
ite or component but it must have
sync. The single positive supply is
12V but could be as low as 6V for the
LT1227.
The output of the LT1227 CFA
used here can swing to within 2.5V of
the negative supply with a 150Ω load
over the commercial temperature
range of 0°C to 70°C. Five diodes in
the feedback loop are used, in con-
junction with C5, to level shift the
output to ground. The video from the
output of the LT1227 charges C5 and
the voltage across it allows the output
to swing to ground or even slightly
negative. However, the level of this
negative swing will depend on the
video signal and so will be unpredict-
able. When the scene is black, there
must be sync on the video for C5 to
remain charged. A zero-level compo-
nent video signal with no sync will not
work with this circuit. The CFA out-
put will try to go to zero, or as low as
it can, and the diodes will turn off.
The load will be disconnected from
the CFA output and connected
through the feedback resistor to the
network of R6 and R7. This causes
about 150mVDC to appear at the
output, instead of the 0V that should
be there.
The ground-referenced video sig-
nal at the input needs to be level
shifted into the input common mode
range of the LT1227 (3V above nega-
tive supply). R4 and R5 shift the input
signal to 3V. In the process, the input
video is attenuated by a factor of 2.5.
For correct gain, no offset and with a
zero source impedance, R4 would be
1.5k. To compensate for the presence
of R3, R4 is made 1.5k minus R3, or
1.46k. The trade off is a gain error of
about 1.5%. If R4 is left 1.5k, the gain
is correct, but there is an offset error
of 75mV. R6, R7 and R8 set the gain
and the output offset of the amplifier.
A noninverting gain of five is taken to
compensate for the attenuation in the
input level shifter and the cable ter-
mination.
The voltage offset on the output of
this circuit is a rather sensitive func-
tion of the value of the input resistors.
For instance, an error of 1% in the
value of R6 will cause an offset of
30mV (1% of 3V) on the output. This
is in addition to the offset error intro-
duced by the op amp. Precision resistor
networks are available (BI technolo-
gies, 714-447-2345) with matching
specifications of 0.1% or better. These
could be used for the level shifting
resistors, although this would make
adjustments like the one made to R4
difficult.
+
+
–
+
LT1227
5× 1N4148
R9 75ΩLOAD
R10
75Ω
C3 47µF
C4
0.1µFC5 4.7µF
R8 1.5k
R7
1.5k
R6
499Ω
C2
4.7µF
C1
10µF
FILM
R5
1k
*R4
1.46k
*R3
38.1Ω
*R2
77.37Ω
R1 75Ω
SOURCE
5V 12V
75Ω VIDEO SOURCE
USED FOR TESTING
*RESISTORS ARE A COMBINATION OF TWO 1% VALUES,
R2 IS A SERIES COMBINATION OF 75 Ω AND 2.37Ω
R3 IS A PARALLEL COMBINATION OF 75 Ω AND 77.3Ω
R4 IS A SERIES COMBINATION OF 1.3k + 160 Ω = 1.46k
ALL RESISTORS ARE 1% METAL FILM
B
A
by Frank Cox
Figure 1. Amplifier and cable driver for current-output video DAC
continued on page 36
Linear Technology Magazine • November 1998
31
DESIGN INFORMATION
Component and Measurement
Advances Ensure 16-Bit DAC
Settling Time (Part Two) by Jim Williams
Introduction
Reliable measurement of 16-bit DAC
settling time is extremely challeng-
ing. Part one of this article (in the
August 1998 issue of Linear Technol-
ogy magazine) described a method for
making this measurement. This sec-
ond part discusses detailed circuitry
and presents results.
Detailed
Settling-Time Circuitry
Figure 1 is a detailed schematic of the
16-bit DAC settling-time-measure-
ment circuitry. The input pulse
switches all DAC bits simultaneously
and is also routed to the oscilloscope
via a delay-compensation network.
The delay network, composed of
CMOS inverters and an adjustable
RC network, compensates the
oscilloscope’s input step signal for
the 12ns delay through the circuit’s
measurement path. The DAC
amplifier’s output is compared against
the LT1236-10V reference via the pre-
cision 3k summing resistor ratio set.
The LT1236 also furnishes the DAC
reference, making the measurement
ratiometric. The clamped settle node
is unloaded by A1, which drives the
sampling bridge. Note the additional
clamp diodes at A1’s output. These
diodes prevent any possibility of
abnormal A1 outputs (due to lost
supply or supply sequencing anoma-
lies) from damaging the diode array.
A3 and associated components tem-
+
7
11 D5
AC
BALANCE
2.5k RESIDUE
AMPLIFIER
OUTPUT TO
OSCILLOSCOPE
0.01V/DIV = 500µV/DIV
AT DAC AMPLIFIER
OUTPUT
SAMPLING BRIDGE
SAMPLING BRIDGE
TEMPERATURE CONTROL
108
4
14
1.1k
Q1
Q4
11
10 13
8
7
96
Q3
5pF
3pF
0.1µF10µF
510Ω
D6
33Ω*
1.3k*
Q2
D7
CA3039
ARRAY
12
113
–5V
–5V
–5V
SKEW COMP
2.5k
3
25
2.2k1.1k
5V
15V
15V
–15V
–5V
1k
0.01µF
2.2k 10µF 0.1µF
470Ω
560Ω
51Ω
820Ω51Ω680Ω
500Ω
BASELINE
ZERO
62Ω
HEAT
SENSE
: 74HC04
: 1N4148
SAMPLING BRIDGE AND TEMPERATURE
CONTROL DIODES: HARRIS CA3039M (800) 442-7747
*1% FILM RESISTOR
**VISHAY VHD-200, RATIO SET: 10ppm MATCHING
D7 TO D9: 1N5711
Q1, Q2: MRF-501
Q3, Q4: LM3045 ARRAY
USE IN-LINE COAXIAL 50Ω TERMINATOR FOR
PULSE GENERATOR INPUT. DO NOT MOUNT
50Ω RESISTOR ON BOARD
DERIVE 5V AND –5V SUPPLIES FROM ±15V.
USE LT317A FOR 5V, LT1175-5 FOR –5V
CONSTRUCTION IS CRITICAL—SEE TEXT
Q5
2N2219
1.5k*
(SELECT—
SEE TEXT)
10k*
10k*
–
+
A2
LT1222
–
+
A3
LT1012
0.1µF10µF
+
+
V
CC
RC1
5k
5V
WIDTH
SAMPLE DELAY/
WINDOW GENERATOR
5V
5V
74HC123
5V
4.7k
4.7k
20k
DELAY
1000pF
5.1k
C1 Q1 Q2 CLR2 B2 A2
A1 B1 CLR1 Q1 Q2 C2 RC2 GND
470pF
AN74 F06
5.1k
REF
5V
15V
LT1236-10
OUTNC IN
47µF
TANT
0.1µF510Ω
–10V
REF
GND
SAMPLING
BRIDGE
DRIVER
SETTLE
NODE
3k**
–15V
15V
–15V
–15V
DUT
LTC1597
C
COMP
(SELECT—
SEE TEXT)
0V TO 10V
TRANSITION
TIME CORRECTED INPUT STEP
TO OSCILLOSCOPE
–
+
15pF
1k
5V
PULSE
GENERATOR
INPUT
50Ω
IN-LINE TERMINATION
(SEE TEXT AND NOTES)
BRIDGE DRIVER/RESIDUE AMPLIFIER
DELAY COMPENSATION ≈12ns AUT
LT1468
+
3k**
D8 D9
–
+
A1
LT1220
SAMPLING BRIDGE SWITCHING CONTROL
Figure 1. Detailed schematic of DAC-settling-time measurement circuit; optimum performance requires attention to layout.
Linear Technology Magazine • November 1998
32
DESIGN INFORMATION
perature control the sampling diode
bridge by comparing a diodes’s for-
ward drop to a stable potential derived
from the –5V regulator. Another diode,
operated in the reverse direction (V
Z
≈
7V) serves as a chip heater. The pin
connections shown on the schematic
have been selected to provide the best
temperature-control performance.
The input pulse triggers the
74HC123 one shot. The one shot is
arranged to produce a delayed (con-
trollable by the 20k potentiometer)
pulse whose width (controllable by
the 5k potentiometer) sets diode bridge
on-time. If the delay is set appropri-
ately, the oscilloscope will not see any
input until settling is nearly complete,
eliminating overdrive. The sample
window width is adjusted so that all
remaining settling activity is observ-
able. In this way, the oscilloscope’s
output is reliable and meaningful data
may be taken. The one shot’s output
is level shifted by the Q1–Q4 transis-
tors, providing complementary
switching drive to the bridge. The
actual switching transistors, Q1–Q2,
are UHF types, permitting true differ-
ential bridge switching with less than
1ns of time skew.
A2 monitors the bridge output,
provides gain and drives the oscillo-
scope. Figure 2 shows circuit
waveforms. Trace A is the input pulse,
trace B the DAC amplifier output,
trace C the sample gate and trace D
the residue amplifier output. When
the sample gate goes low, the bridge
switches cleanly and the last 1.5mV
of slew are easily observed. Ring time
is also clearly visible and the ampli-
fier settles nicely to final value. When
the sample gate goes high, the bridge
switches off, with only 600µV of feed-
through. The 100µV peak before
bridge switching (at ≈3.5 vertical divi-
sions) is feedthrough from A1’s out-
put, but it is similarly well controlled.
Note that there is no off-screen activ-
ity at any time—the oscilloscope is
never subjected to overdrive.
The circuit requires trimming to
achieve this level of performance. The
bridge temperature control point is
set by grounding Q5’s base prior to
applying power. Next, apply power
and measure A3’s positive input with
respect to the –5V rail. Select the
indicated resistor (1.5k nominal) for a
voltage at A3’s negative input (again,
with respect to –5V) that is 57mV
below the positive input’s value.
Unground Q5’s base and the circuit
will control the sampling bridge to
about 55°C:
25°C ROOM +
= 30°C RISE = 55°C
57mV
1.9mV/°C DIODE DROP
A = 10V/DIV
B = 10V/DIV
C = 10V/DIV
D = 500µV/DIV
1µs/DIV 1µs/DIV
B = 10V/DIV
A = 10V/DIV
C = 500µV/DIV
Figure 2. Settling time circuit waveforms include time-corrected
input pulse (Trace A), DAC amplifier output (Trace B), sample gate
(Trace C) and settling-time output (Trace D). The sample gate
window’s delay and width are variable.
Figure 3. Settling time circuit’s output (Trace C) with unadjusted
sampling bridge AC and DC trims. The DAC is disabled and the
settle node grounded for this test. Excessive switch-drive
feedthrough and baseline offset are present. Traces A and B are
the input pulse and sample window, respectively.
1µs/DIV
B = 10V/DIV
A = 10V/DIV
C = 500µV/DIV
B = 500µV/DIV
1µs/DIV
A = 10V/DIV
Figure 5. Oscilloscope display with inadequate sample gate
delay: the sample window (Trace A) occurs too early,
resulting in off-screen activity in the settle output (Trace B).
The oscilloscope is overdriven, making displayed
information questionable.
Figure 4. The settling time circuit’s output (Trace C) with the
sampling bridge trimmed. As in Figure 3, the DAC is disabled and the
settle node grounded for this test. Switch drive feedthrough and
baseline offset are minimized. Traces A and B are the input pulse
and sampling gate, respectively.
Linear Technology Magazine • November 1998
33
DESIGN INFORMATION
The DC and AC bridge trims are
made once the temperature control is
functional. Making these adjustments
requires disabling the DAC and
amplifier (disconnect the input pulse
from the DAC and set all DAC inputs
low) and shorting the settle node
directly to the ground plane. Figure 3
shows typical results before trimming.
Trace A is the input pulse, trace B the
sample gate and trace C the residue
amplifier output. With the DAC-
amplifier disabled and the settle node
grounded, the residue amplifier out-
put should (theoretically) always be
zero. The photo shows this is not the
case for an untrimmed bridge. AC and
DC errors are present. The sample
gate’s transitions cause large, off-
screen residue amplifier swings (note
residue amplifier’s response to the
sample gate’s turn-off at the ≈8.5 ver-
tical division). Additionally, the residue
amplifier output shows significant DC
offset error during the sampling inter-
val. Adjusting the AC balance and
skew compensation minimizes the
switching induced transients. The DC
offset is adjusted out with the base-
line zero trim. Figure 4 shows the
results after making these adjust-
ments. All switching-related activity
is now well on-screen and offset error
is reduced to unreadable levels. Once
this level of performance has been
achieved, the circuit is ready for use.
Unground the settle node and restore
the input pulse connection to the DAC.
Using the Sampling-Based
Settling Time Circuit
Figures 5 through 7 underscore the
importance of positioning the sam-
pling window properly in time. In
Figure 5 the sample gate delay ini-
tiates the sample window (trace A) too
early and the residue amplifier’s
output (trace B) overdrives the oscil-
loscope when sampling commences.
Figure 6 is better, with only slight off-
screen activity. Figure 7 is optimal.
All amplifier residue is well inside the
screen boundaries.
In general, it is good practice to
“walk” the sampling window up to the
last millivolt or so of amplifier slewing
so that the onset of ring time is
observable. The sampling based
approach provides this capability and
it is a very powerful measurement
tool. Additionally, remember that
slower amplifiers may require
extended delay and/or sampling win-
dow times. This may necessitate larger
capacitor values in the 74HC123 one-
shot timing networks.
Compensation
Capacitor Effects
The DAC amplifier requires frequency
compensation to get the best possible
settling time. The DAC has appreciable
output capacitance, complicating
amplifier response and making care-
ful compensation capacitor selection
even more important. Figure 8 shows
effects of very light compensation.
1µs/DIV
A = 10V/DIV
B = 500µV/DIV
1µs/DIV
A = 10V/DIV
B = 500µV/DIV
Figure 7. Optimal sample-gate delay positions the
sampling window (Trace A) so that all settle output
(Trace B) information is well inside screen boundaries.
Figure 6. Increasing the sample-gate delay positions
the sample window (Trace A) so settle output (Trace
B) activity is on-screen.
500ns/DIV
A = 5V/DIV
B = 500µV/DIV
500ns/DIV
A = 5V/DIV
B = 500µV/DIV
Figure 9. Excessive feedback capacitance
overdamps response (t
SETTLE
= 3.3µs).
Figure 8. This settling profile with inadequate feedback
capacitance shows underdamped response. Excessive ringing
feeds through during the sample gate off-period (third through ≈
sixth vertical divisions) but is tolerable (t
SETTLE
= 2.8µs).
Linear Technology Magazine • November 1998
34
DESIGN INFORMATION
Trace A is the time-corrected input
pulse and trace B the residue ampli-
fier output. The light compensation
permits very fast slewing but excessive
ringing amplitude over a protracted
time results. The ringing is so severe
that it feeds through during a portion
of the sample gate off-period, although
no overdrive results. When sampling
is initiated (just prior to the sixth
vertical division) the ringing is seen to
be in its final stages, although still
offensive. Total settling time is about
2.8µs. Figure 9 presents the opposite
extreme. Here, a large value compen-
sation capacitor eliminates all ringing
but slows down the amplifier so much
that settling stretches out to 3.3µs.
The best case appears in Figure 10.
This photo was taken with the com-
pensation capacitor carefully chosen
for the best possible settling time.
Damping is tightly controlled and set-
tling time goes down to 1.7µs.
Settling Times
of Various Amplifiers
The previous results, using the
LT1468 amplifier, provide extremely
fast settling times with high accuracy
over temperature. Many applications
can tolerate reduced speed, reduced
temperature stability or both. Set-
tling times for a number of amplifiers,
along with commentary, can be found
in LTC Application Note 74, Figure
34. “Optimized” settling times were
recorded after individually trimming
the feedback capacitors. The “con-
servative” times represent the
worst-case settling times using stan-
dard-value compensation capacitors
with no trimming.
Conclusion
The sampling-based settling-time cir-
cuit appears to be a very useful
measurement solution. Expanded dis-
cussion and tutorial appear in this
article’s “root” publication: LTC
Application Note 74, Component and
Measurement Advances Ensure 16-
Bit DAC Settling Time.
500ns/DIV
B = 500µV/DIV
A = 5V/DIV
Figure 10. Optimal feedback capacitance yields a tightly
damped signature and the best settling time (t
SETTLE
= 1.7µs).
Net1 and Net2 Serial Interface Chip
Set Supports Test Mode by David Soo
Some serial networks use a test mode
to exercise all of the circuits in the
interface. The network is divided into
local and remote data terminal
equipment (DTE) and data-circuit-
terminating equipment (DCE), as
shown in Figure 1. Once the network
is placed in a test mode, the local DTE
will transmit on the driver circuits
and expect to receive the same sig-
nals back from either a local or remote
DCE. These tests are called local or
remote loopback.
As introduced in the February 1998
issue of Linear Technology, the
LTC1543/LTC1544/LTC1344A chip
set has taken the integrated approach
to multiple protocol. By using this
chip set, the Net1 and Net2 design
work is done. The LTC1545 extends
the family by offering test mode capa-
bility. By replacing the 6-circuit
LTC1544 with the 9-circuit LTC1545,
the optional circuits TM (Test Mode),
RL (Remote Loopback) and LL (Local
Loopback) can now be implemented.
Figure 2 shows a typical applica-
tion using the LTC1543, LTC1545
and LTC1344A. By just mapping the
chip pins to the connector, the design
of the interface port is complete. The
chip set supports the V.28, V.35, V.36,
RS449, EIA-530, EIA-530A or X.21
protocols in either DTE or DCE mode.
Shown here is a DCE mode connec-
tion to a DB-25 connector. The
mode-select pins, M0, M1 and M2,
are used to select the interface proto-
col, as summarized in Table 1.
LOCAL
DTE
LOCAL
DCE LL REMOTE
DCE RL REMOTE
DTE
5451CTL/3451CTL
emaNedoM2M1M0M
desUtoN 000
A035-AIE 001
035-AIE 010
12.X 011
53.V 100
63.V/944SR 101
82.V/232SR 110
elbaCoN 111
Table 1. Mode pin functions
Figure 1. Serial network
Linear Technology Magazine • November 1998
35
DESIGN INFORMATION
10
17
18
D2
D1
LTC1545
D3
R2
R1
R3
VCC
VDD
VEE
GND
D4
1,19
2,20
3
4
5
6
7
8
9
R4EN
D4ENB 15
16
24
23
22
25
26
27
28
29
30
31
32
33
34
35
36
M0
M1
M2
DCE/DTE
11
12
13
14
D5 21
R4
R5
D2
LTC1543
RXD
RXC
TXC
SCTE
TXD
CTS
DSR
DCD
DTR
RI
LL
RTS
RL
TM
M0
M1
M2
DCE/DTE
VCC
NC
NC
3
16
17
9
15
12
24
11
2
1
5
13
6
8
22
10
20
23
4
19
7
14
1544 F24
D3
R2
R1
R3
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
VCC
VCC
VCC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
CHARGE
PUMP
+
28
3
1
2
4
5
6
7
8
9
10
NC
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
VEE
M0
M1
M2
21
LATCH
C12
1µF
C13
1µF
C11
1µF
C10
1µF
C9
1µF
RXD A (104)
RXD B
RXC A (115)
RXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
TXC A (114)
TXC B
SGND (102)
SHIELD (101)
DB-25 FEMALE
CONNECTOR
CTS A (106)
CTS B
DSR A (107)
DSR B
RTS A (105)
RTS B
DCD A (109)
DCD B
DTR A (108)
DTR B
18
21
25
LL (141)
RL (140)
TM (142)
RI (125)*
VDD
VCC
VEE
C1–
C1+
C2–
VEE
C2+
*OPTIONAL: FOR USE WITH
DB-26 CONNECTOR
Figure 2. Typical application: Controller-selectable DCE port with DB-25 connector
Linear Technology Magazine • November 1998
36
Fortunately, there is always syn-
chronization information associated
with video. A simple circuit can be
used to DC restore voltage offsets
produced by resistor mismatch, op
amp offset or DC errors in the input
video. Figure 2 shows the additional
–
+
5V
0V
VIDEO
HOLD
SAMPLE
CLAMP PULSE
B
A
5V 12V
1/2 LTC201A
13
2, 15
4, 51, 16
3, 14
R1
10k
R2
10k
R3 10k
5V
R4
1.40k
R5
50k
R6
20k
C4 0.1µF
1/2 LT1632
C2 6800pF
FILM
C3
0.1µF
12V
R7 10k
C1
10µF
FILM
TO FIGURE 1,
POINT
TO FIGURE 1,
POINT
DC RESTORE LEVEL
(ADJUST FOR DESIRED
BLANKING LEVEL)
circuitry needed to perform this func-
tion. The LTC201A analog switch and
C1 store the offset error during blank-
ing. The clamp pulse should be 3µs or
wider and should occur during blank-
ing. It can conveniently be made by
delaying the sync pulse with one shots.
If the sync tip is clamped, the clamp
pulse must start after and end before
the sync pulse or offset errors will be
introduced. The integrator made with
the LT1632 adjusts the voltage at
point B (see Figure 1) to correct the
offset.
Figure 2. DC restore subcircuit
configuration, the part performs one
conversion, then automatically enters
the power-down mode. The duration
of the power-down mode is propor-
tional to the capacitor value.
While CS is held high, the serial
data out pin is high impedance. Once
CS is pulled low, the part begins
outputting data under the control of
the SCLK pin.
This device can operate with either
an internal or external serial clock. If
the SCLK pin is left floating, the
LTC2400 automatically detects this
state and switches to internal clock
mode. If the user drives the SCLK pin
with his own clock, the part is auto-
matically switched to external clock
mode.
Many delta-sigma ADC’s on the
market include a PGA. These PGAs
require that the designer deal with
more device pins, status registers and
timing sequences. Additionally, they
limit the circuit’s input range. For
example, if the PGA’s gain is 256 and
the reference is 2.5V the resulting
input range is 0mV to 10mV.
V
CC
V
REF
V
IN
GND
f
O
SCLK
D
OUT
CS
LTC2400
2.5V
–300mV
TO
2.8V
}
3-WIRE
SPI
INTERFACE
60Hz
REJECTION
2.7V–5.5V
1µF
The LTC2400 provides better noise
and TUE (total unadjusted error) per-
formance than previous delta-sigma
ADCs; moreover, the user is no longer
confined to a 10mV input range. The
input can still range between –12.5%
× V
REF
and 112.5% × V
REF
. The eight
MSBs determine the coarse input
range. For example, if the eight MSBs
= 00h, the input (V
IN
) is in the range:
0 < V
IN
< 10mV, whereas 01h
corre-
sponds to 10mV < V
IN
< 20mV, and so
on. This enables the LTC2400 to
directly digitize a variety of low level
sensors with large offsets.
The LTC2400 package is the small-
est on the market (SO-8). This tiny
chip combined with no external com-
ponents enables the user to greatly
reduce the board area required by
existing designs.
Conclusion
The LTC2400 is the first of a family of
delta-sigma converters from LTC. It
offers a combination of the best char-
acteristics of delta-sigma converters
and conventional converters. Its
attributes include latency-free
operation and high precision INL, DNL
and offset. It frees the user from adding
external components and is easy to
use. The on-chip sinc
4
filter reduces
line frequency noise and its harmon-
ics by 120dB, making it ideal for use
in noisy environments. With only eight
pins, an on-chip oscillator, 24-bit DNL,
4ppm INL and 10ppm TUE, the
LTC2400 is the new state of the art in
analog-to-digital conversion.
Notes:
1.Candy, J.C and G.C. Temes. “Oversampling Meth-
ods for A/D and D/A Conversion,” in Oversampling
Delta-Sigma Data Converters. IEEE Press, 1992.
2. Hauser, Max W. “Principles of Oversampling and
A/D Conversion.” Journal of the Audio Engineering
Society, Vol. 39, No. 1/2 (January/February 1991)
pp. 3–26.
Figure 8. LTC2400 typical application
LTC2400, continued from page 4
Level Shift, continued from page 30
CONTINUATIONS
Linear Technology Magazine • November 1998
37
NEW DEVICE CAMEOS
New Device Cameos
LTC1436A/LTC1436A-PLL/
LTC1437A: High Efficiency,
PLL-Lockable Switching
Regulators
The LTC1436A/LTC1436A-PLL/
LTC1437A are high efficiency, low
noise, synchronous switching regu-
lators that drive external N-channel
power MOSFETs in a phase-lockable,
fixed frequency architecture and are
ideal for notebook computers and
battery-powered equipment requir-
ing high frequency, low duty cycle
operation.
The LTC1436A/LTC1436A-PLL/
LTC1437A have all of the outstanding
features of the LTC1436/LTC1436-
PLL/LTC1437 with a reduced
minimum on-time of 300ns or less
and improved noise immunity at low
output voltages. With these improve-
ments, high performance can be
achieved at output voltages down to
1.3V with operating frequencies in
excess of 250kHz and input supply
voltages above 22V.
As with the originals, the improved
parts feature the optional Adaptive
Power™ output stage to provide good
low current efficiency while main-
taining constant frequency operation
by selectively driving two topside
N-channel MOSFETs sized for the
appropriate load range. An auxiliary
low dropout linear regulator is avail-
able to generate an additional supply
that can be used as a CPU I/O supply
or low noise audio supply. A second-
ary-winding-feedback/burst-disable
input guarantees regulation regard-
less of the primary supply load by
forcing continuous operation when
needed.
Other features include a power-on
reset timer that generates a logic-low
output signal persisting for 65,536
clock cycles after the output is within
7.5% of the regulated output voltage,
low dropout operation (99% duty
cycle), a low-battery comparator with
open-drain output and a wide supply
range for operation from 3.5V to 36V.
The parts are available in 24-lead
narrow SSOP for the LTC1436A and
LTC1436A-PLL and 28-lead SSOP for
the LTC1437A.
LTC1625 No R
SENSE
Controller Now Available in
Industrial Temperature Grade
An industrial temperature grade ver-
sion of the LTC1625 No R
SENSE
™
controller is now available for appli-
cations that require the enhanced
temperature range (–40°C to 85°C).
The LTC1625 provides true current
mode control in step-down DC/DC
converters without using a sense
resistor. A current sense signal is
obtained by monitoring the voltage
drop across the MOSFET switches,
making them perform double duty as
current sense elements. Eliminating
the sense resistor reduces board area,
lowers costs and increases efficiency.
Popular features from Linear
Technology’s other controllers have
been incorporated, such as fixed
frequency operation, N-channel MOS-
FET drive, Burst Mode™ operation,
soft-start and output voltage program-
ming. These features make the
LTC1625 an excellent choice for DC/
DC converter designs in a variety of
applications that require the highest
performance.
LTC1694:
SMBus Accelerator
The LTC1694 is a dual active SMBus
pull-up designed to enhance data-
transmission speed and reliability
under all specified SMBus loading
conditions. It consists of two bilevel,
hysteretic current source pull-ups
that replace the pull-up resistors in a
typical SMBus implementation. With
the LTC1694, the user can connect
multiple SMBus devices or use longer,
more capacitive interconnects with-
out compromising slew rates or
penalizing bus performance.
Resistive pull-ups are used in many
communications protocols that em-
ploy open-collector or open-drain
drivers. Their simplicity is offset by
the relatively slow rise times they
afford when bus capacitance is high.
Rise times can be improved by using
lower pull-up resistance values, but
the additional current through the
low value resistors increases the low
state bus voltage, decreasing noise
margins. Slow rise times can seri-
ously affect data reliability, enforcing
a maximum practical bus speed well
below the theoretical SMBus maxi-
mum transmission rate.
The LTC1694 overcomes these limi-
tations by using bilevel, hysteretic
current sources as pull-ups. During
positive bus transitions, the current
sources provide 2.2mA to quickly slew
any parasitic bus capacitance. Dur-
ing negative transitions or steady DC
levels, the current sources switch to
275µA to improve negative slew rate
and improve low state noise margins.
The fast rise times coupled with
improved low state logic swings allow
maximum transmission speed for any
given bus loading conditions.
The LTC1694 is available in the
5-lead SOT-23 plastic surface mount
package, requiring virtually the same
board area as two surface mount
resistors. The LTC1694 is specified
for operation over the 0°C to 70°C
temperature range.
LTC1530: High Power
Synchronous Switching
Regulator Controller with
Current Limit in SO-8
The LTC1530 is a high power, high
efficiency switching regulator
controller optimized for 5V buck con-
verter applications. A typical LTC1530
circuit can provide output currents of
up to 20A. Packaged in an SO-8, the
LTC1530 operates on a single supply
of up to 14V. It includes a precision
internal reference and an internal
feedback system that can provide
output voltage regulation of ±2% over
temperature, load-current and line-
voltage shifts.
The LTC1530 employs a synchro-
nous switching architecture that
drives two external N-channel output
devices. It also senses current through
the drain-source resistance (or on-
Linear Technology Magazine • November 1998
38
NEW DEVICE CAMEOS
For further information on any
of the devices mentioned in this
issue of Linear Technology, use
the reader service card or call
the LTC literature service
number:
1-800-4-LINEAR
Ask for the pertinent data sheets
and Application Notes.
resistance) of the upper N-channel
MOSFET, eliminating the need for an
external, low value sense resistor.
The current-limit trip point is set with
a single external resistor; a tempera-
ture compensation circuit keeps the
current-limit level constant as the
external MOSFET R
DS(ON)
increases
with temperature. The part also
includes an on-chip soft-start capaci-
tor; the soft-start slew rate is 0.4V/
ms. It also has a thermal protection
circuit that disables both internal
gate drivers and reduces the supply
current to 1mA when excessive die
temperatures occur. In shutdown
mode, the LTC1530 supply current
drops to 45µA.
LTC1753: Programmable
Synchronous Switching
Regulator Controller
The LTC1753 is a high power, high
efficiency, synchronous switching
regulator controller that generates a
digitally programmable output volt-
age between 1.3V and 3.5V. Step-down
conversion is optimized for a 5V input.
The internal 5-bit DAC accepts a par-
allel word and programs the output
voltage from 1.3V to 2.05V in 50mV
increments and from 2.1V to 3.5V in
100mV increments. The precision
internal reference and feedback sys-
tem provide an output voltage
accuracy of ±1.5% at room tem-
perature and ±2% (typical) over
temperature, load current and line
voltage shifts.
The LTC1753 uses a synchronous
switching architecture with two
external N-channel MOSFETs. It pro-
vides more than 14A of load current
at efficiencies exceeding 90%. The
LTC1753 senses output current
through the on-resistance of the upper
N-channel FET and provides adjust-
able current limit without the use of
an external sense resistor. External
MOSFET power dissipation is con-
siderably reduced under output
short-circuit conditions by an over-
current protection scheme built into
the LTC1753.
The free-running 300kHz oscilla-
tor frequency can be synchronized to
a faster clock if desired. Soft-start
eases inrush current and recovery
from overload conditions. Protection
features include overvoltage fault
detection, overtemperature detection
and a power-good signal when the
output voltage is within ±5%
regulation.
The LTC1753 is ideal for high
power, tight tolerance microproces-
sors applications. It is available in
20-pin SO and SSOP packages.
The LTC1597/LTC1591:
Ultra-accurate, Low Power
16- and 14-Bit Multiplying
Current Output DACs
Include On-Chip Resistors
Expanding LTC’s family of current
output, multiplying DACs are the pin-
compatible 16-bit LTC1597 and 14-bit
LTC1591. The LTC1597 features true
16-bit performance (DNL and INL,
1LSB maximum), low glitch impulse
(2nV-s typical) and low supply power
dissipation (10µW typical). The
LTC1591 offers the same level of
performance at 14-bit resolution. The
LTC1597/LTC1591 can be configured
for unipolar, 2-quadrant multiplying
or for bipolar, 4-quadrant multiply-
ing applications with no external
resistors. For a fixed 10V reference
input, the DAC unipolar output range
is 0V to –10V and the DAC bipolar
output range is ±10V. The LTC1597,
coupled with LT1468 op amp, settles
to within 0.0015% of full scale in 2µs.
The LTC1597/LTC1591 have an asyn-
chronous clear input that resets the
output to zero scale. A second pair of
parts, the LTC1597-1/LTC1591-1,
resets to a midscale output. These
devices also have a power-on reset.
The LTC1597 and LTC1591 feature
16- and 14-bit
parallel input data
busses,
respectively.
The LTC1597 and LTC1591 are
designed for applications such as
process control and industrial auto-
mation, direct digital waveform
generation, software-controlled gain
adjustment and automatic test equip-
ment. Available in 28-pin SSOP or
DIP packages, the LTC1597/LTC1591
operate on single 5V supplies.
LTC1258-2.5 Micropower
Low Dropout Reference
The LTC1258-2.5 is a micropower
bandgap reference that combines high
accuracy and low drift with very low
supply current and small package
size. The combination of only 4µA
quiescent current and low, 200mV
Max dropout makes it ideal for bat-
tery-powered equipment.
This reference uses curvature
compensation to obtain a low
temperature coefficient and trimmed
thin-film resistors to achieve high
output accuracy. The reference can
supply up to 10mA and sink up to
2mA, making it ideal for precision
regulator applications. The LTC1258-
2.5 is stable without an output bypass
capacitor, but is also stable with
capacitance up to 1µF. This feature is
important in critical applications
where PC board space is at a premium
and fast settling is demanded.
This series reference provides sup-
ply current and power dissipation
advantages over shunt references that
must idle the entire load current to
operate.
The LTC1258-2.5 is available in 8-
pin SO and MSOP packages.
for
the latest information
on LTC products,
visit
www.linear-tech.com
Linear Technology Magazine • November 1998
39
DESIGN TOOLS
Applications on Disk
FilterCAD™
2.0 CD-ROM — This CD is a powerful filter
design tool that supports all of Linear Technology’s high
performance switched capacitor filters. Included is Fil-
terView™, a document navigator that allows you to
quickly find Linear Technology monolithic filter data
sheets, the FilterCAD manual, application notes, design
notes and
Linear Technology
magazine articles. It
does
not
have to be installed to run FilterCAD. It is not
necessary to use FilterView to view the documents, as
they are standard .PDF files, readable with any version
of Adobe Acrobat™. FilterCAD runs on Windows
®
3.1 or
Windows 95. FilterView requires Windows 95. The
FilterCAD program itself is also available on the web and
will be included on the new LinearView™ CD.
Available at no charge.
Noise Disk — This IBM-PC (or compatible) program
allows the user to calculate circuit noise using LTC op
amps, determine the best LTC op amp for a low noise
application, display the noise data for LTC op amps,
calculate resistor noise and calculate noise using specs
for any op amp. Available at no charge
SPICE Macromodel Disk — This IBM-PC (or compat-
ible) high density diskette contains the library of LTC op
amp SPICE macromodels. The models can be used with
any version of SPICE for general analog circuit simula-
tions. The diskette also contains working circuit examples
using the models and a demonstration copy of PSPICE™
by MicroSim. Available at no charge
SwitcherCAD™ — The SwitcherCAD program is a pow-
erful PC software tool that aids in the design and
optimization of switching regulators. The program can
cut days off the design cycle by selecting topologies,
calculating operating points and specifying component
values and manufacturer’s part numbers. 144 page
manual included. $20.00
SwitcherCAD supports the following parts: LT1070 se-
ries: LT1070, LT1071, LT1072, LT1074 and LT1076.
LT1082. LT1170 series: LT1170, LT1171, LT1172 and
LT1176. It also supports: LT1268, LT1269 and LT1507.
LT1270 series: LT1270 and LT1271. LT1371 series:
LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377.
Micropower SwitcherCAD™ — The MicropowerSCAD
program is a powerful tool for designing DC/DC convert-
ers based on Linear Technology’s micropower switching
regulator ICs. Given basic design parameters,
MicropowerSCAD selects a circuit topology and offers
you a selection of appropriate Linear Technology switch-
ing regulator ICs. MicropowerSCAD also performs circuit
simulations to select the other components which sur-
round the DC/DC converter. In the case of a battery
supply, MicropowerSCAD can perform a battery life
simulation. 44 page manual included. $20.00
MicropowerSCAD supports the following LTC micro-
power DC/DC converters: LT1073, LT1107, LT1108,
LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174,
LT1300, LT1301 and LT1303.
Technical Books
1990 Linear Databook, Vol I —This 1440 page collec-
tion of data sheets covers op amps, voltage regulators,
references, comparators, filters, PWMs, data conver-
sion and interface products (bipolar and CMOS), in both
commercial and military grades. The catalog features
well over 300 devices. $10.00
1992 Linear Databook, Vol II — This 1248 page supple-
ment to the 1990 Linear Databook is a collection of all
products introduced in 1991 and 1992. The catalog
contains full data sheets for over 140 devices. The 1992
Linear Databook, Vol II is a companion to the 1990
Linear Databook, which should not be discarded.
$10.00
1994 Linear Databook, Vol III —This 1826 page supple-
ment to the 1990 and 1992 Linear Databooks is a
collection of all products introduced since 1992. A total
of 152 product data sheets are included with updated
selection guides. The 1994 Linear Databook Vol III is a
companion to the 1990 and 1992 Linear Databooks,
which should not be discarded. $10.00
1995 Linear Databook, Vol IV —This 1152 page supple-
ment to the 1990, 1992 and 1994 Linear Databooks is a
collection of all products introduced since 1994. A total
of 80 product data sheets are included with updated
selection guides. The 1995 Linear Databook Vol IV is a
companion to the 1990, 1992 and 1994 Linear Databooks,
which should not be discarded. $10.00
1996 Linear Databook, Vol V —This 1152 page supple-
ment to the 1990, 1992, 1994 and 1995 Linear Databooks
is a collection of all products introduced since 1995. A
total of 65 product data sheets are included with updated
selection guides. The 1996 Linear Databook Vol V is a
companion to the 1990, 1992, 1994 and 1995 Linear
Databooks, which should not be discarded. $10.00
1997 Linear Databook, Vol VI —This 1360 page supple-
ment to the 1990, 1992, 1994, 1995 and 1996 Linear
Databooks is a collection of all products introduced
since 1996. A total of 79 product data sheets are in-
cluded with updated selection guides. The 1997 Linear
Databook Vol VI is a companion to the 1990, 1992, 1994,
1995 and 1996 Linear Databooks, which should not be
discarded. $10.00
1990 Linear Applications Handbook, Volume I —
928 pages full of application ideas covered in depth by
40 Application Notes and 33 Design Notes. This catalog
covers a broad range of “real world” linear circuitry. In
addition to detailed, systems-oriented circuits, this hand-
book contains broad tutorial content together with liberal
use of schematics and scope photography. A special
feature in this edition includes a 22-page section on
SPICE macromodels. $20.00
1993 Linear Applications Handbook, Volume II —
Continues the stream of “real world” linear circuitry
initiated by the 1990 Handbook. Similar in scope to the
1990 edition, the new book covers Application Notes 40
through 54 and Design Notes 33 through 69. References
and articles from non-LTC publications that we have
found useful are also included. $20.00
1997 Linear Applications Handbook, Volume III —
This 976 page handbook maintains the practical outlook
and tutorial nature of previous efforts, while broadening
topic selection. This new book includes Application
Notes 55 through 69 and Design Notes 70 through 144.
Subjects include switching regulators, measurement
and control circuits, filters, video designs, interface,
data converters, power products, battery chargers and
CCFL inverters. An extensive subject index references
circuits in LTC data sheets, design notes, application
notes and
Linear Technology
magazines. $20.00
1998 Data Converter Handbook — This impressive
1360 page handbook includes all of the data sheets,
application notes and design notes for Linear
Technology’s family of high performance data converter
products. Products include A/D converters (ADCs), D/A
converters (DACs) and multiplexers—including the fast-
est monolithic 16-bit ADC, the 3Msps, 12-bit ADC with
the best dynamic performance and the first dual 12-bit
DAC in an SO-8 package. Also included are selection
guides for references, op amps and filters and a glossary
of data converter terms. $10.00
Interface Product Handbook — This 424 page hand-
book features LTC’s complete line of line driver and
receiver products for RS232, RS485, RS423, RS422,
V.35 and AppleTalk
®
applications. Linear’s particular
expertise in this area involves low power consumption,
high numbers of drivers and receivers in one package,
mixed RS232 and RS485 devices, 10kV ESD protection
of RS232 devices and surface mount packages.
Available at no charge
Power Solutions Brochure — This collection of cir-
cuits contains real-life solutions for common power
supply design problems. There are over 88 circuits,
including descriptions, graphs and performance
specifications. Topics covered include battery chargers,
PCMCIA power management, microprocessor power
supplies, portable equipment power supplies, micro-
power DC/DC, step-up and step-down switching
regulators, off-line switching regulators, linear regula-
tors and switched capacitor conversion.
Available at no charge
Data Conversion Solutions Brochure — This 64 page
collection of data conversion circuits, products and
selection guides serves as excellent reference for the
data acquisition system designer. Over 60 products are
showcased, solving problems in low power, small size
and high performance data conversion applications—
with performance graphs and specifications. Topics
covered include ADCs, DACs, voltage references and
analog multiplexers. A complete glossary defines data
conversion specifications; a list of selected application
and design notes is also included.
Available at no charge
Telecommunications Solutions Brochure — This col-
lection of circuits, new products and selection guides
covers a wide variety of products targeted for the
telecommunications industry. Circuits solving real life
problems are shown for central office switching, cellular
phone, base station and other telecom applications.
New products introduced include high speed amplifiers,
A/D converters, power products, interface transceivers
and filters. Reference material includes a telecommuni-
cations glossary, serial interface standards, protocol
information and a complete list of key application notes
and design notes. Available at no charge
DESIGN TOOLS
Information furnished by Linear Technology Corporation
is believed to be accurate and reliable. However, Linear
Technology makes no representation that the circuits
described herein will not infringe on existing patent rights.
continued on page 40
Linear Technology Magazine • November 1998
© 1998 Linear Technology Corporation/Printed in U.S.A./
LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Boulevard
Milpitas, CA 95035-7417
(408) 432-1900 FAX (408) 434-0507
www.linear-tech.com
For Literature Only: 1-800-4-LINEAR
Acrobat is a trademark of Adobe Systems, Inc.; Windows
is a registered trademark of Microsoft Corp.; Macintosh
and AppleTalk are registered trademarks of Apple Com-
puter, Inc. PSPICE is a trademark of MicroSim Corp.
CD-ROM Catalog
LinearView — LinearView™ CD-ROM version 3.0 is
Linear Technology’s latest interactive CD-ROM. It al-
lows you to instantly access thousands of pages of
product and applications information, covering Linear
Technology’s complete line of high performance analog
products, with easy-to-use search tools.
The LinearView CD-ROM includes the complete product
specifications from Linear Technology’s Databook li-
brary (Volumes I–VI) and the complete Applications
Handbook collection (Volumes I–III). Our extensive
collection of Design Notes and the complete collection
of
Linear Technology
magazine are also included.
A powerful search engine built into the LinearView CD-
ROM enables you to select parts by various criteria,
such as device parameters, keywords or part numbers.
All product categories are represented: data conversion,
references, amplifiers, power products, filters and inter-
face circuits. Up-to-date versions of Linear Technology’s
DESIGN TOOLS, continued from page 39
software design tools, SwitcherCAD, Micropower Switch-
erCAD, FilterCAD, Noise Disk and Spice Macromodel
library, are also included. Everything you need to know
about Linear Technology’s products and applications is
readily accessible via LinearView. LinearView runs un-
der Windows 3.1, Windows 95 and Macintosh
®
System
8.0 or later. Available at no charge.
World Wide Web Site
Linear Technology Corporation’s customers can now
quickly and conveniently find and retrieve the latest
technical information covering the Company’s products
on LTC’s internet web site. Located at www.linear-
tech.com, this site allows anyone with internet access
and a web browser to search through all of LTC’s
technical publications, including data sheets, applica-
tion notes, design notes,
Linear Technology
magazine
issues and other LTC publications, to find information
on LTC parts and applications circuits. Other areas
within the site include help, news and information about
Linear Technology and its sales offices.
Other web sites usually require the visitor to download
large document files to see if they contain the desired
information. This is cumbersome and inconvenient. To
save you time and ensure that you receive the correct
information the first time, the first page of each data
sheet, application note and
Linear Technology
maga-
zine is recreated in a fast, download-friendly format.
This allows you to determine whether the document is
what you need, before downloading the entire file.
The site is searchable by criteria such as part numbers,
functions, topics and applications. The search is per-
formed on a user-defined combination of data sheets,
application notes, design notes and
Linear Technology
magazine articles. Any data sheet, application note,
design note or magazine article can be downloaded or
faxed back. (files are downloaded in Adobe Acrobat PDF
format; you will need a copy of Acrobat Reader to view
or print them. The site includes a link from which you
can download this program.)
International
Sales Offices
FRANCE
Linear Technology S.A.R.L.
Immeuble “Le Quartz”
58 Chemin de la Justice
92290 Chatenay Malabry
France
Phone: 33-1-41079555
FAX: 33-1-46314613
GERMANY
Linear Technology GmbH
Oskar-Messter-Str. 24
D-85737 Ismaning
Germany
Phone: 49-89-962455-0
FAX: 49-89-963147
JAPAN
Linear Technology KK
5F NAO Bldg.
1-14 Shin-Ogawa-cho Shinjuku-ku
Tokyo, 162
Japan
Phone: 81-3-3267-7891
FAX: 81-3-3267-8510
KOREA
Linear Technology Korea Co., Ltd
Namsong Building, #403
Itaewon-Dong 260-199
Yongsan-Ku, Seoul 140-200
Korea
Phone: 82-2-792-1617
FAX: 82-2-792-1619
SINGAPORE
Linear Technology Pte. Ltd.
507 Yishun Industrial Park A
Singapore 768734
Phone: 65-753-2692
FAX: 65-754-4113
SWEDEN
Linear Technology AB
Sollentunavägen 63
S-191 40 Sollentuna
Sweden
Phone: (08)-623-1600
FAX: (08)-623-1650
TAIWAN
Linear Technology Corporation
Rm. 602, No. 46, Sec. 2
Chung Shan N. Rd.
Taipei, Taiwan, R.O.C.
Phone: 886-2-521-7575
FAX: 886-2-562-2285
UNITED KINGDOM
Linear Technology (UK) Ltd.
The Coliseum, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone: 44-1276-677676
FAX: 44-1276-64851
World Headquarters
Linear Technology Corporation
1630 McCarthy Boulevard
Milpitas, CA 95035-7417
Phone: (408) 432-1900
FAX: (408) 434-0507
U.S. Area
Sales Offices
NORTHEAST REGION
Linear Technology Corporation
3220 Tillman Drive, Suite 120
Bensalem, PA 19020
Phone: (215) 638-9667
FAX: (215) 638-9764
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Wilmington, MA 01887
Phone: (978) 658-3881
FAX: (978) 658-2701
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Phone: (408) 428-2050
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Echelon IV Suite 400
Austin, TX 78759
Phone: (512) 343-3679
FAX: (512) 343-3680
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Houston, TX 77043
Phone: (713) 463-5001
FAX: (713) 463-5009
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Raleigh, NC 27609
Phone: (919) 870-5106
FAX: (919) 870-8831
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FAX: (818) 703-0517
Linear Technology Corporation
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Phone: (949) 453-4650
FAX: (949) 453-4765
41K
