LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
1
4252b12f
TYPICAL APPLICATION
FEATURES DESCRIPTION
Negative Voltage
Hot Swap Controllers
The LT C
®
4252 negative voltage Hot SwapTM controller
allows a board to be safely inserted and removed from a
live backplane. Output current is controlled by three stages
of current limiting: a timed circuit breaker, active current
limiting and a fast feedforward path that limits peak current
under worst-case catastrophic fault conditions.
Adjustable undervoltage and overvoltage detectors dis-
connect the load whenever the input supply exceeds the
desired operating range. The LTC4252’s supply input is
shunt regulated, allowing safe operation with very high
supply voltages. A multifunction timer delays initial start-
up and controls the circuit breaker’s response time. The
circuit breaker’s response time is accelerated by sensing
excessive MOSFET drain voltage, keeping the MOSFET
within its safe operating area (SOA). An adjustable soft-
start circuit controls MOSFET inrush current at start-up.
The LTC4252-2 provides automatic retry after a fault. The
LTC4252C-1/LTC4252C-2 feature tight ±1% undervoltage/
overvoltage threshold accuracy. The LTC4252 is available
in either an 8-pin or 10-pin MSOP.
The LTC4252B and LTC4252C improve the ruggedness
of the shunt regulator in the LTC4252 and LTC4252A.
–48V/2.5A Hot Swap Controller
Start-Up Behavior
APPLICATIONS
n Allows Safe Board Insertion and Removal from a
Live –48V Backplane
n Floating Topology Permits Very High Voltage Operation
n Current Limit With Circuit Breaker Timer
n Fast Response Time Limits Peak Fault Current
n Programmable Soft-Start Current Limit
n Programmable Timer with Drain Voltage
Accelerated Response
n ±1% Undervoltage/Overvoltage Threshold (LTC4252C)
n Improved Ruggedness Shunt Regulator
■ Adjustable Undervoltage/Overvoltage Protection
■ LTC4252B-1/LTC4252C-1: Latch Off After Fault
■ LTC4252B-2/LTC4252C-2: Automatic Retry After Fault
■ Available in 8-Pin and 10-Pin MSOP Packages
n Hot Board Insertion
n Electronic Circuit Breaker
n –48V Distributed Power Systems
n Negative Power Supply Control
n Central Office Switching
n High Availability Servers
n ATCA
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
4252B12 TA01
–48RTN
OV
UV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252B-1
R1
402k
1%
R2
32.4k
1% CT
0.33µF
DIN†
DDZ13B**
CSS
68nF CC
18nF
–48V
RS
0.02Ω
Q1
IRF530S
VOUT
RC
10Ω
R3
5.1k
RIN
3× 1.8k IN SERIES
1/4W EACH
C1
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
+
RD 1M
LOAD
EN
*
* M0C207
**DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
4252B12 TA01a
GATE
5V/DIV
SENSE
2.5A/DIV
PWRGD
10V/DIV
1ms/DIV
VOUT
20V/DIV
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
2
4252b12f
ABSOLUTE MAXIMUM RATINGS
Current into VIN (100µs Pulse) .............................100mA
VIN, DRAIN Pin Minimum Voltage ........................ –0.3V
Input/Output Pins
(Except SENSE and DRAIN) Voltage .......... –0.3V to 16V
SENSE Pin Voltage .................................... –0.6V to 16V
Current Out of SENSE Pin (20µs Pulse) .......... –200mA
Current into DRAIN Pin (100µs Pulse) ...................20mA
Maximum Junction Temperature .......................... 125°C
All Voltages Referred to VEE (Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
VIN
SS
SENSE
VEE
TIMER
UV/OV
DRAIN
GATE
TJMAX = 125°C, θJA = 160°C/W
1
2
3
4
5
VIN
PWRGD
SS
SENSE
VEE
10
9
8
7
6
TIMER
UV
OV
DRAIN
GATE
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 160°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4252BCMS8-1#PBF LTC4252BCMS8-1#TRPBF LTGDX 8-Lead Plastic MSOP 0°C to 70°C
LTC4252BCMS8-2#PBF LTC4252BCMS8-2#TRPBF LTGDZ 8-Lead Plastic MSOP 0°C to 70°C
LTC4252BIMS8-1#PBF LTC4252BIMS8-1#TRPBF LTGDX 8-Lead Plastic MSOP –40°C to 85°C
LTC4252BIMS8-2#PBF LTC4252BIMS8-2#TRPBF LTGDZ 8-Lead Plastic MSOP –40°C to 85°C
LTC4252BCMS-1#PBF LTC4252BCMS-1#TRPBF LTGDY 10-Lead Plastic MSOP 0°C to 70°C
LTC4252BCMS-2#PBF LTC4252BCMS-2#TRPBF LTGFB 10-Lead Plastic MSOP 0°C to 70°C
LTC4252BIMS-1#PBF LTC4252BIMS-1#TRPBF LTGDY 10-Lead Plastic MSOP –40°C to 85°C
LTC4252BIMS-2#PBF LTC4252BIMS-2#TRPBF LTGFB 10-Lead Plastic MSOP –40°C to 85°C
LTC4252CCMS-1#PBF LTC4252CCMS-1#TRPBF LTGFC 10-Lead Plastic MSOP 0°C to 70°C
LTC4252CCMS-2#PBF LTC4252CCMS-2#TRPBF LTGFD 10-Lead Plastic MSOP 0°C to 70°C
LTC4252CIMS-1#PBF LTC4252CIMS-1#TRPBF LTGFC 10-Lead Plastic MSOP –40°C to 85°C
LTC4252CIMS-2#PBF LTC4252CIMS-2#TRPBF LTGFD 10-Lead Plastic MSOP –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
Consult LT C Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Operating Temperature Range
LTC4252BC-1/LTC4252BC-2
LTC4252CC-1/LTC4252CC-2 .................... 0°C to 70°C
LTC4252BI-1/LTC4252BI-2
LTC4252CI-1/LTC4252CI-2 ................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
3
4252b12f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL PARAMETER CONDITIONS
LTC4252B-1/-2 LTC4252C-1/-2
UNITSMIN TYP MAX MIN TYP MAX
VZVIN – VEE Zener Voltage IIN = 2mA l11.5 13 14.5 11.5 13 14.5 V
rZVIN – VEE Zener Dynamic Impedance IIN = 2mA to 30mA 5 5 Ω
IIN VIN Supply Current UV = OV = 4V, VIN = (VZ – 0.3V) ●0.8 2 0.9 2 mA
VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN)●9.2 11.5 9 10 V
VLKH VIN Undervoltage Lockout Hysteresis 1 0.5 V
VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE)●40 50 60 45 50 55 mV
VACL Analog Current Limit Voltage VACL = (VSENSE – VEE),
SS = Open or 2.2V
●80 100 120 mV
VACL/
VCB
Analog Current Limit Voltage/
Circuit Breaker Voltage
VACL = (VSENSE – VEE),
SS = Open or 1.4V
●1.05 1.20 1.38 V/V
VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE)●150 200 300 150 200 300 mV
VSS SS Voltage After End of SS Timing Cycle 2.2 1.4 V
RSS SS Output Impedance 100 50 kΩ
ISS SS Pin Current UV = OV = 4V, VSENSE = VEE,
VSS = 0V (Sourcing)
22 28 µA
UV = OV = 0V, VSENSE = VEE,
VSS = 2V (Sinking)
28 28 mA
VOS Analog Current Limit Offset Voltage 10 10 mV
VACL+VOS/
VSS
Ratio (VACL + VOS) to SS Voltage 0.05 0.05 V/V
IGATE GATE Pin Output Current UV = OV = 4V, VSENSE = VEE,
VGATE = 0V (Sourcing)
●40 58 80 40 58 80 µA
UV = OV = 4V, VSENSE – VEE = 0.15V,
VGATE = 3V (Sinking)
17 17 mA
UV = OV = 4V, VSENSE – VEE = 0.3V,
VGATE = 1V (Sinking)
190 190 mA
VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA ●10 12 VZ10 12 VZV
VGATEH Gate High Threshold VGATEH = VIN – VGATE, IIN = 2mA,
for PWRGD Status (MS Only)
2.8 2.8 V
VGATEL Gate Low Threshold (Before Gate Ramp-Up) 0.5 0.5 V
VUVHI UV Pin Threshold HIGH ●3.075 3.225 3.375 V
VUVLO UV Pin Threshold LOW ●2.775 2.925 3.075 V
VUV UV Pin Threshold Low-to-High Transition ●3.05 3.08 3.11 V
VUVHST UV Pin Hysteresis (● for LTC4252C Only) ●300 292 324 356 mV
VOVHI OV Pin Threshold HIGH ●5.85 6.15 6.45 V
VOVLO OV Pin Threshold LOW ●5.25 5.55 5.85 V
VOV OV Pin Threshold Low-to-High Transition ●5.04 5.09 5.14 V
VOVHST OV Pin Hysteresis (● for LTC4252C Only) ●600 82 102 122 mV
ISENSE SENSE Pin Input Current UV = OV = 4V, VSENSE = 50mV ● –15 –30 –15 –30 µA
IINP UV, OV Pin Input Current UV = OV = 4V ●±0.1 ±1 ±0.1 ±1 µA
VTMRH TIMER Pin Voltage High Threshold 4 4 V
VTMRL TIMER Pin Voltage Low Threshold 1 1 V
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
4
4252b12f
SYMBOL PARAMETER CONDITIONS
LTC4252B-1/-2 LTC4252C-1/-2
UNITSMIN TYP MAX MIN TYP MAX
ITMR TIMER Pin Current Timer On (Initial Cycle/Latchoff/
Shutdown Cooling, Sourcing),
VTMR = 2V
5.8 5.8 µA
Timer Off (Initial Cycle, Sinking),
VTMR = 2V
28 28 mA
Timer On (Circuit Breaker, Sourcing,
IDRN = 0µA), VTMR = 2V
230 230 µA
Timer On (Circuit Breaker, Sourcing,
IDRN = 50µA), VTMR = 2V
630 630 µA
Timer Off (Circuit Breaker/
Shutdown Cooling, Sinking),
VTMR = 2V
5.8 5.8 µA
∆ITMRACC/
∆IDRN
[(ITMR at IDRN = 50µA) – (ITMR at IDRN =
0µA)]/∆IDRN
Timer On (Circuit Breaker with
IDRN = 50µA)
8 8 µA/µA
VDRNL DRAIN Pin Voltage Low Threshold For PWRGD Status (MS Only) 2.385 2.385 V
IDRNL DRAIN Leakage Current VDRAIN = 5V (4V for LTC4252C) ±0.1 ±1 ±0.1 ±1 µA
VDRNCL DRAIN Pin Clamp Voltage IDRN = 50µA 7 6 V
VPGL PWRGD Output Low Voltage IPG = 1.6mA (MS Only)
IPG = 5mA (MS Only)
●
●
0.2 0.4
1.1
0.2 0.4
1.1
V
V
IPGH PWRGD Pull-Up Current VPWRGD = 0V (Sourcing) (MS Only) ●40 58 80 40 58 80 µA
tSS SS Default Ramp Period SS Pin Floating, VSS Ramps from
0.2V to 2V
180 µs
SS Pin Floating, VSS Ramps from
0.1V to 0.9V
230 µs
tPLLUG UV Low to Gate Low 0.4 0.4 µs
tPHLOG OV High to Gate Low 0.4 0.4 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specified.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
5
4252b12f
TYPICAL PERFORMANCE CHARACTERISTICS
IIN vs VIN
Undervoltage Lockout VLKO
vs Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Analog Current Limit Voltage
VACL vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
VZ vs Temperature rZ vs Temperature IIN vs Temperature
TEMPERATURE (°C)
–55
V
Z
(V)
14.5
14.0
13.5
13.0
12.5
12.0 –15 25 45 125
4252B12 G01
–35 5 65 85 105
IIN = 2mA
TEMPERATURE (°C)
–55
r
Z
(Ω)
10
9
8
7
6
5
4
3
2–15 25 45 125
4252B12 G02
–35 5 65 85 105
IIN = 2mA
TEMPERATURE (°C)
–55
I
IN
(µA)
2000
1800
1600
1400
1200
1000
800
600
400
200
0–15 25 45 125
4252B12 G03
–35 5 65 85 105
VIN = (VZ – 0.3V)
VIN (V)
0 2 4 6 8 10 12 14 16 18 20 22
I
IN
(mA)
1000
100
10
1
0.1
4252B12 G04
125°C
85°C
25°C
–40°C
TEMPERATURE (°C)
–55
V
LKO
(V)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0 –15 25 45 125
4252B12 G05
–35 5 65 85 105
TEMPERATURE (°C)
–55
0.5
V
LKH
(V)
0.7
1.1
1.3
1.5
–15 25 45 125
4252B12 G06
0.9
–35 5 65 95 105
TEMPERATURE (°C)
–55
V
CB
(mV)
60
58
56
54
52
50
48
46
44
42
40 –15 25 45 125
4252B12 G07
–35 5 65 85 105
TEMPERATURE (°C)
–55
V
ACL
(mV)
120
115
110
105
100
95
90
85
80 –15 25 45 125
4252B12 G08
–35 5 65 85 105
TEMPERATURE (°C)
–55
V
FCL
(mV)
300
275
250
225
200
175
150 –15 25 45 125
4252B12 G09
–35 5 65 85 105
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
6
4252b12f
TYPICAL PERFORMANCE CHARACTERISTICS
VOS vs Temperature (VACL + VOS)/VSS vs Temperature IGATE (Sourcing) vs Temperature
IGATE (ACL, Sinking)
vs Temperature
IGATE (FCL, Sinking)
vs Temperature VGATE vs Temperature
VSS vs Temperature RSS vs Temperature ISS (Sinking) vs Temperature
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
SS
(V)
4252B12 G10
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
R
SS
(kΩ)
4252B12 G11
110
108
106
104
102
100
98
96
94
92
90
TEMPERATURE (°C)
–55 –35 –15
0
I
SS
(mA)
5
15
20
25
65 85 105
45
4252B12 G12
10
5 25 45 125
30
35
40
UV = OV = VSENSE = VEE
IIN = 2mA
VSS = 2V
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
OS
(mV)
4252B12 G13
11.0
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
9.0
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
(V
ACL
+ V
OS
)/V
SS
(V/V)
4252B12 G14
0.060
0.058
0.056
0.054
0.052
0.050
0.048
0.046
0.044
0.042
0.040
TEMPERATURE (C)
–55
I
GATE
(A)
70
65
60
55
50
45
40 –15 25 45 125
4252B12 G15
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE = VEE
VGATE = 0V
TEMPERATURE (°C)
–55
I
GATE
(mA)
30
25
20
15
10
5
0–15 25 45 125
4252B12 G16
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.15V
VGATE = 3V
TEMPERATURE (°C)
–55
I
GATE
(mA)
400
350
300
250
200
150
100
50
0–15 25 45 125
4252B12 G17
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE – VEE = 0.3V
VGATE = 1V
TEMPERATURE (°C)
–55
V
GATE
(V)
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0 –15 25 45 125
4252B12 G18
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
VSENSE = VEE
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
7
4252b12f
TYPICAL PERFORMANCE CHARACTERISTICS
OV Threshold vs Temperature ISENSE vs Temperature ISENSE vs (VSENSE – VEE)
TIMER Threshold
vs Temperature
ITMR (Initial Cycle, Sourcing)
vs Temperature
ITMR (Initial Cycle, Sinking)
vs Temperature
VGATEH vs Temperature VGATEL vs Temperature UV Threshold vs Temperature
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
GATEH
(V)
4252B12 G19
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
VGATEH = VIN – VGATE,
IIN = 2mA
(MS ONLY)
TEMPERATURE (°C)
–55
V
GATEL
(V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0–15 25 45 125
4252B12 G20
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP-UP
TEMPERATURE (°C)
–55
UV THRESHOLD (V)
3.375
3.275
3.175
3.075
2.975
2.875
2.775 –15 25 45 125
4252B12 G21
–35 5 65 85 105
VUVH
VUV
VUVL
TEMPERATURE (°C)
–55
OV THRESHOLD (V)
6.45
6.25
6.05
5.85
5.65
5.45
5.25
5.05
4.85 –15 25 45 125
4252B12 G22
–35 5 65 85 105
VOVH
VOVL
VOV
TEMPERATURE (°C)
–55
I
SENSE
(A)
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30 –15 25 45 125
4252B12 G23
–35 5 65 85 105
UV/0V = 4V
TIMER = 0V
GATE = HIGH
VSENSE – VEE = 50mV
(VSENSE – VEE) (V)
–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
–I
SENSE
(mA)
0.01
0.1
1.0
10
100
1000
4252B12 G24
UV/0V = 4V
TIMER = 0V
GATE = HIGH
TA = 25°C
TEMPERATURE (°C)
–55
TIMER THRESHOLD (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–15 25 45 125
4252B12 G25
–35 5 65 85 105
VTMRH
VTMRL
TEMPERATURE (°C)
–55
I
TMR
(µA)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
4252B12 G26
–35 5 65 85 105
TIMER = 2V
TEMPERATURE (°C)
–55
I
TMR
(mA)
50
45
40
35
30
25
20
15
10 –15 25 45 125
4252B12 G27
–35 5 65 85 105
TIMER = 2V
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
8
4252b12f
TYPICAL PERFORMANCE CHARACTERISTICS
ITMR vs IDRN ∆ITMRACC/∆IDRN vs Temperature IDRN vs VDRAIN
VDRNL vs Temperature VDRNCL vs Temperature VPGL vs Temperature
ITMR (Circuit Breaker, Sourcing)
vs Temperature
ITMR (Circuit Breaker, IDRN = 50µA,
Sourcing) vs Temperature
ITMR (Cooling Cycle, Sinking)
vs Temperature
TEMPERATURE (°C)
–55
I
TMR
(µA)
280
260
240
220
200
180 –15 25 45 125
4252B12 G28
–35 5 65 85 105
TIMER = 2V
IDRN = 0µA
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
550
I
TMR
(µA)
570
590
610
690
4252B12 G29
630
650
670
TIMER = 2V
IDRN = 50µA
TEMPERATURE (°C)
–55
I
TMR
(A)
10
9
8
7
6
5
4
3
2
1
0–15 25 45 125
4252B12 G30
–35 5 65 85 105
TIMER = 2V
IDRN (mA)
0.001 0.01
0.1
I
TMR
(mA)
1
10
0.1 1 10
4252B12 G31
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
∆I
TMRACC
/I
DRN
(µA/µA)
4252B12 G32
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
TIMER ON
(CIRCUIT BREAKING,
IDRN = 50µA)
VDRAIN (V)
0 2 4 6 8 10 12 14 16
IDRN (mA)
100
10
1
0.1
0.01
0.001
0.0001
0.00001
4252B12 G33
IIN = 2mA
125°C
85°C
25°C
–40°C
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
DRNL
(V)
4252B12 G34
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
FOR PWRGD STATUS (MS ONLY)
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
DRNCL
(V)
4252B12 G35
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
IDRN = 50µA
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
V
PGL
(V)
4252B12 G36
3.0
2.5
2.0
1.5
1.0
0.5
0
(MS ONLY)
IPG = 10mA
IPG = 5mA
IPG = 1.6mA
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
9
4252b12f
PIN FUNCTIONS
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this
pin to the positive side of the supply through a dropping
resistor. A shunt regulator clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO, overriding UV and OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp-
up. If VIN drops below approximately 8.2V, GATE pulls
low immediately.
PWRGD (Pin 2/Not Available): Power Good Status Output
(MS only). At start-up, PWRGD latches low if DRAIN is
below 2.385V and GATE is within 2.8V of VIN. PWRGD
status is reset by UV, VIN (UVLO) or a circuit breaker
fault timeout. This pin is internally pulled high by a 58µA
current source.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the sense
resistor during the soft-start current limiting. At the begin-
ning of a start-up cycle, the SS capacitor (CSS) is ramped
by a 22µA (28µA for the LTC4252C) current source. The
GATE pin is held low until SS exceeds 20 • VOS = 0.2V.
SS is internally shunted by a 100k resistor (RSS) which
limits the SS pin voltage to 2.2V (50k resistor and 1.4V
for the LTC4252C). This corresponds to an analog current
limit SENSE voltage of 100mV (60mV for the LTC4252C). If
the SS capacitor is omitted, the SS pin ramps up in about
180µs. The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor RS con-
nected between SENSE and VEE, and controlled in three
steps. If SENSE exceeds VCB (50mV), the circuit breaker
comparator activates a (230µA + 8 • IDRN) TIMER pull-up
current. If SENSE exceeds VACL, the analog current limit
amplifier pulls GATE down to regulate the MOSFET current
at VACL/RS. In the event of a catastrophic short-circuit,
SENSE may overshoot. If SENSE reaches VFCL (200mV),
the fast current limit comparator pulls GATE low with a
strong pull-down. To disable the circuit breaker and cur-
rent limit functions, connect SENSE to VEE.
(MS/MS8)
TYPICAL PERFORMANCE CHARACTERISTICS
IPGH vs Temperature tSS vs Temperature
tPLLUG and tPHLOG
vs Temperature
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
I
PGH
(µA)
4252B12 G37
62
61
60
59
58
57
56
55
VPWRGD = 0V
(MS ONLY)
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
t
SS
(µs)
4252B12 G38
220
210
200
190
180
170
160
150
SS PIN FLOATING,
VSS RAMPS FROM 0.2V TO 2V
TEMPERATURE (°C)
–55
DELAY (µs)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0–15 25 45 125
4252B12 G39
–35 5 65 85 105
tPLLUG
tPHLOG
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
10
4252b12f
PIN FUNCTIONS
(MS/MS8)
VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect
this pin to the negative side of the power supply.
GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output.
This pin is pulled high by a 58µA current source. GATE is
pulled low by invalid conditions at VIN (UVLO), UV, OV, or
a circuit breaker fault timeout. GATE is actively servoed to
control
the fault current as measured at SENSE. A compen-
sation capacitor at GATE stabilizes this loop. A comparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, GATE ramp-up after an overvoltage
event or restart after a current limit fault. During GATE
start-up, a second comparator detects if GATE is within
2.8V of VIN before PWRGD is set (MS package only).
DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an
external resistor, RD, between this pin and the MOSFET’s
drain (VOUT) allows voltage sensing below 6.15V (5V for
LTC4252C) and current feedback to TIMER. A comparator
detects if DRAIN is below 2.385V and together with the
GATE high comparator sets the PWRGD flag. If VOUT is
above VDRNCL, DRAIN clamps at approximately VDRNCL.
The current through RD is internally multiplied by 8 and
added to TIMER’s 230µA pull-up current during a circuit
breaker fault cycle. This reduces the fault time and MOS-
FET heating.
OV (Pin 8/Pin 7): Overvoltage Input. The active high thresh-
old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV
> 6.15V, GATE pulls low. When OV returns below 5.55V,
GATE start-up begins without an initial timing cycle. The
LTC4252C OV pin is set at 5.09V with 102mV hysteresis.
If OV > 5.09V, GATE pulls low. When OV returns below
4.988V, GATE start-up begins without an initial timing
cycle. If an overvoltage condition occurs in the middle of
an initial timing cycle, the initial timing cycle is restarted
after the overvoltage condition goes away. An overvoltage
condition does not reset the PWRGD flag. The internal UVLO
at VIN always overrides OV. A 1nF to 10nF capacitor at OV
prevents transients and switching noise from affecting
the OV thresholds and prevents glitches at the GATE pin.
UV (Pin 9/Pin 7): Undervoltage Input. The active low thresh-
old at the UV pin is set at 2.925V with 0.3V hysteresis. If
UV < 2.925V, PWRGD pulls high, both GATE and TIMER
pull low. If UV rises above 3.225V, this initiates an initial
timing cycle followed by GATE start-up. The LTC4252C
UV pin is set at 3.08V with 324mV hysteresis. If UV <
2.756V, PWRGD pulls high, both GATE and TIMER pull
low. If UV rises above 3.08V, this initiates an initial timing
cycle followed by GATE start-up. The internal UVLO at VIN
always overrides UV. A low at UV resets an internal fault
latch. A 1nF to 10nF capacitor at UV prevents transients
and switching noise from affecting the UV thresholds and
prevents glitches at the GATE pin.
TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to
generate an initial timing delay at start-up and to delay
shutdown in the event of an output overload (circuit
breaker fault). TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, VIN
clears UVLO, TIMER pin is low, GATE is lower than VGATEL,
SS < 0.2V, and VSENSE – VEE < VCB. A pull-up current
of 5.8µA then charges CT, generating a time delay. If CT
charges to VTMRH (4V), the timing cycle terminates, TIMER
quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit breaker
cycle begins with a 230µA pull-up current charging CT.
If DRAIN is approximately 7V (6V for LTC4252C) during
this cycle, the timer pull-up has an additional current
of 8 • IDRN. If SENSE drops below 50mV before TIMER
reaches 4V, a 5.8µA pull-down current slowly discharges
the CT. In the event that CT eventually integrates up to the
VTMRH threshold, the circuit breaker trips, GATE quickly
pulls low and PWRGD pulls high. The LTC4252-1 TIMER
pin latches high with a 5.8µA pull-up source. This latched
fault is cleared by either pulling TIMER low with an external
device or by pulling UV below VUVLO. The LTC4252-2 starts
a shutdown cooling cycle following an overcurrent fault.
This cycle consists of 4 discharging ramps and 3 charging
ramps. The charging and discharging currents are 5.8µA
and TIMER ramps between its 1V and 4V thresholds. At the
completion of a shutdown cooling cycle, the LTC4252-2
attempts a start-up cycle.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
11
4252b12f
BLOCK DIAGRAM
–
+
4252B12 BD
– (+)
+ (–)
–
+
–
+
–
+
+
–
+
–
VIN
VIN
VEE
VEE
RSS
VEE
VEE
VEE
0.5V
VEE
VEE
VEE
5.8µA
5.8µA
VIN
VEE
VIN
6.15V
(5V)
58µA
230µA
VIN
22µA
(28µA)
95k
(47.5k)
TIMER
6.15V
(5.09V)
2.925V
(3.08V)
4V
1V
+
–
+
–
2.385V
VEE
VEE
VOS = 10mV
VIN
2.8V
–
+
UV *
GATE
SENSE
VIN
VEE
58µA
PWRGD **
DRAIN
OV *
SS
VIN
CB 50mV
+
–
–
+
FCL 200mV
+
–
ACL
5k
(2.5k)
+
–
1×1×
8×1×
LOGIC
*OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE
** ONLY AVAILABLE IN THE MS PACKAGE
FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER
TO THE LTC4252C. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252B
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
12
4252b12f
OPERATION
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4252
is designed to turn on a circuit board supply in a controlled
manner, allowing insertion or removal without glitches or
connector damage.
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or power
conversion circuitry with an external MOSFET switch (see
Figure 1). Both inrush control and short-circuit protection
are provided by the MOSFET.
A detailed schematic for the LTC4252C is shown in Figure2 .
–48V and –48RTN receive power through the longest con-
nector pins and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV and OV determine whether or not the MOSFET
should be turned on based upon internal high accuracy
thresholds and an external divider. UV and OV do double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects –48RTN by way of
a short connector pin that is the last to mate during the
insertion sequence.
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage VIN exceeds VLKO (UVLO).
2. The voltage at UV > VUVHI.
3. The voltage at OV < VOVLO.
4. The (SENSE – VEE) voltage is < 50mV (VCB).
5. The voltage at SS is < 0.2V (20 • VOS).
6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL).
7. The voltage at GATE is < 0.5V (VGATEL).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8µA
into CT. If VIN, UV or OV falls out of range, the start-up
cycle stops and TIMER discharges CT to less than 1V, then
waits until the aforementioned conditions are once again
met. If CT successfully charges to 4V, TIMER pulls low
and both SS and GATE pins are released. GATE sources
58µA (IGATE), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits VSENSE to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of VIN and DRAIN is lower than VDRNL.
4252B12 F01
LTC4252
CLOAD
ISOLATED
DC/DC
CONVERTER
MODULE
LOW
VOLTAGE
CIRCUITRY
+ +
– –
PLUG-IN BOARD
BACKPLANE
–48RTN
–48V
LONG
LONG
+
Figure 1. Basic LTC4252 Hot Swap Topology
Figure 2. –48V, 2.5A Hot Swap Controller
4252B12 F02
–48RTN
–48V
UV
OV
TIMER
VEE
VIN
SENSE GATE
SS DRAIN
LTC4252C-1
R1
392k
1%
DIN+
DDZ13B**
R2
30.1k
1%
RD
1M
CT
0.68µF
CSS
68nF
CC
10nF
RS
0.02Ω
Q1
IRF530S
RC
10Ω
RIN
3 × 1.8k IN SERIES
1/4W EACH
C1
10nF
CIN
1µF
CLOAD
100µF
LONG
LONG
SHORT
+
**DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
13
4252b12f
OPERATION
Tw o modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nominal
design current. One possibility is that the MOSFET will turn
on gradually so that the inrush into the load capacitance
remains a low value. The output will simply ramp to –48V
and the LTC4252 will fully enhance the MOSFET. A second
possibility is that the load current exceeds the soft-start
current limit threshold of [VSS(t)/20 – VOS]/RS. In this case
the LTC4252 will ramp the output by sourcing soft-start
limited current into the load capacitance. If the soft-start
voltage is below 1.2V, the circuit breaker TIMER is held
low. Above 1.2V, TIMER ramps up. It is important to set
the timer delay so that, regardless of which start-up mode
is used, the TIMER ramp is less than one circuit breaker
delay time. If this condition is not met, the LTC4252-1 may
shut down after one circuit breaker delay time whereas
the LTC4252-2 may continue to autoretry.
Board Removal
If the board is withdrawn from the card cage, the UV and
OV divider is the first to lose connection. This shuts off
the MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop (60mV for the LTC4252C); and
200mV for a fast, feedforward comparator which limits
peak current in the event of a catastrophic short-circuit.
If, owing to an output overload, the voltage drop across RS
exceeds 50mV, TIMER sources 230µA into CT. CT even-
tually charges to a 4V threshold and the LTC4252 shuts
off. If the overload goes away before CT reaches 4V and
SENSE measures less than 50mV, CT slowly discharges
(5.8µA). In this way the LTC4252’s circuit breaker function
responds to low duty cycle overloads and accounts for fast
heating and slow cooling characteristics of the MOSFET.
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches VACL, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of VACL/RS. In current limit mode,
VOUT typically rises and this increases MOSFET heating.
If VOUT > VDRNCL, connecting an external resistor, RD,
between VOUT and DRAIN allows the fault timing cycle to
be shortened by accelerating the charging of the TIMER
capacitor. The TIMER pull-up current is increased by 8 •
IDRN. Note that because SENSE > 50mV, TIMER charges
CT during this time and the LTC4252 will eventually shut
down.
Low impedance failures on the load side of the LTC4252
coupled with 48V or more driving potential can produce
current slew rates well in excess of 50A/µs. Under these
conditions, overshoot is inevitable. A fast SENSE com-
parator with a threshold of 200mV detects overshoot and
pulls GATE low much harder and hence much faster than
the weaker current limit loop. The VACL/RS current limit
loop then takes over and servos the current as previously
described. As before, TIMER runs and shuts down the
LTC4252 when CT reaches 4V.
If CT reaches 4V, the LTC4252-1 latches off with a 5.8µA
pull-up current source whereas the LTC4252-2 starts a
shutdown cooling cycle. The LTC4252-1 circuit breaker
latch is reset by either pulling UV momentarily low or
dropping the input voltage VIN below the internal UVLO
threshold or pulling TIMER momentarily low with a switch.
The LTC4252-2 retries after its shutdown cooling cycle.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher voltage
supply, transient currents caused by faults on adjacent
circuit boards sharing the same power bus or the inser-
tion of non-hot-swappable products could cause higher
than anticipated input current and temporary detection
of an overcurrent condition. The action of TIMER and CT
rejects these events allowing the LTC4252 to “ride out”
temporary overloads and disturbances that could trip a
simple current comparator and, in some cases, blow a fuse.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
14
4252b12f
SHUNT REGULATOR
A fast responding shunt regulator clamps the VIN pin to 13V
(VZ). Power is derived from –48RTN by an external current
limiting resistor, RIN. A 1µF decoupling capacitor, CIN filters
supply transients and contributes a short delay at start-up.
To meet creepage requirements RIN may be split into two or
more series connected units. This introduces a wider total
spacing than is possible with a single component while at
the same time ballasting the potential across the gap under
each resistor. The LTC4252 is fundamentally a low voltage
device that operates with –48V as its reference ground. To
further protect against arc discharge into its pins, the area
in and around the LTC4252 and all associated components
should be free of any other planes such as chassis ground,
return, or secondary-side power and ground planes.
VIN may be biased with additional current up to 30mA to
accommodate external loading such as the PWRGD opto-
coupler shown in Figure 23. As an alternative to running
higher current, simply buffer VIN with an emitter follower
as shown in Figure 3. Another method shown in Figure
19 cascodes the PWRGD output.
VIN is rated handle 30mA within the thermal limits of the
package, and is tested to survive a 100µs, 100mA pulse. To
protect VIN against damage from higher amplitude spikes,
clamp VIN to VEE with a 13V Zener diode. Star connect
VEE and all VEE-referred components to the sense resistor
APPLICATIONS INFORMATION
Kelvin terminal as illustrated in Figure 3, keeping trace
lengths between VIN, CIN, DIN and VEE as short as possible.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors VIN for undervolt-
age. The thresholds are defined by VLKO and its hysteresis,
VLKH. When VIN rises above VLKO the chip is enabled; below
(VLKO – VLKH) it is disabled and GATE is pulled low. The
UVLO function at VIN should not be confused with the
UV/OV pin(s). These are completely separate functions.
UV/OV COMPARATORS (LTC4252B)
An UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (VUVHI) = 3.225V
UV high-to-low (VUVLO) = 2.925V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (VOVHI) = 6.150V
OV high-to-low (VOVLO) = 5.550V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 82V when con-
nected together as in the typical application. A divider (R1,
R2) is used to scale the supply voltage. Using R1 = 402k
4252B12 F03
–48RTN
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252B-1
R1
432k
1%
R3
38.3k
1%
R2
4.75k
1%
CT
330nF
CSS
68nF CC
18nF
–48V
RS
0.02Ω
Q1
IRF530S
RC
10Ω
R5
2.2k
Q2
RIN
10k
1/2W
1
9
8
10
3
2
7
6
4
5
C2
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
+
RD 1M
LOAD
EN
R4
22k
*
* M0C207
Q2: MMBT5551LT1
**DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
Figure 3. –48V/2.5A Application with Different Input Operating Range
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
15
4252b12f
APPLICATIONS INFORMATION
and R2 = 32.4k gives a typical operating range of 43.2V
to 82.5V. The undervoltage shutdown and overvoltage
recovery thresholds are then 39.2V and 74.4V. 1% divider
resistors are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA and
define an impedance at UV/OV of 30kΩ. In most applica-
tions, 30kΩ impedance coupled with 300mV UV hysteresis
makes the LTC4252B insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
from UV/OV to VEE.
Separate UV and OV pins are available in the 10-pin MS
package and can be used for a different operating range
such as 35.5V to 76V as shown in Figure 3. Other combi-
nations are possible with different resistor arrangements.
UV/OV COMPARATORS (LTC4252C)
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (VUV) = 3.08V
UV high-to-low (VUV – VUVHST) = 2.756V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (VOV) = 5.09V
OV high-to-low (VOV – VOVHST) = 4.988V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connected together as in Figure 2. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 390k and R2
= 30.1k gives a typical operating range of 43V to 71V. The
undervoltage shutdown and overvoltage recovery thresh-
olds are then 38.5V and 69.6V respectively. 1% divider
resistors are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in Figure 2 set a standing
current of slightly more than 100µA and define an impedance
at UV/OV of 28kΩ. In most applications, 28kΩ impedance
coupled with 324mV UV hysteresis makes the LTC4252C
insensitive to noise. If more noise immunity is desired, add
a 1nF to 10nF filter capacitor from UV/OV to VEE.
The UV and OV pins can be used for a wider operat-
ing range such as 35.5V to 76V as shown in Figure 4.
Other combinations are possible with different resistor
arrangements.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and pull
the GATE and TIMER pins low. A low-to-high UV transition
will initiate an initial timing sequence if the other interlock
4252B12 F04
–48RTN
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
464k
1%
R3
34k
1%
R2
10k
1%
CT
0.68µF
CSS
68nF CC
10nF
–48V
RS
0.02Ω
Q1
IRF530S
RC
10Ω
R5
2.2k
Q2
RIN
10k
1/2W
1
9
8
10
3
2
7
6
4
5
C2
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
+
RD 1M
LOAD
EN
R4
22k
*
* M0C207
Q2: MMBT5551LT1
**DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
Figure 4. –48V/2.5A Application with Wider Input Operating Range
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
16
4252b12f
APPLICATIONS INFORMATION
conditions are met. A high-to-low transition in the UV
comparator immediately shuts down the LTC4252, pulls
the MOSFET gate low and resets the latched PWRGD high.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
DRAIN
Connecting an external resistor, RD, to the dual function
DRAIN pin allows VOUT sensing* without it being dam-
aged by large voltage transients. Below 5V, negligible pin
leakage allows a DRAIN low comparator to detect VOUT
less than 2.385V (VDRNL). This condition, together with
the GATE low comparator, sets the PWRGD flag.
If VOUT > VDRNCL, the DRAIN pin is clamped at about
VDRNCL and the current flowing in RD is given by:
IDRN ≈VOUT -VDRNCL
RD
(1)
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230µA TIMER current.
This accelerates the fault TIMER pull-up when the MOS-
FET’s drain-source voltage exceeds VDRNCL and effectively
shortens the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor CT is used at
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
1) A 5.8µA slow charge; initial timing and shutdown cool-
ing delay.
2) A (230µA + 8 • IDRN) fast charge; circuit breaker delay.
3) A 5.8µA slow discharge; circuit breaker “cool off” and
shutdown cooling.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the interlock conditions are met.
CT charges to 4V in a time period given by:
t= 4V •CT
5.8µA
(2)
When CT reaches 4V (VTMRH), the low impedance switch
turns on and discharges CT. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
RS, the TIMER pin charges CT with (230µA + 8 • IDRN). If CT
charges to 4V, the GATE pin pulls low and the LTC4252-1
latches off while the LTC4252-2 starts a shutdown cooling
cycle. The LTC4252-1 remains latched off until the UV
pin is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or VIN dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
t= 4V •CT
230µA +8 •IDRN
(3)
If VOUT < 5V, an internal PMOS device isolates any DRAIN
pin leakage current, making IDRN = 0µA in Equation (3).
If VOUT > VDRNCL during the circuit breaker fault period,
the charging of CT accelerates by 8 • IDRN of Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
will not reach 4V and the LTC4252 will not
shut the external
MOSFET off. To handle this situation, the TIMER discharges
CT slowly with a 5.8µA pull-down whenever the SENSE
voltage is less than 50mV. Therefore, any intermittent
overload with VOUT > 5V and an aggregate duty cycle of
*VOUT as viewed by the MOSFET; i.e., VDS.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
17
4252b12f
APPLICATIONS INFORMATION
2.5% or more will eventually trip the circuit breaker and
shut down the LTC4252. Figure 5 shows the circuit breaker
response time in seconds normalized to 1µF for IDRN =
0µA. The asymmetric charging and discharging of CT is
a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
t
CT(µF) =4
235.8+8 •IDRN
( )
•D–5.8
(4)
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8µA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry ver-
sion), a shutdown cooling cycle begins if TIMER reaches
the 4V threshold. TIMER starts with a 5.8µA pull-down
until it reaches the 1V threshold. Then, the 5.8µA pull-up
turns back on until TIMER reaches the 4V threshold. Four
5.8µA pull-down cycles and three 5.8µA pull-up cycles
occur between the 1V and 4V thresholds, creating a time
interval given by:
tSHUTDOWN =7•3V •CT
5.8µA
(5)
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load.
If SS floats, an internal current source ramps SS from 0V
to 2.2V for the LTC4252B or 0V to 1.4V for the LTC4252C
in about 230µs. Connecting an external capacitor CSS
from SS to ground modifies the ramp to approximate an
RC response of:
VSS (t)≈VSS •1–e
–t
RSS •CSS
(6)
An internal resistive divider (95k/5k for the LTC4252B or
47.5k/2.5k for the LTC4252C) scales VSS(t) down by 20
times to give the analog current limit threshold:
VACL (t)= VSS (t)
20 –VOS
(7)
This allows the inrush current to be limited to VACL(t)/RS.
The offset voltage, VOS (10mV), ensures CSS is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58µA current source charges the MOSFET gate and
any associated external capacitance. VIN limits the gate
drive to no more than 14.5V.
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
FAULT DUTY CYCLE (%)
0 20 40 60 80 100
NORMALIZED RESPONSE TIME (s/µF)
10
1
0.1
0.01
4252B12 F05
= 4
[(235.8 + 8 • IDRN) • D – 5.8]
t
CT(µF)
IDRN = 0µA
Figure 5. Circuit-Breaker Response Time
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
18
4252b12f
APPLICATIONS INFORMATION
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥ 10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
relative to VIN and, together with the DRAIN low compara-
tor, sets PWRGD status during GATE startup.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
230µA TIMER pull-up. At 100mV (60mV for the LTC4252C),
the ACL amplifier servos the MOSFET current and, at
200mV, the FCL comparator abruptly pulls GATE low in
an attempt to bring the MOSFET current under control. If
any of these conditions persists long enough for TIMER
to charge CT to 4V (see Equation3), the LTC4252 shuts
down and pulls GATE low.
If the SENSE pin encounters a voltage greater than VACL,
the ACL amplifier will servo GATE downwards in an attempt
to control the MOSFET current. Since GATE overdrives the
MOSFET in normal operation, the ACL amplifier needs time
to discharge GATE to the threshold of the MOSFET. For a
mild overload the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV the FCL comparator
takes over, quickly discharging the GATE pin to near VEE
potential. FCL then releases and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically over
corrects the current limit loop and GATE undershoots. A
zero in the loop (resistor RC in series with the gate capaci-
tor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 6 for the LTC4252. Initially, the
current overshoots the fast current limit level of VSENSE =
200mV (Trace 2) as the GATE pin works to bring VGS under
control (Trace 3). The overshoot glitches the backplane
in the negative direction and when the current is reduced
to 100mV/RS, the backplane responds by glitching in the
positive direction.
TIMER commences charging CT (Trace 4) while the analog
current limit loop maintains the fault current at 100mV/RS,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. Timer pull-up is ac-
celerated by VOUT. When CT reaches 4V, GATE turns off,
PWRGD pulls high, the load current drops to zero and the
backplane rings up to over 100V. The transient associated
with the GATE turn off can be controlled with a snubber to
reduce ringing and a transient voltage suppressor (such as
Diodes Inc. SMAT70A) to clip off large spikes. The choice
of RC for the snubber is usually done experimentally. The
value of the snubber capacitor is usually chosen between
10 to 100 times the MOSFET COSS. The value of the snub-
ber resistor is typically between 3Ω to 100Ω.
4252B12 F06
–48RTN
50V/DIV
GATE
10V/DIV
SENSE
200mV/DIV
TIMER
5V/DIV
0.5ms/DIV
FAST CURRENT LIMIT
SUPPLY RING OWING TO
CURRENT OVERSHOOT
SUPPLY RING OWING TO
MOSFET TURN OFF
ANALOG CURRENT LIMIT
ONSET OF OUTPUT SHORT-CIRCUIT
CTIMER RAMP LATCH OFF
Figure 6. Output Short-Circuit Behavior of LTC4252
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
19
4252b12f
APPLICATIONS INFORMATION
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 6 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4252s are used by the other
cards, they respond by limiting the inrush current to a
value of 100mV/RS. If CT is sized correctly, the capacitors
will recharge long before CT times out.
POWER GOOD, PWRGD
PWRGD latches low if GATE charges up to within 2.8V of
VIN and DRAIN pulls below VDRNL during start-up. PWRGD
is reset in UVLO, in a UV condition or if CT charges up to
4V. An overvoltage condition has no effect on PWRGD
status. A 58µA current pulls this pin high during reset.
Due to voltage transients between the power module and
PWRGD, optoisolation is recommended. This pin provides
sufficient drive for an opto-coupler. Figure 19 shows an
alternative NPN configuration with a limiting base resistor
for the PWRGD interface. The module enable input should
have protection from the negative input current.
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take prece-
dence over DC current ratings. A MOSFET with adequate
SOA for a given application can always handle the required
current, but the opposite may not be true. Consult the
manufacturer’s MOSFET data sheet for safe operating
area and effective transient thermal impedance curves.
MOSFET selection is a 3-step process by assuming the
absence of a soft-start capacitor. First, RS is calculated
and then the time required to charge the load capacitance
is determined. This timing, along with the maximum
short-circuit current and maximum input voltage defines
an operating point that is checked against the MOSFET’s
SOA curve.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker cur-
rent trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at VSUPPLY(MIN).
RS is given by:
RS=
V
CB(MIN)
IL(MAX)
(8)
where VCB(MIN) = 40mV (45mV for LTC4252C) represents
the guaranteed minimum circuit breaker threshold.
During the initial charging process, the LTC4252B may
operate the MOSFET in current limit, forcing (VACL) between
80mV to 120mV (VACL is 54mV to 66mV for LTC4252C)
across RS. The minimum inrush current is given by:
IINRUSH(MIN)=80mV
RS
(9)
Maximum short-circuit current limit is calculated using
the maximum VACL. This gives
ISHORTCIRCUIT(MAX)=120mV
RS
(10)
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
for CT is calculated based on the maximum time it takes
the load capacitor to charge. That time is given by:
tCL(CHARGE) =C•V
I=CL•VSUPPLY(MAX)
IINRUSH(MIN)
(11)
The maximum current flowing in the DRAIN pin is given by:
IDRN(MAX) =
V
SUPPLY(MAX)
–V
DRNCL
RD
(12)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
20
4252b12f
Approximating a linear charging rate as IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3)
can be approximated with 0.5 • IDRN(MAX). Rearranging
equation, TIMER capacitor CT is given by:
CT=tCL(CHARGE) •230µA+4•IDRN(MAX)
( )
4V
(13)
Returning to Equation (3), the TIMER period is calcu-
lated and used in conjunction with VSUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If VSUPPLY(MAX)
= 72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS
= 40mΩ; Equation (13) gives CT = 441nF. To account for
errors in RS, CT, TIMER current (230µA), TIMER threshold
(4V), RD, DRAIN current multiplier and DRAIN voltage
clamp (VDRNCL), the calculated value should be multiplied
by 1.5, giving the nearest standard value of CT = 680nF.
If a short-circuit occurs, a current of up to 120mV/40mΩ = 3 A
will flow in the MOSFET for 5.6ms as dictated by CT=680nF
in Equation (3). The MOSFET must be selected based on
this criterion. The IRF530S can handle 100V and 3A for
10ms and is safe to use in this application.
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
ICB(MAX)=VCB(MAX)
RS
(14)
where VCB(MAX) = 60mV (55mV for the LTC4252C).
From the SOA curves of a prospective MOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
CSS =
t
SOA(MAX)
0.916 •RSS
(15)
In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX)
for the IRF530S is 40ms. From Equation (15), CSS =
437nF. Actual board evaluation showed that CSS = 100nF
was appropriate. The ratio (RSS • CSS) to tCL(CHARGE) is
a good gauge as a large ratio may result in the time-out
period expiring. This gauge is determined empirically with
board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2 with the LTC4252C. It was designed
for 80W.
Calculate the maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, IIN(MAX) = 2.2A.
Calculate RS: from Equation (8) RS = 20mΩ.
Calculate ISHORTCIRCUIT(MAX): from Equation (10)
ISHORTCIRCUIT(MAX) =66mV
20mΩ =3.3A
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate CT: from Equation (13) CT = 322nF. Select
CT = 680nF, which gives the circuit breaker time-out
period t= 5.6ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.2ms, so it is safe to use in this application.
Calculate CSS: using Equations (14) and (15) select
CSS=68nF.
FREQUENCY COMPENSATION
The LTC4252C typical frequency compensation network for
the analog current limit loop is a series RC (10Ω) and CC
connected to VEE. Figure 7 depicts the relationship between
the compensation capacitor CC and the MOSFET’s CISS.
The line in Figure 7 is used to select a starting value for CC
based upon the MOSFET’s CISS specification. Optimized
values for CC are shown for several popular MOSFETs.
Differences in the optimized value of CC versus the starting
value are small. Nevertheless, compensation values should
be verified by board level short-circuit testing.
APPLICATIONS INFORMATION
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
21
4252b12f
APPLICATIONS INFORMATION
As seen in Figure 6 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramatically
owing to series inductance. If this voltage avalanches the
MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
Zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4252’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 8 illustrates the correct way of making
connections between the LTC4252 and the sense resis-
tor. PCB layout should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
MOSFET CISS (pF)
0
COMPENSATION CAPACITANCE CC (nF)
60
50
40
30
20
10
02000 4000
4252B12 F07
6000 8000
NTY100N10
IRF3710
IRF540S
IRF530S
IRF740
Figure 7. Recommended Compensation
Capacitor CC vs MOSFET CISS
Figure 8. Making PCB Connections to the Sense Resistor
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
VEE
4252B12 F08
time point 1, the supply ramps up, together with UV/OV,
VOUT and DRAIN. VIN and PWRGD follow at a slower rate
as set by the VIN bypass capacitor. At time point 2, VIN
exceeds VLKO and the internal logic checks for UV > VUVHI,
OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged
by a 5.8µA current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the condi-
tions of GATE < VGATEL, SENSE < VCB and SS<20•VOS
must be satisfied before a GATE ramp-up cycle begins.
SS ramps up as dictated by RSS • CSS (as in Equation 6);
GATE is held low by the analog current limit (ACL) ampli-
fier until SS crosses 20 • VOS. Upon releasing GATE, 58µA
sources into the external MOSFET gate and compensation
network. When the GATE voltage reaches the MOSFET’s
threshold, current begins flowing into the load capacitor
at time point 5. At time point 6, load current reaches the
SS control level and the analog current limit loop activates.
Between time points 6 and 8, the GATE voltage is servoed,
the SENSE voltage is regulated at VACL(t) (Equation 7) and
soft-start limits the slew rate of the load current. If the
SENSE voltage (VSENSE – VEE) reaches the VCB threshold
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN)
current pull-up. As the load capacitor nears full charge,
load current begins to decline.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
22
4252b12f
APPLICATIONS INFORMATION
At time point 8, the load current falls and the SENSE voltage
drops below VACL(t). The analog current limit loop shuts
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below VCB, the fault TIMER cycle
ends, followed by a 5.8µA discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
GATE ramp-up. When GATE ramps past the VGATEH thresh-
old at time point 10, PWRGD pulls low. At time point11,
GATE reaches its maximum voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 10, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a
short pin. This ensures the power
connections are firmly established before the LTC4252 is
activated. At time point 1, the power pins make contact
and VIN ramps through VLKO. At time point 2, the UV/OV
divider makes contact and its voltage exceeds VUVHI. In
addition, the internal logic checks for OV < VOVHI, GATE
< VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER <
VTMRL. If all conditions are met, an initial timing cycle
starts and the TIMER capacitor is charged by a 5.8µA
current source pull-up. At time point 3, TIMER reaches the
VTMRH threshold and the initial timing cycle terminates.
The TIMER capacitor is quickly discharged. At time point
4, the VTMRL threshold is reached and the conditions of
GATE < VGATEL, SENSE < VCB and SS < 20 • VOS must be
GND – VEE OR
(–48RTN) – (–48V)
UV/OV
VIN
TIMER
GATE
VLKO
SENSE
VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
VOUT
1 2 3 4 56 7 8
VACL
VCB
9
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
SS
DRAIN
PWRGD
230µA + 8 • IDRN
5.8µA
20 • VOS
58µA
10 11
VIN – VGATEH
VDRNL
VDRNCL
20 • (VCB + VOS)
20 • (VACL + VOS)
VGATEL
VTMRL
VTMRH
5.8µA 5.8µA
58µA
4252B12 F09
GATE
START-UP
INITIAL TIMING
Figure 9. System Power-Up Timing (All Waveforms Are Referenced to VEE)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
23
4252b12f
APPLICATIONS INFORMATION
satisfied before a GATE start-up cycle begins. SS ramps up
as dictated by RSS•CSS; GATE is held low by the analog
current limit amplifier until SS crosses 20 • VOS. Upon
releasing GATE, 58µA sources into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor at time point 5. At time point 6,
load current reaches the SS control level and the analog
current limit loop activates. Between time points 6 and 8,
the GATE voltage is servoed, the SENSE voltage is regulated
at VACL(t) and soft-start limits the slew rate of the load
current. If the SENSE voltage (VSENSE – VEE) reaches the
VCB threshold at time point 7, the circuit breaker TIMER
activates. The TIMER capacitor, CT, is charged by a (230µA
+ 8 • IDRN) current pull-up. As the load capacitor nears full
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below VACL(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below VCB and the fault TIMER cycle ends, followed by a
5.8µA discharge cycle (cool off). When GATE ramps past
VGATEH threshold at time point 10, PWRGD pulls low.
At time point 11, GATE reaches its maximum voltage as
determined by VIN.
5.8µA
58µA
5.8µA 5.8µA
58µA
GATE
START-UP
INITIAL TIMING
UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
1 2 3 4 56 7 8 9
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1011
4252B12 F10
GND – VEE OR
(–48RTN) – (–48V)
UV/OV
VIN
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD
VLKO
VUVHI
VACL
VCB
230µA + 8 • IDRN
20 • VOS
VIN – VGATEH
VDRNL
VDRNCL
20 • (VCB + VOS)
20 • (VACL + VOS)
VGATEL
VTMRL
VTMRH
Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
24
4252b12f
APPLICATIONS INFORMATION
Undervoltage Timing
In Figure 11 when UV pin drops below VUVLO (time point1),
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears VUVHI (time point 2), an initial timer
cycle begins followed by a GATE start-up cycle.
VIN Undervoltage Lockout Timing
The VIN undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 12, both UV and OV pins are connected together.
When UV clears VUVHI (time point 1), an initial timing
cycle starts. If the system bus voltage overshoots VOVHI
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the VOVLO
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shown at time point 1 of Figure 13, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull down
and the load is disconnected. At time point 2, OV recovers
and drops below the VOVLO threshold. A GATE start-up
cycle begins. If the overvoltage glitch is long enough to
deplete the load capacitor, a full start-up cycle as shown
between time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 14a, the TIMER capacitor charges at 230µA if
the SENSE pin exceeds VCB but VDRN is less than 5V. If
the SENSE pin drops below VCB before TIMER reaches
UV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5.8µA
58µA
5.8µA
5.8µA
58µA
UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
1 2 3 4 56 7 8 9
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
10 11
4252B12 F11
UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
VACL
VCB
230µA + 8 • IDRN
20 • VOS
VIN – VGATEH
VDRNL
VDRNCL
20 • (VCB + VOS)
20 • (VACL + VOS)
VGATEL
VTMRL
VTMRH
VUVHI
VUVLO
GATE
START-UP
INITIAL TIMING
Figure 11. Undervoltage Timing (All Waveforms Are Referenced to VEE)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
25
4252b12f
APPLICATIONS INFORMATION
UV/OV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5.8µA
58µA
58µA
5.8µA 5.8µA
UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
1 2 3 4 5 67 8 9
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
101112
4252B12 F12
UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE
UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE
VACL
VCB
230µA + 8 • IDRN
20 • VOS
VIN – VGATEH
VDRNL
VDRNCL
20 • (VCB + VOS)
20 • (VACL + VOS)
VGATEL
VTMRL
VTMRH
VOVHI
VUVHI
VOVLO
GATE
START-UP
INITIAL TIMING
OV
TIMER
GATE
SENSE
SS
5.8µA
58µA
58µA
5.8µA
1 2 34 5 67 8 9
4252B12 F13
OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
VACL
VCB
230µA + 8 • IDRN
20 • VOS
VIN – VGATEH
20 • (VCB + VOS)
20 • (VACL + VOS)
VGATEL
VOVHI
VTMRH
VOVLO
GATE
START-UP
Figure 13. Overvoltage Timing (All Waveforms Are Referenced to VEE)
Figure 12. Undervoltage Timing with an Overvoltage Glitch (All Waveforms Are Referenced to VEE)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
26
4252b12f
APPLICATIONS INFORMATION
CB FAULT
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD
CB FAULTCB FAULT CB FAULT
5.8µA 5.8µA
1 2
4252B12 F14
1 2
CB TIMES OUT
1 432
CB TIMES OUT
VACL
VCB
VACL
VDRNCL
VCB
VACL
VTMRH VTMRH VTMRH
VCB
230µA + 8 • IDRN
VDRNCL
230µA + 8 • IDRN
230µA + 8 • IDRN
230µA + 8 • IDRN
(14a) Momentary Circuit-Breaker Fault
Figure 14. Circuit-Breaker Timing Behavior (All Waveforms Are Referenced to VEE)
(14b) Circuit-Breaker Time Out (14c) Multiple Circuit-Breaker Fault
the VTMRH threshold, TIMER is discharged by 5.8µA. In
Figure 14b, when TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. In Figure 14c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach VTMRH. GATE pull down follows and the
LTC4252 shuts down. During shutdown, the LTC4252-1
latches TIMER high with a 5.8µA pull-up current source;
the LTC4252-2 activates a shutdown cooling cycle.
Resetting a Fault Latch (LTC4252-1)
The latched circuit breaker fault of LTC4252-1 benefits
from long cooling time. It is reset by pulling the UV pin
below VUVLO with a switch. Reset is also accomplished by
pulling the VIN pin momentarily below (VLKO – VLKH). A
third reset method involves pulling the TIMER pin below
VTMRL as shown in Figure 15. An initial timing cycle is
skipped if TIMER is used for reset. An initial timing cycle
is generated if reset by the UV pin or the VIN pin.
The duration of the TIMER reset pulse should be smaller
than the time taken to reach 0.2V at SS pin. With a single
pole mechanical pushbutton switch, this may not be
feasible. A double pole, single throw pushbutton switch
removes this restriction by connecting the second switch
to the SS pin. With this method, both the SS and TIMER
pins are released at the same time (see Figure 24).
Shutdown Cooling Cycle (LTC4252-2)
Figure 16 shows the timer behavior of the LTC4252-2.
At time point 2, TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. TIMER starts
a shutdown cooling cycle by discharging TIMER with
5.8µA to the VTMRL threshold. TIMER then charges with
5.8µA to the VTMRH threshold. There are four 5.8µA
discharge phases and three 5.8µA charge phases in this
shutdown cooling cycle spanning time points 2 and 3. At
time point 3, the LTC4252 automatic retry occurs with a
start-up cycle. Good thermal management techniques are
highly recommended; power and thermal dissipation must
be carefully evaluated when implementing the automatic
retry scheme.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
27
4252b12f
APPLICATIONS INFORMATION
TIMER
GATE
SENSE
VACL
VCB
SS
DRAIN
230µA + 8 • IDRN
VIN – VGATEH
VDRNL
425212B F15
VDRNCL
VGATEL
VTMRL
VTMRH
PWRGD
5.8µA
5.8µA
5.8µA
58µA
58µA
1 2 34 5 67 8 9
SWITCH RELEASES SS
SWITCH RESETS LATCHED TIMER
GATE START-UP
20 • VOS
20 • (VCB + VOS)
20 • (VACL + VOS)
MOMENTARY DPST SWITCH RESET
TIMER
GATE
SENSE
VOUT
VACL
VCB
SS
DRAIN
230µA + 8 • IDRN
VTMRH
VTMRL
VGATEL
230µA + 8 • IDRN
VIN – VGATEH
VDRNL
4252B12 F16
VDRNCL
PWRGD
58µA
58µA
5.8µA 5.8µA 5.8µA
5.8µA5.8µA5.8µA
5.8µA5.8µA5.8µA
GATE
START-UP
SHUTDOWN COOLING
CB FAULT
20 • VOS
20 • (VCB + VOS)
20 • (VACL + VOS)
1 2 3 4 5 6 78 9 10
RETRY
CIRCUIT BREAKER TIMES OUT
Figure 16. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms Are Referenced to VEE)
Figure 15. Pushbutton Reset of LTC4252-1’s Latched Fault
(All Waveforms Are Referenced to VEE)
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
28
4252b12f
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
In Figure 17a, when SENSE exceeds VACL, GATE is
regulated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 17b, when a severe fault occurs, SENSE exceeds
VFCL and GATE immediately pulls down until the analog
current amplifier establishes control. If the severe fault
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 230µA. This accelerated TIMER current of
[230µA+8 • IDRN] produces a shorter circuit breaker fault
delay. Careful selection of CT, RD and MOSFET can help
prevent SOA damage in a low impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 180µs (or 0V to
1.4V in 230µs for the LTC4252C) at GATE start-up, as
shown in Figure 18a. If a soft-start capacitor, CSS, is con-
nected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation6), as
shown in Figure 18b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from VTMRH to VTMRL
(time points 1 to 2) or by the OV pin falling below the
VOVLO threshold after an OV condition. When the SS pin
is below 0.2V, the analog current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58µA ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
gm, the MOSFET current quickly reaches the soft-start
control value of VACL(t) (Equation 7). At time point 6, the
GATE voltage is controlled by the current limit amplifier.
The soft-start control voltage reaches the circuit breaker
voltage, VCB, at time point 7 and the circuit breaker TIMER
activates. As the load capacitor nears full charge, load
TIMER
GATE
SENSE
VOUT
VACL
VCB
SS
DRAIN
VTMRH
230µA + 8 • IDRN
4252B12 F17
PWRGD
5.8µA 5.8µA TIMER
GATE
SENSE
VOUT
VACL VCB
VFCL
SS
DRAIN
VTMRH
VDRNCL
230µA + 8 • IDRN
PWRGD
1 21 432
CB TIMES OUT
Figure 17. Current Limit Behavior (All Waveforms Are Referenced to VEE)
(17a) Analog Current Limit Fault (17b) Fast Current Limit Fault
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
29
4252b12f
APPLICATIONS INFORMATION
current begins to decline below VACL(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point9, the SENSE voltage falls below VCB and TIMER
deactivates.
Large values of CSS can cause premature circuit breaker
time out as VACL(t) may exceed the VCB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large CSS values is SOA duration
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below VCB will not activate the
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252C-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, VSUPPLY. The D1 Zener voltage, VZ
is set to be the same as the low supply operating volt-
age, VSUPPLY(MIN) = 43V. If the goal is to have the high
supply operating voltage, VSUPPLY(MAX) = 71V giving the
same power at VSUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
R6
R4 =VCB
VSUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
POWERMAX =VSUPPLY(MIN) +VSUPPLY(MAX)
( )
2
4•VSUPPLY(MIN) •VSUPPLY(MAX)
•POWERSUPPLY(MIN)
=1.064•POWERSUPPLY(MIN)
(17)
when
VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V.
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWERFAULT =
VSUPPLY
RS
•VACL – VSUPPLY –VZ
( )
•R6
R4
(18)
TIMER
GATE
SENSE
SS
DRAIN
VTMRH
VDRNCL
VACL
VCB
VDRNL
VGS(th)
VIN – VGATEH
VTMRL
4252B12 F18
PWRGD
5.8µA
58µA
58µA
TIMER
GATE
SENSE
SS
DRAIN
VTMRH
VDRNCL
VCB
VACL
VDRNL
VGS(th)
VIN – VGATEH
VTMRL
PWRGD
5.8µA
58µA
58µA
12 34 567 7a 8 9 10 11
END OF INTIAL TIMING CYCLE
12 3 4 5 6 7 8 9 10 11
END OF INTIAL TIMING CYCLE
20 • VOS
20 • (VCB + VOS)
20 • (VACL + VOS)
20 • VOS
20 • (VCB + VOS)
20 • (VACL + VOS)
230µA + 8 • IDRN 230µA + 8 • IDRN
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to VEE)
(18a) Without External CSS (18b) With External CSS
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
30
4252b12f
APPLICATIONS INFORMATION
4252B12 F19
–48RTN
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
392k
1%
R2
30.1k
1%
CT
0.68µF
CSS
68nF CC
10nF
–48V
RS
0.02Ω
Q1
IRF530S
VOUT
RC
10Ω
R5
100k
R4
38.3k
D1
BZV85C43
RIN
3× 1.8k
1/4W EACH
1
9
8
10
3
2
7
6
4
5
C1
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
+
RD 1M
R6 27Ω
LOAD
EN
*
*FMMT493 **DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
Figure 19. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit
Figure 20 shows the LTC4252C in a foldback current
limit application. When VOUT is shorted to the –48V RTN
supply, current flows through resistors R4 and R5. This
results in a voltage drop across R5 and a corresponding
reduction in voltage drop across the sense resistor, RS,
as the ACL amplifier servos the sense voltage between
the SENSE and VEE pins to about 60mV. The short-circuit
current through RS reduces as the VOUT voltage increases
during an output short-circuit condition. Without foldback
current limiting resistor R5, the current is limited to 3A
during analog current limit. With R5, the short-circuit
current is limited to 0.5A when VOUT is shorted to 71V.
Inrush Control Without a Sense Resistor
During Power-Up
Figure 21 shows the LTC4252C in an application where the
inrush current is controlled without a sense resistor during
power-up. This setup is suitable only for applications that
don’t require short-circuit protection from the LTC4252C.
Resistor R4 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
C2=IGATE •CL
IINRUSH
(19)
where IGATE = 58µA and CL is the total load capacitance.
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up
to a voltage roughly equal to VEE • C2/CGS(Q1) before the
LTC4252C powers up. By placing capacitor C3 in parallel
with the gate capacitance of Q1 and isolating them from
C2 using resistor R4, the problem is solved. The value of
C3 is given by:
C3= VSUPPLY(MAX)
VGS(TH),Q1
•C2+CGD(Q1)
( )
(20)
C3 ≈ 35 • C2 for VSUPPLY(MAX) = 71V
where VGS(TH),Q1 is the MOSFET’s minimum gate threshold
and VSUPPLY(MAX) is the maximum operating input voltage.
Diode-ORing
Figure 22 shows the LTC4252B used as diode-oring with
Hot Swap capability in a dual –48V power supply applica-
tion. The conventional diode-OR method uses two high
power diodes and heat sinks to contain the large heat
dissipation of the diodes. With the LTC4252B controlling
the external FETs Q2 and Q3 in a diode-OR manner, the
small turn-on voltage across the fully enhanced Q2 and
Q3 reduces the power dissipation significantly.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
31
4252b12f
APPLICATIONS INFORMATION
4252B12 F20
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
392k
1%
R2
30.1k
1%
CT
0.68µF
CSS
68nF CC
10nF
–48V
RS
0.02Ω
R4
38.3k Q1
IRF530S
VOUT
RC
10Ω
R3
5.1k
RIN
3× 1.8k
1/4W EACH
1
9
8
10
3
2
7
6
4
5
C1
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
–48RTN
RD 1M
R5 27Ω
RG 10Ω
LOAD
EN
*
*MOC207
+
**DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
4252B12 F21
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
392k
1%
R2
30.1k
1%
CT
0.68µF
CSS
68nF
C3
330nF
25V
C2
10nF
100V
–48V
R4
1k
1% Q1
IRF530S
VOUT
R3
5.1k
RIN
3× 1.8k
1/4W EACH
1
9
8
10
3
2
7
6
4
5
C1
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
–48RTN
RD 1M
RG 10Ω
LOAD
EN
*
*MOC207 **DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
+
Figure 20. Circuit Breaker with Foldback Current Limit Application
Figure 21. Inrush Control Without a Sense Resistor Application
At power-up, Q5 and Q8 are held off low by the SS pin of
the LTC4252B; resistors R5 and R8 pull the SENSE pin
closed to VEE. VEE is connected to the power supply with
lower voltage through the body diodes Q2 or Q3 until Q2
or Q3 is turned on. This allows the LTC4252B to perform
a start-up cycle and ramp up the SS and GATE voltage.
As the SS voltage ramps up to 2.2V, it turns on Q5 and Q8
and pulls TIMER low through Q6 and Q9. The sense voltage
rises as current flows into R5 and R8 through resistors
R3 and R6. The ACL amplifier of the LTC4252B servos
the sense voltage to about 100mV as the GATE voltage
regulates Q2 and Q3. Current flows into R4, Q4 and R7,
Q7 as Q2 and Q3 turn on. The respective node voltages at
the R3 and R4 connection and the R6 and R7 connection
are always kept equal to their respective sense voltages
by the Q4 and Q2 VDS drop and the Q7 and Q3 VDS drop
assuming the Q5 and Q8 VDS drop is negligible.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
32
4252b12f
APPLICATIONS INFORMATION
UV/OV
VEE
VIN
SENSESS
TIMER GATE
DRAIN
LTC4252B-1
R1
402k
R2
32.4k
CT
0.33µF
CSS
68nF
CC1
22nF
RC1
10Ω
Q1
IRF530S
RS
0.02Ω
RIN1
3 × 1.8k IN SERIES
1/4W EACH
1
7
8
2
6
5
3
4
C1
10nF
CIN
1µF
Hot Swap SECTION
DIODE-OR CIRCUIT FOR CHANNEL A
–48RTN
–48V A
RD
1M
LOAD
MODULE
UV
VEE
VIN
SENSE
OV
R5
560Ω
SS
TIMER
PWRGD
GATE
DRAIN
LTC4252B-2
1
9
2
10
Q6
FDV301N
Q5
FDV301N
Q2
IRF530S
Q4
BSS131
CIN2
1µF
RIN2
3 × 1.8k IN SERIES
1/4W EACH
3
8
7
4
6
5
RC2
10µ
R3
12k
R4
150Ω
CC2
22nF
DIODE-OR CIRCUIT FOR CHANNEL B
–48V B
UV
VEE
VIN
SENSE
OV
R8
560Ω
SS
TIMER
PWRGD
GATE
DRAIN
LTC4252B-2
1
9
2
10
Q9
FDV301N
Q8
FDV301N
Q3
IRF530S
Q7
BSS131
CIN3
1µF
RIN3
3 × 1.8k IN SERIES
1/4W EACH
3
8
7
4
6
5
RC3
10Ω
R6
12k
R7
150Ω
CC3
22nF
4252B12 F22
DIN1†
DDZ13B**
DIN3†
DDZ13B**
DIN2†
DDZ13B**
**DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 22. –48V/2.5A Diode-OR Application
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
33
4252b12f
APPLICATIONS INFORMATION
The internal fault latches of the LTC4252B are disabled as
the TIMER pin is always held low by the SS voltage when
Q2 and Q3 are in analog current limit.
If both power supplies from channel A and B are exactly
equal, then equal load current will flow through Q2 and
Q3 to the load module via the Hot Swap section.
If the channel A supply is greater than the channel B by
more than 100mV, the sense voltage will rise above the
fast comparator trip threshold of 200mV, the GATE will
be pulled low and Q2 is turned off. The GATE ramps up
and regulates Q2 when the channel A supply is equal to
the channel B supply. Likewise, if the channel B supply is
greater than channel A by more than 100mV, it trips the
fast comparator and GATE is pulled low and Q3 is turned
off. The GATE ramps up and regulates Q3 when the channel
B supply is equal to the channel A supply.
Resistors R4, R7 and external FETs Q4 and Q7 limit the
current flow into Q5 and Q8 during their respective sup-
ply source short. When the channel A supply is shorted
to the –48V RTN (or GND), large current flows into Q4
momentarily and creates a voltage drop across R4, which
in turn reduces the gate-to-source voltage of Q4, limiting
the current flow. The sense voltage is lifted up and causes
the fast comparator of LTC4252B to trip and pull the GATE
low instantly. The channel A supply short will not cause
Q3 of channel B diode-OR circuit to turn off.
Similarly, when the channel B supply is shorted to the
–48V RTN (or GND), large current flows into Q7 momen-
tarily and creates a voltage drop across R7, which in turn
reduces the gate-to-source voltage of Q7, thus limiting
the current flow. The increase in sense voltage will trip
the fast comparator of LTC4252B and pull the GATE low
instantly. The channel B supply short will not cause Q2
of channel A diode-OR circuit to turn off. The load short
at the output of Q1 is protected by the Hot Swap section.
Using an EMI Filter Module
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
using the Lucent FLTR100V10 filter module is shown in
Figure 23. When using a filter, an opto-isolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
Figure 23. Typical Application Using a Filter Module
4252B12 F23
UV
OV
VEE
VIN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
392k
1%
R2
30.1k
1% CT
0.68µF CSS
68nF CC
10nF
–48V
RS
0.02Ω
Q1
IRF530S 1N4003
VIN+
C2
0.1µF
100V
VIN–
VOUT+
VOUT–
RC
10Ω
R3
5.1k
RIN
3× 1.8k
1/4W
1
9
8
10
3
2
7
6
4
5
C1
10nF
CIN
1µF
–48RTN
(SHORT PIN)
–48RTN
(LONG PIN)
RD
1M
*MOC207
*
+
C3
0.1µF
100V
C4
100µF
100V
C6
100µF
16V
C5
0.1µF
100V
LUCENT
FLTR100V10
CASE
VIN+
ON/OFF
VIN–
VOUT+
1
2
4 5
6
7
8
95V
3
SENSE+
SENSE–
TRIM
VOUT–
LUCENT
JW050A1-E
CASE
+
DIN†
DDZ13B**
**DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
34
4252b12f
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
35
4252b12f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
36
4252b12f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
LT 0112 • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to – 80V
LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Latched Off/Autoretry
LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V
LTC4214 Negative Voltage Hot Swap Controller Operates from –6V to –16V
LTC4220 Dual Supply Hot Swap Controller ±2.2V to ±16.5V Operation
LT4250 –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –20V to –80V
LTC4251B/
LTC4251B-1/
LTC4251B-2
–48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V
LTC4253B –48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs,
Supplies from –15V
4252B12 F24
–48RTN
UV/OV
VEE
VIN
SENSESS
TIMER GATE
DRAIN
LTC4252B-1
R1
402k
1%
R2
32.4k
1% CT
150nF
PUSH
RESET
CSS
27nF CC
22nF
–48V
RS
0.01Ω
Q1
IRF540S
VOUT
RC
10Ω
RIN
2× 5.1k IN SERIES
1/4W EACH
1
7
8
2
6
5
3
4
C1
10nF
CIN
1µF
CL
100µF
–48RTN
(SHORT PIN)
+
RD
1M
R3
22Ω
LOAD
**DIODES, INC †RECOMMENDED FOR HARSH ENVIRONMENTS
DIN†
DDZ13B**
Figure 24. –48V/5A Application
