©2001 Integrated Device Technology, Inc.
NOVEMBER 2001
DSC 3039/9
1
HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM WITH INTERRUPT
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial 20/25ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70261S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT70261L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆◆
◆◆
◆Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆◆
◆◆
◆IDT70261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆◆
◆◆
◆M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆◆
◆◆
◆Busy and Interrupt Flags
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆TTL-compatible, single 5V (±10%) power supply
◆◆
◆◆
◆Available in 100-pin Thin Quad Flatpack
◆◆
◆◆
◆Industrial temperature range (-40OC to +85OC) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
IDT70261S/L
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
BUSY
L
A
13L
A
0L
3039 drw 01
UB
L
LB
L
CE
L
OE
L
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
R/
W
R
BUSY
R
UB
R
LB
R
CE
R
OE
R
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
A
13R
A
0R
R/W
R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
14 14
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
2
Pin Configurations(1,2,3)
Pin Names
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Description
The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT70261 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT70261 is packaged in a 100-pin TQFP.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099989796 95 949392 9190 8988 8786 8584 8382 81 8079 787776
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
CC
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
3039 drw 02
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
GND
M/S
BUSY
R
INT
R
A
0R
N/C
N/C
N/C
BUSY
L
A
1R
A
2R
A
3R
A
4R
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
SEM
R
CE
R
UB
R
LB
R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
13L
A
13R
IDT70261PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
A
6L
A
5R
,
11/16/01
Left Port Right Port Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Re ad /Write Enab le
OE
L
OE
R
Outp ut Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/O
15L
I/O
0R
- I/O
15R
Data Inp ut/Output
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upp er Byte S ele ct
LB
L
LB
R
Lo we r By te Select
INT
L
INT
R
Inte rrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
3039 tbl 01
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
3
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's(I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.
Maximum Operating Temperature
and Supply Voltage(1,2)
Truth Table II – Semaphore Read/Write Control(1)
Truth Table I – Non-Contention Read/Write Control
Recommended DC Operating
Conditions
NOTE:
1. A0L — A13L ≠ A0R — A13R.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on"case temperature.
Grade Ambient
Temperature GND Vcc
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to + 85
O
C0V 5.0V
+
10%
3039 t b l 02
Symbol Parameter Min. Typ. Max. Unit
VCC Sup ply Voltag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Input High Voltag e 2.2
____
6.0
(2)
V
VIL Inp ut Lo w Vo ltag e -0. 5
(1)
____
0.8 V
3039 tb l 03
Inputs
(1)
Outputs
Mode
CE R/WOE UB LB SEM I/O
8-15
I/O
0-7
HXXXXHHigh-ZHigh-ZDeselected: Power-Down
X X X H H H Hig h-Z Hi g h-Z B o th B y te s De s e l e c te d
LLXLHHDATA
IN
Hi g h-Z Wri te to Up p e r By te Only
LLXHLHHigh-ZDATA
IN
Wr ite to Lo wer B y te O nly
LLXLLHDATA
IN
DATA
IN
Wr ite to B o th Byte s
LHLLHHDATA
OUT
Hig h-Z Read Upp er Byte Only
LHLHLHHigh-ZDATA
OUT
Re ad Lo we r By te Only
LHLLLHDATA
OUT
DATA
OUT
Read Both Bytes
XXHXXXHigh-ZHigh-ZOutputs Disabled
3039 t bl 04
Inputs Outputs
Mode
CE R/WOE UB LB SEM I/O
8-15
I/O
0-7
HHLXXLDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
XHLHHLDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
H
↑
XXXLDATA
IN
DATA
IN
Write I/O
0
into Semaphore Flag
X
↑
XHHLDATA
IN
DATA
IN
Write I/O
0
into Semaphore Flag
LXXLXL
______ ______
Not All owe d
LXXXLL
______ ______
Not All owe d
3039 tbl 05
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Figure 1. AC Output Test Load
Capacitance(1) (TA = +25°C, f = 1.0Mhz)Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2 . 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol Rating Commercial
& I n du strial Unit
V
TERM
(2)
Termi nal Vo ltag e
wi th Res p e c t
to G ND
-0.5 to +7.0 V
T
BIAS
Temperature
Und er Bias -55 to +125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
I
OUT
DC Output
Current 50 mA
3039 tbl 06
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Cap ac ita nce V
IN
= 3dV 9 pF
C
OUT
Output
Capacitance V
OUT
= 3dV 10 pF
3039 t bl 07
Symbol Parameter Test Conditi ons
70261S 70261L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Output Le akag e Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Lo w Voltag e I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
3039 t bl 0 8
Input Pulse Levels
Inp ut Ris e /Fall Time s
Inp ut Timing Refe renc e Le v els
Outp ut Re fe re nc e Le ve ls
Outp ut Lo ad
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
3039 tbl 09
3039 drw 04
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
3039 drw 03
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
70261X15
Com'l Onl y 70261X20
Com'l & Ind 70261X25
Com 'l & I nd
Symbol P arameter Test Condi tion Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating Current
(B o th P o rts A cti ve ) CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX(3)
COM'L S
L190
190 325
285 180
180 315
275 170
170 305
265 mA
IND S
L
____
____
____
____
____
180
____
315 170
____
345
____
I
SB1
Standby Current
(Both Po rts - TTL Lev el
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX(3)
COM'L S
L35
35 95
70 30
30 85
60 25
25 85
60 mA
IND S
L
____
____
____
____
____
30
____
80 25
____
100
____
I
SB2
Standby Current
(O n e Port - TTL Lev el In pu ts) CE
"A"
= V
IL
and CE
"B"
= V
IH(5)
A cti ve Po rt Outp uts Dis ab le d ,
f=f
MAX(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L125
125 220
190 115
115 210
180 105
105 200
170 mA
IND S
L
____
____
____
____
____
115
____
210 105
____
230
____
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0 .2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
IND S
L
____
____
____
____
____
0.2
____
10 1.0
____
30
____
I
SB4
Full Standby Current
(O ne Port - All C M OS L evel
Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
A cti ve Po rt Outp uts Disab led
f = f
MAX(3)
COM'L S
L120
120 195
170 110
110 185
160 100
100 170
145 mA
IND S
L
____
____
____
____
____
110
____
185 100
____
200
____
3039 tbl 10
70261X35
Com'l Only 70261X55
Com'l Only
Symbol Parameter Test Condi tion Version Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dy na mi c O p e r ati ng
Current
(B o th P o rts A cti ve )
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L160
160 295
255 150
150 270
230 mA
IND S
L
____
____
____
____
____
____
____
____
mA
I
SB1
Standby Current
(Both Po rts - TTL Lev el
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L20
20 85
60 13
13 85
60 mA
IND S
L
____
____
____
____
____
____
____
____
mA
I
SB2
Standby Current
(One Po rt - TTL Level
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
A cti ve Po rt Outp uts Dis ab le d ,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L95
95 185
155 85
85 165
135 mA
IND S
L
____
____
____
____
____
____
____
____
mA
I
SB3
Full Standb y Current
(B o th P o rts - All CMOS
Le v el Inp u ts )
Both Ports CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0 .2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
5mA
IND S
L
____
____
____
____
____
____
____
____
mA
I
SB4
Full Standb y Current
(One Po rt - All CMOS
Le v el Inp u ts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
A cti ve Po rt Outp uts Dis ab le d
f=f
MAX
(3)
COM'L S
L90
90 160
135 80
80 135
110 mA
IND S
L
____
____
____
____
____
____
____
____
mA
3039 tbl 1
1
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
6
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70261X15
Com'l Only 70261X20
Com'l & Ind 70261X25
Com'l & Ind
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
20
____
25
____
ns
t
AA
Address Acce ss Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
20
____
25 ns
t
ABE
Byte Enable Access Time
(3)
____
15
____
20
____
25 ns
t
AOE
Output Enable Acce ss Time
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po we r Do wn Time
(2)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
12
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
25 ns
3 039 tb l 12 a
70261X35
Com'l Only 70261X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
ns
t
AA
Address Acce ss Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3)
____
35
____
55 ns
t
ABE
Byte Enable Access Time
(3)
____
35
____
55 ns
t
AOE
Output Enable Acce ss Time
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25 ns
t
PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po we r Do wn Time
(2)
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55 ns
3039 tbl 12b
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
7
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Waveform of Read Cycles(5)
Timing of Power-Up Power-Down
t
RC
R/W
CE
ADDR
t
AA
OE
UB, LB
3039 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3, 4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
3039 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
,
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
Symbol Parameter
70261X15
Com 'l Only 70261X20
Com'l & I nd 70261X25
Com 'l & Ind
UnitMin. Max. Min. Max. Min. Max.
WR I T E CY C LE
t
WC
Wri te Cy cle Time 15
____
20
____
25
____
ns
t
EW
Chip Enable to End -o f-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
DH
Data Ho l d Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
12
____
15 ns
t
OW
Outp ut Activ e fro m E nd -of-Write
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Fl ag Co ntention Wind o w 5
____
5
____
5
____
ns
3 039 tbl 13 a
Symbol Parameter
70261X35
Com'l Only 70261X55
Com'l Only
UnitMin. Max. Min. Max.
WRI TE CYCL E
t
WC
Wri te Cy c le Ti me 35
____
55
____
ns
t
EW
Chip Enab le to End-o f-Write
(3)
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Wri te P uls e Wi d th 25
____
40
____
ns
t
WR
Wri te Re c o v e ry Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25 ns
t
DH
Data Ho ld Time
(4)
0
____
0
____
ns
t
WZ
Write En able to Output in High-Z
(1,2)
____
15
____
25 ns
t
OW
Output Active from End-of-Write
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM F lag Write to Read Time 5
____
5
____
ns
t
SPS
SEM Flag Co nte ntio n Window 5
____
5
____
ns
3039 tbl 1 3b
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
9
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB or LB
3039 drw 07
(9)
CE or SEM
(9)
(7)
(3)
3039 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
10
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. DOR = DOL = V IL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
SEM
3039 drw 09
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
SEM"A"
3039 drw 10
tSPS
MATCH
R/W"A"
MATCH
A0"A"-A2"A"
SIDE "A"
(2)
SEM"B"
R/W"B"
A0"B"-A2"B"
SIDE
(2)
"B"
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Symbol Parameter
70261X15
Com 'l Only 70261X20
Com'l & I nd 70261X25
Com 'l & Ind
UnitMin. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ns
t
BDA
BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns
t
BAC
BUSY Acc ess Time fro m Chip Enab le Lo w ____ 15 ____ 20 ____ 20 ns
t
BDC
BUSY Access Time from Chip Enable High ____ 15 ____ 17 ____ 17 ns
t
APS
Arbitration Priority Set-up Time
(2)
5____ 5____ 5____ ns
t
BDD
BUSY Disable to Valid Data
(3)
____ 18 ____ 30 ____ 30 ns
t
WH
Write Hold After BUSY
(5)
12 ____ 15 ____ 17 ____ ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY In p ut to Wri te
(4)
0____ 0____ 0____ ns
t
WH
Write Hold After BUSY
(5)
12 ____ 15 ____ 17 ____ ns
PORT-TO-PORT DELAY TI MI NG
t
WDD
Write Puls e to Data De la y
(1)
____ 30 ____ 45 ____ 50 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____ 25 ____ 30 ____ 35 ns
3 039 tbl 14 a
Symbol Parameter
70261X35
Com'l Onl y 70261X55
Com 'l Only
UnitMin. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match ____ 20 ____ 45 ns
t
BDA
BUSY Disable Time from Address Not Matched ____ 20 ____ 40 ns
t
BAC
BUSY Acc ess Time fro m Chip Enab le Lo w ____ 20 ____ 40 ns
t
BDC
BUSY Access Time from Chip Enable High ____ 20 ____ 35 ns
t
APS
Arbitration Priority Set-up Time
(2)
5____ 5____ ns
t
BDD
BUSY Disable to Valid Data
(3)
____ 35 ____ 40 ns
t
WH
Write Hold After BUSY
(5)
25 ____ 25 ____ ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY In p ut to Wri te
(4)
0____ 0____ ns
t
WH
Write Hold After BUSY
(5)
25 ____ 25 ____ ns
PORT-TO-PORT DELAY TIMI NG
t
WDD
Write Puls e to Data De la y
(1)
____ 60 ____ 80 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____ 45 ____ 65 ns
3039 tbl 14b
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
12
3039 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
Timing Waveform of Write with Port-to-Port Read and BUSY
(M/S = VIH)(2,4,5)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “SLAVE” version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
3039 drw 12
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(2)
(3)
(1)
,
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
13
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
Waveform of BUSY Arbitration Cycle Controlled by
Address Match Timing (M/S = VIH)(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3039 drw 13
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
3039 drw 14
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
Symbol Parameter
70261X15
Com'l On ly 70261X20
Com 'l & Ind 70261X25
Com'l & Ind
UnitMin. Max. Min. Max. Min. Max.
INTERRUPT TI MING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recove ry Time 0
____
0
____
0
____
ns
t
INS
In te rru p t S e t Ti m e
____
15
____
20
____
20 ns
t
INR
In te rru p t Reset Time
____
15
____
20
____
20 ns
3 039 tbl 15 a
Symbol Parameter
70261X35
Co m'l Onl y 70261X55
Com'l Only
UnitMin. Max. Min. Max.
INTERRUPT T IMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Rec ove ry Time 0
____
0
____
ns
t
INS
Inte rrupt S et Tim e
____
25
____
40 ns
t
INR
Inte rrupt Re se t Time
____
25
____
40 ns
3039 tbl 15b
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
14
Waveform of Interrupt Timing(1)
Truth Tables
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1)
3039 drw 15
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
3039 drw 16
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left P ort Ri ght Port
FunctionR/W
L
CE
L
OE
L
A
13L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
13R
-A
0R
INT
R
LLX3FFFXXXX X L
(2)
S e t Ri g h t INT
R
Flag
XXX X XXLL3FFFH
(3)
Re s e t Ri g ht INT
R
Fl ag
XXX X L
(3)
L L X 3FFE X Set Le ft INT
L
Flag
XLL3FFEH
(2)
XXXXXReset Left INT
L
Flag
3039 tb l 16
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
15
Truth Table IV —
Address BUSY Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70261 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70261 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE = VIH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX), where a write is defined as CER = R/WR = V IL per Truth Table
III. The left port clears the interrupt through access of address location
3FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
port interrupt flag (INTR) is asserted when the left port writes to memory
location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port
must read the memory location 3FFF. The message (16 bits) at 3FFE or
3FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and 3FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Inputs Outputs
Function
CELCERAOL-A13L
AOR-A13R BUSYL
(1)
BUSYR
(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhib it
(3)
3039 tbl 17
Functions D0 - D15 Left D
0
- D
15
Righ t Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semap hore 0 1 Left port has semaphore to ken
Right P ort Write s " 0" to Se map hore 0 1 No change . Rig ht sid e ha s no write ac ce s s to s emap ho re
Left Port Writes "1" to Semap hore 1 0 Right port obtains semaphore token
Left P ort Wri te s " 0" to Se mapho re 1 0 No chang e . Le ft po rt ha s no write ac ce s s to s emap ho re
Rig ht Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semap hore 1 1 Semaphore free
Rig ht Port Writes "0" to Semaphore 1 0 Right po rt has semaphore token
Rig ht Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semap hore 0 1 Left port has semaphore to ken
Left Port Writes "1" to Semap hore 1 1 Semaphore free
3 039 tbl 18
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
16
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins high. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port low.
The BUSY outputs on the IDT 70261 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70261 RAMs.
Width Expansion with Busy Logic
Master/Salve Arrays
When expanding an IDT70261 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT70261 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT70261 is an extremely fast Dual-Port 16K x 16 CMOS Static
RAM with an additional 8 address locations dedicated to binary semaphore
flags. These flags allow either processor on the left or right side of the Dual-
Port RAM to claim a privilege over the other processor for functions defined
by the system designer’s software. As an example, the semaphore can
be used by one processor to inhibit the other from accessing a portion of
the Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table V where CE and SEM are both HIGH .
Systems which can best use the IDT70261 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70261's hardware sema-
phores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70261 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
3039 drw 17
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
,
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
17
that semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70261 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none
of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table V). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
V). As an example, assume a processor writes a zero to the left port at a
free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
Figure 4. IDT70261 Semaphore Logic
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time.
The semaphore logic is specially designed to resolve this problem.
If simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making the
request, the first side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70261’s Dual-Port RAM. Say the 16K x 16
RAM was to be divided into two 8K x 16 blocks which were to be dedicated
at any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control
D
3039 drw 18
0DQ
WRITE
D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ
SEMAPHORE
READ
,
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
18
of the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
19
Ordering Information
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
PF 100-pin TQFP (PN100-1)
15
20
25
35
55
S
L
Standard Power
Low Power
XXXXX
Device
Type
256K (16K x 16) Dual-Port RAM with Interrupt
70261
IDT
Speed
in nanoseconds
3039 drw 19
I
(1)
Industrial (-40°C to +85°C)
Commercial
Commercial & Industrial
Commercial & Industrial
Commercial Only
Commercial Only
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/14/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
6/4/99: Changed drawing format
Page 1 Corrected DSC number
2/18/00: Added Industrial Temperature Ranges and removed related notes
Replaced IDT logo
Changed ±200mV in table and waveform notes to 0mV
5/22/00: Page 3 Clarified TA parameter
Page 4 Increased storage temperature parameter
Page 5 DC Electrical parameters–changed wording from open to disabled
11/20/01: Page 2 Added date revision for pin configuration
Page 5 Removed Industrial temp for standard power 20ns speed from DC Electrical Characteristics
Removed Industrial temp for low power 25ns speed from DC Electrical Characteristics
Removed Industrial temp for standard and low power for 35ns & 55ns speeds from DC Electrical Characteristics
Pages 6,8,11&13 Removed Industrial temp for 35ns and 55ns speeds from AC Electrical Characteristics
Page 19 Removed Industrial temp from 35ns and 55ns in ordering information
NOTE:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
